Deposition processes for forming semiconductor devices and systems

Abstract

The present disclosure relates to deposition processes for forming semiconductor devices and systems. A method includes placing a semiconductor substrate in a deposition chamber, wherein the semiconductor substrate includes a trench; and performing an atomic layer deposition (ALD) process to deposit a dielectric material in the trench, including: flowing a first precursor of the dielectric material into the deposition chamber as a vapor phase; flowing a second precursor of the dielectric material into the deposition chamber as a vapor phase; and controlling the pressure and temperature in the deposition chamber such that the second precursor condenses as a liquid phase of the second precursor on a surface in the trench, wherein the liquid phase of the second precursor exhibits a capillary phenomenon.

Description

Technical Field

[0001] The present disclosure relates to deposition processes for forming semiconductor devices and systems. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers onto a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] According to one embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: placing a semiconductor substrate in a deposition chamber, wherein the semiconductor substrate includes a trench; and performing an atomic layer deposition (ALD) process to deposit a dielectric material in the trench, comprising: causing a first precursor of the dielectric material to flow into the deposition chamber as a gas phase; causing a second precursor of the dielectric material to flow into the deposition chamber as a gas phase; and controlling the pressure and temperature in the deposition chamber so that the second precursor as a liquid phase of the second precursor condenses on a surface in the trench, wherein the liquid phase of the second precursor has a capillary phenomenon.

[0005] According to another embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a semiconductor structure comprising a trench in a substrate; and depositing a dielectric material in the trench using an atomic layer deposition (ALD) process performed using a process chamber, wherein the ALD process comprises an ALD cycle, wherein the ALD cycle comprises: exposing the semiconductor structure to a first precursor; and exposing the semiconductor structure to a second precursor, wherein the second precursor condenses on a surface of the semiconductor structure as a liquid with capillary action; wherein a vertical deposition rate of the dielectric material from a bottom surface of the trench is greater than a lateral deposition rate of the dielectric material from a sidewall of the trench.

[0006] According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: a fin protruding from a substrate; an isolation region surrounding the fin; a gate stack located above the fin; a source / drain region adjacent to the gate stack in the fin; an interlayer dielectric (ILD) located above the source / drain region, wherein a top surface of the gate stack is recessed from a top surface of the ILD; a hard mask covering the gate stack, wherein a top surface of the hard mask is flush with a top surface of the ILD, wherein the hard mask has no seam, wherein the hard mask has a height:width aspect ratio in a range between 1:3 and 1:25; and wherein the hard mask comprises a metal oxide; and a conductive feature extending through the hard mask to contact the gate stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1A and Figure 1B is an illustration of a deposition system for performing a capillary-assisted atomic layer deposition (ALD) process, according to some embodiments.

[0009] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 and Figure 10 is a cross-sectional view of an intermediate stage in performing a capillary assisted deposition (ALD) process according to some embodiments.

[0010] Figure 11 is a diagram of an ALD cycle of a capillary assisted deposition (ALD) process according to some embodiments.

[0011] Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 、 Figure 19 、 Figure 20 、 Figure 21 、 Figure 22 、 Figure 23 、 Figure 24 、 Figure 25 、 Figure 26 、 Figure 27 and Figure 28 are various views of intermediate stages in fabricating a FinFET according to some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are directly in contact with each other, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact with each other. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatially relative terms, such as "below," "beneath," "below," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another (or multiple) elements or features as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0014] Various embodiments provide a process for depositing gap filling materials using a capillary assisted atomic layer deposition (ALD) process for performing a partially bottom-up deposition process. The capillary assisted ALD process described herein includes controlling the process pressure and / or process temperature during the ALD process so that one or more precursors condense on the surface as a liquid. The (one or more) precursors can be selected as suitable precursors that have capillarity in the liquid phase. Due to the capillarity of the condensed precursors, the precursors can be drawn into deep or narrow spaces by capillary action. In this way, the material in these deep or narrow spaces can have bottom-up growth, while the material can also have conformal growth on more exposed or shallower surfaces. This allows gap filling deposition of materials in deep or narrow spaces without forming defects such as seams or voids. The technology described herein allows the use of thermal ALD or plasma ALD to improve material deposition without the use of inhibitors or other additives. Semiconductor devices formed according to the process described herein can have fewer device defects and improved performance.

[0015] Some of the embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments contemplate aspects for use in planar devices (e.g., planar FETs) or aspects for use in nanostructured FETs (e.g., nanosheets or "gate-around" FETs, etc.). Additionally, embodiments of the gapfill deposition processes described herein may be used in other steps of forming FinFETs other than those shown, or may be used to form other types of devices or structures. For example, the embodiments described herein may be used to form other front-end-of-line (FEOL) features or back-end-of-line features, such as for forming passivation layers, insulating layers, sacrificial layers, spacers, contacts, vias, metal lines, or other conductive wiring; for performing gapfill deposition steps in a multi-patterning process, and the like.

[0016] Figure 1A and 1B Illustrated is a deposition system 100 that may be used to deposit material on a substrate 110 in accordance with some embodiments. The deposition system 100 may be used to deposit material using a capillary assisted atomic layer deposition process (ALD). Figures 2 to 11 Illustrative examples of capillary assisted ALD processes are described in more detail. Figures 12 to 28 Process steps for forming the FinFET device 310 using a capillary assisted ALD process to deposit a dielectric hard mask 380 are described in accordance with some embodiments.

[0017] Go to Figures 1A-1B , shows a deposition system 100 that can be used to deposit materials using a capillary assisted atomic layer deposition process (ALD), such as the following for Figure 2-11 The deposition system 100 can be used to deposit material on a substrate 110, which can be, for example, a semiconductor structure (e.g., Figure 2 structure 210 shown), a wafer (e.g., Figure 12 wafer 310 as shown), a device, a package, another structure, etc.

[0018] In some embodiments, deposition system 100 receives precursor materials from a first precursor delivery system 105 and a second precursor delivery system 106 and forms a layer of the materials on substrate 110. First and second precursor delivery systems 105, 106 can work in conjunction with each other to supply various precursor materials to deposition chamber 103, where substrate 110 is positioned. In some cases, first and second precursor delivery systems 105, 106 can have similar physical components. For example, first precursor delivery system 105 can include a gas source 107A and a flow controller 109A, and second precursor delivery system 106 can include a gas source 107B and a flow controller 109B. In embodiments where the precursors are stored in a gaseous state, gas sources 107A / B can supply the precursors to deposition chamber 103. Gas sources 107A / B can be containers, such as gas storage tanks, located locally or remotely from deposition chamber 103. In another embodiment, gas sources 107A / B can be facilities that independently prepare precursors and deliver them to corresponding flow controllers 109A / B. Any suitable source of precursors can be used as gas sources 107A and / or 107B, and all such sources are fully intended to be included within the scope of the embodiments.

[0019] Gas sources 107A / B can supply the desired precursors to corresponding flow controllers 109A / B. Flow controllers 109A / B can be used to control the flow of precursors to precursor gas controller 113 and ultimately to deposition chamber 103, thereby also helping to control the pressure within deposition chamber 103. Flow controllers 109A and / or 109B can be, for example, proportional valves, regulating valves, needle valves, pressure regulators, mass flow controllers, combinations of these, and the like. However, any suitable method for controlling and regulating the flow of gas to precursor gas controller 113 can be used, and all such components and methods are fully intended to be included within the scope of the embodiments.

[0020] As will be appreciated by one of ordinary skill in the art, although the first precursor delivery system 105 and the second precursor delivery system 106 are described herein as having the same components, this is merely an illustrative example and is not intended to limit the embodiments in any way. Any type of suitable precursor delivery system may be used, having any type and number of individual components that are the same or different than any other precursor delivery system within the deposition system 100. All such precursor systems are fully intended to be included within the scope of the embodiments.

[0021] Additionally, in embodiments where the precursor is stored in a solid or liquid state, the gas source 107A / B can store a carrier gas and introduce the carrier gas into a precursor tank (not separately shown) that stores the precursor in a solid or liquid state. The carrier gas is then used to propel and carry the precursor as it evaporates or sublimates into the gas portion of the precursor tank, which is then sent to the precursor gas controller 113. Any suitable method and combination of components can be used to provide the precursor, and all such combinations of components are fully intended to be included within the scope of the embodiments.

[0022] The first precursor delivery system 105 and the second precursor delivery system 106 can supply their respective precursor materials to the precursor gas controller 113. The precursor gas controller 113 connects and isolates the first precursor delivery system 105 and the second precursor delivery system 106 from the deposition chamber 103 so as to deliver the required precursor materials to the deposition chamber 103. The precursor gas controller 113 may include devices such as valves, flow meters, sensors, etc. to control the delivery rate (e.g., flow rate) of each precursor, and may be controlled by the control unit 115 (hereinafter referred to as Figure 1B Further description) to control the received instructions.

[0023] The precursor gas controller 113, upon receiving instructions from the control unit 115, can open and close valves to connect one or more of the first precursor delivery system 105 and the second precursor delivery system 106 to the deposition chamber 103 and guide the desired precursor material into the deposition chamber 103 and the nozzle 117 through the manifold 116. The nozzle 117 can be used to disperse the selected (one or more) precursor materials into the deposition chamber 103 and can be designed to evenly disperse the precursor materials so as to minimize undesirable process conditions caused by uneven dispersion. In an embodiment, the nozzle 117 can have a circular design with openings evenly dispersed around the nozzle 117 to allow the desired precursor material to be dispersed into the deposition chamber 103.

[0024] However, as will be appreciated by one of ordinary skill in the art, the introduction of the precursor material into the deposition chamber 103 through a single showerhead 117 or through a single introduction point, as described above, is for illustration only and is not intended to be limiting of the embodiments. Any number of separate and independent showerheads 117 or other openings for introducing the precursor material into the deposition chamber 103 may be used. All such combinations of showerheads and other introduction points are fully intended to be included within the scope of the embodiments.

[0025] The deposition chamber 103 can receive the desired precursor material and expose the substrate 110 to the precursor material, and can be any desired shape suitable for dispersing the precursor material and bringing the precursor material into contact with the semiconductor device 100. Figure 1AIn the illustrated embodiment, deposition chamber 103 has cylindrical sidewalls and a bottom. However, deposition chamber 103 is not limited to a cylindrical shape, and any other suitable shape may be used, such as a hollow square tube, an octagon, etc. Furthermore, deposition chamber 103 may be surrounded by a housing 119 made of a material that is inert to the various process materials. Thus, while housing 119 may be any suitable material capable of withstanding the chemicals and pressures involved in the deposition process, in embodiments, housing 119 may be steel, stainless steel, nickel, aluminum, alloys of these materials, combinations of these materials, and the like.

[0026] During the deposition process, the substrate 110 may be placed on a mounting platform 121 within the deposition chamber 103 to position and control the substrate 110 and the semiconductor device 100. The mounting platform 121 may include a heating mechanism to heat the substrate 110 during the deposition process. For example, the mounting platform 121 may be heated during a thermal ALD process.

[0027] In some embodiments, the precursor material can be ignited into a plasma to assist in the deposition process, such as for a plasma ALD process. In this embodiment, the mounting platform 121 can further include a first electrode 123 coupled to a first RF generator 133. The first electrode 123 can be electrically biased at an RF voltage by the first RF generator 133 (under the control of the control unit 115) during the deposition process. Through the electrical bias, the first electrode 123 is used to provide a bias to the incoming second precursor material and to assist in igniting the precursor material into a plasma. In addition, the first electrode 123 is also used to maintain the precursor plasma during the deposition process by maintaining the bias voltage.

[0028] In an embodiment, the showerhead 117 may also be or include (or otherwise cooperate with) a second electrode 129 to serve as a plasma generator to assist the deposition chamber 103. In an embodiment, the plasma generator may be a transformer-coupled plasma generator and may be, for example, a coil. The coil may be attached to a second RF generator 127 for providing power to the second electrode 129 (under the control of the control unit 115) to ignite the plasma during the introduction of the precursor material.

[0029] However, although the second electrode 129 is described above as a transformer-coupled plasma generator, the embodiments are not intended to be limited to transformer-coupled plasma generators. Instead, any suitable method of generating plasma may be used, such as an inductively coupled plasma system, magnetically enhanced reactive ion etching, electron cyclotron resonance, a remote plasma generator, etc. All such methods are fully intended to be included within the scope of the embodiments.

[0030] In addition, although Figure 1AA single mounting platform 121 is shown in the figure, but any number of mounting platforms 121 may be included in the deposition chamber 103. In addition, the deposition chamber 103 and the mounting platform 121 may be part of a cluster tool system (not shown). The cluster tool system may be used in conjunction with an automated handling system to position and place the substrate 110 in the deposition chamber 103 before the deposition process, position and hold the substrate 110 during the deposition process, and remove the substrate 110 from the deposition chamber 103 after deposition.

[0031] The deposition chamber 103 may also have an exhaust outlet 125 for exhausting gases from the deposition chamber 103. A vacuum pump 131 may be connected to the exhaust outlet 125 of the deposition chamber 103 to facilitate exhaust of the exhaust gases. Under the control of the control unit 115, the vacuum pump 131 may also be used to reduce and control the pressure within the deposition chamber 103 to a desired pressure, and may also be used to exhaust precursor materials from the deposition chamber 103 in preparation for the introduction of the next precursor material.

[0032] Figure 1B A schematic diagram of a precursor gas controller 113 and a vacuum pump 131 (eg, Figure 1A 1 and 2. The control unit 115 may be any form of computer processor that can be used in an industrial setting to control process machinery. In an embodiment, the control unit 115 may include a processing unit 101, such as a desktop computer, workstation, laptop computer, or a dedicated unit customized for a specific application. The control unit 115 may be equipped with a display 143 and one or more input / output components 145, such as a command output, sensor input, mouse, keyboard, printer, combinations of these, and the like. The processing unit 101 may include a central processing unit (CPU) 146, memory 148, mass storage device 150, video adapter 154, and I / O interface 156 connected to a bus 158.

[0033] Bus 158 may be one or more of any type of bus architecture, including a memory bus or memory controller, a peripheral bus, or a video bus. CPU 146 may include any type of electronic data processor, and memory 148 may include any type of system memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), or read-only memory (ROM). Mass storage device 150 may include any type of storage device configured to store data, programs, and other information and make the data, programs, and other information accessible via bus 158. Mass storage device 150 may include, for example, one or more of a hard drive, a magnetic disk drive, or an optical disk drive.

[0034] Video adapter 154 and I / O interface 156 provide interfaces for coupling external input and output devices to processing unit 101. Figure 1B As shown, examples of input and output devices include a display 143 coupled to a video adapter 154 and I / O components 145, such as a mouse, keyboard, printer, etc., coupled to an I / O interface 156. Other devices may be coupled to the processing unit 101, and additional or fewer interface cards may be used. For example, a serial interface card (not shown) may be used to provide a serial interface for a printer. The processing unit 101 may also include a network interface 160, which may be a wired link and / or a wireless link to a local area network (LAN) or wide area network (WAN) 162.

[0035] It should be noted that the control unit 115 may include other components. For example, the control unit 115 may include a power supply, cables, a motherboard, removable storage media, a chassis, etc. Figure 1B These other components are not shown in FIG, but are considered part of the control unit 115 .

[0036] Now go to Figure 2-11 , illustrates an intermediate step in an exemplary capillary assisted ALD process according to some embodiments. The capillary assisted ALD process described herein can be used, for example, to deposit gap fill materials in narrow areas of a structure, which reduces the chance of forming seams or voids. The process shown is an illustrative example of using a deposition system (e.g., deposition system 100, etc.) to perform a capillary assisted ALD process that deposits material 240 on structure 210. For example, the process previously described for Figure 1A The depicted substrate 110 may include a structure 210 . A capillary-assisted ALD process includes an ALD process in which at least one precursor of a material 240 exhibits capillary behavior on a surface of the structure 210 . Figure 2-11 The exemplary capillary assisted ALD process of FIGURE 1 describes a process in which the first precursor 220 does not exhibit capillary behavior and the second precursor 230 exhibits capillary behavior, but in other embodiments, both precursors may exhibit capillary behavior, or the precursors used in different steps of the process may exhibit capillary behavior. In some embodiments, the conditions of the deposition process may be controlled to enhance the capillary behavior of one or more precursors to improve the quality or gap filling ability of the deposited material 240. The specific characteristics of the precursors used may depend on the material 240. Figure 11 A capillary-assisted ALD process is depicted in an ALD cycle diagram 250 , which shows an exemplary single ALD cycle comprising two steps.

[0037] Go to Figure 2, shows a structure 210 according to some embodiments. Structure 210 includes two features 202 protruding from substrate 203, where features 202 are separated by trench 201. The structure 210 shown is an example, and the techniques described herein can be used to deposit material on any suitable structure or in any suitable trench or groove. As another example, Figure 23-24 An embodiment is described in which a dielectric hard mask material 380' is deposited in the recess 378 as part of forming the FinFET device 310. These and other structures are considered within the scope of the present disclosure.

[0038] Figure 2 The trench 201 shown in FIG has a width W1, which can, for example, be in a range between about 3 nm and about 30 nm, although other widths are possible. The trench 201 can have a depth D1, which can be in a range between about 9 nm and about 300 nm, although other depths are possible. Thus, the trench 201 can have a height:width aspect ratio in a range between about 1:2 and 1:25, although other aspect ratios are possible. The features 202 can have a pitch P1 in a range between about 5 nm and about 200 nm, although other pitches are possible. In some cases, a capillary-assisted ALD process as described herein can deposit material into trenches, grooves, etc. having a width W1 less than about 10 nm, a depth greater than about 100 nm, or an aspect ratio greater than about 1:10, without forming seams or voids in the deposited material. This can improve yield and process reliability when depositing materials using an ALD process.

[0039] Go to Figure 3 , the first precursor material 220 can be flowed (eg, "pulsed") into a deposition chamber (eg, deposition chamber 103). This corresponds to Figure 11 First precursor stream 252A of step 1 is shown. In this example process, first precursor material 220 does not exhibit capillary action. First precursor material 220 adsorbs onto and reacts with exposed surfaces of structure 210, forming first reaction products 221 that are bonded to these surfaces. Once first precursor material 220 reacts with all available reaction sites on the surface, no additional first reaction products 221 can be formed. In this manner, the formation of first reaction product 221 can be a "self-limiting reaction."

[0040] After the first precursor material 220 has reacted, the deposition chamber may then be purged of excess first precursor material 220 or other reaction products. This corresponds to Figure 11The first purge 252B of step 1 is shown. The purge can be performed before or after the self-limiting reaction to form the first reaction product 221 is complete. For example, the purge can be performed by flowing a purge gas such as nitrogen, argon, xenon, etc. into the deposition chamber. After performing the first purge 252B, step 1 of the ALD cycle is completed.

[0041] Go to Figure 4 , the second precursor material 230 can then flow into the deposition chamber. This corresponds to Figure 11 The first precursor stream 254A of step 2 is shown. In this example process, the second precursor material 230 exhibits capillary action. The second precursor material 230 adsorbs on the first reaction product 221 and reacts therewith, thereby forming a second reaction product 231 that is bonded to the first reaction product 221. It should be noted that the first reaction product 221 may undergo chemical changes during the reaction with the second precursor material 230, and the first reaction product 221 after reacting with the second precursor material 230 is therefore Figure 4 The reaction between the first reaction product 221 and the second precursor material 230 results in a layer (eg, a single layer) of material 240, partially or entirely formed. Figure 4 The formation of a monolayer of material 240 may also be a self-limiting reaction because the reaction is limited by the number of unreacted sites of the first reaction product 221.

[0042] also, Figure 4 An embodiment is shown in which the deposition process conditions (e.g., pressure and / or temperature) are controlled and / or the second precursor material 230 is selected so that the second precursor material 230 condensed on the structure 210 is subjected to capillary forces. For example, the second precursor material 230 can be selected as a material that exhibits capillary properties in the liquid phase (referred to herein as a "capillary liquid"). Some example precursors exhibiting capillary properties are described below. In some embodiments, the pressure and / or temperature of the deposition chamber can be controlled to promote the condensation or adsorption of the second precursor material 230 as a liquid onto a surface (e.g., on the reaction product 221). Some example process conditions are also described below. In some embodiments, a higher pressure and / or lower temperature within the deposition chamber can promote the condensation of the second precursor material 230 on the surface. The pressure and / or temperature used during the process can depend on the properties of the second precursor material 230 (e.g., melting point, boiling point, etc.). For example, a precursor with a higher melting point can condense at a lower temperature than a precursor with a lower melting point, or a precursor with a lower boiling point can condense at a higher temperature than a precursor with a higher boiling point.

[0043] like Figure 4As shown, the second precursor material 230 introduced into the deposition chamber can condense on the surface as a liquid. As a capillary liquid, this second precursor material 230 in the liquid phase can be pulled toward the surface by capillary forces. Specifically, the second precursor material 230 in the liquid phase can be pulled into the groove by capillary forces from the sidewalls surrounding the groove. For example, the second precursor material 230 in the liquid phase can be pulled toward the bottom of the groove 201 by capillary forces from the sidewalls of the feature 202 and the bottom surface of the substrate 203. In this way, the capillary liquid precursor can be more easily formed on some surfaces in narrow or confined areas than, for example, precursors in the gas phase. This can promote the growth of the desired material on surfaces that are difficult for gaseous precursors to reach, such as surfaces near the groove bottom, surfaces within grooves with high aspect ratios, and surfaces within deep openings. The capillary action allows the second precursor material 230 to react with the first reaction product 221 on these surfaces to form material 240. In this way, the capillary action of the precursor during the ALD process can promote the growth of material from the bottom of the trench as well as from the sidewalls of the trench. This can allow the material to grow in the trench without forming seams or voids.

[0044] Additionally, the second precursor material 230 that condenses on the upper or top surface of the structure 210 can react with the first reaction product 221 to form material 240 on those surfaces. In this way, material 240 can be conformally deposited on the upper or top surface of the structure in addition to the surfaces within the trenches. Thus, the use of capillary assisted ALD as described herein can form the desired material over all surfaces of the structure and form the material with less likelihood of incomplete coverage of the surface. In some cases, due to capillary condensation effects, condensation of the second precursor material 230 in relatively confined areas (e.g., near the bottom of the trench 201) can be promoted, where the liquid may be more likely to condense in an area closer to relatively more surfaces.

[0045] like Figure 4 As shown, due to the capillary action, the second precursor material 230 in the liquid phase is gathered near the bottom of the groove 201. A relatively large amount of liquid second precursor material 230 generated by the capillary action is formed in the groove 201. Figure 4 2. The second precursor material 230A is shown in FIG. 2. An extended meniscus or capillary bridge may be formed near the bottom of the trench 201 between the features 202 formed by the liquid second precursor material 230A. The meniscus or bridge may have a Figure 4 The concave surface shown may also have a flat surface or a convex surface.

[0046] After the second precursor material 230 has reacted to form the material 240, the deposition chamber may then be purged of excess second precursor material 230 or other reaction products. This corresponds to Figure 11The second purge 254B of step 2 is shown. The purge can be performed before or after the self-limiting reaction to form the monolayer of material 240 is completed. For example, the purge can be performed by flowing a purge gas such as nitrogen, argon, xenon, etc. into the deposition chamber.

[0047] After purging the deposition chamber in second purge 254B, step 2 of the ALD cycle is complete, and the entire ALD cycle for forming material 240 is complete. Figure 5 The resulting layer of material 240 is shown as material layer 240A. Figure 2-4 and Figure 11 The ALD cycle is repeated until the desired thickness of material 240 has been formed, or until sufficient gap fill (eg, gap fill of trench 201) is achieved. For example, Figure 6 The first precursor material 220 is shown introduced into the deposition chamber where it reacts with the material layer 240A to form a first reaction product 221, which corresponds to a first precursor flow 252A. A first purge 252B may then be performed. Figure 7 In the deposition chamber, the second precursor 230 is introduced into the deposition chamber, wherein the second precursor 230 condenses on the surface of the first reaction product 221 and reacts therewith to form another layer of material 240 as a material layer 240B, as shown in FIG. Figure 7 shown.

[0048] Figure 8-9 An embodiment is shown in which the second purge 254B after forming the material layer 240B does not completely remove the unreacted second precursor material 230 from the deposition chamber according to some embodiments. For example, by reducing the rate or duration of the purge gas flow, the purge can be controlled to be incomplete. In addition, the pressure and / or temperature of the deposition chamber can be controlled to maintain the presence of the condensed precursor material. As an illustrative example, in Figure 7 A capillary-assisted ALD process using incomplete purge is shown in the context of what happens next, but the technique can be used with any other embodiment, process, or technique of a capillary-assisted ALD process, such as the capillary-assisted ALD process described herein. In some embodiments, one or more incomplete purges are performed in each ALD cycle, but in other embodiments, all purges are complete or nearly complete.

[0049] refer to Figure 8 , performing an incomplete second purge 254B after the second precursor stream 254A can keep the remaining portion of the second precursor material 230 in the liquid phase as residual liquid 230, as shown in FIG. Figure 8As shown. The residual liquid 230 may be preferentially maintained in relatively narrow or confined areas, such as near the bottom of the trench 201, due to capillary forces. In some cases, residual liquid 230 may be present during the subsequent first precursor flow 252A. The first precursor material 220 can react with the second precursor material 230 in the residual liquid 230B, and because the additional second precursor material 230 present in the residual liquid 230B is capable of reacting with the first reaction product 221, more than one monolayer of material 240 is formed in these areas. In this way, the growth of material 240 may be greater in areas where the residual liquid 230B is present, such as near the bottom of the trench 201. Therefore, during a single ALD cycle, the material 240 formed in the trench 201 grows faster in a "bottom-up" direction from the bottom of the trench 201 than from the sidewalls of the trench 201. This is as shown in FIG. Figure 9 2 , wherein a subsequently formed material layer 240C is thicker near the bottom of the trench 201 than the material layer 240C on the sidewalls of the trench 201. Growth of the material 240 in such a "bottom-up" direction can improve gap filling of narrow or high aspect ratio grooves and can also reduce the chance of seams or voids forming within the material 240 during growth.

[0050] Figure 10 The structure 210 is shown after multiple ALD cycles have completely filled the trench 201 with material 240, according to some embodiments. As previously mentioned, the capillary-assisted ALD process described herein can be used as a seamless gapfill deposition process. Furthermore, the capillary-assisted ALD process described herein can also maintain conformal deposition on the top surface and top corners of the structure, thereby allowing for improved material deposition, for example, in a partial gapfill process step.

[0051] In some embodiments, the capillary-assisted ALD processes described herein can be used to deposit materials (e.g., material 240) comprising dielectric materials such as nitrides, oxides, metal oxides, and the like. One or more precursors to the material can be selected to be capillary liquids to facilitate growth within narrow or high-aspect-ratio trenches. For example, in some embodiments, one of the precursors to the material can be water (H2O), which exhibits capillary behavior in the liquid phase. In some embodiments, a particular precursor can be selected to have a higher boiling point and / or lower melting point than other precursors, which can allow the precursor to condense at a lower temperature. For example, a precursor with a longer carbon chain may have a higher boiling point than a similar precursor with a shorter carbon chain. Example precursors that include a carbon chain include trimethylaluminum (Al(CH3)3) (also referred to as "TMA"), diethylzinc (C2H5)2Zn, H2Si[N(C2H5)2]2, tris(dimethylamino)silane (Me2N)3SiH, or various other suitable precursors.

[0052] As an example, the capillary assisted ALD process described herein can be used to deposit aluminum oxide (Al2O3), which can be formed using TMA and water (e.g., water vapor) as precursors. For example, material 240 can be formed from aluminum oxide deposited using TMA as the first precursor material 220 and water as the second precursor material 230. In some embodiments where the deposited material is aluminum oxide, TMA can flow into the deposition chamber at a flow rate between about 50 sccm and about 300 sccm, wherein the carrier gas flow rate is between about 50 sccm and about 1000 sccm. The time for TMA to flow can be between about 0.1 seconds and about 10 seconds. In addition, during the flow of TMA, the deposition chamber can be maintained at a pressure between about 0.5 Torr and about 50 Torr and at a temperature between about 30°C and about 300°C. In some embodiments, water can flow into the deposition chamber at a flow rate between about 50 sccm and about 600 sccm, wherein the carrier gas flow rate is between about 50 sccm and about 1000 sccm. The time for water to flow can be between about 0.1 seconds and about 10 seconds. Furthermore, during the water flow, the deposition chamber can be maintained at a pressure between about 0.5 Torr and about 50 Torr and a temperature between about 30° C. and about 300° C. Using these temperatures and / or pressures can allow water introduced into the deposition chamber to condense on surfaces, such as Figure 4 As stated.

[0053] In other embodiments, the material deposited using the capillary-assisted ALD process can be another material for which water is used as a precursor. For example, the capillary-assisted ALD process can deposit materials such as lanthanum oxide (La2O3) formed using La(iPrCp)2(iPr-amd) and water as precursors, hafnium oxide (HfO2) formed using HfCl4 and / or CpHf(NMe2)3 and water as precursors, or zirconium oxide (ZrO2) formed using ZrCl4 and / or CpZr(NMe2)3 and water as precursors. In some embodiments, these or other precursors can be used at a process pressure between about 0.5 Torr and about 6 Torr or at a process temperature between about 250°C and about 350°C, although other process conditions may be used. Other materials, precursors, or process conditions are possible.

[0054] Other materials can be formed from other precursors by a capillary assisted ALD process, such as SiN formed using SiH2Cl2 and / or SiH2I2 and NH3 as precursors. In some cases, NH3 exhibits capillary behavior in the liquid phase. In some embodiments, these or other precursors can be used at a process pressure between about 0.5 Torr and about 6 Torr, at a process temperature between about 150°C and about 600°C, or at a precursor flow between about 10 sccm and about 2000 sccm, but other process conditions may be used. The capillary assisted ALD process may include a thermal ALD process and / or a plasma ALD process. As will be appreciated by one of ordinary skill in the art, these materials, precursors, and process conditions are for illustration only, as any suitable precursor or process condition may be used to deposit materials using a capillary assisted ALD process while remaining within the scope of the embodiments.

[0055] Figures 12 to 28 1 shows an intermediate stage in a process of forming a FinFET device 310 using a capillary assisted ALD process as described herein, according to some embodiments. Specifically, Figure 12-28 An embodiment is described in which a dielectric hard mask material 380 ′ is deposited within the recess 378 using a capillary assisted ALD process as part of forming the FinFET device 310 .

[0056] exist Figure 12 In the embodiment, a substrate 320 is provided. The substrate 320 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., using p-type or n-type dopants) or undoped. The semiconductor substrate 320 may be part of a wafer 310 (e.g., a silicon wafer). Typically, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates such as multilayer or gradient substrates may also be used. In some embodiments, the semiconductor material of the semiconductor substrate 320 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof.

[0057] Further references Figure 12, forming a well region 322 in the substrate 320. According to some embodiments of the present disclosure, the well region 322 is an n-type well region formed by injecting n-type impurities (which may be phosphorus, arsenic, antimony, etc.) into the substrate 320. According to other embodiments of the present disclosure, the well region 322 is a p-type well region formed by injecting p-type impurities (which may be boron, indium, etc.) into the substrate 320. The resulting well region 322 may extend to the top surface of the substrate 320. The n-type or p-type impurity concentration may be equal to or less than 10 18 cm -3 , for example, at about 10 17 cm -3 to about 10 18 cm -3 within the range between.

[0058] Reference Figure 13 , the isolation region 324 is formed to extend from the top surface of the substrate 320 into the substrate 320. The isolation region 324 is alternatively referred to as a shallow trench isolation (STI) region hereinafter. The portion of the substrate 320 between adjacent STI regions 324 is referred to as a semiconductor strip 326. In order to form the STI region 324, a pad oxide layer 328 and a hard mask layer 330 are formed on the semiconductor substrate 320 and then patterned. The pad oxide layer 328 can be a thin film formed of silicon oxide. According to some embodiments of the present disclosure, the pad oxide layer 328 is formed in a thermal oxidation process, in which the top surface layer of the semiconductor substrate 320 is oxidized. The pad oxide layer 328 acts as an adhesion layer between the semiconductor substrate 320 and the hard mask layer 330. The pad oxide layer 328 can also act as an etch stop layer for etching the hard mask layer 330. According to some embodiments of the present disclosure, the hard mask layer 330 is formed of silicon nitride, for example, using low pressure chemical vapor deposition (LPCVD). According to other embodiments of the present disclosure, the hard mask layer 330 is formed by thermal nitridation of silicon or plasma enhanced chemical vapor deposition (PECVD). A photoresist (not shown) is formed on the hard mask layer 330 and then patterned. The patterned photoresist is then used as an etching mask to pattern the hard mask layer 330 to form a Figure 13 A hard mask 330 is shown.

[0059] Next, patterned hard mask layer 330 is used as an etch mask to etch pad oxide layer 328 and substrate 320, and the resulting trenches in substrate 320 are then filled with dielectric material(s). A planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, is performed to remove excess portions of the dielectric material, and the remaining portions of the dielectric material(s) are STI regions 324. STI regions 324 may include a liner dielectric (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of substrate 320. The liner dielectric may also be a deposited silicon oxide layer, silicon nitride layer, or the like, formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). STI regions 324 may also include a dielectric material located above the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, or the like. According to some embodiments, the dielectric material located above the liner dielectric may include silicon oxide.

[0060] The top surface of hard mask 330 and the top surface of STI regions 324 may be substantially flush with each other. Semiconductor strips 326 are located between adjacent STI regions 324. According to some embodiments of the present disclosure, semiconductor strips 326 are part of the original substrate 320, and therefore, the material of semiconductor strips 326 is the same as the material of substrate 320. According to alternative embodiments of the present disclosure, semiconductor strips 326 are replacement strips formed by etching the portion of substrate 320 between STI regions 324 to form grooves, and performing epitaxy to re-grow another semiconductor material in the grooves. Therefore, semiconductor strips 326 are formed of a semiconductor material different from the semiconductor material of substrate 320. According to some embodiments, semiconductor strips 326 are formed of silicon germanium, silicon carbon, or a III-V compound semiconductor material.

[0061] refer to Figure 14 , STI region 324 is recessed so that the top portion of semiconductor strip 326 protrudes above top surface 324A of the remaining portion of STI region 324 to form protruding fin 336. Etching can be performed using a dry etching process, using, for example, HF and NH3 as etching gases. During the etching process, plasma can be generated. Argon gas can also be included. According to an alternative embodiment of the present disclosure, recessing STI region 324 is performed using a wet etching process. For example, the etching chemical can include HF.

[0062] In the embodiments shown above, the fins can be patterned by any suitable method. For example, the fins can be patterned using one or more photolithography processes (including double patterning or multi-patterning processes). Typically, the double patterning or multi-patterning process combines photolithography and self-alignment processes so that the pattern is created to have a spacing smaller than that obtainable using a single direct photolithography process, for example. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a photolithography process. A spacer is formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacer or mandrel can then be used to pattern the fins.

[0063] refer to Figure 15 , the dummy gate stack 338 is formed to extend over the top surface and sidewalls of the (protruding) fin 336. The dummy gate stack 338 may include a dummy gate dielectric 340 and a dummy gate electrode 342 located above the dummy gate dielectric 340. For example, polysilicon can be used to form the dummy gate electrode 342, and other materials may also be used. Each of the dummy gate stacks 338 may also include one (or more) hard mask layers 344 located above the dummy gate electrode 342. The hard mask layer 344 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or a multilayer thereof. The dummy gate stack 338 may span a single or multiple protruding fins 336 and / or STI regions 324. The dummy gate stack 338 also has a longitudinal direction that is perpendicular to the longitudinal direction of the protruding fin 336.

[0064] Next, gate spacers 346 are formed on the sidewalls of the dummy gate stack 338. According to some embodiments of the present disclosure, the gate spacers 346 are formed of one or more dielectric materials such as silicon nitride, silicon carbonitride, etc., and can have a single-layer structure or a multi-layer structure including multiple dielectric layers.

[0065] An etching process is then performed to etch the portions of the protruding fins 336 that are not covered by the dummy gate stack 338 and the gate spacers 346, thereby producing Figure 16 The structure shown. The etching can be anisotropic, and thus the portion of the fin 336 directly below the dummy gate stack 338 and the gate spacer 346 is protected and not etched. According to some embodiments, the top surface of the recessed semiconductor strip 326 can be lower than the top surface 324A of the STI region 324. Accordingly, a recess 350 is formed. The recess 350 includes portions on opposite sides of the dummy gate stack 338 and a portion between the remaining portions of the protruding fin 336.

[0066] Next, epitaxial regions (source / drain regions) 354 are formed by selectively growing (by epitaxy) semiconductor material in the recesses 350, thereby producing Figure 17 structure in. Depending on whether the FinFET produced is a p-type FinFET or an n-type FinFET, p-type or n-type impurities can be in-situ doped as the epitaxy proceeds. For example, when the FinFET produced is a p-type FinFET, silicon germanium boron (SiGeB) or silicon boron (SiB) can be grown. Conversely, when the FinFET produced is an n-type FinFET, silicon phosphorus (SiP) or silicon carbon phosphorus (SiCP) can be grown. According to an alternative embodiment of the present disclosure, the epitaxial region 354 contains a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, multilayers thereof, etc. After filling the groove 350 with the epitaxial region 354, further epitaxial growth of the epitaxial region 354 causes the epitaxial region 354 to expand horizontally, and a small facet can be formed. Further growth of the epitaxial region 354 can also cause adjacent epitaxial regions 354 to merge with each other. A gap (air gap) 356 can be generated. According to some embodiments of the present disclosure, the formation of the epitaxial regions 354 may be completed when the top surface of the epitaxial regions 354 is still wavy, or when the top surface of the merged epitaxial regions 354 has become substantially flat, by Figure 17 This is achieved by further growth on the epitaxial region 354 shown.

[0067] After the epitaxial growth process, the epitaxial region 354 may be further implanted with p-type or n-type impurities to form source and drain regions, which are also indicated by reference numeral 354. According to an alternative embodiment of the present disclosure, when the epitaxial region 354 is in-situ doped with p-type or n-type impurities during epitaxy, the implantation step is skipped.

[0068] Figure 18 A perspective view of the structure after forming a contact etch stop layer (CESL) 358 and an interlayer dielectric (ILD) 360 is shown. CESL 358 may be formed of silicon oxide, silicon nitride, silicon carbonitride, or the like, and may be formed using CVD, ALD, or the like. ILD 360 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or another deposition method. ILD 360 may be formed of an oxygen-containing dielectric material, which may be a silicon oxide-based material such as tetraethyl orthosilicate (TEOS) oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like. A planarization process such as a CMP process or a mechanical grinding process may be performed to make the top surfaces of ILD 360, dummy gate stack 338, and gate spacer 346 flush with each other.

[0069] Figure 19 Shown Figure 18, which shows the dummy gate stack 338. Next, the dummy gate stack 338 including the hard mask layer 344, the dummy gate electrode 342 and the dummy gate dielectric 340 is etched to form trenches 362 between the gate spacers 346, as shown in FIG. Figure 20 As shown, the top surface and sidewalls of the protruding fin 336 are exposed to the trench 362 .

[0070] Next, if Figure 21 and Figure 22 As shown, a replacement gate stack 372 is formed in the trench 362 ( Figure 20 ). Figure 22 Shown Figure 21 The replacement gate stack 372 includes a gate dielectric 368 and a corresponding gate electrode 370 .

[0071] According to some embodiments of the present disclosure, gate dielectric 368 includes an interfacial layer (IL) 364 as its lower portion. IL 364 is formed on the exposed surface of protruding fin 336. IL 364 may include an oxide layer, such as a silicon oxide layer, formed by thermal oxidation, chemical oxidation, or deposition of protruding fin 336. Gate dielectric 368 may also include a high-k dielectric layer 366 formed above IL 364. High-k dielectric layer 366 includes a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, etc. The dielectric constant (k value) of the high-k dielectric material is greater than 3.9, and may be higher than approximately 7.0, and sometimes even as high as 21.0 or higher. High-k dielectric layer 366 covers and may contact IL 364. High-k dielectric layer 366 is formed as a conformal layer and extends over the sidewalls of protruding fin 336 and the top surface and sidewalls of gate spacer 346. According to some embodiments of the present disclosure, the high-k dielectric layer 366 is formed using ALD, CVD, PECVD, molecular beam deposition (MBD), or the like.

[0072] Further references Figure 22 , a gate electrode 370 is formed on the gate dielectric 368. The gate electrode 370 may include a plurality of metal-containing layers 374, the plurality of metal-containing layers 374 may be formed as a conformal layer, and a fill metal region 376 fills the remaining portion of the trench not filled by the plurality of metal-containing layers 374. The metal-containing layer 374 may include a barrier layer, a work function layer on the barrier layer, and one or more metal capping layers on the work function layer.

[0073] Figure 23The gate stack 372 and gate spacer 346 are shown recessed to form a recess 378 in accordance with some embodiments. The recess 378 can be formed, for example, using one or more anisotropic etching processes. For example, the etching process can be performed using one or more etching gases that have a high etch selectivity for the material of the gate stack 372 relative to the material of the CESL 358 or the ILD 360, such that the CESL 358 or the ILD 360 is not significantly etched or damaged. Figure 23 Recesses 378 are shown where the top surfaces of the gate spacers 346 are higher than the top surface of the gate stack 372, but in other embodiments, the top surfaces of the gate spacers 346 are flush with the top surface of the gate stack 372. In other embodiments, the gate spacers 346 are not recessed.

[0074] exist Figure 24 In some embodiments, a hard mask material 380' is deposited over the structure and within the recess 378 using a capillary assisted ALD process. The capillary assisted ALD process may be similar to the capillary assisted ALD process described above. The hard mask material 380' is used to form a hard mask 380 covering the gate stack 372, such as Figure 24 As shown. In some embodiments, the hard mask material 380' can be a metal oxide (e.g., aluminum oxide) deposited by a capillary assisted ALD process using the process parameters and precursors previously described. In some cases, aluminum oxide can have a high etch selectivity relative to the materials of other features (e.g., CESL 358 or ILD 360). For example, the higher etch selectivity of the hard mask material 380' of aluminum oxide relative to the CESL 358 or ILD 360d formed of silicon oxide, silicon nitride, etc. can allow for the subsequent formation of gate contact openings 386 (see FIG. Figure 27 ) through the hard mask 380 (see Figure 25 ) is formed while reducing the risk of etching damage or etching loss or in forming the gate contact portion 388 (see Figure 28 ) during the deposition process. In this manner, the higher etch selectivity of the hard mask 380 formed of a metal oxide can allow the gate contact 388 to be formed as a self-aligned contact. Furthermore, using a capillary-assisted ALD process to deposit the hard mask material 380′ can allow the hard mask 380 to be formed with reduced risk of seams or voids, and can also allow for improved gap filling of the recess 378 due to the capillary forces described previously. In other embodiments, other materials, process parameters, or precursors can be used to form the hard mask material 380′.

[0075] Figure 25A perspective view of the formation of a hard mask 380 according to some embodiments is shown. After the hard mask material 380' has been deposited, the hard mask material 380' can be planarized to remove excess material, thereby forming the hard mask 380. For example, the hard mask material 380' can be planarized using a CMP or grinding process to remove excess material. The ILD 360 can be exposed by the planarization process and can also be planarized.

[0076] Figure 24 A cross-sectional view (along AA) of the formation of an etch stop layer 382 and a hard mask 384 is shown according to some embodiments. The etch stop layer 382 and the hard mask 384 may be used to form and maintain a gate contact opening 386 (see FIG. Figure 27 ). Etch stop layer 382 may be formed of oxide, nitride, carbide, oxycarbide, or the like. Hard mask 384 may be formed of titanium nitride, boron nitride, oxide, nitride, or the like. In other embodiments, etch stop layer 382 is not formed. In other embodiments, neither etch stop layer 382 nor hard mask 384 is formed, and thus gate contact opening 386 is formed without using etch stop layer 382 or hard mask 384.

[0077] Figure 27 The formation of a gate contact opening 386 is shown in accordance with some embodiments. The gate contact opening 386 is formed to expose the gate stack 372. In some embodiments, a photoresist (not shown) is formed over the hard mask 384 and patterned, and then the hard mask 384 and the etch stop layer 382 are etched using the patterned photoresist as an etch mask. Portions of the hard mask 384 and the etch stop layer 382 can be etched in such a manner that an opening 386 is formed in the hard mask 384 and the etch stop layer 382 that expose the hard mask 380. Next, the hard mask 380 can be etched to extend the gate contact opening 386 through the hard mask 380 and expose the gate stack 372. For example, the gate contact opening 386 can be etched using one or more anisotropic gate etching processes. The anisotropic etching process can include an etching process that has a high selectivity of the material of the hard mask 380 relative to the material of the gate spacers 346.

[0078] Next, in Figure 28In some embodiments, a gate contact 388 is formed in the gate contact opening 386. The gate contact 388 can be formed by filling the gate contact opening 386 with a conductive material. The conductive material may include a diffusion barrier layer, which may be formed of titanium nitride, tantalum nitride, titanium, tantalum, etc. and a conductive filling material (e.g., copper, tungsten, cobalt, aluminum, ruthenium, etc.) or a combination thereof. Other conductive materials may also be used. The conductive material may be formed on the upper surface of the hard mask 384. After the conductive material is formed, a planarization process may be performed to remove excess conductive material. In some embodiments, the planarization process may also remove the hard mask 384 and the etch stop layer 382, ​​such as Figure 28 shown.

[0079] Although not explicitly shown, it will be readily understood by those skilled in the art that Figure 28 For example, source / drain contacts may be formed to contact source / drain regions 54 , or various intermetallic dielectrics (IMDs) and their corresponding metallizations may be formed over ILD 360 .

[0080] Although the hard mask material 380' is described as being formed using the capillary-assisted ALD process described herein, it should be noted that the capillary-assisted ALD process described herein can be used to deposit materials in other process steps used to form FinFETs, other structures, or other devices. Thus, the capillary-assisted ALD process described herein can be used in various processing steps for depositing gap fill materials, and the technology is not limited to the examples and embodiments described herein.

[0081] Embodiments herein achieve advantages. Using the capillary assisted ALD technique described herein, materials can be deposited in narrow or confined areas without forming defects such as seams or voids. The capillary assisted ALD technique allows for simultaneous bottom-up deposition (e.g., in narrow or confined areas) and conformal deposition (e.g., on top surfaces or corners), which can allow for more efficient gap filling while improving deposition quality. The technique described herein is compatible with both thermal ALD and plasma ALD. The technique described herein also allows for the bottom-up deposition of materials without the use of inhibitors or other additives, and therefore can avoid defects caused by the presence of inhibitors or other additives. The capillary assisted ALD process described herein also allows for the deposition of a variety of materials for a variety of applications, including materials that are incompatible with other deposition processes, such as metal oxides or materials using water as a precursor. For example, the technique described herein can be used in processes including, but not limited to, FinFET formation, gate-around (GAA) or nanostructured FET formation, front-end-of-line (FEOL) processes, or back-end-of-line (BEOL) processes.

[0082] The disclosed FinFET embodiments may also be applied to nanostructured devices, such as nanostructured (e.g., nanosheets, nanowires, gate wraparounds, etc.) field effect transistors (NSFETs). In NSFET embodiments, the fins are formed by patterning a stack of alternating layers of channel layers and sacrificial layers. A dummy gate stack and epitaxial source / drain regions are formed in a manner similar to that described above. After removing the dummy gate stack, the sacrificial layer may be partially or completely removed in the channel region. A replacement gate structure is formed in a manner similar to that described above and will partially or completely wrap around the channel layer in the channel region of the NSFET device. The ILD and contacts to the gate structure and source / drain are formed in a manner similar to that described above. Nanostructured devices may be formed as disclosed in U.S. Patent Application Publication No. 2016 / 0365414, the entire contents of which are incorporated herein by reference.

[0083] According to an embodiment, a method includes placing a semiconductor substrate in a deposition chamber, wherein the semiconductor substrate includes a trench; and performing an atomic layer deposition (ALD) process to deposit a dielectric material in the trench, the method comprising: flowing a first precursor of the dielectric material into the deposition chamber as a vapor phase; flowing a second precursor of the dielectric material into the deposition chamber as a vapor phase; and controlling the pressure and temperature within the deposition chamber such that the second precursor condenses as a liquid phase of the second precursor on a surface within the trench, wherein the liquid phase of the second precursor exhibits a capillary effect. In an embodiment, the liquid phase of the second precursor forms a thicker layer on a surface within the trench near the bottom of the trench than on a surface within the trench near the top of the trench. In an embodiment, the first precursor of the dielectric material condenses as a liquid phase of the first precursor on the surface within the trench, and the liquid phase of the first precursor exhibits a capillary effect. In an embodiment, the dielectric material fills the trench, and the filling of the trench by the dielectric material is seamless. In an embodiment, the dielectric material is aluminum oxide. In an embodiment, the first precursor is trimethylaluminum (TMA). In an embodiment, the second precursor is water. In an embodiment, when the second precursor is flowed into the deposition chamber, the pressure within the deposition chamber is controlled between 0.5 Torr and 50 Torr, and the temperature within the deposition chamber is controlled between 30°C and 300°C.

[0084] According to an embodiment, a method includes forming a semiconductor structure including a trench in a substrate; and depositing a dielectric material in the trench using an atomic layer deposition (ALD) process performed using a process chamber, wherein the ALD process includes an ALD cycle including exposing the semiconductor structure to a first precursor; and exposing the semiconductor structure to a second precursor, wherein the second precursor condenses on a surface of the semiconductor structure as a liquid having a capillary effect; wherein a vertical deposition rate of the dielectric material from a bottom surface of the trench is greater than a lateral deposition rate of the dielectric material from a sidewall of the trench. In an embodiment, the dielectric material includes silicon nitride, the first precursor includes SiH2Cl2 or SiH2I2, and the second precursor is ammonia (NH3). In an embodiment, the ALD process includes flowing the first precursor or the second precursor into the process chamber at a flow rate between 10 sccm and 2000 sccm using a process pressure between 0.5 Torr and 6 Torr and a process temperature between 150°C and 600°C. In an embodiment, the dielectric material comprises zirconium oxide, the first precursor comprises ZrCl4 or CpZr(NMe2)3, and the second precursor is water. In an embodiment, the ALD process comprises using a process pressure between 0.5 Torr and 6 Torr and using a process temperature between 250°C and 350°C. In an embodiment, the dielectric material comprises aluminum oxide, the first precursor is trimethylaluminum (TMA), and the second precursor is water. In an embodiment, the ALD process is inhibitor-free. In an embodiment, the ALD process deposits the dielectric material to fill the trench, and the dielectric material is conformally deposited on the top surface of the substrate, wherein the dielectric material filling the trench is seamless.

[0085] According to an embodiment, a semiconductor device includes: a fin protruding from a substrate; an isolation region surrounding the fin; a gate stack located above the fin; source / drain regions adjacent to the gate stack in the fin; an interlayer dielectric (ILD) located above the source / drain regions, wherein a top surface of the gate stack is recessed from a top surface of the ILD; a hard mask covering the gate stack, wherein a top surface of the hard mask is flush with a top surface of the ILD, wherein the hard mask has no seam, wherein the hard mask has a height:width aspect ratio in a range between 1:3 and 1:25; and wherein the hard mask comprises a metal oxide; and a conductive feature extending through the hard mask to contact the gate stack. In an embodiment, the metal oxide is aluminum oxide, zirconium oxide, or hafnium oxide. In an embodiment, the semiconductor device includes gate spacers along sidewalls of the gate stack, wherein the hard mask covers the gate spacers. In an embodiment, the hard mask has a minimum width in a range between 3 nm and 10 nm.

[0086] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0087] Example 1 is a method for forming a semiconductor device, comprising: placing a semiconductor substrate in a deposition chamber, wherein the semiconductor substrate includes a groove; and performing an atomic layer deposition (ALD) process to deposit a dielectric material in the groove, comprising: allowing a first precursor of the dielectric material to flow into the deposition chamber as a gas phase; allowing a second precursor of the dielectric material to flow into the deposition chamber as a gas phase; and controlling the pressure and temperature in the deposition chamber so that the second precursor as a liquid phase of the second precursor condenses on a surface within the groove, wherein the liquid phase of the second precursor has a capillary phenomenon.

[0088] Example 2 is the method of Example 1, wherein the liquid phase of the second precursor forms a thicker layer on a surface within the trench near a bottom of the trench than on a surface within the trench near a top of the trench.

[0089] Example 3 is the method of Example 1, wherein the first precursor of the dielectric material condenses on the surface within the trench as a liquid phase of the first precursor, and wherein the liquid phase of the first precursor has a capillary phenomenon.

[0090] Example 4 is the method of Example 1, wherein the dielectric material fills the trench, and wherein the dielectric material filling the trench is seamless.

[0091] Example 5 is the method of Example 1, wherein the dielectric material is aluminum oxide.

[0092] Example 6 is the method of Example 1, wherein the first precursor is trimethylaluminum (TMA).

[0093] Example 7 is the method of Example 1, wherein the second precursor is water.

[0094] Example 8 is the method of Example 7, wherein when the second precursor is flowed into the deposition chamber, the pressure within the deposition chamber is controlled between 0.5 Torr and 50 Torr, and wherein the temperature within the deposition chamber is controlled between 30°C and 300°C.

[0095] Example 9 is a method for forming a semiconductor device, comprising: forming a semiconductor structure including a trench in a substrate; and depositing a dielectric material in the trench using an atomic layer deposition (ALD) process performed using a process chamber, wherein the ALD process includes an ALD cycle, and the ALD cycle includes: exposing the semiconductor structure to a first precursor; and exposing the semiconductor structure to a second precursor, wherein the second precursor condenses on the surface of the semiconductor structure as a liquid with capillary phenomenon; wherein a vertical deposition rate of the dielectric material from the bottom surface of the trench is greater than a lateral deposition rate of the dielectric material from the sidewalls of the trench.

[0096] Example 10 is the method of Example 9, wherein the dielectric material comprises silicon nitride, wherein the first precursor comprises SiH2Cl2 or SiH2I2, and wherein the second precursor is ammonia (NH3).

[0097] Example 11 is the method described in Example 10, wherein the ALD process includes: using a process pressure between 0.5 Torr and 6 Torr and a process temperature between 150°C and 600°C, so that the first precursor or the second precursor flows into the process chamber at a flow rate between 10 sccm and 2000 sccm.

[0098] Example 12 is the method of Example 9, wherein the dielectric material comprises zirconium oxide, wherein the first precursor comprises ZrCl4 or CpZr(NMe2)3, and wherein the second precursor is water.

[0099] Example 13 is the method of Example 12, wherein the ALD process includes using a process pressure between 0.5 Torr and 6 Torr and using a process temperature between 250° C. and 350° C.

[0100] Example 14 is the method of Example 9, wherein the dielectric material comprises aluminum oxide, wherein the first precursor is trimethylaluminum (TMA), and wherein the second precursor is water.

[0101] Example 15 is the method of Example 9, wherein the ALD process is inhibitor-free.

[0102] Example 16 is the method of Example 9, wherein the ALD process deposits a dielectric material to fill the trench, and the dielectric material is conformally deposited on the top surface of the substrate, wherein the dielectric material fills the trench seamlessly.

[0103] Example 17 is a semiconductor device comprising: a fin protruding from a substrate; an isolation region surrounding the fin; a gate stack located above the fin; a source / drain region adjacent to the gate stack in the fin; an interlayer dielectric (ILD) located above the source / drain region, wherein a top surface of the gate stack is recessed from a top surface of the ILD; a hard mask covering the gate stack, wherein a top surface of the hard mask is flush with a top surface of the ILD, wherein the hard mask has no seams, wherein the hard mask has a height:width aspect ratio in a range between 1:3 and 1:25; and wherein the hard mask comprises a metal oxide; and a conductive feature extending through the hard mask to contact the gate stack.

[0104] Example 18 is the semiconductor device of 17, wherein the metal oxide is aluminum oxide, zirconium oxide, or hafnium oxide.

[0105] Example 19 is the semiconductor device of Example 17, further comprising a gate spacer along a sidewall of the gate stack, wherein the hard mask covers the gate spacer.

[0106] Example 20 is the semiconductor device of Example 17, wherein the hard mask has a minimum width in a range between 3 nm and 10 nm.

Claims

1. A method for forming a semiconductor device, comprising: placing a semiconductor substrate in a deposition chamber, wherein the semiconductor substrate comprises a trench; and performing an atomic layer deposition (ALD) process to deposit a dielectric material in the trench, comprising: flowing a first precursor of the dielectric material into the deposition chamber as a vapor phase; flowing a second precursor of the dielectric material into the deposition chamber as a vapor phase; controlling the pressure and temperature in the deposition chamber so that the second precursor as a liquid phase of the second precursor condenses on the surface in the groove, wherein the liquid phase of the second precursor has a capillary phenomenon; and Unreacted second precursor is not completely purged, such that a portion of the unreacted second precursor remains in the liquid phase near the bottom of the trench.

2. The method according to claim 1, wherein The liquid phase of the second precursor forms a thicker layer on surfaces within the trench near a bottom of the trench than on surfaces within the trench near a top of the trench.

3. The method according to claim 1, wherein The first precursor of the dielectric material condenses on the surface within the trench as a liquid phase of the first precursor, and wherein the liquid phase of the first precursor has a capillary phenomenon.

4. The method according to claim 1, wherein The dielectric material fills the trench, and wherein the dielectric material filling the trench is seamless.

5. The method according to claim 1, wherein The dielectric material is aluminum oxide.

6. The method according to claim 1, wherein The first precursor is trimethylaluminum (TMA).

7. The method according to claim 1, wherein The second precursor is water.

8. The method according to claim 7, wherein: When the second precursor is flowed into the deposition chamber, a pressure within the deposition chamber is controlled between 0.5 Torr and 50 Torr, and wherein a temperature within the deposition chamber is controlled between 30° C. and 300° C.

9. A method for forming a semiconductor device, comprising: forming a semiconductor structure including a trench in a substrate; as well as Depositing a dielectric material in the trench using an atomic layer deposition (ALD) process performed using a process chamber, wherein the atomic layer deposition (ALD) process includes an ALD cycle, the ALD cycle including: exposing the semiconductor structure to a first precursor; and exposing the semiconductor structure to a second precursor, wherein the second precursor condenses on the surface of the semiconductor structure as a liquid with capillary behavior; incompletely purging unreacted second precursor such that a portion of the unreacted second precursor remains in a liquid phase near a bottom of the trench; The vertical deposition rate of the dielectric material from the bottom surface of the trench is greater than the lateral deposition rate of the dielectric material from the sidewall of the trench.

10. The method according to claim 9, wherein: The dielectric material comprises silicon nitride, wherein the first precursor comprises SiH2Cl2 or SiH2I2, and wherein the second precursor is ammonia (NH3).

11. The method according to claim 10, wherein: The atomic layer deposition (ALD) process includes: using a process pressure between 0.5 Torr and 6 Torr and a process temperature between 150° C. and 600° C., and flowing the first precursor or the second precursor into the process chamber at a flow rate between 10 sccm and 2000 sccm.

12. The method according to claim 9, wherein The dielectric material comprises zirconium oxide, wherein the first precursor comprises ZrCl 4 or CpZr(NMe 2 ) 3 , and wherein the second precursor is water.

13. The method according to claim 12, wherein: The atomic layer deposition (ALD) process includes using a process pressure between 0.5 Torr and 6 Torr and a process temperature between 250° C. and 350° C.

14. The method according to claim 9, wherein The dielectric material comprises aluminum oxide, wherein the first precursor is trimethylaluminum (TMA), and wherein the second precursor is water.

15. The method according to claim 9, wherein The atomic layer deposition ALD process does not contain any inhibitors.

16. The method according to claim 9, wherein The atomic layer deposition (ALD) process deposits a dielectric material to fill the trench, and the dielectric material is conformally deposited on the top surface of the substrate, wherein the dielectric material fills the trench seamlessly.

17. A semiconductor device comprising: a fin protruding from the substrate; an isolation region surrounding the fin; a gate stack located above the fin; a source / drain region adjacent to the gate stack in the fin; an interlayer dielectric (ILD) located above the source / drain regions, wherein a top surface of the gate stack is recessed from a top surface of the ILD; a hard mask covering the gate stack, wherein a top surface of the hard mask is flush with a top surface of the ILD, wherein the hard mask is formed without a seam by using a capillary-assisted ALD process, wherein the capillary-assisted ALD process does not completely remove unreacted precursor such that a portion of the unreacted precursor remains in a liquid phase near a bottom of a trench, wherein the hard mask has a height:width aspect ratio in a range between 1:3 and 1:25; and wherein the hard mask comprises a metal oxide; and A conductive feature extends through the hard mask to contact the gate stack.

18. The semiconductor device according to claim 17, wherein The metal oxide is aluminum oxide, zirconium oxide or hafnium oxide.

19. The semiconductor device of claim 17, further comprising a gate spacer along a sidewall of the gate stack, wherein The hard mask covers the gate spacers.

20. The semiconductor device according to claim 17, wherein The hard mask has a minimum width in a range between 3 nm and 10 nm.

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