Time-interleaved successive approximation register analog-to-digital converter and calibration method thereof

Abstract

The application provides a time-interleaved successive approximation register analog-to-digital converter (TISAR ADC) calibration method and a TISAR ADC. The TISAR ADC calibration method comprises: sampling an analog signal input into the TISAR ADC to generate a reference digital signal; obtaining a capacitance array calibration parameter of each analog-to-digital conversion sub-module and a time delay calibration parameter of each analog-to-digital conversion sub-module according to the reference digital signal and an output digital signal generated by the analog-to-digital conversion sub-module; adjusting a capacitance array of the corresponding analog-to-digital conversion sub-module according to each capacitance array calibration parameter; and adjusting a time delay of the corresponding analog-to-digital conversion sub-module according to each time delay calibration parameter. The application provides the TISAR ADC and the calibration method thereof, which can jointly calibrate the capacitance array error and the time error, thereby improving the calibration precision of the capacitance array error and the time error in the TISAR ADC, and further improving the precision and performance of the TISAR ADC.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of signal processing and communication, in particular, to a calibration method of a time-interleaved successive approximation register analog-to-digital converter and a time-interleaved successive approximation register analog-to-digital converter. BACKGROUND

[0002] In the field of modern communication, a radio frequency sampling receiver can directly digitize a received signal and then process it in the digital domain, which has the advantages of low cost, low power consumption and good performance.

[0003] A radio frequency sampling receiver mainly converts the received analog signal into a digital signal through an analog-to-digital converter (ADC), and a successive approximation register analog-to-digital converter (SAR ADC) further reduces power consumption compared with a pipelined ADC, which has recently attracted widespread attention.

[0004] However, the SAR ADC is difficult to increase the rate due to successive approximation and other reasons. The time-interleaved SAR ADC uses multiple SAR ADCs to work simultaneously and alternately outputs the conversion results, thereby doubling the conversion rate of the system without increasing the design difficulty, which provides an effective solution to break through the bottleneck of the SAR ADC rate difficult to increase.

[0005] However, the time-interleaved SAR ADC will cause nonlinearity due to the capacitance error of each SAR ADC and generate spurs due to time error, which restricts the conversion accuracy of the time-interleaved SAR ADC and cannot meet the requirements of high speed and high accuracy in wireless communication.

[0006] Therefore, how to solve the spurs and nonlinearity generated by the mismatch of each SAR ADC and the capacitance array error of the time-interleaved SAR ADC and improve the conversion accuracy has become a technical problem to be solved in the field. SUMMARY

[0007] To solve at least one aspect of the above problems existing in the prior art, the present disclosure provides a calibration method of a time-interleaved successive approximation register analog-to-digital converter and a time-interleaved successive approximation register analog-to-digital converter.

[0008] As a first aspect of the present disclosure, a calibration method of a time-interleaved successive approximation register analog-to-digital converter (TISAR ADC) is provided, comprising:

[0009] sampling an analog signal input to the TISAR ADC to generate a reference digital signal;

[0010] The capacitance array calibration parameters of each of the sub-ADCs and the time delay calibration parameters of each of the sub-ADCs are obtained according to the reference digital signal and the output digital signal generated by each of the sub-ADCs of the TISAR ADC;

[0011] The capacitance array of each of the sub-ADCs is adjusted according to the capacitance array calibration parameters of the corresponding sub-ADC respectively.

[0012] The time delay of each of the sub-ADCs is adjusted according to the time delay calibration parameters of the corresponding sub-ADC respectively.

[0013] Optionally, the step of obtaining the capacitance array calibration parameters of each of the sub-ADCs and the time delay calibration parameters of each of the sub-ADCs according to the reference digital signal and the output digital signal generated by each of the sub-ADCs of the TISAR ADC comprises:

[0014] The difference between the value of the output digital signal generated by each of the sub-ADCs and the value of the reference digital signal at the corresponding sampling time is calculated respectively.

[0015] The capacitance array calibration parameters of each of the sub-ADCs are calculated respectively according to the calculated differences.

[0016] The time delay calibration parameters of each of the sub-ADCs are calculated respectively according to the calculated differences.

[0017] Optionally, the step of calculating the capacitance array calibration parameters of each of the sub-ADCs according to the calculated differences comprises:

[0018] The weight error of the capacitance array of each of the sub-ADCs is calculated according to the difference.

[0019] The calibration weight of the capacitance array of the corresponding sub-ADC is calculated according to the weight error, and each of the calibration weights is taken as the capacitance array calibration parameter of the corresponding sub-ADC.

[0020] Optionally, the step of calculating the time delay calibration parameters of each of the sub-ADCs according to the calculated differences comprises:

[0021] The square sum of the corresponding difference of each of the sub-ADCs at different sampling times is calculated respectively.

[0022] For each of the sub-ADCs, the analog delay line digital control code of the corresponding sub-ADC is calculated according to the square sum, and each of the analog delay line digital control codes is taken as the time delay calibration parameter of the corresponding sub-ADC.

[0023] Optionally, before the step of sampling the analog signal input to the TISAR ADC to generate a reference digital signal, the calibration method further comprises:

[0024] detecting a temperature of the TISAR ADC;

[0025] in a case where the temperature collected within a predetermined time exceeds a predetermined range, performing the step of sampling the analog signal input to the TISAR ADC to generate a reference digital signal.

[0026] Optionally, after the step of sampling the analog signal input to the TISAR ADC to generate a reference digital signal, the calibration method further comprises:

[0027] determining whether a difference between the reference digital signal and an output digital signal of the TISAR ADC is greater than a first threshold value; wherein,

[0028] in a case where the difference between the reference digital signal and the output digital signal of the TISAR ADC is greater than the first threshold value, performing the step of obtaining a capacitance array calibration parameter of each analog-digital conversion sub-module of the TISAR ADC and a time delay calibration parameter of each analog-digital conversion sub-module of the TISAR ADC according to an output digital signal generated by each analog-digital conversion sub-module of the TISAR ADC and the reference digital signal.

[0029] Optionally, after the step of sampling the analog signal input to the TISAR ADC to generate a reference digital signal, the calibration method further comprises:

[0030] determining whether a difference between the reference digital signal and an output digital signal of the TISAR ADC is less than a second threshold value; wherein,

[0031] in a case where the difference between the reference digital signal and the output digital signal of the TISAR ADC is less than the second threshold value, stopping the step of obtaining a capacitance array calibration parameter of each analog-digital conversion sub-module of the TISAR ADC and a time delay calibration parameter of each analog-digital conversion sub-module of the TISAR ADC according to an output digital signal generated by each analog-digital conversion sub-module of the TISAR ADC and the reference digital signal.

[0032] Optionally, before the step of sampling the analog signal input to the TISAR ADC to generate a reference digital signal, the calibration method further comprises:

[0033] an iteration number of the steps of adjusting the capacitance array of the corresponding analog-to-digital conversion sub-module according to the capacitance array calibration parameter of each of the capacitance array calibration parameters and adjusting the time delay of the corresponding analog-to-digital conversion sub-module according to the time delay calibration parameter of each of the time delay calibration parameters;

[0034] in a case where the iteration number exceeds a predetermined threshold, stopping the step of sampling the analog signal input to the TISAR ADC to generate the reference digital signal.

[0035] As a second aspect of the present disclosure, a time-interleaved successive approximation register analog-to-digital converter (TISAR ADC) is provided, comprising:

[0036] an analog-to-digital conversion module comprising a plurality of analog-to-digital conversion sub-modules, the plurality of analog-to-digital conversion sub-modules being configured to time-interleaved sample an analog signal input to the TISAR ADC, each of the analog-to-digital conversion sub-modules being configured to generate an output digital signal;

[0037] a reference analog-to-digital converter module configured to sample the analog signal to generate a reference digital signal;

[0038] a calibration parameter calculation module configured to obtain a capacitance array calibration parameter of each of the analog-to-digital conversion sub-modules and a time delay calibration parameter of each of the analog-to-digital conversion sub-modules according to the reference digital signal generated by the reference analog-to-digital converter module and the output digital signal generated by each of the analog-to-digital conversion sub-modules;

[0039] a capacitance array error compensation module comprising a plurality of error compensation sub-modules, the number of the error compensation sub-modules being the same as the number of the analog-to-digital conversion sub-modules, and the error compensation sub-modules corresponding to the analog-to-digital conversion sub-modules one-to-one, the error compensation sub-modules being configured to adjust the capacitance array of the corresponding analog-to-digital conversion sub-module according to the capacitance array calibration parameter of each of the analog-to-digital conversion sub-modules;

[0040] a time delay adjustment module comprising a plurality of analog delay line sub-modules, the number of the analog delay line sub-modules being the same as the number of the analog-to-digital conversion sub-modules, and the analog delay line sub-modules corresponding to the analog-to-digital conversion sub-modules one-to-one, the analog delay line sub-modules being configured to adjust the time delay of the corresponding analog-to-digital conversion sub-module according to the time delay calibration parameter of each of the analog-to-digital conversion sub-modules.

[0041] Optionally, the calibration parameter calculation module comprises:

[0042] a subtracter configured to calculate a difference value between a value of the output digital signal generated by each of the analog-to-digital conversion sub-modules and a value of the reference digital signal at a corresponding sampling time, respectively;

[0043] a capacitance array calibration parameter calculation module configured to calculate a capacitance array calibration parameter of each of the analog-to-digital conversion sub-modules according to each of the differences obtained by the subtracter calculation;

[0044] a time delay calibration parameter calculation module configured to calculate a time delay calibration parameter of each of the analog-to-digital conversion sub-modules according to each of the differences obtained by the subtracter calculation.

[0045] Optionally, the capacitance array calibration parameter calculation module comprises:

[0046] an error estimation module configured to calculate a weight error of a capacitance array of each of the analog-to-digital conversion sub-modules according to each of the differences obtained by the subtracter calculation;

[0047] a weight calculation module configured to calculate a calibration weight of the capacitance array of each of the analog-to-digital conversion sub-modules according to each of the weight errors obtained by the error estimation module, and to take each of the calibration weights as a capacitance array calibration parameter of each of the analog-to-digital conversion sub-modules.

[0048] Optionally, the time delay calibration parameter calculation module comprises:

[0049] a square sum module configured to calculate a square sum of each of the differences corresponding to each of the analog-to-digital conversion sub-modules at different sampling time points;

[0050] a digital control code calculation module configured to calculate an analog delay line digital control code of each of the analog-to-digital conversion sub-modules according to the square sum obtained by the square sum module, and to take each of the analog delay line digital control codes as a time delay calibration parameter of each of the analog-to-digital conversion sub-modules.

[0051] Optionally, the TISAR ADC comprises:

[0052] a temperature sensor configured to detect a temperature of the TISAR ADC and generate a temperature signal;

[0053] the reference analog-to-digital converter module is configured to receive the temperature signal generated by the temperature sensor, and to sample an analog signal input to the TISAR ADC to generate a reference digital signal in a case where the temperature collected within a predetermined time exceeds a predetermined range.

[0054] Optionally, the calibration parameter calculation module is configured to determine whether a difference between the reference digital signal generated by the reference analog-to-digital converter module and the output digital signal of the TISAR ADC is greater than a first threshold value, and configured to obtain the capacitance array calibration parameter of each of the analog-to-digital conversion sub-modules and the time delay calibration parameter of each of the analog-to-digital conversion sub-modules according to the reference digital signal and the output digital signal generated by each of the analog-to-digital conversion sub-modules of the TISAR ADC, in a case that the difference between the reference digital signal and the output digital signal of the TISAR ADC is greater than the first threshold value.

[0055] Optionally, the calibration parameter calculation module is configured to determine whether a difference between the reference digital signal generated by the reference analog-to-digital converter module and the output digital signal of the TISAR ADC is less than a second threshold value, and configured to stop obtaining the capacitance array calibration parameter of each of the analog-to-digital conversion sub-modules and the time delay calibration parameter of each of the analog-to-digital conversion sub-modules according to the reference digital signal and the output digital signal generated by each of the analog-to-digital conversion sub-modules of the TISAR ADC, in a case that the difference between the reference digital signal and the output digital signal of the TISAR ADC is less than the second threshold value.

[0056] Optionally, the TISAR ADC comprises:

[0057] a counting module configured to obtain an iteration number of adjusting the capacitance array of each of the analog-to-digital conversion sub-modules by the capacitance array error compensation module according to the capacitance array calibration parameter of each of the analog-to-digital conversion sub-modules and adjusting the time delay of each of the analog-to-digital conversion sub-modules by the time delay adjustment module according to the time delay calibration parameter of each of the analog-to-digital conversion sub-modules;

[0058] the reference analog-to-digital converter module is configured to stop sampling the analog signal input to the TISAR ADC in a case that the iteration number exceeds a predetermined threshold value.

[0059] In the present disclosure, by comparing the reference digital signal and the output digital signal generated by each analog-to-digital conversion sub-module of the TISAR ADC, the error of the output digital signal of each analog-to-digital conversion sub-module is obtained, and the above-mentioned error is used to calculate the capacitance array calibration parameter of each analog-to-digital conversion sub-module for calibrating the capacitance array error of the TISAR ADC, and at the same time, the time delay calibration parameter of each analog-to-digital conversion sub-module for calibrating the time error of the TISAR ADC is calculated, thereby realizing the joint calibration of the capacitance array error and the time error in the TISAR ADC, and reducing the mutual influence of the capacitance array error and the time error. In addition, when calculating the capacitance array calibration parameter and the time delay calibration parameter of each analog-to-digital conversion sub-module, the error of the output digital signal of each analog-to-digital conversion sub-module does not need to be repeatedly calculated, thereby reducing the consumption of computing resources and reducing the design requirements for the hardware circuit of the TISAR ADC. BRIEF DESCRIPTION OF DRAWINGS

[0060] The accompanying drawings are included to provide a further understanding of the application, and constitute a part of the specification, and are used together with the specific embodiments described below to explain the application, but do not constitute a limitation on the application. In the drawings:

[0061] Figure 1 is a flowchart of one embodiment of the calibration method provided by the present disclosure;

[0062] Figure 2 is a flowchart of another embodiment of the calibration method provided by the present disclosure;

[0063] Figure 3 is a structural schematic diagram of a SAR ADC;

[0064] Figure 4 is a flowchart of another embodiment of the calibration method provided by the present disclosure;

[0065] Figure 5 is a flowchart of another embodiment of the calibration method provided by the present disclosure;

[0066] Figure 6 is a structural schematic diagram of a conventional TISAR ADC;

[0067] Figure 7 is a sampling schematic diagram of the calibration method provided by the present disclosure;

[0068] Figure 8 is a flowchart of another embodiment of the calibration method provided by the present disclosure;

[0069] Figure 9 is a flowchart of another embodiment of the calibration method provided by the present disclosure;

[0070] Figure 10 is a flowchart of still another embodiment of the calibration method provided by the present disclosure;

[0071] Figure 11 is a flowchart of still another embodiment of the calibration method provided by the present disclosure;

[0072] Figure 12 is a schematic diagram of a TISAR ADC structure provided by the present disclosure;

[0073] Figure 13 is a schematic diagram of a calibration parameter calculation module in a TISAR ADC provided by the present disclosure. DETAILED DESCRIPTION

[0074] The specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely intended to illustrate and explain the present application, and are not intended to limit the present application.

[0075] The inventors of the present disclosure have found that, in the prior art, in order to improve the accuracy and performance of a time-interleaved SAR ADC, the following solutions are adopted: a method for eliminating time-interleaved SAR ADC capacitor array errors and a method for eliminating time-interleaved SAR ADC sampling time errors. The above methods calibrate time-interleaved errors and capacitor array errors separately, and have the defects of slow convergence speed, high requirements for analog design, and influence on the dynamic range of the ADC. However, in practice, the calibration of time errors often affects the calibration of capacitor array errors, and the existence of capacitor array errors also causes the performance of time error calibration to decrease, and both types of errors vary with PVT (Process, Voltage, Temperature).

[0076] Therefore, eliminating time-interleaved errors or capacitor array errors alone cannot effectively improve the accuracy and performance of a time-interleaved SAR ADC. Figure 1 In view of this, as a first aspect of the present disclosure, a calibration method for a time-interleaved successive approximation register analog-to-digital converter (TISAR ADC) is provided, as shown in

[0077] In step S130, an analog signal input to the TISAR ADC is sampled to generate a reference digital signal;

[0078] In step S140, capacitor array calibration parameters of each analog-to-digital conversion sub-module and time delay calibration parameters of each analog-to-digital conversion sub-module are obtained according to the reference digital signal and output digital signals generated by each analog-to-digital conversion sub-module of the TISAR ADC;

[0079] adjusting the capacitance array of the corresponding analog-to-digital conversion submodule according to each of the capacitance array calibration parameters in step S150;

[0080] adjusting the time delay of the corresponding analog-to-digital conversion submodule according to each of the time delay calibration parameters in step S160.

[0081] It should be noted that the present application does not specially limit the sequence of step S150 and step S160. For example, step S150 can be performed before S160, step S150 can also be performed after S160, and step S150 and S160 can also be performed simultaneously.

[0082] In the present disclosure, the analog signal input to the TISAR ADC can be a specific reference signal known, and the ideal conversion result of the SAR ADC is theoretically taken as the reference digital signal, so as to realize the foreground calibration of the TISAR ADC. The analog signal input to the TISAR ADC can also be the input signal input to the TISAR ADC when the TISAR ADC is working. At this time, the digital signal generated by sampling and quantizing the input signal is taken as the reference digital signal, so as to realize the background calibration of the TISAR ADC without interfering with the normal working of the TISAR ADC.

[0083] In the present disclosure, by comparing the reference digital signal and the output digital signal generated by each analog-to-digital conversion submodule of the TISAR ADC in step S140, the error of the output digital signal of each analog-to-digital conversion submodule is obtained, and the above error is used to calculate the capacitance array calibration parameter of each analog-to-digital conversion submodule, which is used to calibrate the capacitance array error of the TISAR ADC in step S150, and the time delay calibration parameter of each analog-to-digital conversion submodule is calculated at the same time, which is used to calibrate the time error of the TISAR ADC in step S160, so as to realize the joint calibration of the capacitance array error and the time error in the TISAR ADC, and reduce the mutual influence of the capacitance array error and the time error. In addition, when calculating the capacitance array calibration parameter and the time delay calibration parameter of each analog-to-digital conversion submodule, it is not necessary to repeatedly calculate the error of the output digital signal of each analog-to-digital conversion submodule, so as to reduce the consumption of computing resources and reduce the design requirements of the hardware circuit of the TISAR ADC.

[0084] The calibration method of the TISAR ADC provided by the present disclosure utilizes a high-precision reference digital signal to jointly calibrate the capacitance array error and the time error in the TISAR ADC, can reduce the mutual influence of the capacitance array error and the time error, thereby improving the calibration accuracy of the capacitance array error and the time error in the TISAR ADC, and further improving the accuracy and performance of the TISAR ADC. Simultaneously using the error of the reference digital signal and the output digital signal of each analog-digital conversion sub-module to calibrate the capacitance array error and the time error of the TISAR ADC can reduce the consumption of computing resources. In addition, the calibration method provided by the present disclosure can not only perform foreground calibration on the TISAR ADC, but also perform background calibration, so that real-time calibration can be performed according to PVT changes without affecting the operation of the TISAR ADC, thereby improving the stability of the accuracy and performance of the TISAR ADC.

[0085] Reference will be made to Figure 7 Some concepts involved in the calibration method provided by the present disclosure are explained. In the embodiments shown in Figure 7 , the TISAR ADC includes two analog-digital conversion sub-modules and a reference analog-digital converter, wherein an analog signal S in is input into the TISAR ADC, ADC1 clock is a clock signal for sampling S in by one of the analog-digital conversion sub-modules (for the convenience of description, referred to as the first analog-digital conversion sub-module), T1 is the period of ADC1 clock, ADC2 clock is a clock signal for sampling S in by the other analog-digital conversion sub-module (for the convenience of description, referred to as the second analog-digital conversion sub-module), T2 is the period of ADC2 clock, ADC ref clock is a clock signal for sampling S in by the reference analog-digital converter, and T3 is the period of ADC ref clock. In the TISAR ADC, the first analog-digital conversion sub-module and the second analog-digital conversion sub-module are the same SAR ADC, so the sampling frequencies of the first analog-digital conversion sub-module and the second analog-digital conversion sub-module are the same, i.e., T1=T2.

[0086] In the embodiments shown in Figure 7 , each analog-digital conversion sub-module and the reference analog-digital converter sample the analog signal S in at the rising edge of the respective clock signal. For example, at t1, the first analog-digital conversion sub-module samples S inThe voltage level at point P1 is sampled, and the generated output digital signal is the output digital signal of the TISAR ADC at time t1; at time t2, the second analog-to-digital converter submodule samples the voltage level at the rising edge of the clock signal ADC2 clock. in The voltage level at point P2 is sampled, and the generated output digital signal is the output digital signal of the TISAR ADC at time t2. It can be seen that the first analog-to-digital converter (ADC) and the second ADC do not simultaneously sample the voltage at point S. in Instead of sampling to generate the output digital signal, it samples S... in Time-interleaved sampling generates the digital output signal of the TISAR ADC. Each analog-to-digital conversion submodule uses its own clock signal period as the sampling period, sampling the analog signal S... in Periodic sampling is performed. Furthermore, the reference analog-to-digital converter also functions as an ADC. ref The clock period is the sampling period for S. in Periodic sampling is performed to generate a reference digital signal.

[0087] In this disclosure, the sampling time refers to the moment when the analog-to-digital conversion submodule samples the input analog signal to generate the output digital signal. For example, t1 is the sampling time of the output digital signal of the first analog-to-digital conversion submodule at time t1, and t2 is the sampling time of the output digital signal of the second analog-to-digital conversion submodule at time t2. Each analog-to-digital conversion submodule corresponds to multiple sampling times.

[0088] As a specific implementation of this disclosure, the error of the output digital signal of each analog-to-digital conversion (ADC) submodule is obtained by subtracting the value of the output digital signal generated by each ADC submodule from the value of the reference digital signal at the corresponding time. Based on this difference, the capacitor array calibration parameters and time delay calibration parameters of each ADC submodule described in step S140 are obtained. Accordingly, as... Figure 2 As shown, step S140 specifically includes the following steps:

[0089] In step S141, the difference between the value of the output digital signal generated by each of the analog-to-digital conversion submodules and the value of the reference digital signal at the corresponding sampling time is calculated.

[0090] In step S142, the capacitor array calibration parameters of each analog-to-digital conversion submodule are calculated based on the calculated differences.

[0091] In step S143, the time delay calibration parameters of each of the analog-to-digital conversion submodules are calculated based on the calculated differences.

[0092] by Figure 7For example, each of the aforementioned analog-to-digital conversion submodules is the first analog-to-digital conversion submodule and the second analog-to-digital conversion submodule described above.

[0093] like Figure 7 As shown, at time t1, the first analog-to-digital converter submodule performs a step-by-step operation on the rising edge of the clock signal ADC1 clock, corresponding to S. in The voltage level at point P1 is sampled to generate an output digital signal, which is then used as a reference to the analog-to-digital converter (ADC) on the clock signal. ref The rising edge of the clock corresponds to S in The level of point P1 is sampled to generate a reference digital signal; at time t4, the second analog-to-digital converter submodule samples the S signal at the rising edge of the clock signal ADC2 clock. in The voltage level at point P4 is sampled to generate an output digital signal, which is then used as a reference to the analog-to-digital converter (ADC) on the clock signal. ref The rising edge of the clock corresponds to S in The level of point P4 is sampled to generate a reference digital signal; at time t5, the first analog-to-digital converter submodule samples the S signal at the rising edge of the clock signal ADC1 clock. in The voltage level at point P5 is sampled to generate an output digital signal, which is then used as a reference to the analog-to-digital converter (ADC) on the clock signal. ref The rising edge of the clock corresponds to S in The level at point P5 is sampled to generate a reference digital signal; at time t6, the second analog-to-digital converter submodule samples the S signal at the rising edge of the clock signal ADC2 clock. in The voltage level at point P6 is sampled to generate an output digital signal, which is then used as a reference to the analog-to-digital converter (ADC) on the clock signal. ref The rising edge of the clock affects S in The reference digital signal is generated by sampling the level at point P6. It can be seen that at different times, when the reference analog-to-digital converter samples S... in When sampling to generate a reference digital signal, for S in The analog-to-digital conversion submodules that perform sampling to generate the output digital signal may be different.

[0094] It should be noted that at certain times, the analog-to-digital converter (ADC) submodule samples the input signal, but the reference ADC does not sample the input signal. For example, in Figure 7 In the above, at time t2, the second analog-to-digital converter submodule performs a step on S at the rising edge of the clock signal ADC2 clock. in The output digital signal is generated by sampling the level of point P2. At time t3, the first analog-to-digital converter submodule samples the S signal at the rising edge of the clock signal ADC2 clock. inThe voltage level at point P3 is sampled to generate the output digital signal, but because of the ADC ref The clock has no rising edge at times t2 and t3, therefore the reference analog-to-digital converter did not adjust S. in Perform sampling.

[0095] In this disclosure, the error of the output digital signal of each analog-to-digital conversion (ADC) submodule in a TISAR ADC is determined by comparing it with a reference digital signal, and then each ADC submodule is calibrated accordingly. In the TISAR ADC, each ADC submodule... in Perform time-interleaved sampling, that is, not simultaneously sampling S in Sampling is performed to generate an output digital signal. Therefore, in step S141, taking the first analog-to-digital converter (ADC) submodule as an example, to obtain the error of the output digital signal of the first ADC submodule relative to the reference digital signal, it is necessary to calculate the error when the first ADC submodule and the reference ADC simultaneously sample S... in At the time of sampling, the difference between the value of the digital output signal generated by the first analog-to-digital converter submodule and the value of the reference digital signal generated by the reference analog-to-digital converter. More specifically, such as Figure 7 As shown, at sampling time t1, the first analog-to-digital converter submodule and the reference analog-to-digital converter simultaneously sample S. in Sampling is performed. In step S141, the difference between the digital output signal generated by the first analog-to-digital converter (ADC) at sampling time t1 and the reference digital signal generated by the reference ADC is calculated. In step S142, the capacitor array calibration parameters of the first ADC are calculated based on this difference. In step S143, the time delay calibration parameters of the first ADC are calculated based on this difference. At sampling time t4, the second ADC and the reference ADC simultaneously sample the digital output signal at sampling time t1. in Sampling is performed. In step S141, the difference between the value of the digital output signal generated by the second analog-to-digital converter submodule and the value of the reference digital signal generated by the reference analog-to-digital converter at sampling time t4 is calculated. In step S142, the capacitor array calibration parameters of the second analog-to-digital converter submodule are calculated based on the difference. In step S143, the time delay calibration parameters of the second analog-to-digital converter submodule are calculated based on the difference.

[0096] In this disclosure, the analog-to-digital conversion submodule is composed of a SAR ADC, and the calibration of the capacitance array error of the TISAR ADC is mainly performed in the digital domain. Figure 3As shown in FIG. 1, the structure diagram of the SAR ADC is shown. After the input signal is input into the sampling circuit 210, the input signal is compared with the voltage value of the capacitor array 225 by the comparator 220, and a digital code is output. The digital code is output through the logic module 235 to control the capacitor switch 230, so as to change the voltage value of the capacitor array 225. Each sub capacitor C i The digital code output d is obtained by sequentially comparing the input signal. i In the capacitor array of the SAR ADC, the sub capacitor C i occupies the weight of The digital output of the SAR ADC obtained through the weight conversion is shown in formula (1):

[0097]

[0098] Since the capacitance cannot be without deviation in practice, and the capacitance will also change due to changes in temperature and the like, the weight occupied by each sub capacitor C i in the capacitor array 225 of the SAR ADC has deviation, which further causes the TISAR ADC to generate a capacitor array error. Therefore, in the present disclosure, the weight error of the capacitor array of each analog-to-digital conversion sub-module is calculated according to each difference value, and the calibration weight of the capacitor array of the corresponding analog-to-digital conversion sub-module is calculated according to the weight error, as the capacitor array calibration parameter, so that the weight occupied by each sub capacitor C i in the capacitor array 225 of each analog-to-digital conversion sub-module can be calibrated to be as close to the theoretical value as possible, so that the capacitor array error of each analog-to-digital conversion sub-module can be calibrated, and the capacitor array error of the TISAR ADC can be calibrated. Accordingly, as shown in FIG. 1, step S142 specifically includes: Figure 4

[0099] In step S142a, the weight error of the capacitor array of each analog-to-digital conversion sub-module is calculated according to each difference value.

[0100] In step S142b, the calibration weight of the capacitor array of the corresponding analog-to-digital conversion sub-module is calculated according to the weight error, and each calibration weight is taken as the capacitor array calibration parameter of each analog-to-digital conversion sub-module.

[0101] ​In the present disclosure, the calibration of the time error in the TISAR ADC is mainly performed in the analog domain. Specifically, by adjusting the analog delay lines of each analog-digital conversion sub-module of the TISAR ADC, the time error of each analog-digital conversion sub-module is compensated, and thus the time error of the TISAR ADC is calibrated. In addition, the inventors of the present disclosure have found that the square of the difference between the value of the output digital signal of the TISAR ADC and the value of the reference digital signal is positively correlated with the size of the time error of the TISAR ADC. Therefore, in the present disclosure, as shown in Figure 5 Step S143 further includes:

[0102] In step S143a, the square sum of the difference corresponding to each analog-digital conversion sub-module at different sampling times is calculated respectively.

[0103] In step S143b, for each analog-digital conversion sub-module, the analog delay line digital control code of the corresponding analog-digital conversion sub-module is calculated according to the square sum, and each analog delay line digital control code is taken as the time delay calibration parameter of each analog-digital conversion sub-module.

[0104] It should be noted that at different times, when the reference analog-digital converter samples S in to generate a reference digital signal, the analog-digital conversion sub-module that samples S in to generate an output digital signal can be different, and when a large number of samples of the reference digital signal are taken and the difference is calculated through step S141, there can be multiple differences, each corresponding to a different sampling time of the same analog-digital conversion sub-module, and in step S143a, the square sum of the above multiple differences is obtained. For example, as shown in Figure 7 At times t1 and t5, the differences calculated through step S141 both correspond to the first analog-digital conversion sub-module, and at times t4 and t6, the differences calculated through step S141 both correspond to the second analog-digital conversion sub-module.

[0105] The present disclosure provides a specific embodiment for obtaining the capacitance array calibration parameter of each analog-digital conversion sub-module and the time delay calibration parameter of each analog-digital conversion sub-module according to the reference digital signal and the output digital signal generated by each analog-digital conversion sub-module of the TISAR ADC.

[0106] As shown in Figure 6 In a conventional TISAR ADC, the input analog signal S in is time-interleaved sampled by multiple SAR ADCs, and the sampling output S s of the high-speed ADC with a sampling frequency of f outWhen the M-path SAR ADC is included in the TISAR ADC, the sampling frequency of each path of the SAR ADC is f s / M.

[0107] In the present disclosure, when sampling the analog signal input to the TISAR ADC to generate a reference digital signal, the sampling frequency can be f s / N. Wherein N and M are co-prime. It should be noted that, as Figure 7 shown, N and M are set to co-prime natural numbers, so that each sub-SAR ADC in the TISAR ADC has a reference digital signal corresponding to its output signal every certain time, for example, at t1 and t5, the reference digital signal corresponds to the first analog-digital conversion sub-module, and at t4 and t6, the reference digital signal corresponds to the second analog-digital conversion sub-module, thereby realizing calibration of multiple sub-SAR ADCs in the TISAR ADC using one reference ADC.

[0108] In the present disclosure, based on statistical principles, the output digital signals of each path of the SAR ADC and the reference digital signal are sampled to obtain a plurality of samples. Since in the TISAR ADC, each analog-digital conversion sub-module samples the input signal through time interleaving to generate the output digital signal of the TISAR ADC, in order to calculate the difference between the numerical value of the output digital signal generated by each path of the SAR ADC and the numerical value of the reference digital signal at the corresponding time, the numerical value of the output digital signal of each path of the SAR ADC at each time and the numerical value of the reference digital signal at the corresponding time need to be associated.

[0109] Specifically, the reference digital signal and the output digital signal generated by each analog-digital conversion sub-module can be associated in the following manner:

[0110] Suppose ADC1[k] and ADC2[k] are the outputs of the first path of the SAR ADC and the second path of the SAR ADC in the TISAR ADC at the kth time, and ADC ref [k] is the output of the reference channel ADC at the kth time, then the corresponding relationship between ADC1[k], ADC2[k] and ADC ref [k] is shown in equations (2) and (3):

[0111] ADC ref [2k]→ADC1[3k]k=0,1,2,... (2)

[0112] ADC ref [2k+1]→ADC2[3k+1]k=0,1,2,... (3)

[0113] Generally, the output of the mth SAR ADC at the kth time instant and the corresponding relationship with the reference digital signal can be expressed as formula (4):

[0114] ADC ref [2k]→ADC m [3k+m-1]k=0,1,2,... (4)

[0115] For the mth SAR ADC, it is assumed that C im The actual weight W im The corresponding theoretical weight, the actual weight and the theoretical weight have a deviation ε im That is, as shown in formula (5):

[0116]

[0117] From formula (1), the digital output obtained by the mth SAR ADC through weight conversion can be expressed as formula (6):

[0118]

[0119] The difference between the output digital signal of the mth SAR ADC and the reference digital signal is formula (7):

[0120] e m =ADC m -ADC ref (7)

[0121] From formula (6), it can be further transformed into formula (8):

[0122]

[0123] Assuming that the number of samples after correlating the value of the output digital signal of the mth SAR ADC at each time instant with the value of the reference digital signal at the corresponding time instant is K, the optimal estimate value of the weight error of the capacitor array of the mth SAR ADC can be calculated using the cost function in formula (9):

[0124]

[0125] According to the least square criterion, the estimate value of the capacitor array weight error of the mth SAR ADC is shown in formula (10):

[0126] ε m =pinv(D m )*e m (10)

[0127] wherein ε m = [ε 1m , ε 2m , ε 3m ,..., ε Dm ] T wherein D m is a matrix formed by K samples of the code of the SAR ADC output. It can be expressed as formula (11):

[0128]

[0129] e m = [e1, e2,..., e K ] T is the difference between the output digital signal of the mth SAR ADC and the value of the reference digital signal at the same time.

[0130] In the present disclosure, the calibration weight of the capacitor array of the analog-digital conversion sub-module can be expressed as formula (12) by iteratively calibrating the error of the capacitor array:

[0131]

[0132] wherein is a vector composed of the capacitor weights of the mth SAR ADC at the current time; u1 is a step factor, which is used to control the convergence speed of the algorithm and can be set according to actual needs.

[0133] In the present disclosure, the time error is calibrated by an iterative method.

[0134] The sum of squares of the difference between the value of the output digital signal of the mth SAR ADC at different times and the value of the reference digital signal at the corresponding time can be expressed as formula (13):

[0135]

[0136] wherein K is the number of samples needed to be accumulated in one iteration.

[0137] Through the J m of the current iteration and the last iteration, the J' m is obtained, so that the direction and step length of the digital code iteration can be determined, as shown in formula (14):

[0138]

[0139] Further, formula (15) can be obtained:

[0140] D m,n = D m,n-1 + u2J' m (15)

[0141] wherein D m,n and D m,n-1 respectively represent the digital control code of the analog delay line of the mth SAR ADC at the current time and the previous time, u2 is a step factor for controlling the convergence speed of the algorithm, which can be set according to actual needs.

[0142] Because temperature is an important factor affecting the delay of an integrated circuit, in the present disclosure, temperature change can be used as a condition for initiating the calibration method of the TISAR ADC provided by the present disclosure. Accordingly, in addition to including the steps S130 to S160 described above, the calibration method provided by the present disclosure further includes, before the step S130, as shown in the following figure: Figure 8

[0143] In the step S120, the temperature of the TISAR ADC is detected.

[0144] In the case where the temperature collected within a predetermined time exceeds a predetermined range, the step S130 and the subsequent steps are performed.

[0145] As another specific embodiment of the present disclosure, the error size of the output digital signal of the TISAR ADC can also be used as a condition for initiating the calibration method provided by the present disclosure, so that calibration is initiated in time when the error of the output digital signal is greater than a first threshold value. Accordingly, in addition to including the steps S130 to S160 described above, the calibration method provided by the present disclosure further includes, before the step S130, as shown in the following figure: Figure 9

[0146] In the step S110, it is determined whether the difference between the reference digital signal and the output digital signal of the TISAR ADC is greater than a first threshold value.

[0147] In the case where the difference between the reference digital signal and the output digital signal of the TISAR ADC is greater than the first threshold value, the step S130 and the subsequent steps are performed.

[0148] In the present disclosure, when the error of the output digital signal of the TISAR ADC after calibration with respect to the reference digital signal is less than a second threshold value, it is determined that the calibration of the TISAR ADC is completed, and the calibration method is terminated. Accordingly, in addition to including the steps S130 to S160 described above, the calibration method provided by the present disclosure further includes, after the step S130, as shown in the following figure: Figure 10

[0149] In the step S170, it is determined whether the difference between the reference digital signal and the output digital signal of the TISAR ADC is less than a second threshold value.​​​

[0150] In a case where the difference between the reference digital signal and the output digital signal of the TISAR ADC is less than the second threshold value, the step S140 and subsequent steps are stopped.

[0151] The calibration method provided by the present disclosure is performed in an iterative manner, so when the number of iterations reaches a predetermined threshold value, it can be determined that the calibration of the TISAR ADC is completed, and the calibration method is terminated, thereby saving computing resources. Accordingly, in addition to the steps S130 to S160 described above, the calibration method provided by the present disclosure also includes, as shown in the following step S170, before the step S130: Figure 11

[0152] In the step S180, the number of iterations of the steps S150 and S160 is obtained.

[0153] In a case where the number of iterations exceeds a predetermined threshold value, the step S130 and subsequent steps are stopped.

[0154] It should be noted that in actual applications, different steps in the calibration method provided in the embodiments of the present disclosure can be combined to obtain a new technical solution, which should also be within the protection scope of the present disclosure.

[0155] The following provides a specific embodiment of the calibration method provided by the present disclosure.

[0156] Taking a two-channel TISAR ADC as an example, the rate of the two-channel TISAR ADC is 2Gsps, the sub-ADC adopts a SAR architecture, the rate is 1Gsps, the analog delay line step length corresponding to one digital symbol is 75fs, and the rate of the reference channel is 666.67MHz.

[0157] An input of 389MHz single tone signal. Turn on the double-channel time-interleaved SAR ADC to sample the analog signal, correlate the sampling data of the two-channel SAR ADC and the reference channel ADC, and respectively obtain the difference e mk ,k=1,2,...,200. When the amount of correlated data reaches 200, the e m is calculated, the SAR ADC step parameter u1 is set to 0.5, the new capacitor array error calibration parameter is obtained through iteration, and the SAR ADC capacitor weight is updated, and the digital calibration update is completed.

[0158] According to the obtained difference e mk ,k=1,2,...,200, the square sum of the difference is calculated, and J' m [n] is obtained, the step parameter u2 is set to 1000, the digital symbol D​m,n-1 By iterating, we can obtain the digital symbol D at the current moment. m,n And use this digital code to adjust the analog delay line.

[0159] Repeat the above process, iterating 50 times or... When the value is less than a given value of 0.00001, the calibration is complete, and the calibrated TISAR ADC output can be obtained.

[0160] As a second aspect of this disclosure, a time-interleaved successive approximation analog-to-digital converter (TISAR ADC) is provided, such as... Figure 12 As shown, it includes:

[0161] The analog-to-digital conversion module 300 includes multiple analog-to-digital conversion sub-modules 310, which are used to perform time-interleaved sampling on the analog signals input to the TISAR ADC, and each analog-to-digital conversion sub-module 310 can generate an output digital signal.

[0162] A reference analog-to-digital converter module 100 is used to sample the analog signal to generate a reference digital signal;

[0163] The calibration parameter calculation module 400 is used to obtain the capacitor array calibration parameters and the time delay calibration parameters of each analog-to-digital converter submodule 310 based on the reference digital signal generated by the reference analog-to-digital converter module 100 and the output digital signal generated by each analog-to-digital converter submodule 310.

[0164] The capacitor array error compensation module 500 includes multiple error compensation sub-modules 510. The number of error compensation sub-modules 510 is the same as the number of analog-to-digital conversion sub-modules 310, and the error compensation sub-modules 510 correspond one-to-one with the analog-to-digital conversion sub-modules 310. The capacitor error compensation sub-modules 510 are used to adjust the capacitor array of the corresponding analog-to-digital conversion sub-module 310 according to the capacitor array calibration parameters of each analog-to-digital conversion sub-module 310.

[0165] The time delay adjustment module 600 includes multiple analog delay line sub-modules. The number of analog delay line sub-modules is the same as that of the analog-to-digital conversion sub-modules 310, and each analog delay line sub-module corresponds to one analog-to-digital conversion sub-module 310. The analog delay line sub-module is used to adjust the time delay of the corresponding analog-to-digital conversion sub-module 310 according to the time delay calibration parameters of each analog-to-digital conversion sub-module 310.

[0166] It should be noted that in the present disclosure, the shown capacitor array error compensation module 500 is specifically a CDAC, that is, a capacitive digital-to-analog conversion structure.

[0167] The time-interleaved successive approximation register analog-to-digital converter TISAR ADC provided by the application compares the reference digital signal generated by the reference analog-to-digital converter module 100 with the output digital signal generated by each analog-to-digital conversion submodule 310 of the TISAR ADC, obtains the error of the output digital signal of each analog-to-digital conversion submodule 310, and calculates the capacitor array calibration parameter of each analog-to-digital conversion submodule 310 by using the error, so as to calibrate the capacitor array error of each analog-to-digital conversion submodule 310 by using the capacitor array calibration parameter. The calibration parameter calculation module 400 simultaneously calculates the time delay calibration parameter of each analog-to-digital conversion submodule 310, and the time delay adjustment module 600 calibrates the time error of each analog-to-digital conversion submodule 310 by using the time delay calibration parameter, so as to realize the joint calibration of the capacitor array error and the time error in the TISAR ADC, and reduce the mutual influence of the capacitor array error and the time error. In addition, when calculating the capacitor array calibration parameter and the time delay calibration parameter of each analog-to-digital conversion submodule 310, the calibration parameter calculation module 400 only needs to calculate the error of the output digital signal of each analog-to-digital conversion submodule 310 once, so as to reduce the consumption of the calculation resource and simplify the hardware circuit of the TISAR ADC.

[0168] Optionally, as shown in the figure, Figure 13 the calibration parameter calculation module 400 comprises:

[0169] a subtracter 420, configured to calculate the difference value between the numerical value of the output digital signal generated by each analog-to-digital conversion submodule 310 and the numerical value of the reference digital signal at the corresponding sampling time, respectively;

[0170] a capacitor array calibration parameter calculation module 430, configured to calculate the capacitor array calibration parameter of each analog-to-digital conversion submodule 310 according to each difference value calculated by the subtracter 420, respectively;

[0171] a time delay calibration parameter calculation module 440, configured to calculate the time delay calibration parameter of each analog-to-digital conversion submodule 310 according to each difference value calculated by the subtracter 420, respectively.

[0172] Optionally, as shown in the figure, Figure 13 the capacitor array calibration parameter calculation module 430 comprises:

[0173] an error estimation module 431 configured to calculate a weight error of the capacitance array of each of the sub-ADCs 310 according to the difference value calculated by the subtractor 420;

[0174] a weight calculation module 432 configured to calculate a calibration weight of the capacitance array of each of the sub-ADCs 310 according to the weight error calculated by the error estimation module 431, and use each of the calibration weights as a calibration parameter of the capacitance array of each of the sub-ADCs 310.

[0175] Optionally, as shown in Figure 13 the delay calibration parameter calculation module 440 includes:

[0176] a square sum module 441 configured to calculate a square sum of the difference value corresponding to each of the sub-ADCs 310 at different sampling times;

[0177] a digital control code calculation module 442 configured to calculate an analog delay line digital control code of each of the sub-ADCs 310 according to the square sum calculated by the square sum module 441, and use each of the analog delay line digital control codes as a delay calibration parameter of each of the sub-ADCs 310.

[0178] Optionally, the TISAR ADC includes:

[0179] a temperature sensor configured to detect the temperature of the TISAR ADC and generate a temperature signal;

[0180] the reference ADC module 100 is configured to receive the temperature signal generated by the temperature sensor, and sample an analog signal input to the TISAR ADC to generate a reference digital signal when the temperature collected within a predetermined time exceeds a predetermined range.

[0181] Optionally, the calibration parameter calculation module 400 is configured to determine whether the difference between the reference digital signal generated by the reference ADC module 100 and the output digital signal of the TISAR ADC is greater than a first threshold value, and calculate the calibration parameter of the capacitance array of each of the sub-ADCs 310 and the delay calibration parameter of each of the sub-ADCs 310 according to the reference digital signal and the output digital signal generated by each of the sub-ADCs 310 when the difference between the reference digital signal and the output digital signal of the TISAR ADC is greater than the first threshold value.

[0182] Optionally, the calibration parameter calculation module 400 is configured to determine whether a difference between the reference digital signal generated by the reference analog-to-digital converter module and the output digital signal of the TISAR ADC is less than a second threshold value, and to stop obtaining the capacitance array calibration parameter of each of the analog-to-digital conversion sub-modules 310 and the time delay calibration parameter of each of the analog-to-digital conversion sub-modules 310 according to the reference digital signal and the output digital signal generated by each of the analog-to-digital conversion sub-modules 310 of the TISAR ADC if the difference between the reference digital signal and the output digital signal of the TISAR ADC is less than the second threshold value.

[0183] Optionally, the TISAR ADC comprises:

[0184] a counting module configured to obtain an iteration number of adjusting the capacitance array of each of the analog-to-digital conversion sub-modules according to the capacitance array calibration parameter of each of the analog-to-digital conversion sub-modules and adjusting the time delay of each of the analog-to-digital conversion sub-modules according to the time delay calibration parameter of each of the analog-to-digital conversion sub-modules by the capacitance array error compensation module and the time delay adjustment module;

[0185] the reference analog-to-digital converter module 100 is configured to stop sampling the analog signal input to the TISAR ADC if the iteration number exceeds a predetermined threshold value.

[0186] It can be understood that the above embodiments are only exemplary embodiments for illustrating the principles of the present application, and the present application is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and essence of the present application, and these modifications and improvements are also considered to be within the protection scope of the present application.

Claims

1. A method for calibrating a time-interleaved successive approximation register analog-to-digital converter (TISAR ADC), comprising: sampling an analog signal input to the TISAR ADC to generate a reference digital signal; obtaining a capacitance array calibration parameter of each analog-to-digital conversion sub-module of the TISAR ADC and a time delay calibration parameter of each analog-to-digital conversion sub-module of the TISAR ADC according to the reference digital signal and an output digital signal generated by each analog-to-digital conversion sub-module of the TISAR ADC; adjusting a capacitance array of each analog-to-digital conversion sub-module according to a corresponding capacitance array calibration parameter; adjusting a time delay of each analog-to-digital conversion sub-module according to a corresponding time delay calibration parameter; after the step of sampling the analog signal input to the TISAR ADC to generate the reference digital signal, the method further comprises: judging whether a difference between the reference digital signal and an output digital signal of the TISAR ADC is greater than a first threshold value; in the case that the difference between the reference digital signal and the output digital signal of the TISAR ADC is greater than the first threshold value, performing the step of obtaining the capacitance array calibration parameter of each analog-to-digital conversion sub-module of the TISAR ADC and the time delay calibration parameter of each analog-to-digital conversion sub-module of the TISAR ADC according to the reference digital signal and the output digital signal generated by each analog-to-digital conversion sub-module of the TISAR ADC.

2. The calibration method of claim 1, wherein, The step of obtaining the capacitance array calibration parameter of each analog-to-digital conversion sub-module of the TISAR ADC and the time delay calibration parameter of each analog-to-digital conversion sub-module of the TISAR ADC according to the reference digital signal and the output digital signal generated by each analog-to-digital conversion sub-module of the TISAR ADC comprises: calculating a difference between a value of the output digital signal generated by each analog-to-digital conversion sub-module and a value of the reference digital signal at a corresponding sampling time; calculating the capacitance array calibration parameter of each analog-to-digital conversion sub-module according to each calculated difference; calculating the time delay calibration parameter of each analog-to-digital conversion sub-module according to each calculated difference.

3. The calibration method of claim 2, wherein, The step of calculating the capacitance array calibration parameter of each analog-to-digital conversion sub-module according to each calculated difference comprises: calculating a weight error of the capacitance array of each analog-to-digital conversion sub-module according to each difference; calculating a calibration weight of the capacitance array of each analog-to-digital conversion sub-module according to the weight error, and taking each calibration weight as the capacitance array calibration parameter of each analog-to-digital conversion sub-module.

4. The calibration method of claim 2, wherein, The step of calculating the time delay calibration parameter of each analog-to-digital conversion sub-module according to each calculated difference comprises: calculating a sum of squares of the corresponding difference at different sampling times for each analog-to-digital conversion sub-module; for each analog-to-digital conversion sub-module, calculating an analog delay line digital control code of the corresponding analog-to-digital conversion sub-module according to the sum of squares, and taking each analog delay line digital control code as the time delay calibration parameter of each analog-to-digital conversion sub-module.

5. The calibration method of any one of claims 1 to 4, wherein, Before the step of sampling the analog signal input to the TISAR ADC to generate a reference digital signal, the calibration method further comprises: detecting the temperature of the TISAR ADC; if the temperature collected within a predetermined time exceeds a predetermined range, performing the step of sampling the analog signal input to the TISAR ADC to generate a reference digital signal.

6. The calibration method of any one of claims 1 to 4, wherein, After the step of sampling the analog signal input to the TISAR ADC to generate a reference digital signal, the calibration method further comprises: determining whether the difference between the reference digital signal and the output digital signal of the TISAR ADC is less than a second threshold value; if the difference between the reference digital signal and the output digital signal of the TISAR ADC is less than the second threshold value, stopping the step of obtaining the capacitance array calibration parameter of each analog-digital conversion submodule and the time delay calibration parameter of each analog-digital conversion submodule according to the output digital signal generated by each analog-digital conversion submodule and the reference digital signal generated by the reference analog-digital converter module.

7. The calibration method of any one of claims 1 to 4, wherein, Before the step of sampling the analog signal input to the TISAR ADC to generate a reference digital signal, the calibration method further comprises: obtaining the iteration number of the step of adjusting the capacitance array of the corresponding analog-digital conversion submodule according to each capacitance array calibration parameter and the step of adjusting the time delay of the corresponding analog-digital conversion submodule according to each time delay calibration parameter; if the iteration number exceeds a predetermined threshold value, stopping the step of sampling the analog signal input to the TISAR ADC to generate a reference digital signal.

8. A time-interleaved successive approximation register analog-digital converter (TISAR ADC), comprising: an analog-digital conversion module comprising a plurality of analog-digital conversion submodules, the plurality of analog-digital conversion submodules being configured to time-interleaved sample an analog signal input to the TISAR ADC, each analog-digital conversion submodule being capable of generating an output digital signal; a reference analog-digital converter module configured to sample the analog signal to generate a reference digital signal; a calibration parameter calculation module configured to obtain a capacitance array calibration parameter of each analog-digital conversion submodule and a time delay calibration parameter of each analog-digital conversion submodule according to the reference digital signal generated by the reference analog-digital converter module and the output digital signal generated by each analog-digital conversion submodule; a capacitance array error compensation module comprising a plurality of error compensation submodules, the number of error compensation submodules being the same as the number of analog-digital conversion submodules, and each error compensation submodule corresponding to one analog-digital conversion submodule, the error compensation submodule being configured to adjust the capacitance array of the corresponding analog-digital conversion submodule according to the capacitance array calibration parameter of the analog-digital conversion submodule. The time delay adjustment module comprises a plurality of analog delay line sub-modules, the number of the analog delay line sub-modules is the same as that of the analog-to-digital conversion sub-modules, and the analog delay line sub-modules correspond to the analog-to-digital conversion sub-modules one by one, and the analog delay line sub-modules are used to adjust the time delay of the corresponding analog-to-digital conversion sub-modules according to the time delay calibration parameters of the analog-to-digital conversion sub-modules; The calibration parameter calculation module is used to judge whether the difference between the reference digital signal generated by the reference analog-to-digital converter module and the output digital signal of the TISAR ADC is greater than a first threshold value, and is used to obtain the capacitance array calibration parameters of each analog-to-digital conversion sub-module and the time delay calibration parameters of each analog-to-digital conversion sub-module according to the reference digital signal and the output digital signal generated by each analog-to-digital conversion sub-module of the TISAR ADC in the case that the difference between the reference digital signal and the output digital signal of the TISAR ADC is greater than the first threshold value.

9. The TISAR ADC of claim 8, wherein, The calibration parameter calculation module comprises: a subtracter used to calculate the difference between the numerical value of the output digital signal generated by each analog-to-digital conversion sub-module and the numerical value of the reference digital signal at the corresponding sampling time; a capacitance array calibration parameter calculation module used to calculate the capacitance array calibration parameters of each analog-to-digital conversion sub-module according to each difference value calculated by the subtracter; a time delay calibration parameter calculation module used to calculate the time delay calibration parameters of each analog-to-digital conversion sub-module according to each difference value calculated by the subtracter.

10. The TISAR ADC of claim 9, wherein, The capacitance array calibration parameter calculation module comprises: an error estimation module used to calculate the weight error of the capacitance array of each analog-to-digital conversion sub-module according to each difference value calculated by the subtracter; a weight calculation module used to calculate the calibration weight of the capacitance array of the corresponding analog-to-digital conversion sub-module according to each weight error calculated by the error estimation module, and each calibration weight is used as the capacitance array calibration parameter of each analog-to-digital conversion sub-module.

11. The TISAR ADC of claim 9, wherein, The time delay calibration parameter calculation module comprises: a square sum module used to calculate the square sum of the corresponding difference value of each analog-to-digital conversion sub-module at different sampling times; a digital control code calculation module, for each analog-to-digital conversion sub-module, the digital control code calculation module is used to calculate the analog delay line digital control code of the corresponding analog-to-digital conversion sub-module according to the square sum calculated by the square sum module, and each analog delay line digital control code is used as the time delay calibration parameter of each analog-to-digital conversion sub-module.

12. The TISAR ADC of any one of claims 8-11, wherein, The TISAR ADC comprises: a temperature sensor used to detect the temperature of the TISAR ADC and generate a temperature signal; the reference analog-to-digital converter module is used to receive the temperature signal generated by the temperature sensor, and is used to sample the analog signal input into the TISAR ADC to generate a reference digital signal in the case that the temperature collected within a predetermined time exceeds a predetermined range.

13. The TISAR ADC of any one of claims 8-11, wherein: the calibration parameter calculation module is configured to determine whether a difference between a reference digital signal generated by the reference analog-to-digital converter module and an output digital signal of the TISAR ADC is less than a second threshold value, and to stop obtaining the capacitance array calibration parameter of each of the analog-to-digital conversion sub-modules and the time delay calibration parameter of each of the analog-to-digital conversion sub-modules from the reference digital signal and the output digital signal generated by each of the analog-to-digital conversion sub-modules of the TISAR ADC if the difference between the reference digital signal and the output digital signal of the TISAR ADC is less than the second threshold value.

14. The TISAR ADC of any one of claims 8-11, wherein, The TISAR ADC comprises: a counting module configured to obtain an iteration number of adjusting the capacitance array of each of the analog-to-digital conversion sub-modules by the capacitance array error compensation module and adjusting the time delay of each of the analog-to-digital conversion sub-modules by the time delay adjustment module according to the time delay calibration parameter of each of the analog-to-digital conversion sub-modules; the reference analog-to-digital converter module is configured to stop sampling the analog signal input to the TISAR ADC if the iteration number exceeds a predetermined threshold value.

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