Quantum computing device coupled to an insertion layer and a heat sink

Abstract

In one embodiment, a quantum device includes an insertion layer including a set of through-holes. In one embodiment, the quantum device includes a dielectric layer formed on a first side of the insertion layer, the dielectric layer including a set of transmission lines communicatively coupled to the set of through-holes. In one embodiment, the quantum device includes a plurality of qubit chips coupled to opposite sides of the insertion layer, each qubit chip of the plurality of qubit chips including: a plurality of qubits on the first side of the qubit chip and a plurality of protrusions on a second side of the qubit chip. In one embodiment, the quantum device includes a heat sink thermally coupled to the plurality of qubit chips, the heat sink including a plurality of recesses aligned with the plurality of protrusions of the plurality of qubit chips.

Description

Technical Field

[0001] The present invention generally relates to apparatus, methods, and systems for assembling quantum computing devices. More specifically, the present invention relates to apparatus, methods, and systems for flip-chip assembly of quantum computing devices. Background Art

[0002] In the following, unless explicitly distinguished in usage, the “Q” prefix in a phrase indicates that the word or phrase is referenced in the context of quantum computing.

[0003] Molecules and subatomic particles obey the laws of quantum mechanics, a branch of physics that explores how the physical world works at its most fundamental level. At this level, particles behave in bizarre ways, existing in multiple states simultaneously and interacting with other particles at great distances. Quantum computing exploits these quantum phenomena to process information.

[0004] The computers we use today are called classical computers (also referred to herein as "conventional" computers, conventional nodes, or "CNs"). Conventional computers use conventional processors fabricated using semiconductor materials and techniques, semiconductor memory, and magnetic or solid-state storage devices—a concept known as the von Neumann architecture. Specifically, the processors in conventional computers are binary processors; that is, they operate on binary data represented by 1s and 0s.

[0005] Quantum processors (q-processors) exploit the unique properties of entangled quantum bit devices (referred to herein as "qubits" or "qubits") to perform computational tasks. In the specific realm of quantum mechanics, matter particles can exist in multiple states—for example, "on," "off," and both "on" and "off" simultaneously. While binary computing using semiconductor processors is limited to using only on and off states (equal to 1 and 0 in binary code), quantum processors exploit these quantum states of matter to output signals that can be used for data computation.

[0006] Conventional computers encode information in bits. Each bit can take on a value of 1 or 0. These 1s and 0s act as on / off switches, ultimately driving the computer's functionality. Quantum computers, on the other hand, are based on qubits, which operate according to two key principles of quantum physics: superposition and entanglement. Superposition means that each qubit can represent both 1 and 0 simultaneously. Entanglement means that qubits in superposition can be correlated in a nonclassical way; that is, the state of one (whether it's 1, 0, or both) depends on the state of the other, and more information can be determined about the two entangled qubits than if they were treated separately.

[0007] Using these two principles, qubits function as more complex information processors, enabling quantum computers to operate in a manner that allows them to solve difficult problems that are intractable using conventional computers. IBM has successfully built and demonstrated the operability of a quantum processor using superconducting qubits (IBM is a registered trademark of International Business Machines Corporation in the U.S. and other countries).

[0008] A superconducting qubit includes a Josephson junction. A Josephson junction is formed by separating two thin-film superconducting metal layers with a non-superconducting material. When the metal in the superconducting layer becomes superconducting—for example, by cooling the metal to a specified cryogenic temperature—electron pairs can tunnel from one superconducting layer through the non-superconducting layer to the other superconducting layer. In a qubit, a Josephson junction, acting as a dispersed nonlinear inductor, is electrically coupled in parallel with one or more capacitive devices that constitute a nonlinear microwave oscillator. The resonant / transition frequency of the oscillator is determined by the inductance and capacitance values in the qubit circuit. Unless explicitly distinguished, any reference to the term "qubit" refers to a superconducting qubit circuit employing a Josephson junction.

[0009] The information processed by the qubit is carried or transmitted in the form of microwave signals / photons in the microwave frequency range. The microwave signals are captured, processed, and analyzed to decipher the quantum information encoded therein. A readout circuit is coupled to the qubit to capture, read, and measure the qubit's quantum state. The output of the readout circuit is information that can be used by the q-processor to perform computations.

[0010] A superconducting qubit has two quantum states—|0> and |1>. These two states can be the two energy states of an atom, for example, the ground state (|g>) and the first excited state (|e>) of a superconducting artificial atom (superconducting qubit). Other examples include the up and down spins of a nuclear or electron spin, the two positions of a crystal defect, and the two states of a quantum dot. Due to the quantum nature of the system, any combination of these two states is allowed and valid.

[0011] For quantum computations using qubits to be reliable, quantum circuits (q-circuits), such as the qubits themselves, the readout circuitry associated with the qubits, and other parts of the quantum processor, must not alter the qubit's energy state, for example by injecting or dissipating energy in any significant way or by affecting the relative phase between the qubit's |0> and |1> states. This operational constraint on any circuit operating with quantum information requires special considerations when fabricating the semiconductor and superconducting structures used in such circuits.

[0012] Currently available superconducting quantum circuits are formed using materials that superconduct at ultra-low temperatures (e.g., about 10-100 millikelvin (mK) or about 4K). External circuits connected to quantum circuits typically operate at room temperature (approximately 270-300K) or higher. Therefore, the connections between the external circuit and the q-circuit (e.g., input lines to the q-circuit, output lines from the q-circuit, or both) must be thermally isolated from the external circuit's environment.

[0013] To provide this thermal isolation, the lines connected to the q-circuit are passed through a series of one or more dilution refrigerator stages (referred to herein as "stages" or "stages"). A dilution refrigerator is a heat exchange device that causes a component to be cooled compared to the temperature at which it was introduced into the dilution refrigerator, or maintains the component at a specified reduced temperature, or both. For example, a dilution refrigerator stage can reduce the temperature of the input line to the q-circuit, while another dilution refrigerator stage located downstream in the series of dilution refrigerator stages can house the q-circuit.

[0014] The signals on the wires passing through the stage may contain noise. This noise may be in the microwave spectrum. For the reasons described in this article, microwave-frequency noise is undesirable when the wires and signals are used for quantum computing using q-circuits.

[0015] Flip chip assembly is a method of interconnecting an electronic device with an external circuit by depositing metal solder bumps on the electronic device's pads. The pads on the electronic device are aligned with matching pads on the external circuit.

[0016] The illustrative embodiments recognize certain shortcomings of currently available quantum device assembly methods. For example, in most cases, currently available methods do not provide the positional accuracy to ensure that pads on the electronic device are aligned with matching pads on the external circuit. In addition, currently available methods cannot effectively transfer heat away from the quantum device.

[0017] Therefore, there is a need in the art to address the aforementioned problems. Summary of the Invention

[0018] Viewed from a first aspect, the present invention provides a quantum device comprising: an insertion layer comprising a set of through-vias; a dielectric layer formed on a first side of the insertion layer, the dielectric layer comprising a set of transmission lines communicatively coupled to the set of through-vias; a plurality of qubit chips coupled to opposite sides of the insertion layer, each qubit chip comprising: a plurality of qubits on the first side of the qubit chip; and a plurality of protrusions on a second side of the qubit chip; and a heat sink thermally coupled to the plurality of qubit chips, the heat sink comprising a plurality of recesses aligned with the plurality of protrusions of the plurality of qubit chips.

[0019] Viewed from another aspect, the present invention provides a method comprising: forming an interposer layer comprising a set of vias; forming a dielectric layer on a first side of the interposer layer, the dielectric layer comprising a set of transmission lines communicatively coupled to the set of vias; forming a plurality of protrusions on a plurality of qubit chips; coupling the plurality of qubit chips to opposite sides of the interposer layer; and forming a plurality of recesses on a heat sink; coupling the plurality of qubit chips to the heat sink, the plurality of recesses being aligned with the plurality of protrusions.

[0020] Viewed from another aspect, the present invention provides a circuit fabrication system that performs operations comprising: forming an interposer layer comprising a set of vias; forming a dielectric layer on a first side of the interposer layer, the dielectric layer comprising a set of transmission lines communicatively coupled to the set of vias; forming a plurality of protrusions on a plurality of qubit chips; coupling the plurality of qubit chips to opposite sides of the interposer layer; and forming a plurality of recesses on a heat sink; coupling the plurality of qubit chips to the heat sink, the plurality of recesses being aligned with the plurality of protrusions.

[0021] Illustrative embodiments provide a quantum computing device and a method and system for manufacturing the same. The device of an embodiment includes an insertion layer comprising a set of through-holes. In one embodiment, the quantum device includes a dielectric layer formed on a first side of the insertion layer, the dielectric layer comprising a set of transmission lines communicatively coupled to the set of through-holes. In one embodiment, the quantum device includes a plurality of qubit chips coupled to opposite sides of the insertion layer, each qubit chip in the plurality of qubit chips comprising: a plurality of qubits on the first side of the qubit chip and a plurality of protrusions on a second side of the qubit chip.

[0022] In one embodiment, a quantum device includes a heat sink thermally coupled to a plurality of qubit chips, the heat sink including a plurality of recesses aligned with a plurality of protrusions of the plurality of qubit chips. In one embodiment, the device includes a signal connector communicatively connected to the set of transmission lines. In one embodiment, the plurality of protrusions are shaped to self-align with the plurality of recesses. In one embodiment, the device includes a second heat sink coupled to the dielectric layer. In one embodiment, the plurality of protrusions have a pyramidal shape.

[0023] In one embodiment, the device includes a first set of pads on the plurality of qubit chips, each pad connected to a corresponding qubit. In one embodiment, the device includes a second set of pads on the interposer layer, the second set of pads being formed over the vias.

[0024] In one embodiment, the device includes a first layer disposed on a second set of solder pads. In one embodiment, the device includes a set of solder bumps disposed on the first layer, the set of solder bumps configured to bond the first set of solder pads to the second set of solder pads. In one embodiment, the set of solder bumps is at least one selected from the group consisting of indium, tin, and bismuth. In one embodiment, the second layer is at least one selected from the group consisting of titanium and gold.

[0025] In one embodiment, the device includes a first layer disposed on a plurality of protrusions of a plurality of qubit chips. In one embodiment, a second layer is disposed on a plurality of recesses of a heat sink. In one embodiment, the first layer is a layer selected from at least one of the group consisting of titanium, silver, copper, platinum, and gold. In one embodiment, the second layer is a layer selected from at least one of the group consisting of titanium, silver, copper, platinum, and gold.

[0026] Embodiments include a manufacturing method for manufacturing a device. In one embodiment, the method includes forming an insertion layer including a set of through-holes. In one embodiment, the method includes forming a dielectric layer formed on a first side of the insertion layer, the dielectric layer including a set of transmission lines communicatively coupled to the set of through-holes. In one embodiment, the method includes forming a plurality of protrusions on a plurality of qubit chips.

[0027] In one embodiment, the method includes coupling a plurality of qubit chips to opposite sides of an interposer layer. In one embodiment, the method includes forming a plurality of recesses on a heat sink.

[0028] In one embodiment, the method includes coupling a plurality of qubit chips to a heat sink, with the plurality of recesses aligned with the plurality of protrusions.

[0029] In one embodiment, the method includes communicatively coupling a signal connector to the set of transmission lines. In one embodiment, the method includes attaching a handle to the dielectric layer using a temporary adhesive to thin the interposer layer and expose the set of vias on opposite sides. In one embodiment, the method includes detaching the handle from the interposer layer after bonding the plurality of qubit chips to the interposer layer.

[0030] In one embodiment, the method includes depositing a first set of pads on the plurality of qubit chips. In one embodiment, the method includes depositing a second set of pads on the interposer layer, the second set of pads being deposited over the vias. In one embodiment, the method includes depositing a first layer over the second set of pads. In one embodiment, the method includes depositing a set of solder bumps on the first layer, the set of solder bumps being configured to bond the first set of pads to the second set of pads.

[0031] In one embodiment, the method includes depositing a first layer on a plurality of protrusions of a plurality of qubit chips. In one embodiment, the method includes depositing a second layer on a plurality of recesses of a heat sink.

[0032] In one embodiment, the first layer is a layer selected from the group consisting of titanium, silver, copper, platinum, and gold. In one embodiment, the second layer is a layer selected from the group consisting of titanium, silver, copper, platinum, and gold. In one embodiment, the shape of the plurality of protrusions is configured to self-align with the plurality of recesses.

[0033] Embodiments include a manufacturing system for manufacturing a device. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The novel features characteristic of the invention are set forth in the appended claims. However, the invention itself, its preferred mode of use, further objects and advantages will be best understood from the following detailed description of illustrative embodiments read in conjunction with the accompanying drawings, in which:

[0035] Figure 1 depicts a block diagram of a network of data processing systems in which the illustrative embodiments may be implemented;

[0036] Figure 2 depicts a block diagram of a data processing system in which the illustrative embodiments may be implemented;

[0037] Figure 3 depicts a block diagram of an example qubit chip in accordance with an illustrative embodiment;

[0038] Figure 4 Depicted is a block diagram of an example qubit chip configuration in accordance with an illustrative embodiment.

[0039] Figure 5 A block diagram of an example heat sink configuration is depicted in accordance with an illustrative embodiment.

[0040] Figure 6 A block diagram of an example heat sink configuration is depicted in accordance with an illustrative embodiment.

[0041] Figure 7 depicts a block diagram of an example heat sink configuration in accordance with an illustrative embodiment;

[0042] Figure 8 A block diagram of an example configuration is depicted in accordance with an illustrative embodiment.

[0043] Figure 9 depicts a block diagram of an example configuration according to an illustrative embodiment;

[0044] Figure 10 depicts a block diagram of an example configuration according to an illustrative embodiment;

[0045] Figure 11 depicts a block diagram of an example configuration according to an illustrative embodiment;

[0046] Figure 12 depicts a block diagram of an example configuration according to an illustrative embodiment;

[0047] Figure 13 depicts a block diagram of an example configuration according to an illustrative embodiment;

[0048] Figure 14 depicts a block diagram of an example configuration according to an illustrative embodiment;

[0049] Figure 15 depicts a block diagram of an example configuration according to an illustrative embodiment;

[0050] Figure 16 depicts a block diagram of an example flip-chip configuration in accordance with an illustrative embodiment;

[0051] Figure 17 depicts a block diagram of an example flip-chip configuration in accordance with an illustrative embodiment;

[0052] Figure 18 depicts a block diagram of an example flip-chip configuration in accordance with an illustrative embodiment;

[0053] Figure 19 depicts a flow chart of a qubit chip formation process according to an illustrative embodiment;

[0054] Figure 20 depicts a flow chart of a process for forming an interposer layer according to an illustrative embodiment; and

[0055] Figure 21 A flowchart of a qubit chip formation process is depicted in accordance with an illustrative embodiment. DETAILED DESCRIPTION

[0056] The illustrative embodiments used to describe the present invention generally address and solve the above-mentioned needs for quantum device assembly. The illustrative embodiments provide a method for quantum device assembly that solves the above-mentioned needs or problems.

[0057] Operations described herein that occur with respect to a frequency or frequencies should be interpreted as operations that occur with respect to a signal at that frequency or frequencies. Unless explicitly used to the contrary, all references to "signal" are references to microwave signals.

[0058] An embodiment of the present invention provides a configuration for a signal connector for a microwave circuit. Another embodiment of the present invention provides a design / construction method for a signal connector, which can be implemented as a software application. The application implementing the design / construction method embodiment can be configured for use in conjunction with existing circuit manufacturing systems (e.g., circuit assembly systems).

[0059] For clarity of description and not intended to limit any aspect thereof, embodiments of the present invention are described using some example configurations. Based on this disclosure, one of ordinary skill in the art will be able to conceive of many variations, adaptations, and modifications of the described configurations for achieving the described objectives, and these variations, adaptations, and modifications are contemplated within the scope of the present invention.

[0060] In addition, simplified diagrams of example device components are used in the figures and example embodiments. In actual manufacturing or circuits, additional structures or components not shown or described herein may be present, or other structures or components that are different from the structures or components shown but have similar functions as described herein, without departing from the scope of the present invention.

[0061] Furthermore, while embodiments of the present invention have been described with respect to specific actual or hypothetical components only as examples, the steps described herein may be adapted to fabricate circuits using a variety of components that may be intended or re-intended to provide the described functionality within a signal connector for a microwave circuit, and such adaptations are considered within the scope of the present invention.

[0062] The illustrative embodiments are described with respect to certain types of materials, electrical characteristics, steps, quantities, frequencies, circuits, components, and applications, by way of example only. Any particular representation of these and other similar artifacts is not intended to limit the present invention. Any suitable representation of these and other similar artifacts may be selected within the scope of the illustrative embodiments.

[0063] The examples in this disclosure are provided for clarity of description only and are not intended to limit the present invention. Any advantages listed herein are merely examples and are not intended to limit the present invention. Additional or different advantages may be achieved by specific embodiments of the present invention. Furthermore, specific illustrative embodiments of the present invention may have some, all, or none of the advantages listed above.

[0064] With reference to the accompanying drawings, in particular with reference to Figure 1 and 2 , these figures are illustrative diagrams of data processing environments in which illustrative embodiments may be implemented. Figure 1 and Figure 2 This is merely an example and is not intended to assert or imply any limitation with regard to the environments in which different embodiments may be implemented. Specific implementations may make many modifications to the depicted environments based on the following description.

[0065] Figure 1 A block diagram depicts a network of data processing systems in which the illustrative embodiments may be implemented. Data processing environment 100 is a network of computers in which the illustrative embodiments may be implemented. Data processing environment 100 includes network 102. Network 102 is a medium used to provide communication links between various devices and computers connected together in data processing environment 100. Network 102 may include connections such as wired, wireless communication links, or fiber optic cables.

[0066] Client or server are merely example roles for certain data processing systems connected to network 102 and are not intended to exclude other configurations or roles of these data processing systems. Server 104 and server 106 are coupled to network 102 along with storage unit 108. Software applications may be executed on any computer in data processing environment 100. Clients 110, 112, and 114 are also coupled to network 102. Data processing systems such as servers 104 or 106 or clients 110, 112, or 114 may contain data and may execute software applications or software tools thereon.

[0067] Device 132 is an example of a mobile computing device. For example, device 132 may take the form of a smartphone, a tablet computer, a laptop computer, a fixed or portable form of client 110, a wearable computing device, or any other suitable device. Figure 1 Any software application executed in another data processing system in is configured to execute in device 132 in a similar manner. Figure 1 Any data or information stored or generated in another data processing system in may be configured to be stored or generated in device 132 in a similar manner.

[0068] Application 105 implements the embodiments described herein. Fabrication system 107 is any suitable system for fabricating quantum devices. Application 105 provides instructions to system 107 for flip-chip assembly of quantum devices in the manner described herein.

[0069] refer to Figure 2 , which depicts a block diagram of a data processing system in which the illustrative embodiments may be implemented. Data processing system 200 is an example of a computer, such as Figure 1 Servers 104 and 106 or clients 110, 112, and 114, or another type of device, may have computer usable program code or instructions implementing the processes for the illustrative embodiments located therein.

[0070] Data processing system 200 also represents a data processing system or configuration thereof, such as Figure 1Data processing system 132 in which computer usable program code or instructions implementing the processes of the exemplary embodiments may be located. Data processing system 200 is described as a computer only as an example and is not limited thereto. Figure 1 Implementations in other device forms, such as device 132 in , may modify data processing system 200 by, for example, adding a touch interface, or even eliminating certain depicted components from data processing system 200 without departing from the general description of the operation and functionality of data processing system 200 described herein.

[0071] In the depicted example, data processing system 200 employs memory controller hub (NB / MCH) 202 and input / output (I / O) controller hub (SB / ICH) 204. Processing unit 206, main memory 208, and graphics processor 210 are coupled in the exemplary manner shown in the figure. Local area network (LAN) adapter 212, audio adapter 216, keyboard and mouse adapter 220, modem 222, read-only memory (ROM) 224, universal serial bus (USB) and other ports 232, and PCI / PCIe devices 234 are coupled via bus 238. Hard disk drive (HDD) or solid-state drive (SSD) 226 and CD-ROM 230 are coupled via bus 240. Super I / O (SIO) device 236 may be coupled via bus 238.

[0072] Memories such as main memory 208, ROM 224, or flash memory (not shown) are some examples of computer-usable storage devices. Hard disk drives or solid-state drives 226, CD-ROMs 230, and other similarly available devices are some examples of computer-usable storage devices, including computer-usable storage media.

[0073] Used for example Figure 1 Instructions for an application or program, such as application 105 in FIG. 2 , are located on a storage device, such as in the form of code 226A on hard drive 226, and may be loaded into at least one of one or more memories, such as main memory 208, for execution by processing unit 206. The processes of the illustrative embodiments may be performed by processing unit 206 using computer-implemented instructions, which may be located in a memory, such as main memory 208, read-only memory 224, or in one or more peripheral devices.

[0074] Furthermore, in one instance, code 226A can be downloaded from remote system 201B via network 201A, where similar code 201C is stored on storage device 201D. In another instance, code 226A can be downloaded to remote system 201B via network 201A, where downloaded code 201C is stored on storage device 201D.

[0075] Figure 1-2 The hardware in the may vary depending on the implementation. Other internal hardware or peripheral devices, such as flash memory, equivalent non-volatile memory, or optical disk drives, may be used in addition to or instead of Figure 1-2 Additionally, the processes of the illustrative embodiments may be applied to a multi-processor data processing system.

[0076] refer to Figure 3 , which depicts a block diagram of an exemplary qubit chip in accordance with an illustrative embodiment. Figure 1 Applications 105 in interact with manufacturing system 107 to produce or manipulate configuration 300 described herein.

[0077] Configuration 300 includes a substrate 302. Substrate 302 includes a material having a high thermal conductivity (above a threshold) in a cryogenic temperature range. In one embodiment, substrate 302 is formed using a material that exhibits a residual resistivity (RRR) of at least 100 and a thermal conductivity greater than 1 W / (cm*K) at a threshold thermal conductivity level of 4 Kelvin. The RRR is the ratio of the resistivity of a material at room temperature and at 0K. Since 0K cannot be achieved in practice, an approximate value of 4K is used. For example, sapphire, silicon, quartz, gallium arsenide, fused silica, amorphous silicon, or diamond can be used to form substrate 302 to operate in a temperature range of 77K to 0.01K. These examples of substrate materials are not intended to be limiting. Based on this disclosure, one of ordinary skill in the art will be able to conceive of many other materials suitable for forming the substrate, and such materials are contemplated within the scope of the exemplary embodiments.

[0078] Configuration 300 also includes at least one pad 304 and at least one junction 306. One embodiment enables a manufacturing system, e.g. Figure 1In the manufacturing system 107 in, a structure (formation) 310 is formed on the back side of the chip 300. For example, the grinding device 308 can be configured to remove a portion of the substrate 302 to form the structure 310. As another example, deep reactive ion etching can be used to form the structure 310. In one embodiment, the structure 310 includes a triangular cross-section. In one embodiment, the structure 310 includes a plurality of protrusions. In one embodiment, the milling device 306 is a micro-milling device having a diamond milling cutter or a laser milling cutter. These examples of milling devices are not intended to be limiting. In light of this disclosure, one of ordinary skill in the art will be able to conceive of many other milling devices suitable for forming structures on the back side of the qubit chip, and such structures are contemplated within the scope of the exemplary embodiments. In addition, in light of this disclosure, one of ordinary skill in the art will be able to conceive of many other devices and methods suitable for forming structures in the back side of the qubit chip, and such devices and methods are contemplated within the scope of the exemplary embodiments.

[0079] In one embodiment, substrate 302 is a portion of a wafer substrate that includes a set of qubit chips. In one embodiment, each qubit chip in the set of qubit chips includes at least one pad and at least one junction. In one embodiment, each qubit chip includes a plurality of qubits. One embodiment causes a manufacturing system, such as manufacturing system 107, to form structure 310 on the back side of the wafer substrate. For example, grinding device 308 can remove material from the wafer substrate to form structure 310 on the back side of the wafer substrate. As another example, deep reactive ion etching or anisotropic chemical etching can be used to form structure 310 on the back side of the wafer substrate.

[0080] refer to Figure 4 , which depicts a block diagram of an exemplary qubit chip configuration in accordance with an illustrative embodiment. Figure 1 Application 105 in interacts with manufacturing system 107 to produce or manipulate configuration 400 described herein.

[0081] The embodiment causes the manufacturing system to deposit material 406 to form a first layer 410. The first layer 410 includes a material 406 having a high thermal conductivity (above a threshold) in the cryogenic temperature range. In one embodiment, the first layer 410 is formed using a material that exhibits an RRR of at least 100 and has a thermal conductivity greater than 1 W / (cm*K) at a thermal conductivity threshold level of 4 Kelvin. For example, the first layer 410 can be formed using gold, silver, copper, titanium, or platinum to operate in a temperature range of 77K to 0.01K. These examples of layer materials are not intended to be limiting. Based on this disclosure, one of ordinary skill in the art will be able to conceive of many other materials suitable for forming the first layer, and such materials are contemplated within the scope of the illustrative embodiments.

[0082] In one embodiment, a first layer 410 is deposited on the back side of the configuration 400. For example, the first layer 410 can be a thin film deposition of particles 408 on the structure 404. In one embodiment, the first layer 410 comprises a thickness in the range of approximately 10 nm to 1000 nm, inclusive. This example of a deposition method is not intended to be limiting. Based on this disclosure, one of ordinary skill in the art will be able to identify many other methods and processes suitable for forming the first layer, and such methods and processes are contemplated within the scope of the illustrative embodiments.

[0083] refer to Figure 5 , which depicts a block diagram of an example heat sink configuration in accordance with an illustrative embodiment. Figure 1 Application 105 in interacts with manufacturing system 107 to produce or manipulate configuration 500 described herein.

[0084] Configuration 500 includes a heat sink 502. Heat sink 502 includes a material having a high thermal conductivity (above a threshold) in a cryogenic temperature range. In one embodiment, heat sink 502 is formed using a material that exhibits an RRR of at least 100 and a thermal conductivity greater than 1 W / (cm*K) at a thermal conductivity threshold level of 4 Kelvin. For example, heat sink 502 can be formed using gold, silver, copper, or aluminum in a temperature range of 77K to 0.01K. These examples of heat sink materials are not intended to be limiting. Based on this disclosure, one of ordinary skill in the art will be able to conceive of many other materials suitable for forming a heat sink, and such materials are contemplated within the scope of the exemplary embodiments.

[0085] Embodiments enable manufacturing systems such as Figure 1 In the manufacturing system 107 in, a structure 506 is formed on the surface of the heat sink 502. For example, the milling device 504 can be configured to remove a portion of the heat sink 502 to form the structure 506. As another example, etching can be used to form the structure 506. In one embodiment, the structure 506 includes a triangular cutout. In one embodiment, the structure 506 includes a plurality of recesses. In one embodiment, the milling device 504 is a micro-milling device having a diamond milling cutter or a laser milling cutter. These examples of milling devices are not intended to be limiting. In light of this disclosure, one of ordinary skill in the art will be able to conceive of many other milling devices suitable for forming structures on a heat sink, and such devices are contemplated within the scope of the exemplary embodiments. In addition, in light of this disclosure, one of ordinary skill in the art will be able to conceive of many other devices and methods suitable for forming structures on a heat sink, and such devices and methods are contemplated within the scope of the exemplary embodiments.

[0086] refer to Figure 6 , which depicts a block diagram of an example heat sink configuration in accordance with an illustrative embodiment. Figure 1 Application 105 in interacts with manufacturing system 107 to produce or manipulate configuration 600 described herein.

[0087] The embodiment causes the manufacturing system to deposit material 606 to form a first layer 610. The first layer 610 includes a material 606 having a high thermal conductivity (above a threshold) in the cryogenic temperature range. In one embodiment, the first layer 610 is formed using a material that exhibits an RRR of at least 100 and has a thermal conductivity greater than 1 W / (cm*K) at a thermal conductivity threshold level of 4 Kelvin. For example, the first layer 610 can be formed using gold, silver, copper, titanium, or platinum to operate in a temperature range of 77K to 0.01K. These examples of layer materials are not intended to be limiting. Based on this disclosure, one of ordinary skill in the art will be able to conceive of many other materials suitable for forming the first layer, and such materials are contemplated within the scope of the illustrative embodiments.

[0088] In one embodiment, a first layer 610 is deposited on the heat sink 602 of the configuration 600. For example, the first layer 610 can be a thin film deposition of particles 608 on the structure 604. In one embodiment, the first layer 610 comprises a thickness in the range of approximately 10 nm to 1000 nm, inclusive. This example of a deposition method is not intended to be limiting. Based on this disclosure, one of ordinary skill in the art will be able to identify many other methods and processes suitable for forming the first layer, and such methods and processes are contemplated within the scope of the illustrative embodiments.

[0089] refer to Figure 7 , which depicts a block diagram of an example heat sink configuration in accordance with an illustrative embodiment. Figure 1 Application 105 in interacts with manufacturing system 107 to generate or manipulate configuration 700 as described herein.

[0090] An embodiment provides a manufacturing system to couple a set of qubit chips 704, 706, 708 to a heat sink 702. In one embodiment, qubit chips 704, 706, 708 are similar to Figure 4 In one embodiment, the heat sink 702 is similar to Figure 6 Heat sink 602 in FIG. Qubit chips 704, 706, and 708 include structure 710. Heat sink 702 includes structure 712. In one embodiment, structure 712 corresponds to a complementary shape of structure 710. For example, structure 712 includes a plurality of recesses configured to accommodate a plurality of protrusions of structure 710. In one embodiment, structure 710 is configured to self-align a corresponding qubit chip with a corresponding coupling site of structure 712 during coupling. For example, a manufacturing system can compressively bond structure 710 within structure 712.

[0091] refer to Figure 8 , which depicts a block diagram of an example configuration in accordance with an illustrative embodiment. Figure 1 Application 105 in interacts with manufacturing system 107 to produce or manipulate configuration 800 described herein.

[0092] Configuration 800 includes a substrate 802. The substrate 802 includes a material having a high thermal conductivity (above a threshold) in the cryogenic temperature range. In one embodiment, the substrate 802 is formed using a material that exhibits an RRR of at least 100 and has a thermal conductivity greater than 1 W / (cm*K) at a thermal conductivity threshold level of 4 Kelvin. For example, sapphire, silicon, quartz, gallium arsenide, fused silica, amorphous silicon, or diamond can be used to form the substrate 802 to operate in the temperature range of 77K to 0.01K. These examples of substrate materials are not intended to be limiting. Based on this disclosure, one of ordinary skill in the art will be able to conceive of many other materials suitable for forming the substrate, and such materials are contemplated within the scope of the exemplary embodiments.

[0093] Embodiments enable manufacturing systems such as Figure 1 In the manufacturing system 107 in, a structure 806 is formed on a substrate 802. For example, a milling device 804 can be configured to remove a portion of the substrate 802 to produce the structure 806. As another example, deep reactive ion etching can be used to produce the structure 806. In one embodiment, the structure 806 includes a plurality of recesses. For example, the structure 806 can include a plurality of rectangular grooves in the substrate 802. In one embodiment, the milling device 804 is a micro-milling device having a diamond milling cutter or a laser milling cutter. These examples of milling devices are not intended to be limiting. In light of this disclosure, one of ordinary skill in the art will be able to conceive of many other milling devices suitable for forming structures on substrates, and such devices are contemplated within the scope of the exemplary embodiments. In addition, in light of this disclosure, one of ordinary skill in the art will be able to conceive of many other devices and methods suitable for forming structures in substrates, and such devices and methods are contemplated within the scope of the exemplary embodiments.

[0094] refer to Figure 9 , which depicts a block diagram of an example configuration in accordance with an illustrative embodiment. Figure 1 Application 105 in interacts with manufacturing system 107 to produce or manipulate configuration 900 described herein.

[0095] The embodiment enables the manufacturing system to deposit materials to form the plurality of vias 906. For example, the plurality of vias 906 can be formed using tungsten, indium, copper, or tin to operate in a temperature range of 77K to 0.01K. These examples of layer materials are not intended to be limiting. Based on this disclosure, one of ordinary skill in the art will be able to identify many other materials suitable for forming the plurality of vias, and such materials are contemplated within the scope of the exemplary embodiments.

[0096] In one embodiment, a plurality of through-holes 906 are deposited in recesses of structure 904 in substrate 902. For example, the plurality of through-holes 906 can be formed by electroplating or injection mold soldering (IMS). This example of a deposition method is not intended to be limiting. Based on this disclosure, one of ordinary skill in the art will be able to identify many other methods and processes suitable for forming the plurality of through-holes, and such methods and processes are contemplated within the scope of the exemplary embodiments.

[0097] refer to Figure 10 , which depicts a block diagram of an example configuration in accordance with an illustrative embodiment. Figure 1 Applications 105 in interact with manufacturing system 107 to produce or manipulate configuration 1000 described herein.

[0098] The embodiment causes the manufacturing system to deposit materials to form the second layer 1006. The second layer 1006 includes a stack of dielectric materials. These examples of layer materials are not intended to be limiting. Based on this disclosure, one of ordinary skill in the art will be able to identify many other materials suitable for forming the second layer, and such materials are contemplated within the scope of the exemplary embodiments.

[0099] In one embodiment, the second layer 1006 is deposited on the substrate (interposer) 1002. For example, the second layer 1006 can be formed by spin coating. This example of a deposition method is not intended to be limiting. Based on this disclosure, one of ordinary skill in the art will be able to conceive of many other methods and processes suitable for forming the second layer, and these methods and processes are contemplated within the scope of the exemplary embodiments. A set of transmission lines 1008 is connected to the plurality of vias 1004. In one embodiment, the set of transmission lines 1008 is formed using copper. In one embodiment, the set of transmission lines is exposed to provide signal connection points.

[0100] refer to Figure 11 , which depicts a block diagram of an example configuration in accordance with an illustrative embodiment. Figure 1 Applications 105 in interact with manufacturing system 107 to produce or manipulate configuration 1100 described herein.

[0101] The embodiment provides for a manufacturing system to couple a third layer (handle) 1108 to the second layer 1104. In one embodiment, the third layer 1108 is formed using glass or silicon. These examples of layer materials are not intended to be limiting. Based on this disclosure, one of ordinary skill in the art will be able to identify many other materials suitable for forming the first layer, and such materials are contemplated within the scope of the illustrative embodiments.

[0102] In one embodiment, handle (third layer) 1108 is bonded to second layer 1104 via adhesive layer 1110. In one embodiment, adhesive layer 1110 is a temporary adhesive. This example of a bonding method is not intended to be limiting. Based on this disclosure, one of ordinary skill in the art will be able to devise many methods and materials suitable for bonding the third layer to the second layer, and such methods and materials are contemplated within the scope of the exemplary embodiments.

[0103] refer to Figure 12 , which depicts a block diagram of an example configuration in accordance with an illustrative embodiment. Figure 1 Application 105 in interacts with manufacturing system 107 to produce or manipulate configuration 1200 described herein.

[0104] Configuration 1200 includes a substrate 1202. Substrate 1202 includes a material having a high thermal conductivity (above a threshold) in a cryogenic temperature range. In one embodiment, substrate 1202 is formed using a material that exhibits an RRR of at least 100 and has a thermal conductivity greater than 1 W / (cm*K) at a thermal conductivity threshold level of 4 Kelvin. For example, substrate 1202 can be formed using sapphire, silicon, quartz, gallium arsenide, fused silica, amorphous silicon, or diamond to operate in a temperature range of 77K to 0.01K. These examples of substrate materials are not intended to be limiting. Based on this disclosure, one of ordinary skill in the art will be able to conceive of many other materials suitable for forming the substrate, and such materials are contemplated within the scope of the exemplary embodiments.

[0105] Embodiments enable a manufacturing system (e.g., Figure 1The manufacturing system 107 in FIG. 1 reduces the thickness of substrate 1202. For example, milling device 1208 can be configured to remove a portion of substrate 1202. As another example, deep reactive ion etching can be used to remove a portion of substrate 1202. In one embodiment, the milling device removes a portion of substrate 1202 to expose a set of through-holes 1210. For example, milling device 1208 can be configured to reduce the thickness of substrate 1208 until the surface of substrate 1208 is substantially flush with the surface of set of through-holes 1210, for example, within 5 percent. In one embodiment, milling device 1208 is a micro-milling device having a diamond milling cutter or a laser milling cutter. As another example, chemical mechanical polishing methods can be used to grind 1202. These examples of milling devices are not intended to be limiting. Based on this disclosure, one of ordinary skill in the art will be able to identify many other milling devices suitable for reducing the thickness of a substrate, and such devices are contemplated within the scope of the exemplary embodiments. Furthermore, based on this disclosure, one of ordinary skill in the art will be able to identify many other devices and methods suitable for reducing the thickness of a substrate, and such devices and methods are contemplated within the scope of the exemplary embodiments.

[0106] refer to Figure 13 , which depicts a block diagram of an example configuration in accordance with an illustrative embodiment. Figure 1 Application 105 in interacts with manufacturing system 107 to produce or manipulate configuration 1300 described herein.

[0107] An embodiment causes a manufacturing system to deposit material 1306 to form a set of pads 1310 and a set of resonators 1312. In one embodiment, material 1306 is a thin film deposition of particles 1308. For example, a set of pads 1310 may be deposited on the set of vias 1304.

[0108] refer to Figure 14 , which depicts a block diagram of an example configuration in accordance with an illustrative embodiment. Figure 1 Application 105 in interacts with manufacturing system 107 to produce or manipulate configuration 1400 described herein.

[0109] The embodiment causes the manufacturing system to deposit material 1404 to form a first layer 1408 on a set of pads 1402. In one embodiment, first layer 1408 is formed using at least one of titanium, palladium, gold, silver, copper, or platinum to operate within a temperature range of 77K to 0.01K. These examples of first layer materials are not intended to be limiting. Based on this disclosure, one of ordinary skill in the art will be able to identify many other materials suitable for forming the first layer, and such materials are contemplated within the scope of the illustrative embodiments.

[0110] In one embodiment, first layer 1408 is deposited on set of pads 1402. For example, first layer 1408 is a thin film deposition of particles 1406. As another example, first layer 1408 is deposited by sputtering. As yet another example, first layer 1408 is deposited by under-bump metallurgy (UBM). These examples of deposition methods are not intended to be limiting. Based on this disclosure, one of ordinary skill in the art will be able to identify many other methods and processes suitable for forming the first layer, and such methods and processes are contemplated within the scope of the illustrative embodiments.

[0111] refer to Figure 15 , which depicts a block diagram of an example configuration in accordance with an illustrative embodiment. Figure 1 Application 105 in interacts with manufacturing system 107 to produce or manipulate configuration 1500 described herein.

[0112] The embodiment causes the manufacturing system to deposit material 1504 to form a second layer 1508 on the first layer 1502. In one embodiment, the second layer 1508 is a set of solder bumps. In one embodiment, the second layer 1508 is formed using indium, tin, and bismuth to operate within a temperature range of 77K to 0.01K. In one embodiment, the second layer 1508 is indium bumps. This example of the first layer material is not intended to be limiting. Based on this disclosure, one of ordinary skill in the art will be able to identify many other materials suitable for forming the second layer, and such materials are contemplated within the scope of the illustrative embodiments.

[0113] In one embodiment, second layer 1508 is deposited on first layer 1502. For example, second layer 1508 is an IMS deposition of particles 1506. This example of a deposition method is not intended to be limiting. Based on this disclosure, one of ordinary skill in the art will be able to identify many other methods and processes suitable for forming the first layer, and these methods and processes are contemplated within the scope of the illustrative embodiments.

[0114] refer to Figure 16 , which depicts a block diagram of an example flip-chip configuration in accordance with an illustrative embodiment. Figure 1 Application 105 in interacts with manufacturing system 107 to produce or manipulate configuration 1600 described herein.

[0115] An embodiment enables a manufacturing system to couple multiple qubit chips to an interposer 1602. In one embodiment, qubit chip 1608 is similar to Figure 4 In one embodiment, the heat sink 1610 is similar to Figure 6 In one embodiment, the second layer 1604 is similar to Figure 10 In one embodiment, the third layer 1606 is similar to Figure 11 In one embodiment, the manufacturing system compression bonds a set of pads of the qubit chip to a set of pads of the interposer layer 1602 at a set of indium bumps 1612.

[0116] refer to Figure 17 , which depicts a block diagram of an example flip-chip configuration in accordance with an illustrative embodiment. Figure 1 Application 105 in interacts with manufacturing system 107 to produce or manipulate configuration 1700 described herein.

[0117] An embodiment enables the manufacturing system to decouple the third layer from the second layer 1704. In one embodiment, the adhesive material bonding the third layer to the second layer 1704 is removed from the surface of the second layer 1704. In one embodiment, a set of resonators 1712 is aligned with a corresponding set of junctions 1714.

[0118] refer to Figure 18 , which depicts a block diagram of an example flip-chip configuration in accordance with an illustrative embodiment. Figure 1 Application 105 in interacts with manufacturing system 107 to produce or manipulate configuration 1800 described herein.

[0119] An embodiment provides for a manufacturing system to couple a heat sink 1806 and a signal connector 1808 to the configuration 1800. The heat sink 1806 comprises a material having a high thermal conductivity (above a threshold) in a cryogenic temperature range. In one embodiment, the heat sink 1806 is formed using a material that exhibits an RRR of at least 100 and has a thermal conductivity greater than 1 W / (cm*K) at a thermal conductivity threshold level of 4 Kelvin. For example, the heat sink 1806 can be formed using gold, silver, copper, or aluminum for operation in a temperature range of 77K to 0.01K. These examples of heat sink materials are not intended to be limiting. Based on this disclosure, one of ordinary skill in the art will be able to conceive of many other materials suitable for forming a heat sink, and such materials are contemplated within the scope of the exemplary embodiments.

[0120] In one embodiment, heat sink 1806 is disposed between signal connector 1808 and second layer 1804. In one embodiment, signal connector 1808 is coupled to heat sink 1810 via a set of fasteners 1812. Signal connector 1808 is connected to a set of transmission lines 1814 at pins 1816. Signal connector 1808 is configured to transmit qubit signals from transmission lines 1814 to external circuitry for signal processing.

[0121] refer to Figure 19 , which depicts a flow chart of a process for forming a qubit chip according to an illustrative embodiment. Process 1900 may be performed at Figure 1105 is implemented in the application to form a heat sink and a qubit chip as described above. Figure 3 、 4 , 5, 6 and 7 described structures.

[0122] The application causes the manufacturing system to etch a structure in the heat sink (block 1902). In one embodiment, the application causes the manufacturing system to form a plurality of recesses in the heat sink. The application causes the manufacturing system to deposit a first layer on the heat sink (block 1904). In one embodiment, the application causes the manufacturing system to deposit the first layer on the plurality of recesses. The application causes the manufacturing system to etch a structure in the qubit chip (block 1906). In one embodiment, the application causes the manufacturing system to form a plurality of protrusions on the plurality of qubit chips. The application causes the manufacturing system to deposit a second layer on the qubit chip (block 1908). In one embodiment, the application causes the manufacturing system to deposit the second layer on the plurality of protrusions. The application causes the manufacturing system to couple the qubit chip and the heat sink (block 1910). In one embodiment, the application causes the manufacturing system to couple the plurality of qubit chips to the heat sink. Thereafter, the application ends process 1900.

[0123] refer to Figure 20 , which depicts a flow chart of a process for forming an interposer layer according to an illustrative embodiment. Process 2000 may be performed in Figure 1 105 is implemented in the application to form a heat sink and a qubit chip as described above. Figure 8 、 9 , 10, 11, 12, 13, 14 and 15 described structures.

[0124] The application causes the manufacturing system to etch a structure in a substrate (interposer layer) (block 2002). In one embodiment, the application causes the manufacturing system to form a plurality of recesses in the substrate. The application causes the manufacturing system to fill the structure in the substrate (block 2004). In one embodiment, the application causes the manufacturing system to fill the plurality of recesses in the substrate. The application causes the manufacturing system to connect a transmission line in a dielectric layer to the filled structure (block 2006). The application causes the manufacturing system to couple (attach) a handle (third layer) to the dielectric layer (block 2008). The application causes the manufacturing system to etch the substrate to expose the filled structure (block 2010). The application causes the manufacturing system to form a set of resonators on the substrate (block 2012). The application causes the manufacturing system to form a set of pads on the filled structure (block 2014). The application causes the manufacturing system to deposit a first layer on the set of resonators (block 2016). The application causes the manufacturing system to deposit a second layer on the set of resonators (block 2018). Thereafter, the application ends process 2000.

[0125] refer to Figure 21 , which depicts a flow diagram of a qubit chip formation process in accordance with an illustrative embodiment.

[0126] Process 2100 can be Figure 1 is implemented in application 105 to form a heat sink and a qubit chip as described above. Figure 16 、 17 and the structure described in 18.

[0127] The application causes the manufacturing system to form an electrical connection between the substrate package and the qubit chip package (block 2102). The application causes the manufacturing system to separate the handle from the dielectric layer (block 2104). The application causes the manufacturing system to remove the adhesive from the dielectric layer (block 2106). The application causes the manufacturing system to attach the heat sink to the substrate package (block 2108). The application causes the manufacturing system to form an electrical connection between the signal connector and the substrate package (block 2110). Thereafter, the application ends process 2100.

[0128] Various embodiments of the present invention are described herein with reference to the relevant drawings. Alternative embodiments of the present invention may be designed without departing from the scope of the present invention. Although various connections and positional relationships (e.g., above, below, adjacent, etc.) are set forth between elements in the following description and drawings, those skilled in the art will recognize that many of the positional relationships described herein are independent of orientation and can maintain the described functions even if the orientation is changed. Unless otherwise specified, these connections and / or positional relationships may be direct or indirect, and the present invention is not intended to be limited in this respect. Therefore, the coupling of entities may refer to direct or indirect coupling, and the positional relationship between entities may be direct or indirect positional relationship. As an example of an indirect positional relationship, it is mentioned in this specification that forming layer "A" on layer "B" includes the case where one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B", as long as the intermediate layer does not substantially change the relevant features and functions of layer "A" and layer "B".

[0129] The following definitions and abbreviations are used to interpret the claims and description. As used herein, the terms "comprises," "comprising," "including," "having," or any other variations thereof are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0130] Additionally, the term "illustrative" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "illustrative" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" should be understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "plurality" should be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connected" may include both indirect and direct connections.

[0131] References in the specification to "one embodiment," "an embodiment," "an example embodiment," etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment may or may not include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is understood that it is within the knowledge of those skilled in the art to be able to affect such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0132] The terms "approximately," "substantially," "substantially," and variations thereof are intended to include the degree of error associated with measurement of a particular quantity based on the equipment available at the time the application is filed. For example, "about" may include a range of ±8%, or 5%, or 2% of a given value.

[0133] The descriptions of various embodiments of the present invention have been provided for purposes of illustration, but are not intended to be exhaustive or limited to the disclosed embodiments of the invention. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments of the invention. The terminology used herein is selected to best explain the principles of the embodiments of the invention, practical applications or technical improvements to existing commercially available technologies, or to enable others skilled in the art to understand the invention as described herein.

Claims

1. A quantum device comprising: an interposer layer including a set of through holes; a dielectric layer formed on a first side of the interposer layer, the dielectric layer including a set of transmission lines communicatively coupled to the set of vias; A plurality of qubit chips coupled to opposite sides of the insertion layer, each qubit chip comprising: a plurality of qubits on a first side of the qubit chip; and a plurality of protrusions on a second side of the qubit chip; a first heat sink thermally coupled to the plurality of qubit chips, the first heat sink comprising a plurality of recesses aligned with the plurality of protrusions of the plurality of qubit chips and featuring a signal connector communicatively coupled to the set of transmission lines, and A second heat sink is coupled to the dielectric layer, the second heat sink being disposed between the signal connector and the dielectric layer, and the signal connector is coupled to the first heat sink via a set of fasteners.

2. The quantum device according to claim 1, wherein The shapes of the plurality of protrusions are configured to self-align the plurality of protrusions with the plurality of recesses.

3. The quantum device according to any one of claims 1-2, wherein the plurality of protrusions have a pyramid shape.

4. The quantum device according to any one of claims 1 to 2, further comprising: a first set of pads on the plurality of qubit chips, each pad being connected to a corresponding qubit; as well as A second set of pads is provided on the interposer layer, the second set of pads being formed on the through-holes.

5. The quantum device according to claim 4, further comprising: a first layer disposed on a second set of pads; as well as A set of solder bumps is disposed on the first layer, the set of solder bumps being configured to bond the first set of solder pads and the second set of solder pads. 6 . The quantum device according to claim 5 , wherein the set of solder bumps is at least one selected from the group consisting of indium, tin, and bismuth.

7. The quantum device according to any one of claims 1-2, further comprising: a first layer disposed on the plurality of protrusions of the plurality of qubit chips; as well as A second layer is disposed on the plurality of recesses of the heat sink. 8 . The quantum device according to claim 7 , wherein the first layer is a layer of at least one selected from the group consisting of titanium, silver, copper, platinum, and gold.

9. The quantum device according to claim 7, wherein the second layer is a layer selected from at least one of the group consisting of titanium, silver, copper, platinum, and gold.

10. A method for coupling a qubit chip to a heat sink, comprising: forming an interposer layer including a set of through holes; a dielectric layer formed on a first side of the interposer layer, the dielectric layer including a set of transmission lines communicatively coupled to the set of vias; forming a plurality of protrusions on the plurality of qubit chips; coupling a plurality of qubit chips to opposite sides of the insertion layer; and forming a plurality of recesses on the heat sink; as well as coupling the plurality of qubit chips to a heat sink, with the plurality of recesses aligned with the plurality of protrusions; and The characteristics are, communicatively coupling a signal connector to the set of transmission lines; as well as A second heat sink is coupled to the dielectric layer, the second heat sink is disposed between the signal connector and the dielectric layer, and the signal connector is coupled to the first heat sink via a set of fasteners.

11. The method according to claim 10, wherein: The shapes of the plurality of protrusions are configured to self-align the plurality of protrusions with the plurality of recesses.

12. The method according to claim 10 or 11, further comprising: attaching the handle to the dielectric layer using an adhesive; and The interposer is thinned to expose the set of vias on opposite sides of the interposer.

13. The method according to claim 12, further comprising: After coupling multiple qubit chips onto the insertion layer, the handle is separated from the insertion layer.

14. The method according to any one of claims 10-11, further comprising: depositing a first set of pads on the plurality of qubit chips; A second set of pads is deposited on the interposer layer, the second set of pads being deposited on the vias.

15. The method according to claim 14, further comprising: depositing a first layer on the second set of pads; A set of solder bumps is deposited on the first layer, the set of solder bumps being configured to bond the first set of pads and the second set of pads.

16. The method according to any one of claims 10-11, further comprising: depositing a first layer on the plurality of protrusions of the plurality of qubit chips; A second layer is deposited over the plurality of recesses of the heat sink. 17 . The method according to claim 16 , wherein the first layer is a layer of at least one selected from the group consisting of titanium, silver, copper, platinum, and gold.

18. The method according to claim 16, wherein the second layer is a layer of at least one selected from the group consisting of titanium, silver, copper, platinum, and gold.

Images