A computing control module based on dual FPGA and dynamic configuration method

Abstract

A computing control module based on dual FPGA and a dynamic configuration method, the computing control module based on dual FPGA includes a PCB substrate and a connector arranged on the PCB substrate; a core control unit including a central processing unit and a Nor Flash connected to the central processing unit; the central processing unit is connected to the connector via an SGMII communication port; a first data processing unit includes a first FPGA and a first Flash and a first memory respectively connected to the first FPGA; the first FPGA is respectively connected to the central processing unit and the Nor Flash; a second data processing unit includes a second FPGA and a second Flash and a second memory respectively connected to the second FPGA; the second FPGA is respectively connected to the connector, the central processing unit, and the first FPGA. The embodiment of the present invention can realize remote dynamic update of the first FPGA. When the first FPGA is used as the main unit for data processing, the time for function upgrade can be greatly reduced, which effectively saves manpower, material resources and time, and is suitable for industrial promotion.

Description

Technical Field

[0001] The present invention belongs to the field of electronic information technology, and in particular relates to a dual FPGA-based computing control module and a dynamic configuration method. Background Art

[0002] With the development of society, satellites have been widely used in military, civil, aerospace and other fields, and have become an indispensable component. The operation control system in the satellite and the various platforms supporting the satellite operation are the basis for the normal operation of the entire satellite. And these platforms inevitably need to use computer control modules. However, when the computer control modules currently used need to be configured and updated, most of them can only be updated locally by technicians, which requires a lot of manpower and a long time; at the same time, the use of technicians to perform local shutdown updates has great limitations. Once no technicians can arrive at the site for update in time, the platform may be paralyzed for a long time. If there is a problem with an important platform, it may cause the operation control of the entire satellite to fail, causing great losses. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes a dual FPGA-based computing control module, which solves the problem of requiring technicians to update locally and the time-consuming update. The present invention also proposes a dynamic configuration method.

[0004] According to the first aspect of the present invention, a dual FPGA-based computing control module includes a PCB substrate and:

[0005] Connectors;

[0006] A core control unit, comprising a central processing unit and a Nor Flash connected to the central processing unit; the central processing unit is connected to the connector via an SGMII communication port to obtain first dynamic configuration data; the NorFlash is used to store the first dynamic configuration data;

[0007] A first data processing unit includes a first FPGA and a first Flash and a first memory respectively connected to the first FPGA; the first FPGA is respectively connected to the central processor and the Nor Flash; the first Flash is used to write the first dynamic configuration data through the first FPGA;

[0008] The second data processing unit includes a second FPGA and a second Flash and a second memory respectively connected to the second FPGA; the second FPGA is respectively connected to the connector, the central processing unit, and the first FPGA, and is used to obtain second dynamic configuration data through the connector; the second Flash is used to write the second dynamic configuration data through the second FPGA.

[0009] According to the dual FPGA computing control module of the embodiment of the present invention, at least the following technical effects are achieved: after the first dynamic configuration data is obtained by the central processing unit, and the second dynamic configuration data is obtained by the second FPGA, it can be written into the Nor Flash, the first Flash, and the second Flash to realize the dynamic storage of the first dynamic configuration data and the second dynamic configuration data, and then when it is necessary to update, the first FPGA and the second FPGA can be directly controlled by the central processing unit to load the corresponding dynamic configuration data for updating, without the need for manual updating by technical personnel. At the same time, the first dynamic configuration data can be obtained at any time by the central processing unit and stored in the Nor Flash. At this time, the dual FPGA data processing structure composed of the first FPGA and the second FPGA can still work normally. It only needs to stop the first FPGA for a short time when the first FPGA loads the first dynamic configuration data. At this time, the second FPGA can still receive data without stopping the work of the entire computing control module, and the dynamic update of the first FPGA can be realized; in addition, although the update of the second FPGA cannot completely stop the work of the entire computing control module, the remote acquisition of the second dynamic configuration data by the central processing unit can still greatly save the manpower, material resources, and time costs required for the update. The dual-FPGA-based computing control module of the embodiment of the present invention can realize remote dynamic update of the first FPGA. When the first FPGA is used as the main unit for data processing, the time for functional upgrades can be greatly reduced, effectively saving manpower, material resources and time, and is suitable for industrial promotion.

[0010] According to some embodiments of the present invention, the above-mentioned dual FPGA-based computing control module also includes a network communication module, which is connected to the connector through the SGMII communication port and connected to the central processing unit through the RGMII interface.

[0011] According to some embodiments of the present invention, the first FPGA and the second FPGA are connected via an LVDS bus; and the second FPGA is also connected to the SRIO communication port on the connector.

[0012] According to some embodiments of the present invention, the second FPGA is also connected to a QSFP optical fiber module.

[0013] According to some embodiments of the present invention, the above-mentioned dual FPGA-based computing control module also includes an operation data detection circuit connected to the central processing unit, and the operation data detection circuit is used to collect voltage data and current data.

[0014] According to some embodiments of the present invention, the operation data detection circuit includes:

[0015] A voltage collection circuit having a plurality of output terminals for collecting the voltage data;

[0016] A current sampling resistor, used to be connected in series with the output end of the input power supply and collect current data;

[0017] The safety management processor is connected to the voltage acquisition circuit, the current sampling resistor and the central processing unit respectively.

[0018] According to some embodiments of the present invention, the operation data detection circuit also includes a MOS tube, the gate of the MOS tube is connected to the security management processor, the current sampling resistor is connected in series between the drain and the input power supply, and the source is used as an output terminal.

[0019] The dynamic configuration method according to the second aspect of the present invention is applied to the above-mentioned dual FPGA-based computing control module, and includes the following steps:

[0020] Acquire the first dynamic configuration data through the SGMII communication port of the connector and transmit it to the central processing unit;

[0021] The central processing unit writes the first dynamic configuration data into Nor Flash;

[0022] The first FPGA writes the first dynamic configuration data in the Nor Flash into the first Flash;

[0023] Acquire the second dynamic configuration data through the PCIE communication port of the connector, and transmit it to the second FPGA;

[0024] The second FPGA writes the second dynamic configuration data into the second Flash;

[0025] In response to a first dynamic configuration instruction, the central processing unit controls the first FPGA to obtain the first dynamic configuration data from the Nor Flash or the first Flash for configuration;

[0026] In response to the second dynamic configuration instruction, the central processing unit controls the second FPGA to obtain the second dynamic configuration data from the second Flash for configuration.

[0027] According to the dynamic configuration method of the embodiment of the present invention, at least the following technical effects are achieved: after the first dynamic configuration data is obtained by the central processing unit, and the second dynamic configuration data is obtained by the second FPGA, and written into NorFlash, the first Flash, and the second Flash, the first dynamic configuration data and the second dynamic configuration data are dynamically stored, and then when an update is required, the first FPGA and the second FPGA can be directly controlled by the central processing unit to load the corresponding dynamic configuration data for updating, without the need for manual updating by a technician. At the same time, the first dynamic configuration data can be obtained at any time by the central processing unit and stored in Nor Flash, at which time the dual FPGA data processing structure composed of the first FPGA and the second FPGA can still work normally, and only the first FPGA needs to be stopped for a short time when the first FPGA loads the first dynamic configuration data, at which time the second FPGA can still receive data, and the work of the entire calculation control module does not need to be stopped, and the dynamic update of the first FPGA can be completed; in addition, although the update of the second FPGA cannot be completely done without stopping the work of the entire calculation control module, the method of remotely obtaining the second dynamic configuration data by the central processing unit can still greatly save the manpower, material resources, and time costs required for the update. The dynamic configuration method of the embodiment of the present invention can realize remote dynamic update of the first FPGA. When the first FPGA is used as the main unit for data processing, the time for functional upgrades can be greatly reduced, effectively saving manpower, material resources and time, and is suitable for industrial promotion.

[0028] According to some embodiments of the present invention, the above dynamic configuration method further includes the following steps:

[0029] Acquire the first dynamic configuration data through the PCIE communication port of the connector, and transmit it to the second FPGA;

[0030] The second FPGA transmits the first dynamic configuration data to the first FPGA;

[0031] The first FPGA writes the first dynamic configuration data into the first Flash.

[0032] According to some embodiments of the present invention, the above dynamic configuration method further includes the following steps:

[0033] Presetting first preset configuration data and second preset configuration data in the Nor Flash, wherein the first preset configuration data, the second preset configuration data and the first dynamic configuration data and the second dynamic configuration data have no overlapping storage areas in the Nor Flash;

[0034] When an exception occurs when the first FPGA and the second FPGA load the first dynamic configuration data and the second dynamic configuration data, in response to a preset configuration update instruction, the first FPGA obtains the first preset configuration data from the Nor Flash, and the second FPGA obtains the second preset configuration data from the Nor Flash through the central processor.

[0035] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0037] Figure 1 is a system block diagram of a dual FPGA-based computing control module according to an embodiment of the present invention;

[0038] Figure 2 is a flow chart of a dual FPGA-based dynamic configuration method according to an embodiment of the present invention;

[0039] Figure 3 It is a partial schematic diagram of an operation data detection circuit based on dual FPGAs according to an embodiment of the present invention.

[0040] Reference numerals:

[0041] Connector 100,

[0042] CPU 210, Nor Flash 220,

[0043] first FPGA 310, first Flash 320, first memory 330,

[0044] The second FPGA 410, the second Flash 420, the second memory 430, the QSFP optical fiber module 440,

[0045] Network communication module 500,

[0046] Operation data detection circuit 600 , voltage acquisition circuit 610 , safety management processor 620 , MOS tube 630 . DETAILED DESCRIPTION

[0047] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0048] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0049] In the description of the present invention, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed" etc. are understood as not including the number itself, and "above", "below", "within" etc. are understood as including the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing the technical features, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0050] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0051] Reference below Figures 1 to 3 A computing control module based on dual FPGAs according to an embodiment of the first aspect of the present invention is described.

[0052] The dual FPGA-based computing control module according to an embodiment of the present invention includes a PCB substrate and the following components arranged on the PCB substrate: a connector 100, a core control unit, a first data processing unit, and a second data processing unit.

[0053] The connector 100 is used as a port for data interaction with the outside and provides a basis for data interaction;

[0054] The core control unit includes a central processor 210 and a Nor Flash 220 connected to the central processor 210; the central processor 210 is connected to the connector 100 via the SGMII communication port to obtain the first dynamic configuration data; the Nor Flash 220 is used to store the first dynamic configuration data;

[0055] The first data processing unit includes a first FPGA 310 and a first Flash 320 and a first memory 330 respectively connected to the first FPGA 310; the first FPGA 310 is respectively connected to the central processor 210 and the Nor Flash 220; the first Flash 320 is used to write the first dynamic configuration data through the first FPGA 310;

[0056] The second data processing unit includes a second FPGA410 and a second Flash420 and a second memory 430 respectively connected to the second FPGA410; the second FPGA410 is respectively connected to the connector 100, the central processing unit 210, and the first FPGA310, and is used to obtain the second dynamic configuration data through the connector 100; the second Flash420 is used to write the second dynamic configuration data through the second FPGA410.

[0057] refer to Figures 1 to 3 The central processing unit 210 is connected to the connector 100 through the SGMII communication port, and can then communicate data with the external device and receive the first dynamic configuration data transmitted by the external device; after receiving the first dynamic configuration data, the first dynamic configuration data can be written into the Nor Flash 220, and the first dynamic configuration data can be stored in the first step. The second dynamic configuration data can also be written into the Nor Flash 220 for storage in the same way.

[0058] After the first dynamic configuration data is written into Nor Flash 220, the first FPGA 310 will write the first dynamic configuration data in Nor Flash 220 into the first Flash 320 when it is idle, or directly write the first dynamic configuration data into the first Flash 320 using a multithreaded method. At this time, once the central processor 210 receives an instruction to reload the first FPGA 310, it will control the first FPGA 310 to obtain the first dynamic configuration data from the first Flash 320 for reloading. When a loading failure occurs in the first Flash 320 or the first dynamic configuration data in the first Flash 320 is not updated in time, the central processor 210 will directly load the first dynamic configuration data in Nor Flash 220 into the first FPGA 310 to complete the configuration update of the first FPGA 310. In some embodiments of the present invention, an active selection method of updating the flash memory is adopted to complete the loading of the first FPGA 310, that is, the instruction is sent remotely manually, and the central processor 210 selects whether to obtain the first dynamic configuration data from Nor Flash 220 or the first Flash 320 according to the instruction.

[0059] The second FPGA 410 is directly connected to the connector 100 through the PCIE interface, and then obtains the second configuration data from the external device through the connector 100, and writes the second configuration data into the second Flash 420. When the central processor 210 receives an instruction to update the second FPGA 410, it controls the second FPGA 410 to load the second configuration data from the second Flash 420. In some embodiments of the present invention, the second configuration data can also be written into the NorFlash 220 by the central processor 210, and then obtained from the Nor Flash 220 by the central processor 210.

[0060] It should be noted here that in the dual FPGA operation structure composed of the first FPGA 310 and the second FPGA 410, the second FPGA 410 is usually responsible for communicating with the outside to obtain data, while the first FPGA 310 is responsible for management operations. Therefore, in actual projects, the update frequency of the second FPGA 410 will be much lower than that of the first FPGA 310, so it is only necessary to implement the dynamic configuration of the first FPGA 310. The structure of connecting Nor Flash 220 and the first Flash 320 to the first FPGA 310 at the same time can minimize the time occupied by updating the configuration of the first FPGA 310 and avoid the time consumption of data transfer. Because the first dynamic configuration data in Nor Flash 220 can be updated in real time through the central processor 210, the first FPGA 310 can be dynamically configured, and there is no need to obtain the first dynamic configuration data from the remote end again when it is about to be updated. The use of Nor Flash 220 for storing the first dynamic configuration data can also avoid data instability caused by direct real-time transmission of the first dynamic configuration data by an external device.

[0061] According to the dual-FPGA-based computing control module of the embodiment of the present invention, after the first dynamic configuration data is obtained through the central processing unit 210 and the second dynamic configuration data is obtained through the second FPGA410, it can be written into NorFlash220, the first Flash320, and the second Flash420 to realize dynamic storage of the first dynamic configuration data and the second dynamic configuration data. When updating is needed, the first FPGA310 and the second FPGA410 can be directly controlled by the central processing unit 210 to load the corresponding dynamic configuration data for updating, without the need for manual updating by technical personnel. At the same time, the first dynamic configuration data can be obtained at any time through the central processor 210 and stored in the Nor Flash 220. At this time, the dual FPGA data processing structure composed of the first FPGA 310 and the second FPGA 410 can still work normally. It only needs to stop the first FPGA 310 for a short time when the first FPGA 310 loads the first dynamic configuration data. At this time, the second FPGA 410 can still receive data without stopping the work of the entire calculation control module. The dynamic update of the first FPGA 310 can be realized; in addition, although the update of the second FPGA 410 cannot completely stop the work of the entire calculation control module, the remote acquisition of the second dynamic configuration data by the central processor 210 unit can still greatly save the manpower, material resources and time costs required for the update. The calculation control module based on the dual FPGA of the embodiment of the present invention can realize the remote dynamic update of the first FPGA 310. When the first FPGA 310 is used as the main unit for data processing, the time for function upgrade can be greatly reduced, which effectively saves manpower, material resources and time, and is suitable for industrial promotion.

[0062] In some embodiments of the present invention, the above-mentioned dual FPGA-based computing control module further includes a network communication module 500, which is connected to the connector 100 via the SGMII communication port and is connected to the central processor 210 via the RGMII interface. The network communication module 500 can realize data interaction with the remote end through the SGMII communication port, and then use Ethernet to realize ultra-long-distance data transmission, and no longer need to manually go to the local area for data transmission and update. In some embodiments of the present invention, the network communication module 500 adopts 88E1111.

[0063] In some embodiments of the present invention, the first FPGA 310 and the second FPGA 410 are connected via an LVDS bus; the second FPGA 410 is also connected to the SRIO communication port on the connector 100. The SRIO communication port allows the second FPGA 410 to achieve ultra-high-speed communication with the outside, and there are usually multiple SRIO communication ports, which can facilitate function expansion, and multiple SRIO communication ports can be directly connected to the second FPGA 410 to achieve high-speed data interaction. After the second FPGA 410 obtains data through the multiple SRIO communication ports, it can transmit the preliminarily processed data to the first FPGA 310 through the LVDS bus for final management. This can greatly increase the data of the data transmission and effectively utilize the data processing capabilities of the first FPGA 310 and the second FPGA 410.

[0064] In some embodiments of the present invention, the second FPGA 410 is also connected to a QSFP optical fiber module 440. The QSFP optical fiber module 440 enables the second FPGA 410 to have the optical communication capability through the QSFP optical fiber module 440, which can not only match more external devices, but also improve the data receiving capability. In some embodiments of the present invention, the first dynamic configuration data and the second dynamic configuration data transmitted externally can also be received through the QSFP optical fiber module 440.

[0065] In some embodiments of the present invention, the above-mentioned dual FPGA-based computing control module further includes an operation data detection circuit 600 connected to the central processing unit 210, and the operation data detection circuit 600 is used to collect voltage data and current data. After receiving the voltage data and current data, the central processing unit 210 can further transmit them to the remote end through the connector 100, so that the remote end can know the operation status of the computing control module in real time.

[0066] In some embodiments of the present invention, reference Figure 3, the operation data detection circuit 600 includes: a voltage acquisition circuit 610, a current sampling resistor R199, and a safety management processor 620. The voltage acquisition circuit 610 has multiple output terminals for collecting voltage data; the current sampling resistor R199 is used to be connected in series with the output terminal of the input power supply and collect current data; the safety management processor 620 is respectively connected to the voltage acquisition circuit 610, the current sampling resistor R199, and the central processor 210. The voltage +12V_VPX is input by the connector 100, and after the input, the voltage is collected by the voltage acquisition circuit 610, and two voltage signals are output, which are used to judge the voltage overvoltage and voltage undervoltage respectively. In some embodiments of the present invention, the voltage acquisition circuit 610 includes a first voltage divider circuit and a second voltage divider circuit; the first voltage divider circuit is composed of resistors R862 and R854 connected in series between the voltage +12V_VPX and the ground line, and the ratio of R862 and R854 is large, which can be used for overvoltage detection; the second voltage divider circuit is composed of resistors R873 and R880 connected in series between the voltage +12V_VPX and the ground line, and the ratio of R873 and R880 is small, which can be used for undervoltage detection. The current sampling resistor R199 is connected in series between the voltage +12V_VPX and the drain of the MOS tube 630. After the MOS tube 630 is turned on, the loop current of the entire circuit can be directly detected. The voltage difference across the current sampling resistor R199 collected by the security management processor 620 can know the magnitude of the current. By running the data detection circuit 600, when the voltage or current fluctuates, the fault can be known in time so as to troubleshoot the fault as soon as possible; the MOS tube 630 can also be directly controlled to be shut down through the security management processor 620 to timely reduce the damage to the dual FPGA-based computing control module of the embodiment of the present invention. For example: when it is necessary to hot-plug the power supply connected to the connector 100, once the voltage and current fluctuations are too large, the MOS tube 630 can be controlled to be shut down to avoid the current and voltage shock during hot plugging to cause damage to the computing control module.

[0067] In some embodiments of the present invention, reference Figure 3 The operation data detection circuit 600 further includes a MOS transistor 630. The gate of the MOS transistor 630 is connected to the security management processor 620. A current sampling resistor is connected in series between the drain and the input power supply. The source is used as an output terminal. The gate voltage of the MOS transistor 630 is controlled by the security management processor 620. Therefore, the on-off of the MOS transistor 630 can be directly controlled by the security management processor 620, thereby realizing the on-off control of the power input.

[0068] In some embodiments of the present invention, the safety management processor 620 is connected to the central processor 210 via an I2C interface, and can transmit voltage data, current data, and control data of the MOS tube 630 to the central processor 210 in real time, and can then be transmitted to a remote end via the central processor 210.

[0069] In some embodiments of the present invention, the operation data detection circuit 600 also includes a temperature acquisition unit connected to the safety management processor 620, through which the operating environment temperature of the computing control module can be effectively detected to prevent long-term operation at high temperature and cause aging. The temperature data collected by the temperature acquisition unit can be transmitted to the remote end through the safety management processor 620 and the central processor 210, and monitored by the remote end. In some embodiments of the present invention, the temperature acquisition unit can directly use a thermistor.

[0070] In some embodiments of the present invention, the central processor 210 uses an AM335X processor, the first FPGA 310 uses an HW4VSX55, the second FPGA 410 uses an XC7VX485T, and the security management processor 620 uses an LM25066I.

[0071] The dynamic configuration method according to the second aspect of the present invention is applied to the above-mentioned dual FPGA-based computing control module, and includes the following steps:

[0072] Acquire the first dynamic configuration data through the SGMII communication port of the connector 100 and transmit it to the central processor 210;

[0073] The CPU 210 writes the first dynamic configuration data into the Nor Flash 220;

[0074] The first FPGA 310 writes the first dynamic configuration data in the Nor Flash 220 into the first Flash 320;

[0075] Acquire the second dynamic configuration data through the PCIE communication port of the connector 100 and transmit it to the second FPGA 410;

[0076] The second FPGA 410 writes the second dynamic configuration data into the second Flash 420;

[0077] In response to the first dynamic configuration instruction, the CPU 210 controls the first FPGA 310 to obtain the first dynamic configuration data from the Nor Flash 220 or the first Flash 320 for configuration;

[0078] In response to the second dynamic configuration instruction, the CPU 210 controls the second FPGA 410 to obtain the second dynamic configuration data from the second Flash 420 for configuration.

[0079] refer to Figures 1 to 3 , the central processing unit 210 is connected to the connector 100 through the SGMII communication port, and can then communicate data with the external device and receive the first dynamic configuration data transmitted by the external device; after receiving the first dynamic configuration data, the first dynamic configuration data can be written into the Nor Flash 220, and the first step of storing the first dynamic configuration data is performed. After the first dynamic configuration data is written into the Nor Flash 220, the first FPGA 310 will write the first dynamic configuration data in the Nor Flash 220 into the first Flash 320 when idle, or directly write the first dynamic configuration data into the first Flash 320 using a multi-threaded method. The second FPGA 410 is directly connected to the connector 100 through the PCIE interface, and then obtains the second configuration data from the external device through the connector 100, and writes the second configuration data into the second Flash 420. After the above steps, the foundation for dynamic configuration is in place.

[0080] At this time, once the first dynamic configuration instruction is sent to the central processor 210, the central processor 210 will control the first FPGA 310 to obtain the first dynamic configuration data from the first Flash 320 for reloading. When a loading failure occurs in the first Flash 320 or the first dynamic configuration data in the first Flash 320 is not updated in time, the central processor 210 will directly load the first dynamic configuration data in the Nor Flash 220 into the first FPGA 310 to complete the configuration update of the first FPGA 310. In some embodiments of the present invention, the first FPGA 310 is loaded by actively selecting to update the flash memory, that is, the first dynamic configuration instruction sent manually and remotely contains priority information, and the central processor 210 selects to obtain the first dynamic configuration data from the Nor Flash 220 or the first Flash 320 according to the priority. Similarly, once the second dynamic configuration instruction is sent to the central processor 210, the central processor 210 will control the second FPGA 410 to obtain the second dynamic configuration data from the second Flash 420 for reloading.

[0081] The dynamic configuration method according to the embodiment of the present invention has at least the following technical effects: after the first dynamic configuration data is obtained through the central processing unit 210, and the second dynamic configuration data is obtained through the second FPGA410, and written into NorFlash220, the first Flash320, and the second Flash420, dynamic storage of the first dynamic configuration data and the second dynamic configuration data is realized, and when updating is needed, the first FPGA310 and the second FPGA410 can be directly controlled by the central processing unit 210 to load the corresponding dynamic configuration data for updating, without the need for manual updating by technical personnel. At the same time, the first dynamic configuration data can be obtained at any time through the central processor 210 and stored in the Nor Flash 220. At this time, the dual FPGA data processing structure composed of the first FPGA 310 and the second FPGA 410 can still work normally. It is only necessary to stop the first FPGA 310 for a short time when the first FPGA 310 loads the first dynamic configuration data. At this time, the second FPGA 410 can still receive data without stopping the work of the entire calculation control module. The dynamic update of the first FPGA 310 can be realized; in addition, although the update of the second FPGA 410 cannot completely stop the work of the entire calculation control module, the second dynamic configuration data can be obtained remotely through the central processor 210 unit, which can still greatly save the manpower, material resources and time costs required for the update. The dynamic configuration method of the embodiment of the present invention can realize the remote dynamic update of the first FPGA 310. When the first FPGA 310 is used as the main unit for data processing, the time for function upgrades can be greatly reduced, which effectively saves manpower, material resources and time, and is suitable for industrial promotion.

[0082] In some embodiments of the present invention, the above dynamic configuration method further includes the following steps:

[0083] Acquire the first dynamic configuration data through the PCIE communication port of the connector 100 and transmit it to the second FPGA 410;

[0084] The second FPGA 410 transmits the first dynamic configuration data to the first FPGA 310 ;

[0085] The first FPGA 310 writes the first dynamic configuration data into the first Flash 320 .

[0086] In addition to being obtained by the central processing unit 210, the first dynamic configuration data can also be obtained by the second FPGA410. In this way, after a failure of the network communication module 500, the first dynamic configuration data can still be obtained through the second FPGA410 using the PCIE communication port of the VPX. Although there is a larger delay compared to directly obtaining the first dynamic configuration data from the central processing unit 210, the normal update of the first FPGA310 can be guaranteed.

[0087] In some embodiments of the present invention, the above dynamic configuration method further includes the following steps:

[0088] Presetting first preset configuration data and second preset configuration data in Nor Flash 220, wherein the first preset configuration data, the second preset configuration data, and the first dynamic configuration data and the second dynamic configuration data do not overlap in storage areas in Nor Flash 220;

[0089] When an exception occurs when the first FPGA310 and the second FPGA410 load the first dynamic configuration data and the second dynamic configuration data, in response to the preset configuration update instruction, the first FPGA310 obtains the first preset configuration data from Nor Flash220, and the second FPGA410 obtains the second preset configuration data from Nor Flash220 through the central processor 210.

[0090] In actual projects, the first dynamic configuration data and the second dynamic configuration data uploaded may be updated but cannot be loaded successfully, or cannot work normally or lack functions after being loaded successfully. In the face of this situation, the first preset configuration data and the second preset configuration data are preset in Nor Flash 220. The first FPGA 310 and the second FPGA 410 configuration information corresponding to the first preset configuration data and the second preset configuration data usually only have default functions. After the above situation occurs, the first preset configuration data and the second preset configuration data are used to update the configuration, which can ensure that the first FPGA 310 and the second FPGA 410 basically work normally. After that, the remote end can send professional technicians to the site to troubleshoot and troubleshoot the first dynamic configuration data and the second dynamic configuration data that have failed.

[0091] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0092] Although the embodiments of the present invention are described in detail above in conjunction with the accompanying drawings, the present invention is not limited to the above embodiments. Those skilled in the art will understand that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and purpose of the present invention. The scope of the present invention is defined by the claims and their equivalents.

Claims

1. A dynamic configuration method, applied to a computing control module based on dual FPGA, characterized in that: The dual FPGA-based computing control module includes a PCB substrate and: Connectors; A core control unit, comprising a central processing unit and a Nor Flash connected to the central processing unit; the central processing unit is connected to the connector via an SGMII communication port for acquiring first dynamic configuration data; the Nor Flash is used to store the first dynamic configuration data; A first data processing unit includes a first FPGA and a first Flash and a first memory respectively connected to the first FPGA; the first FPGA is respectively connected to the central processor and the Nor Flash; the first Flash is used to write the first dynamic configuration data through the first FPGA; The second data processing unit includes a second FPGA and a second Flash and a second memory respectively connected to the second FPGA; the second FPGA is respectively connected to the connector, the central processor, and the first FPGA, and is used to obtain second dynamic configuration data through the connector; the second Flash is used to write the second dynamic configuration data through the second FPGA; The dynamic configuration method comprises the following steps: Acquire the first dynamic configuration data through the SGMII communication port of the connector and transmit it to the central processing unit; The central processing unit writes the first dynamic configuration data into Nor Flash; The first FPGA writes the first dynamic configuration data in the Nor Flash into the first Flash; Acquire the second dynamic configuration data through the PCIE communication port of the connector, and transmit it to the second FPGA; The second FPGA writes the second dynamic configuration data into the second Flash; In response to a first dynamic configuration instruction, the central processor controls the first FPGA to obtain the first dynamic configuration data from the Nor Flash or the first Flash for configuration; In response to the second dynamic configuration instruction, the central processing unit controls the second FPGA to obtain the second dynamic configuration data from the second Flash for configuration.

2. The dynamic configuration method according to claim 1, characterized in that: The following steps are also included: Acquire the first dynamic configuration data through the PCIE communication port of the connector, and transmit it to the second FPGA; The second FPGA transmits the first dynamic configuration data to the first FPGA; The first FPGA writes the first dynamic configuration data into the first Flash.

3. The dynamic configuration method according to claim 1, characterized in that: The following steps are also included: Presetting first preset configuration data and second preset configuration data in the Nor Flash, wherein the first preset configuration data, the second preset configuration data, and the first dynamic configuration data and the second dynamic configuration data have no overlapping storage areas in the Nor Flash; When an exception occurs when the first FPGA and the second FPGA load the first dynamic configuration data and the second dynamic configuration data, in response to a preset configuration update instruction, the first FPGA obtains the first preset configuration data from the Nor Flash, and the second FPGA obtains the second preset configuration data from the Nor Flash through the central processor.

4. The dynamic configuration method according to claim 1, characterized in that: The dual FPGA-based computing control module also includes a network communication module, which is connected to the connector via the SGMII communication port and connected to the central processing unit via the RGMII interface.

5. The dynamic configuration method according to claim 1, characterized in that: The first FPGA and the second FPGA are connected via an LVDS bus; the second FPGA is also connected to the SRIO communication port on the connector.

6. The dynamic configuration method according to claim 1, characterized in that: The second FPGA is also connected to a QSFP optical fiber module.

7. The dynamic configuration method according to claim 1, characterized in that: The dual FPGA-based computing control module also includes an operation data detection circuit connected to the central processing unit, and the operation data detection circuit is used to collect voltage data and current data.

8. The dynamic configuration method according to claim 7, characterized in that: The operation data detection circuit comprises: A voltage collection circuit having a plurality of output terminals for collecting the voltage data; A current sampling resistor, connected in series with the output end of the input power supply and used to collect the current data; The safety management processor is connected to the voltage acquisition circuit, the current sampling resistor and the central processing unit respectively.

9. The dynamic configuration method according to claim 8, characterized in that: The operation data detection circuit also includes a MOS tube, the gate of the MOS tube is connected to the security management processor, the current sampling resistor is connected in series between the drain and the input power supply, and the source is used as an output terminal.

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