Semiconductor device and method for manufacturing the same

Abstract

A method for manufacturing a semiconductor device includes forming a dummy gate structure above a wafer. A gate spacer is formed on either side of the dummy gate structure. The dummy gate structure is removed to form a gate trench between the gate spacers. A gate dielectric layer is formed in the gate trench. A gate electrode is formed above the gate dielectric layer. Forming the gate dielectric layer includes applying a first bias to the wafer. With the first bias turned on, a first precursor is fed to the wafer. The first bias is turned off. After the first bias is turned off, a second precursor is fed to the wafer. According to other embodiments of the present application, a semiconductor device is also provided.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. During the evolution of ICs, functional density (i.e., the number of interconnected devices per chip area) has increased, while geometry size (i.e., the smallest component or line that can be produced using a manufacturing process) has decreased. This scaling down process increases production efficiency and reduces associated costs.

[0003] This scaling down has also increased the complexity of processing and manufacturing ICs and similar developments in IC processing and manufacturing are needed to achieve these advances.For example, three-dimensional transistors such as fin field effect transistors (FinFETs) have been introduced to replace planar transistors. Summary of the invention

[0004] According to one embodiment of the present application, a method for manufacturing a semiconductor device is provided, comprising: forming a dummy gate structure above a wafer; forming gate spacers on either side of the dummy gate structure; removing the dummy gate structure to form a gate trench between the gate spacers; depositing a gate dielectric layer in the gate trench, comprising: applying a first bias to the wafer; feeding a first precursor to the wafer with the first bias turned on; turning off the first bias; and after turning off the first bias, feeding a second precursor to the wafer; and forming a gate electrode above the gate dielectric layer.

[0005] According to another embodiment of the present application, a method for manufacturing a semiconductor device is provided, including: forming a mask layer over a substrate; patterning the substrate by using the mask layer as a mask to form a groove in the substrate; and forming an isolation structure in the groove, including: feeding a first precursor to the substrate; applying a bias to the substrate after feeding the first precursor; feeding a second precursor to the substrate with the bias turned on; and repeatedly feeding the first precursor, applying the bias, and feeding the second precursor.

[0006] According to another embodiment of the present application, a semiconductor device is provided, comprising: a conductive component; a first dielectric layer above the conductive component; a through hole in the first dielectric layer and above the conductive component; an etch stop layer (ESL) above the first dielectric layer, wherein a side surface of the ESL is in contact with a side wall of the through hole; a second dielectric layer above the ESL; and a conductive wire in the second dielectric layer and above the through hole, the conductive wire being in contact with a side surface of the ESL and a top surface of the ESL. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figures 1A to 1E is a perspective view of various stages of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0009] Figure 2 is a flow chart of a method for a bias induced selective ALD process according to some embodiments of the present disclosure.

[0010] Figure 3 is a schematic diagram of a manufacturing apparatus according to some embodiments of the present disclosure.

[0011] FIG. 4A to FIG. 4E According to some embodiments of the present disclosure, Figure 1C A cross-sectional view taken along line AA.

[0012] Figure 5 is a timing diagram of bias pulses and precursors provided according to some embodiments.

[0013] FIG. 6A to FIG. 6E According to some embodiments of the present disclosure, Figure 1C A cross-sectional view taken along line AA.

[0014] Figure 7 is a flow chart of a method for a bias induced selective ALD process according to some embodiments of the present disclosure.

[0015] FIG. 8A to FIG. 8E According to some embodiments of the present disclosure, Figure 1C A cross-sectional view taken along line AA.

[0016] Fig. 9 is a timing diagram of bias pulses and precursors provided according to some embodiments.

[0017] FIG. 10A to FIG. 10I is a perspective view of various stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0018] FIG. 11A to FIG. 11F According to some embodiments of the present disclosure, Fig.10F A cross-sectional view taken along line BB.

[0019] FIG. 12A to FIG. 12F According to some embodiments of the present disclosure, Fig.10F A cross-sectional view taken along line BB.

[0020] FIG. 13A to FIG. 13F According to some embodiments of the present disclosure, Fig.10F A cross-sectional view taken along line BB.

[0021] Fig.14 is a perspective view of a semiconductor device according to some embodiments.

[0022] FIG. 15A to FIG. 15K is a perspective view of various stages of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0023] FIG. 16A to FIG. 16G is a perspective view of various stages of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0024] In order to implement the different components of the present invention, the following disclosure provides many different embodiments or examples. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an additional component formed between the first component and the second component so that the first component and the second component are not in direct contact. Moreover, the present invention may repeat reference numbers and / or letters in various examples. This repetition is only for simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0025] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. Spatially relative position terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0026] As used herein, "roughly", "about", "approximately", or "substantially" shall generally mean within 20%, or within 10%, or within 5% of a given value or range. Numerical quantities given herein are approximate, meaning that, if not explicitly stated, they can be inferred from the terms "roughly", "about", "approximately", or "substantially".

[0027] The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes including a double patterning process or a multi-patterning process. Typically, the double patterning or multi-patterning process combines a photolithography process with a self-aligned process, thereby allowing the generation of, for example, a pattern with a smaller pitch than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.

[0028] Embodiments of the present disclosure relate to semiconductor structures and methods of forming semiconductor structures by performing a bias-induced selective atomic layer deposition (ALD) process. These embodiments are discussed below in the context of forming a FinFET transistor having a single fin or multiple fins on a bulk silicon substrate.

[0029] Figures 1A to 1E is a perspective view of a method for manufacturing a semiconductor structure at various stages according to some embodiments of the present disclosure. In some embodiments, Figures 1A to 1E The semiconductor structures shown in the drawings may be intermediate devices fabricated during processing of an integrated circuit (IC) or a portion thereof, which may include static random access memory (SRAM); logic circuits; passive components such as resistors, capacitors, and inductors; and active components such as p-type FETs (PFETs), n-type FETs (NFETs), multi-gate FETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof.

[0030] Reference Figure 1A . A substrate 110 is provided. The substrate 110 includes an n-type region 100n and a p-type region 100p. N-type devices (such as NFETs) will be formed on the n-type region 100n, and p-type devices (such as PFETs) will be formed on the p-type region 100p. In some embodiments, the substrate 110 may include silicon (Si). Alternatively, the substrate 110 may include germanium (Ge), silicon germanium, gallium arsenide (GaAs), or other suitable semiconductor materials. In some embodiments, the substrate 110 may include an epitaxial layer. In addition, the substrate 110 may include a semiconductor on insulator (SOI) structure having a buried dielectric layer therein. The buried dielectric layer may be, for example, a buried oxide (BOX) layer. The SOI structure may be formed by a technique known as separation by oxygen implantation (SIMOX), wafer bonding, selective epitaxial growth (SEG), or other suitable methods.

[0031] A mask layer 120 (which may be a hard mask layer) is formed over the top surface 112 of the substrate 110. In some embodiments, the mask layer 120 includes a nitride. For example, the mask layer 120 is made of silicon nitride (SiN). However, other materials such as SiON, silicon carbide, or a combination thereof may also be used. The mask layer 120 may be formed by a process such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or low pressure chemical vapor deposition (LPCVD). Alternatively, the mask layer 120 may be made of silicon oxide and then converted to SiN by nitride.

[0032] In some embodiments, a protective layer 130 is formed above the top surface 112 of the substrate 110 and between the mask layer 120 and the substrate 110. The protective layer 130 protects the top surface 112 from direct contact with the mask layer 120. For example, the protective layer 130 can protect the active area formed in the substrate 110. The active area is used to form a device (such as a transistor, a resistor, etc.). Depending on the device to be formed, the active area may include an n-well or a p-well determined by the design conditions. In some embodiments, the protective layer 130 is made of thermal oxide. Once formed, the mask layer 120 and the protective layer 130 are patterned by suitable photolithography and etching processes to form an opening 132 above the top surface 112.

[0033] refer to Figure 1B The substrate 110 is removed through the opening 132 (see FIG. 1 ) by an etching process such as reactive ion etching (RIE). Figure 1A ) to form a trench 114 in the substrate 110. In some embodiments, the substrate 110 is etched to form a semiconductor fin 116, and the trench 114 is configured to separate two adjacent semiconductor fins 116. In other words, one of the semiconductor fins 116 is between two adjacent trenches 114.

[0034] refer to Figure 1C . Isolation material 140' is selectively formed in trench 114. Isolation material 140' is formed by performing a bias induced selective ALD process, as described in more detail below. Atomic layer deposition (ALD) is a method of filling a dielectric that includes depositing a monolayer of a precursor over substrate 110, purging the chamber, and introducing a reactant that reacts with the precursor to leave a monolayer of a product. This cycle can be repeated multiple times to build a layer with sufficient thickness to function. The thickness of the deposited layer is determined by the deposition cycle of the ALD process.

[0035] Figure 2 is a flow chart of a method M1 of a bias-induced selective ALD process according to some embodiments of the present disclosure. Figure 3is a schematic diagram of a manufacturing apparatus 200 according to some embodiments of the present disclosure. FIG. 4A to FIG. 4E According to some embodiments of the present disclosure, Figure 1C In some embodiments, Figure 1C The isolation material 140' is formed in Figure 3 It should be noted that only FIG. 4B to FIG. 4D The dimensions of the precursors shown in FIG. 1 are for reference only and do not limit the scope of the embodiments.

[0036] refer to Figure 2 , Figure 3 ,and Figure 4A In operation S12 of method M1, a wafer is placed on a suction cup of a manufacturing device. For example, a wafer (eg, Figure 1B The structure in the embodiment of the present invention is placed on a chuck 220 of a manufacturing apparatus 200. In some embodiments, the manufacturing apparatus 200 includes a chamber 210, a chuck 220, a plasma source 230, and a precursor conveyor 240. The chuck 220 is in the chamber 210, and the plasma source 230 and the precursor conveyor 240 are connected to the chamber 210.

[0037] The plasma source 230 may be a remote plasma system separate from the chamber 210. Process gas and carrier gas may be introduced into the plasma source 230, and the process gas may be excited to generate a reactive gas containing plasma. The reactive gas is an active species of plasma ions. In some embodiments, microwaves are used to discharge the process gas to generate a reactive gas containing plasma. Microwaves are generated using a microwave oscillator, and the microwaves are introduced into the plasma source 230 using an optical waveguide. The reactive gas is then fed into the chamber 210 through a conduit.

[0038] In some embodiments, the manufacturing apparatus 200 further includes a turbo pump 250 and a pressure controller 260 (e.g., an automatic pressure controller (APC)). The turbo pump 250 is connected to the chamber 210 through the pressure controller 260. In some embodiments, when the wafer is placed in the chamber 210, a vacuum is applied to the chamber 210 by the turbo pump 250 to remove oxygen and moisture. The pressure controller 260 is configured to control the pressure inside the chamber 210. In some embodiments, when the wafer is placed in the chamber 210, the temperature is raised to an acceptable level suitable for ALD deposition before operation S14.

[0039] In operation S14 of method M1, a bias voltage is applied to the chuck. The bias voltage may be a DC bias voltage and / or a radio frequency (RF) bias voltage. For example, Figure 4AIn the case of , RF bias is applied to the chuck 220. With the RF bias, since the conductivity of the mask layer 120 (e.g., dielectric layer) is lower than the conductivity of the substrate 110 (e.g., semiconductor material), the charges (in this case, electrons) move less within the mask layer 120, such that Figure 4A As shown, more charges remain near the surface of the mask layer 120. In addition, since electrons are lighter than ions, electrons are more likely to accumulate near the surface of the mask layer 120.

[0040] In some embodiments, the manufacturing apparatus 200 further includes: Figure 3 A bias source 270 is shown connected to the suction cup 220. The bias source 270 is configured to apply a bias to the suction cup 220 and therefore to the wafer located thereon. In some embodiments, the bias source 270 is configured to apply a DC and / or RF bias to the suction cup 220. In some embodiments, the bias source 270 is configured to apply a positive or negative DC bias to the suction cup 220 to accelerate or decelerate the deposition rate of the selective ALD process. In some embodiments, the bias may have a power greater than about 0W and equal to or less than about 50W, such as about 20W. If the power is greater than about 50W, the gas (e.g., precursor / processing gas) in the chamber 210 may be ionized to form a plasma, which may bombard the wafer to damage the structure formed thereon. In some embodiments, the bias is an RF bias and its frequency range is in the range of about 3kHz to about 300GHz.

[0041] Figure 5 is a timing diagram of bias pulses and precursors provided according to some embodiments. Figure 3 , Figure 4A ,and Figure 5 .exist Figure 5 In the embodiment of the present invention, the bias voltage applied to the chuck 220 lasts for a first period T1. The bias voltage is applied before the precursor is fed into the chamber 210. Once the RF bias voltage is applied to the chuck 220, the electrons move to the surface of the mask layer 120. Therefore, in this case, the surface of the mask layer 120 is negatively charged.

[0042] In operation S16 of method M1, a first precursor is fed into a chamber of a manufacturing apparatus. Figure 3 and Figure 4B For example, a first precursor P1 (eg, H2O in this case) is fed from a precursor conveyor 240 into the chamber 210. Figure 4BAs shown, each H2O molecule is a polar molecule and has a slight negative charge near its oxygen atom and a slight positive charge near its hydrogen atom. Negative charges (electrons) near the surface of the mask layer 120 repel the H2O molecules due to their partial negative charge (oxygen). The H2O molecules may be mostly attracted to the substrate 110 and thus mostly deposited on the substrate 110 rather than on the mask layer 120. In other words, more H2O molecules are deposited on the substrate 110 rather than on the mask layer 120. As shown in FIG. Figure 4C As shown, the H2O molecules are mostly absorbed on the surface 112 of the substrate 110. In some embodiments, there are still some H2O molecules absorbed on the surface of the dielectric material (ie, the mask layer 120 and the pad layer 130 in this case).

[0043] refer to Figure 5 A timing diagram of . After the bias applied to the suction cup 220 is turned on and before the bias is turned off, the first precursor P1 is fed into the chamber 210 for a second period T2. In some embodiments, the second period T2 is many times shorter than the first period T1. For example, the first period T1 may be ten times or more of the second period T2. In addition, after stopping the feeding of the first precursor P1, the bias is turned off. The third period T3 is between the start of the bias supply and the start of the first precursor feed, and the fourth period T4 is between the end of the first precursor feed (i.e., stopping the first precursor feed) and the end of the bias supply (i.e., turning off the bias supply). In some embodiments, the third period T3 is long enough to charge the mask layer 120, and the fourth period T4 is long enough to provide reaction time for the deposition of the first precursor.

[0044] refer to Figure 3 and Figure 4B . In some embodiments, when the first precursor P1 is fed into the chamber 210, the pressure in the chamber 210 may change. The changing pressure may disturb the charge distribution on the suction cup 220. The pressure controller 260 is configured to maintain the pressure within a predetermined range of values. With this configuration, the pressure in the chamber 210 is well controlled, and the charge distribution caused by the bias voltage applied in operation S14 can be maintained in a substantially stable state. In other words, the pressure controller 260 prevents the charge distribution from being disturbed when the first precursor P1 is fed into the chamber 210.

[0045] In some embodiments, during operation S14 and operation S16, the plasma source 230 is turned off so that there is no plasma or negligible plasma in the chamber 210 when the bias is applied to the chuck 220. In some other embodiments, the first precursor P1 is plasma, and the first precursor P1 is fed from the plasma source 230 into the chamber 210. During this process, the plasma comes from the plasma source 230 instead of in the chamber 210, so a bias with a lower power can be applied to the chuck 220 to perform the selective ALD process because the bias applied to the chuck 220 is not related to the generation of plasma.

[0046] In operation S18 of method M1, the bias voltage is turned off, and then in operation S20 of method M1, the excess first precursor is purged out of the chamber. Specifically, during time periods T2 and T4, some of the first precursor P1 is absorbed onto the surface 112 of the substrate 110 (see FIG. 1 ). Figure 5 ). After the fourth period T4, the bias voltage is turned off so that the electrons near the surface of the mask layer 120 gradually disappear. Then, a replacement gas such as an inert gas (Ar or N2) that is substantially free of oxygen and moisture (e.g., less than about 1 volume %, less than about 0.1%, about 0.01%, about 0.001%, or less) enters the chamber 210 to purge the excess first precursor P1 that is not absorbed on the substrate 110, the mask layer 120, and the pad layer 130 from the chamber 210.

[0047] In some embodiments, Figure 3 The manufacturing apparatus 200 further includes a rotary pump 280 and a valve (e.g., a stop valve) 285. The rotary pump 280 is connected to the chamber 210 via the valve 285, and the rotary pump 280 is configured to pump out the replacement gas and excess first precursor P1 in the chamber 210 when the pressure controller 260 is turned off. In some other embodiments, when the pressure controller 260 is turned on, the turbo pump 250 can pump out the replacement gas and excess first precursor P1 in the chamber 210. In some embodiments, Figure 3 The manufacturing apparatus 200 in FIG. 2 also includes a filter (eg, a capture filter) 290 connected to the chamber 210, the valve 285, and the pressure controller 260. The filter 290 is configured to capture gas (eg, replacement gas and / or precursor) and prevent the gas from being reflected back into the chamber 210.

[0048] In operation S22 of method M1, a second precursor is fed into a chamber of the manufacturing apparatus. Figure 3 and Figure 4D For example, the second precursor P2 (in this case, for example, a silicon precursor) is fed into the chamber 210 from the precursor conveyor 240. Figure 4DAs shown, the second precursor P2 is attracted by the first precursor (in this case, -OH) absorbed on the substrate 110. The second precursor P2 may be attracted by -OH, so more of the second precursor P2 is deposited on the surface 112 of the substrate 110, and less of the second precursor P2 is deposited on the surfaces of the mask layer 120 and the pad layer 130. Figure 4E As shown, a dielectric film 140 is formed on the surfaces of the substrate 110, the mask layer 120, and the pad layer 130.

[0049] exist Figure 4E In the embodiment, a portion of the dielectric film 140" in contact with the substrate 110 is denser than another portion of the dielectric film 140" in contact with the mask layer 120. For example, most of the surface area of ​​the mask layer 120 may be exposed by the dielectric film 140", while most of the surface 112 of the substrate 110 is covered by the dielectric film 140". Therefore, the bias-induced selective ALD process is performed to selectively deposit the dielectric film 140" on the substrate 110 at a faster deposition rate than on the mask layer 120 and the pad layer 130. In some embodiments, the dielectric film 140" is a single layer.

[0050] In some embodiments, the dielectric film 140" may be a silicon-containing layer such as SiO2. In this case, the second precursor P2 may be (3-aminopropyl)triethoxysilane, N-sec-butyl(trimethylsilyl)amine, tris(dimethylamino)silane (TDMAS), tetraethyl orthosilicate (TEOS), SiCl4, tri(tert-butoxy)silanol (TBS), tri(tert-pentyloxy)silane (TPS), or other suitable materials. In some other embodiments, the dielectric film 140" may include other suitable materials (such as high-k materials).

[0051] exist Figure 5 In some embodiments, the charging and replacement of the second precursor P2 is maintained for a fifth period T5. In some embodiments, the sixth period T6 is between the period T4 and the period T5. In some embodiments, the sixth period T6 is used to neutralize the surface of the mask layer 120. In addition, the seventh period T7 is between the fifth period T5 and the next first period T1. In some embodiments, the seventh period T7 provides a reaction time for the deposition of the second precursor.

[0052] In operation S24 of method M1, the excess second precursor is purged out of the chamber. Specifically, during time periods T5 and T7, the second precursor P2 is mostly absorbed onto the surface 112 of the substrate 110 (see FIG. Figure 5 After the fifth period T5, a replacement gas such as an inert gas (Ar or N2) enters the chamber 210 again to purge the excess second precursor P2 from the chamber 210.

[0053] After operation S24, Figure 4EAs shown, the dielectric film 140" is mostly formed on the surface 112 of the substrate 110, and the dielectric film 140" may expose a portion of the surface of the mask layer 120 (and the pad layer 130). That is, the selective ALD deposition process results in no or negligible dielectric film 140" being deposited on the mask layer 120 and the pad layer 130. For example, the dielectric film 140" is unintentionally deposited on the mask layer 120 and the pad layer 130 may have a thickness thinner than that deposited on the substrate 110. Then, the method M1 proceeds to operation S14 to repeat operations S14 to S24, and another dielectric film is formed on the dielectric film 140". Figure 1C As shown, the cycle of operations S14 to S24 may be repeated multiple times to form isolation material 140 ′ in trench 114 .

[0054] In operation S26 of method M1, the wafer is taken out of the chamber. Specifically, after the bias-induced selective ALD process (i.e., in this case, filling the isolation material 140' in the trench 114), the deposition process is completed, and the wafer is taken out of the chamber (e.g., by loading it outside the chamber onto a wafer cassette placed on the chamber load port using one or more robotic arms) to process the next manufacturing process.

[0055] refer to Figure 1D . A planarization process is performed to remove the mask layer 120, the pad layer 130, and the isolation material 140' outside the trench 114, thereby exposing the semiconductor fin 116. In some embodiments, the planarization process is a chemical mechanical polishing (CMP) process. In some embodiments, the CMP process can be omitted as long as the selective ALD process is well controlled so that the isolation material 140' is not deposited on the mask layer 120. In this case, an additional etching process can be optionally performed to remove the mask layer 120 and the pad layer 130 from the fin 116.

[0056] refer to Figure 1E .make Figure 1D The isolation material 140' is recessed to form an isolation structure 140 adjacent to and in contact with the semiconductor fin 116, and a portion of the semiconductor fin 116 protrudes from the isolation structure 140. In the next step, the front-end-of-line (FEOL) process continues to form source / drain regions (e.g., n-doped or p-doped epitaxial structures, n-doped or p-doped implanted regions, etc.), a gate dielectric layer, and a gate electrode on the semiconductor fin 116 to complete the manufacture of FinFETs, and the back-end-of-line (BEOL) process follows the FEOL process to form metal contacts, metal vias, and metal lines over the FinFETs to complete the manufacture of integrated circuits (ICs).

[0057] exist Figure 1CIn the embodiment, the isolation material 140' is formed by performing a bias-induced selective ALD process. By providing a bias voltage on the suction cup 220, the charge has different distributions in different materials. The charge can attract or repel the precursor to increase or decrease the corresponding deposition rate. In some other embodiments, when there is a high deposition selectivity between the dielectric layer (i.e., the mask layer 120) and the semiconductor layer (i.e., the substrate 110), the charge can be omitted. Figure 1D In addition, self-aligned monolayers (SAMs), which may be formed using an additional deposition process and cause defect problems, may be omitted to simplify the manufacturing process.

[0058] Figure 1C The isolation material 140' in may be formed using other biases and / or precursors. FIG. 6A to FIG. 6E According to some embodiments of the present disclosure, Figure 1C The cross-sectional view is taken along the line AA of FIG. Throughout the various views and illustrative embodiments, the same reference numerals are used to designate the same elements. The present embodiment may be repeated in FIG. 4A to FIG. 4E Reference numerals and / or letters are used in the following description. This repetition is for simplicity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. In the following embodiments, the structural and material details previously described are not repeated below and only provide further information to perform the present invention. FIG. 6A to FIG. 6E In some embodiments, Figure 3 The manufacturing device 200 and / or using Figure 2 Method M1 in execution FIG. 6A to FIG. 6E In some embodiments, Figure 5 The timetable is also applied to FIG. 6A to FIG. 6E It should be noted that only FIG. 6A to FIG. 6D The dimensions of the precursors shown in FIG. 1 are for reference only and do not limit the scope of the embodiments.

[0059] refer to Figure 2 , Figure 3 ,and Fig. 6A. In operation S12 of method M1, a wafer is placed on a suction cup of a manufacturing device. In some embodiments, the surface of the structure (i.e., substrate 110 and mask layer 120) may be terminated with a termination substance TS. In some examples, the termination substance TS is hydroxide (-OH), oxygen (-O), etc. For example, due to a cleaning or photoresist stripping process performed on the surface of substrate 110 and mask layer 120 and / or by exposing the surface of substrate 110 and mask layer 120, termination by hydroxide (-OH) and / or oxygen (-O) may occur in a natural environment containing oxygen. The termination species TS may be other species, such as hydrogen (-H), nitrogen (-N), ammonia (-NH3), etc., such as depending on the cleaning and / or stripping process performed on the surface. In some embodiments, the surface of substrate 110 and mask layer 120 initially carries the termination species TS. That is, substrate 110 and mask layer 120 include the termination substance TS itself. In some other embodiments, the surfaces of the substrate 110 and the mask layer 120 are initially neutral, and surface treatment (e.g., the cleaning and / or stripping processes described above) may be performed on the surfaces to change or modify the surface termination. In still other embodiments, H2O is fed into the chamber 110 to form a termination substance TS on the surface.

[0060] In operation S14 of method M1, a bias voltage is applied to the chuck. Fig. 6A In the case of , the bias is a negative DC bias. With a negative DC bias, since the conductivity of the substrate 110 (e.g., semiconductor material) is higher than the conductivity of the mask layer 120 (e.g., dielectric layer), charges (electrons in this case) are accumulated in the substrate 110, so that, as shown in FIG. Fig. 6A As shown, more charges remain near the surface of the substrate 110. Figure 3 The bias source 270 in FIG. 2 is configured to apply a negative DC bias to the chuck 220 , and the bias may have a power greater than about 0 W and equal to or less than about 50 W, for example, about 20 W.

[0061] In some embodiments, Figure 5 As shown, the bias applied to the chuck 220 allows the first time period T1 to continue. The bias is applied before the precursor is fed into the chamber 210. Once the negative DC bias is applied to the chuck 220, the electrons move to the surface of the substrate 110. Therefore, in this case, the surface of the substrate 110 is negatively charged.

[0062] In operation S16 of method M1, a first precursor is fed into a chamber of a manufacturing apparatus. Figure 3 and Figure 6BFor example, a first precursor P1' (in this case, for example, a silicon precursor) is fed from a precursor conveyor 240 into the chamber 210. In some embodiments, by controlling the temperature of the chamber 210 and / or feeding a reactive gas into the chamber 210, a chemical reaction occurs, thereby removing a substituent from the first precursor P1', so that the first precursor P1' partially becomes positive. The first precursor P1' having a partial positive charge is mostly attracted to the substrate 110, and thus is mostly deposited on the substrate 110 rather than on the mask layer 120. As shown in FIG. Figure 6C As shown, the first precursor P1' is mostly absorbed on the surface 112 of the substrate 110. In some embodiments, there is still some first precursor P1' absorbed on the surface of the dielectric material (ie, the mask layer 120 and the pad layer 130 in this case).

[0063] In the second period T2, the first precursor P1' is fed into the chamber 210 (see Figure 5 ). In some embodiments, Figure 5 The third period T3 in the step is long enough to charge the mask layer 120, and Figure 5 The fourth time period T4 is long enough to provide a reaction time for the deposition of the first precursor. In addition, during operation S14 and operation S16, the plasma source 230 is turned off so that when the bias is applied to the chuck 220, there is no plasma or negligible plasma in the chamber 210. In some other embodiments, the first precursor P1' is a plasma, and the first precursor P1' is fed from the plasma source 230 into the chamber 210. During this process, the plasma comes from the plasma source 230 instead of in the chamber 210, so a bias with a lower power can be applied to the chuck 220 to perform a selective ALD process.

[0064] In operation S18 of method M1, the bias voltage is turned off, and then in operation S20 of method M1, the excess first precursor is purged out of the chamber. In operation S22 of method M1, the second precursor is fed into the chamber of the manufacturing apparatus. Figure 3 and Fig.6D For example, a second precursor P2' (eg, an oxidant such as H2O vapor, O3, or O2 plasma in this case) is fed into the chamber 210 from a precursor conveyor 240 or a plasma source 230 (for O2 plasma oxidant). Fig.6D As shown, the second precursor P2' is attracted by the first precursor absorbed on the substrate 110. The second precursor P2' may be attracted by the first precursor, so more second precursor P2' is deposited on the surface of the substrate 110, and less second precursor P2' is deposited on the surfaces of the mask layer 120 and the pad layer 130. Fig. 6E As shown, a dielectric film 140 is formed on the surfaces of the substrate 110, the mask layer 120, and the pad layer 130.

[0065] exist Figure 5 In some embodiments, the second precursor P2' is charged and replaced for a fifth period T5. Figure 5 The sixth time period T6 is used to neutralize the surface 112 of the substrate 110. In some embodiments, Figure 5 The seventh time period T7 provides a reaction time for the second precursor deposition.

[0066] In operation S24 of method M1, excess second precursor is purged from the chamber. After operation S24, as Fig. 6E As shown, the dielectric film 140" is mostly formed on the surface of the substrate 110, and the dielectric film 140" may expose a portion of the surface of the mask layer 120 (and the pad layer 130). That is, the selective ALD deposition process results in no or negligible dielectric film 140" being deposited on the mask layer 120 and the pad layer 130. Then, the method M1 proceeds to operation S14 to repeat operations S14 to S24, and another dielectric film is formed on the dielectric film 140". Figure 1C As shown, the cycle of operations S14 to S24 may be repeated multiple times to form isolation material 140' in trench 114. In operation S26 of method M1, the wafer is taken out of the chamber to perform a next manufacturing process.

[0067] Figure 7 is a flow chart of a method M2 of a bias-induced selective ALD process according to some embodiments of the present disclosure. FIG. 8A to FIG. 8E According to some embodiments of the present disclosure, Figure 1C The cross-sectional view is taken along the line AA of FIG. Throughout the various views and illustrative embodiments, the same reference numerals are used to designate the same elements. The present embodiment may be repeated in FIG. 4A to FIG. 4E Reference numerals and / or letters are used in the following description. This repetition is for simplicity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. In the following embodiments, the structural and material details previously described are not repeated below and only provide further information to perform the present invention. FIG. 8A to FIG. 8E In some embodiments, Figure 3 The manufacturing device 200 is executed FIG. 8A to FIG. 8E It should be noted that only the isolation material 140' is shown. FIG. 8A to FIG. 8D The dimensions of the precursors shown in FIG. 1 are for reference only and do not limit the scope of the embodiments.

[0068] refer to Figure 3 , Figure 7 ,and Fig. 8AIn operation S12 of method M2, the wafer is placed on a chuck of a manufacturing apparatus. In some embodiments, the surface of the structure (ie, substrate 110 and mask layer 120) may be terminated with a termination substance TS. In operation S16 of method M2, a first precursor is fed into a chamber of the manufacturing apparatus. Figure 3 and Fig. 8A For example, a first precursor P1' (in this case, for example, a silicon precursor) is fed from a precursor conveyor 240 into the chamber 210. Figure 8B As shown, the first precursor P1 ′ is absorbed on the surfaces of the substrate 110 and the mask layer 120 .

[0069] Fig. 9 is a timing diagram of bias pulses and precursors provided according to some embodiments. Figure 3 , Fig. 8A ,and Fig. 9 .exist Fig. 9 In the eighth time period T8, the first precursor P1' is fed into the chamber 210. In some embodiments, during operation S16, the plasma source 230 is turned off so that when the first precursor P1' is fed into the chamber 210, there is no plasma or negligible plasma in the chamber 210. In some other embodiments, the first precursor P1 is plasma, and the first precursor P1 is fed into the chamber 210 from the plasma source 230. In some embodiments, Fig. 9 The ninth time period T9 is long enough to provide reaction time for the first precursor deposition.

[0070] In operation S20 of method M2, excess first precursor is purged from the chamber, such as Figure 8B As shown, the first precursor is absorbed on the surfaces of the substrate 110 and the mask layer 120. In operation S14 of method M2, a bias voltage is applied to the chuck. Figure 8C In the case of , the bias is a positive DC bias. With a positive DC bias, since the conductivity of the substrate 110 (e.g., semiconductor material) is higher than the conductivity of the mask layer 120 (e.g., dielectric layer), charges (in this case, holes) accumulate in the substrate 110, such that, as Figure 8C As shown, more charges remain near the surface of the substrate 110. Figure 3 The bias source 270 in FIG. 2 is configured to apply a positive DC bias to the chuck 220 , and the bias may have a power greater than about 0 W and equal to or less than about 50 W, for example, about 20 W.

[0071] like Fig. 9As shown, in some embodiments, the bias applied to the chuck 220 continues for a tenth time period T10. The bias is applied before the second precursor P2' is fed into the chamber 210. Once the positive DC bias is applied to the chuck 220, the electron holes move to the surface 112 of the substrate 110. Therefore, in this case, the surface 112 of the substrate 110 is positively charged.

[0072] In operation S22 of method M2, a second precursor is fed into a chamber of the manufacturing apparatus. Figure 3 and Fig.8D For example, a second precursor P2' (e.g., H2O in this case) is fed from the precursor conveyor 240 into the chamber 210. The positive charges (holes) near the surface of the substrate 110 attract the H2O molecules due to their partial negative charges (oxygen). The H2O molecules may be mostly attracted to the substrate 110 and thus mostly deposited on the substrate 110 rather than on the mask layer 120. Fig. 8E As shown, most of the H2O molecules are absorbed on the surface 112 of the substrate 110 to form the dielectric film 140". In some embodiments, there are still some H2O molecules absorbed on the surface of the dielectric material (ie, the mask layer 120 and the pad layer 130 in this case).

[0073] refer to Fig. 9 . After the bias applied to the suction cup 220 is turned on and before the bias is turned off, the first precursor P2' is fed into the chamber 210 for the eleventh time period T11. In some embodiments, the eleventh time period T11 is many times shorter than the tenth time period T10. In addition, after the feeding of the second precursor P2' is stopped, the bias is turned off. The twelfth time period T12 is between the start of the bias supply and the start of the second precursor feeding, and the thirteenth time period T13 is between the end of the second precursor feeding and the end of the bias supply. In some embodiments, the twelfth time period T12 is long enough to charge the substrate 110, and the thirteenth time period T13 is long enough to provide reaction time for the second precursor deposition.

[0074] In operation S18 of method M2, the bias voltage is turned off, and in operation S24 of method M2, the excess second precursor is purged from the chamber. Fig. 8E As shown, the dielectric film 140" is mostly formed on the surface 112 of the substrate 110, and the dielectric film 140" may expose a portion of the surface of the mask layer 120 (and the pad layer 130). That is, the dielectric film 140" is not or almost not deposited on the mask layer 120 and the pad layer 130. Then, the method M2 proceeds to operation S16 to repeat operations S16 to S24, and another dielectric film is formed on the dielectric film 140". Figure 1CAs shown, the cycle of operations S16 to S24 may be repeated multiple times to form isolation material 140' in trench 114. In operation S26 of method M2, the wafer is taken out of the chamber to perform a next manufacturing process.

[0075] FIG. 10A to FIG. 10I is a perspective view of a method for manufacturing a semiconductor device at various stages according to some embodiments of the present disclosure. In some embodiments, FIG. 6A to FIG. 6E The semiconductor devices shown in the drawings may be intermediate devices fabricated during processing of an integrated circuit (IC) or a portion thereof, which may include static random access memory (SRAM), logic circuits, passive components such as resistors, capacitors, and inductors, and / or active components such as p-type field effect transistors (PFETs), n-type FETs (NFETs), multi-gate FETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof.

[0076] refer to Fig. 10A A semiconductor structure is provided. The semiconductor structure includes a substrate 110, a plurality of semiconductor fins 116, and an isolation structure 140 laterally surrounding the semiconductor fins 116. In some embodiments, the formation of the semiconductor fins 116 may be Figure 1B The process shown is the same or similar, and therefore, the detailed description is not repeated. In some embodiments, the formation of the isolation structure 140 can be similar to Figure 1C to Figure 1E The process shown. In some other embodiments, the isolation structure 140 may include a trench filled with an insulator material such as silicon oxide, silicon nitride, or silicon oxynitride. The filled trench may have a multi-layer structure, such as a thermal oxide liner layer and silicon nitride filling the trench. In some embodiments, the isolation structure 140 may be created by performing a flowable CVD process to deposit a dielectric material and using chemical mechanical planarization (CMP) to remove excess dielectric material.

[0077] Then, a dummy dielectric layer 310 is conformally formed to cover the semiconductor fins 116 and the isolation structure 140. In some embodiments, the dummy dielectric layer 310 may include silicon dioxide, silicon nitride, a high-κ dielectric material, or other suitable materials. In various examples, the dummy dielectric layer 310 may be deposited by an ALD process, a CVD process, a sub-atmospheric pressure CVD (SACVD) process, a flowable CVD process, a PVD process, or other suitable processes. For example, the dummy dielectric layer 310 may be used to prevent damage to the semiconductor fins 116 by subsequent processing (e.g., subsequent formation of a dummy gate structure).

[0078] Subsequently, at least one dummy gate structure 320 is formed over the dummy dielectric layer 310, the semiconductor fins 116, and the isolation structure 140. The dummy gate structure 320 includes a dummy gate electrode 322, a pad layer 324 formed over the dummy gate electrode 322, and a hard mask layer 326 formed over the pad layer 324. In some embodiments, a dummy gate layer (not shown) may be formed over the dummy dielectric layer 310, and the pad layer 324 and the hard mask layer 326 are formed over the dummy gate layer. Then, the dummy gate layer is patterned using the pad layer 324 and the hard mask layer 326 as a mask to form the dummy gate electrode 322. In this way, the dummy gate electrode 322, the pad layer 324, and the hard mask layer 326 are referred to as a dummy gate structure 320. In some embodiments, the dummy gate electrode 322 may be made of polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), or other suitable materials. The pad layer 324 may be made of silicon dioxide or other suitable materials, and the hard mask layer 326 may be made of silicon nitride or other suitable materials.

[0079] refer to Fig. 10B The portion of the dummy dielectric layer 310 not covered by the dummy gate structure 320 is removed to expose the semiconductor fin 116. Then, a spacer structure 330 is formed at least on the opposite side of the dummy gate structure 320. The spacer structure 330 may include a sealing spacer and a main spacer (not shown). The spacer structure 330 includes one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, SiCN, SiC x O y N z , or a combination thereof. The sealing spacer is formed on the sidewall of the dummy gate structure 320, and the main spacer is formed on the sealing spacer. The spacer structure 330 can be formed using a deposition method such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sub-atmospheric pressure chemical vapor deposition (SACVD), etc. The formation of the spacer structure 330 may include blanket forming a spacer layer and then performing an etching operation to remove a horizontal portion of the spacer layer. The remaining vertical portion of the spacer layer forms the spacer structure 330.

[0080] refer to Fig. 10C. Then, an epitaxial structure 340 is formed on the portion of the semiconductor fin 116 not covered by the dummy gate structure 320 and the spacer structure 330 by performing, for example, a selective growth process. The epitaxial structure 340 is formed by epitaxially growing a semiconductor material. The semiconductor material includes a single element semiconductor material such as germanium (Ge) or silicon (Si); a compound semiconductor material such as gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs), or a semiconductor alloy such as silicon germanium (SiGe) and gallium arsenide phosphide (GaAsP). The epitaxial structure 340 has a suitable crystal orientation (for example, (100), (110), or (111) crystal orientation). In some embodiments, the epitaxial structure 340 includes a source / drain epitaxial structure. In some embodiments, where an N-type device is required, the epitaxial structure 340 may include epitaxially grown silicon phosphorus (SiP) or silicon carbon (SiC). In some embodiments, where a P-type device is required, the epitaxial structure 340 may include epitaxially grown silicon germanium (SiGe). The epitaxial process includes CVD deposition techniques (eg, vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and / or other suitable processes.

[0081] refer to Fig. 10D The contact etch stop layer (CESL) 350 is conformally formed on Fig. 10C In some embodiments, the CESL 350 may be one or more stress layers. In some embodiments, the CESL 350 has tensile stress and is formed of Si3N4. In some other embodiments, the CESL 350 includes a material such as oxynitride. In still other embodiments, the CESL 350 may have a composite structure including a plurality of layers, such as a silicon nitride layer covering a silicon oxide layer. The CESL 350 may be formed using plasma enhanced CVD (PECVD), however, other suitable methods may also be used, such as low pressure CVD (LPCVD), atomic layer deposition (ALD), etc.

[0082] Then, an interlayer dielectric (ILD) 360 is formed on the CESL 350. The ILD 360 may be formed by chemical vapor deposition (CVD), high-density plasma CVD, spin coating, sputtering, or other suitable methods. In some embodiments, the ILD 360 includes silicon oxide. In some other embodiments, the ILD 360 may include silicon oxynitride, silicon nitride, or a low-k material. Then, a planarization process such as a chemical mechanical planarization (CMP) process is performed to planarize the ILD 360 and the CESL 350 to expose the dummy gate structure 320.

[0083] refer to Fig. 10EThe replacement gate (RPG) process scheme is adopted. In the RPG process scheme, a pseudo polysilicon gate (in this case Fig. 10A In some embodiments, the dummy gate structure 320 is removed to form a gate trench 332 having the spacer structure 330 as its sidewalls. In some other embodiments, the dummy dielectric layer 310 is also removed (see Fig. 10B ). The dummy gate structure 320 (and the dummy dielectric layer 310) may be removed by dry etching, wet etching, or a combination of dry etching and wet etching. For example, the wet etching process may include exposure to a hydroxide-containing solution (e.g., ammonium hydroxide), deionized water, and / or other suitable etchant solutions.

[0084] refer to Fig.10F A gate dielectric layer 372 is formed in the gate trench 332. The gate dielectric layer 372 is formed by performing a bias induced selective ALD process, as described in more detail below. FIG. 11A to FIG. 11F According to some embodiments of the present disclosure, Fig.10F In some embodiments, the cross-sectional view can be taken along the line BB. Figure 3 The manufacturing device 200 is formed Fig.10F The gate dielectric layer 372 in the embodiment of the present invention and / or by performing Figure 2 The gate dielectric layer 372 is formed by the method M1 in the embodiment. In some embodiments, Figure 5 The timing diagram is also applied to FIG. 11A to FIG. 11F It should be noted that only the FIG. 11B to FIG. 11D The dimensions of the precursors shown in FIG. 1 are for reference only and do not limit the scope of the embodiments.

[0085] refer to Figure 2 , Figure 3 ,and Fig.11A In operation S12 of method M1, a wafer is placed on a suction cup in a manufacturing device. For example, a wafer (eg, Fig. 10E The structure in (a) is placed on a chuck 220 of the fabrication apparatus 200. In some embodiments, a vacuum is applied to the chamber 210 to remove oxygen and moisture and / or to raise the temperature to an acceptable level suitable for ALD deposition.

[0086] In operation S14 of method M1, a bias voltage is applied to the suction cup. Fig.11A In this case, an RF bias is applied to the chuck 220. With the RF bias, since the conductivity of the spacer structure 330 (e.g., dielectric layer) is lower than the conductivity of the substrate 110 (e.g., semiconductor material), the charges (in this case, electrons) move less within the spacer structure 330 (and the ILD 360), thereby Fig.11AAs shown, more charges are retained near the surface of the spacer structure 330 (and the ILD 360). In addition, since electrons are lighter than ions, electrons are more likely to accumulate near the surface of the spacer structure 330. In some embodiments, the bias voltage may have a power greater than about 0 W and equal to or less than about 50 W, such as about 20 W. If the power is greater than about 50 W, the gas (e.g., precursor / processing gas) in the chamber 210 may be ionized to form a plasma, which may bombard the wafer to damage the structure formed thereon.

[0087] In some embodiments, Figure 5 As shown, the bias applied to the chuck 220 allows the first time period T1 to continue. The bias is applied before the precursor is fed into the chamber 210. Once the RF bias is applied to the chuck 220, the electrons move to the surface of the spacer structure 330 (and the ILD 360). Therefore, in this case, the surface of the spacer structure 330 (and the ILD 360) is negatively charged.

[0088] In operation S16 of method M1, a first precursor is fed into a chamber of a manufacturing apparatus. Figure 3 and Fig. 11B For example, a first precursor P1 (eg, H2O in this case) is fed from a precursor conveyor 240 into the chamber 210. Fig. 11B As shown, the negative charges (electrons) near the surface of the spacer structure 330 repel the H2O molecules due to their partial negative charges (oxygen). The H2O molecules may be mostly attracted to the substrate 110 and thus deposited on the substrate 110 instead of the spacer structure 330 and the ILD 360. Fig. 11C As shown, the H2O molecules are mostly absorbed on the surface 112 of the substrate 110. In other words, more H2O molecules are deposited on the substrate 110 rather than on the spacer structure 330 and the ILD 360. In some embodiments, there is still some H2O absorbed on the surface of the dielectric material (i.e., the spacer structure 330 in this case).

[0089] In the second period T2, the first precursor P1 is fed into the chamber 210 (see Figure 5 ). In some embodiments, Figure 5 The third time period T3 in is long enough to charge the spacer structure 330, and Figure 5The fourth time period T4 is long enough to provide a reaction time for the deposition of the first precursor. In addition, during operation S14 and operation S16, the plasma source 230 is turned off so that when the bias is applied to the chuck 220, there is no plasma or negligible plasma in the chamber 210. In some other embodiments, the first precursor P1 is a plasma, and the first precursor P1 is fed from the plasma source 230 into the chamber 210. During this process, the plasma comes from the plasma source 230 instead of in the chamber 210, so a bias with a lower power can be applied to the chuck 220 to perform a selective ALD process.

[0090] In operation S18 of method M1, the bias voltage is turned off, and then in operation S20 of method M1, the excess first precursor P1 is purged out of the chamber. Specifically, during time periods T2 and T4, the first precursor P1 is mostly absorbed onto the surface 112 of the substrate 110 (see FIG. Figure 5 ), and some of the first precursor P1 is absorbed onto the surface of the spacer structure 330. After the fourth period T4, the bias voltage is turned off so that the electrons near the surface of the spacer structure 330 gradually disappear. Then, the charging gas enters the chamber 210 to purge the excess first precursor P1 out of the chamber 210.

[0091] In operation S22 of method M1, a second precursor is fed into a chamber of the manufacturing apparatus. Figure 3 and Fig.11D For example, a second precursor P2 (in this case, for example, a high-k precursor) is fed from a precursor conveyor 240 into the chamber 210. Fig.11D As shown, the second precursor P2 is attracted by the first precursor (in this case, -OH) absorbed on the substrate 110. The second precursor P2 may be attracted by the -OH and thus be mostly deposited on the substrate 110 instead of the spacing structure 330. Fig.11E As shown, the second precursor P2 is mostly absorbed on the surface 112 of the substrate 110 and forms a dielectric film 372 thereon. Fig.11E As shown, a first growth rate (ie, deposition rate) of the dielectric film 372 ″ on the substrate 110 is greater than a second growth rate on the spacer structure 330 , and greater than a third growth rate on the ILD 360 .

[0092] In some embodiments, the dielectric film 372" can be a high-k dielectric layer, such as Al2O3, ZrO2, HfO2, TiO2, or other suitable materials. When the single layer is made of Al2O3, the second precursor P2 can be trimethylaluminum (TMA), triethylaluminum (TEA), tetrakis(dimethylamino)aluminum (TDMAA), or other suitable materials. When the single layer is made of ZrO2, the fourth precursor P4 can be tetrakis(dimethylamino)zirconium (TDMAZ), ZrCl4, or other suitable materials. When the single layer is made of HfO2, the second precursor P2 can be tetrakis(dimethylamino)zirconium (TDMAH), HfCl4, or other suitable materials. When the single layer is made of TiO2, the second precursor P2 can be tetrakis(dimethylamino)titanium (TDMAT), TiCl4, or other suitable materials.

[0093] exist Figure 5 In some embodiments, the second precursor P2 is charged and replaced for a fifth period T5. Figure 5 The sixth period T6 is used to neutralize the surface of the spacer structure 330. In some embodiments, Figure 5 The seventh time period T7 provides a reaction time for the second precursor deposition.

[0094] In operation S24 of method M1, excess second precursor is purged from the chamber. After operation S24, as Fig.11E As shown, the dielectric film 372" is mostly formed on the surface 112 of the substrate 110, and the dielectric film 372" may expose a portion of the surface of the spacer structure 330 (and the ILD 360). That is, the selective ALD deposition process results in no or negligible dielectric film 372" being deposited on the spacer structure 330 and / or the ILD 360. For example, the dielectric film 372" may be unintentionally deposited on the spacer structure 330 and / or the ILD 360 to have a thickness thinner than that deposited on the substrate 110. Then, the method M1 proceeds to operation S14 to repeat operations S14 to S24, and another dielectric film is formed on the dielectric film 372". As shown in FIG. Fig.11F and 10F As shown, the cycle of operations S14 to S24 may be repeated multiple times to form a dielectric layer 372 ′ in the opening 332 .

[0095] exist Fig.11FIn the method M1, the dielectric layer 372' has a bottom portion 372b and a sidewall portion 372s. The bottom portion 372b contacts the substrate 110, and the sidewall portion 372s contacts the spacer structure 330. Due to the bias-induced selective ALD process, the thickness t1 of the bottom portion 372b is greater than the thickness t2 of the sidewall portion 372s. With this configuration, the bottom portion 372b is thick enough to isolate the semiconductor fin 116 and the subsequently formed gate electrode, while the sidewall portion 372s is thin enough to provide a large window for depositing the gate metal material. In operation S26 of method M1, the wafer is taken out of the chamber for the next manufacturing process.

[0096] refer to Figure 10G At least one metal layer is formed in the gate trench 332 and on the gate dielectric layer 372. Subsequently, a chemical mechanical planarization (CMP) process is performed to planarize the metal layer and the dielectric layer 372' (see Fig.10F ) to form a metal gate structure 370 in the opening 332. The metal gate structure 370 spans the semiconductor fin 116. The metal gate structure 370 includes a gate dielectric layer 372 and a metal gate electrode above the gate dielectric layer 372. The metal gate electrode may include one or more metal layers 374, for example, one or more work function metal layers and one or more capping layers, a fill metal 376, and / or other suitable layers. The work function metal layer may include n-type and / or p-type work function metals. Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. The work function metal layer may have multiple layers. One or more work function metal layers may be deposited by CVD, PVD, electroplating and / or other suitable processes. In some embodiments, the metal gate electrode is a p-type metal gate including a p-type work function metal layer. In some embodiments, the capping layer in the metal gate electrode may include a refractory metal and its nitride (e.g., TiN, TaN, W2N, TiSiN, TaSiN). The capping layer may be deposited by PVD, CVD, metal organic chemical vapor deposition (MOCVD) ALD, etc. In some embodiments, the filling metal 376 filling the rest of the gate trench 332 may include tungsten (W). The filling layer 376 may be deposited by ALD, PVD, CVD, or other suitable processes.

[0097] refer to Fig. 10HIn some embodiments, the metal gate structure 370 is etched back to a predetermined level and another gate trench 378 is formed thereon. Then, a capping layer 380 is formed over the etched metal gate structure 370 using, for example, a deposition process to deposit a dielectric material over the substrate 110, followed by a CMP process to remove excess dielectric material outside the gate trench. In some embodiments, the capping layer 380 includes silicon nitride or other suitable dielectric material. In some embodiments, the selective ALD process induced by the bias voltage as described above and using Figure 3 The manufacturing device 200 is used to form the cover layer 380. Since the formation of the cover layer 380 can be Figure 1C The formation of the isolation material 140' in FIG. 3 is the same or similar, so the detailed description in this regard will not be repeated. The capping layer 380 may be used to define a self-aligned contact region, and is therefore referred to as a SAC structure or SAC layer.

[0098] refer to Fig.10I A plurality of source / drain contacts 390 are formed over the epitaxial structure 340. For example, a plurality of source / drain openings are formed through the ILD 360 and the CESL 350 to expose the source / drain epitaxial structure 340, and a conductive material is filled in the openings and over the source / drain epitaxial structure 340. Excess portions of the conductive material are removed to form the source / drain contacts 390. The source / drain contacts 390 may be made of tungsten, aluminum, copper, or other suitable materials.

[0099] exist Fig.10F and Fig.11F , a dielectric layer 372' is formed by performing a bias-induced selective ALD process. By providing a bias on the suction cup 220, the charge has different distributions in different materials. The charge can attract or repel the precursor to increase or decrease the corresponding deposition rate. With this configuration, the bottom 372b of the dielectric layer 372' is thick enough to isolate the semiconductor fin 116 and the subsequently formed gate electrode, while the sidewall portion 372s of the dielectric layer 372' is thin enough to provide a large window for depositing the gate electrode. In addition, self-aligned monolayers (SAMs) that can be formed using an additional deposition process and cause defect problems can be omitted to simplify the manufacturing process.

[0100] In addition, Fig. 10HIn the embodiment of the present invention, the capping layer 380 may be formed by performing a bias-induced selective ALD process. By providing a bias on the suction cup 220, the charge has different distributions in different materials. The charge may attract or repel the precursor to increase or decrease the corresponding deposition rate. In some other embodiments, when there is a high deposition selectivity between the dielectric layer (i.e., the spacer structure 330 and the ILD 360) and the conductive layer (i.e., the metal gate structure 370), the planarization process (e.g., CMP) performed after depositing the capping layer 380 may be omitted. In addition, self-aligned monolayers (SAMs) that may be formed using an additional deposition process and cause defect problems may be omitted to simplify the manufacturing process.

[0101] Fig.10F The dielectric layer 372' in may be formed using other biases and / or precursors. FIG. 12A to FIG. 12F According to some embodiments of the present disclosure, Fig.10F The cross-sectional view is taken along the line BB of FIG. Throughout the various views and illustrative embodiments, the same reference numerals are used to designate the same elements. This embodiment may be repeated in FIG. 11A to FIG. 11E Reference numerals and / or letters are used in the following description. This repetition is for simplicity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. In the following embodiments, the structural and material details previously described are not repeated below and only provide further information to perform the present invention. FIG. 12A to FIG. 12F In some embodiments, Figure 3 The manufacturing device 200 and / or using Figure 2 Method M1 in the implementation Figures 12A to 12F In some embodiments, Figure 5 The timing diagram is also applied to FIG. 12A to FIG. 12F It should be noted that only the FIG. 12A to FIG. 12D The dimensions of the precursors shown in FIG. 1 are for reference only and do not limit the scope of the embodiments.

[0102] refer to Figure 2 , Figure 3 ,and Fig. 12A. In operation S12 of method M1, a wafer is placed on a suction cup of a manufacturing apparatus. In some embodiments, the surface of the structure (i.e., substrate 110, spacer structure 330, and ILD 360) can be terminated with a termination substance TS. In some embodiments, the surfaces of substrate 110, spacer structure 330, and ILD 360 initially carry termination species TS. In some other embodiments, the surfaces of substrate 110, spacer structure 330, and ILD 360 are initially neutral, and surface treatment (e.g., the cleaning and / or stripping process described above) can be performed on the surfaces to change or modify the surface termination. In still other embodiments, H2O is fed into chamber 210 to form termination substance TS on the surface.

[0103] In operation S14 of method M1, a bias voltage is applied to the chuck. Fig. 12A In the case of , the bias is a negative DC bias. With a negative DC bias, since the conductivity of the substrate 110 (e.g., semiconductor material) is higher than the conductivity of the spacer structure 330 and the ILD 360 (e.g., dielectric layer), charges (electrons in this case) accumulate in the substrate 110, such that, as Fig. 12A As shown, more charges remain near the surface of the substrate 110. Figure 3 The bias source 270 in FIG. 2 is configured to apply a negative DC bias to the chuck 220 , and the bias may have a power greater than about 0 W and equal to or less than about 50 W, for example, about 20 W.

[0104] In some embodiments, Figure 5 As shown, the bias applied to the chuck 220 allows the first time period T1 to continue. The bias is applied before the precursor is fed into the chamber 210. Once the negative DC bias is applied to the chuck 220, the electrons move to the surface 112 of the substrate 110. Therefore, in this case, the surface of the substrate 110 is negatively charged.

[0105] In operation S16 of method M1, a first precursor is fed into a chamber of a manufacturing apparatus. Figure 3 and Fig. 12B For example, a first precursor P1' (in this case, for example, a high-k precursor) is fed from a precursor conveyor 240 into the chamber 210. In some embodiments, by controlling the temperature of the chamber 210 and / or feeding a reactive gas into the chamber 210, a chemical reaction occurs, thereby removing a substituent from the first precursor P1', so that the first precursor P1' partially becomes positive. The first precursor P1' having a partial positive charge is mostly attracted to the substrate 110, and thus is mostly deposited on the substrate 110 rather than on the mask layer 120. As shown in FIG. Fig. 12CAs shown, the first precursor P1' is mostly absorbed on the surface 112 of the substrate 110. In some embodiments, some of the first precursor P1' is still absorbed on the surface of the dielectric material (ie, the spacer structure 330 and / or the ILD 360 in this case).

[0106] In the second period T2, the first precursor P1' is fed into the chamber 210 (see Figure 5 ). In some embodiments, Figure 5 The third period T3 in the step is long enough to charge the mask layer 120, and Figure 5 The fourth time period T4 is long enough to provide a reaction time for the deposition of the first precursor. In addition, during operation S14 and operation S16, the plasma source 230 is turned off so that when the bias is applied to the chuck 220, there is no plasma or negligible plasma in the chamber 210. In some other embodiments, the first precursor P1' is a plasma, and the first precursor P1' is fed from the plasma source 230 into the chamber 210. During this process, the plasma comes from the plasma source 230 instead of in the chamber 210, so a bias with a lower power can be applied to the chuck 220 to perform a selective ALD process.

[0107] In operation S18 of method M1, the bias voltage is turned off, and then in operation S20 of method M1, the excess first precursor is purged out of the chamber. In operation S22 of method M1, the second precursor is fed into the chamber of the manufacturing apparatus. Figure 3 and Fig.12D For example, a second precursor P2' (eg, an oxidant such as H2O vapor, O3, or O2 plasma in this case) is fed into the chamber 210 from the precursor conveyor 240 or the plasma source 230 (for O2 plasma oxidant). Fig.12D As shown, the second precursor P2' is attracted by the first precursor absorbed on the substrate 110. The second precursor P2' may be attracted by the first precursor, so more of the second precursor P2' is deposited on the surface 112 of the substrate 110 and less of the second precursor P2' is deposited on the surface of the spacer structure 330 (and / or the ILD 360). Fig.12E As shown, a dielectric film 372 ″ is formed on surfaces of the substrate 110 , the spacer structure 330 , and / or the ILD 360 .

[0108] exist Figure 5 In some embodiments, the second precursor P2' is charged and replaced for a fifth period T5. Figure 5 The sixth period T6 is used to neutralize the surface of the substrate 110. In some embodiments, Figure 5 The seventh time period T7 provides a reaction time for the second precursor deposition.

[0109] In operation S24 of method M1, excess second precursor is purged from the chamber. After operation S24, as Fig.12E As shown, the dielectric film 372" is mostly formed on the surface of the substrate 110, and the dielectric film 372" may expose a portion of the surface of the spacer structure 330 (and / or the ILD 360). That is, the selective ALD process results in no or negligible deposition of the dielectric film 372" on the spacer structure 330 and / or the ILD 360. Then, the method M1 proceeds to operation S14 to repeat operations S14 to S24, and another dielectric film is formed on the dielectric film 372". Fig.12F and 10F As shown, the cycle of operations S14 to S24 may be repeated multiple times to form a dielectric layer 372' in the gate trench. In operation S26 of method M1, the wafer is taken out of the chamber to perform a next manufacturing process.

[0110] FIG. 13A to FIG. 13F According to some embodiments of the present disclosure, Fig.10F The cross-sectional view is taken along the line BB of FIG. Throughout the various views and illustrative embodiments, the same reference numerals are used to designate the same elements. This embodiment may be repeated in FIG. 10A to FIG. 10F Reference numerals and / or letters are used in the following description. This repetition is for simplicity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. In the following embodiments, the structural and material details previously described are not repeated below and only provide further information to perform the present invention. FIG. 13A to FIG. 13F In some embodiments, Figure 3 The manufacturing device 200 is formed and used Figure 7 Method M2 in the implementation Figures 13A to 13F In some embodiments, Fig. 9 The timing diagram is also applied to FIG. 13A to FIG. 13F It should be noted that only the FIG. 13A to FIG. 13D The dimensions of the precursors shown in FIG. 1 are for reference only and do not limit the scope of the embodiments.

[0111] refer to Figure 3 , Figure 7 ,and Fig.13A In operation S12 of method M2, the wafer is placed on a chuck of a manufacturing apparatus. In some embodiments, the surface of the structure (ie, substrate 110, spacer structure 330, and ILD 360) may be terminated with a termination substance TS. In operation S16 of method M2, a first precursor is fed into a chamber of the manufacturing apparatus. Figure 3 and Fig.13AFor example, a first precursor P1' (in this case, for example, a high-k precursor) is fed from a precursor conveyor 240 into the chamber 210. Fig. 13B As shown, the first precursor P1 ′ is absorbed on the surfaces of the substrate 110 , the spacer structure 330 , and the ILD 360 simultaneously.

[0112] refer to Figure 3 , Fig. 9 ,and Fig.13A .exist Fig. 9 In the eighth time period T8, the first precursor P1' is fed into the chamber 210. In some embodiments, during operation S16, the plasma source 230 is turned off so that when the first precursor P1' is fed into the chamber 210, there is no plasma or negligible plasma in the chamber 210. In some other embodiments, the first precursor P1 is plasma, and the first precursor P1 is fed into the chamber 210 from the plasma source 230. In some embodiments, Fig. 9 The ninth time period T9 is long enough to provide reaction time for the first precursor deposition.

[0113] In operation S20 of method M2, excess first precursor is purged from the chamber, such as Fig. 13B As shown, the first precursor is absorbed on the surfaces of the substrate 110, the spacer structure 330, and the ILD 360. In operation S14 of method M2, a bias voltage is applied to the chuck. Fig. 13C In the case of , the bias is a positive DC bias. With a positive DC bias, since the conductivity of the substrate 110 (e.g., semiconductor material) is higher than the conductivity of the spacer structure 330 and the ILD 360 (e.g., dielectric layer), charges (in this case, holes) accumulate in the substrate 110, such that, as shown in FIG. Fig. 13B As shown, more charge remains near the surface 112 of the substrate 110. Figure 3 The bias source 270 in FIG. 2 is configured to apply a positive DC bias to the chuck 220 , and the bias may have a power greater than about 0 W and equal to or less than about 50 W, for example, about 20 W.

[0114] like Fig. 9 As shown, in some embodiments, the bias voltage applied to the suction cup 220 continues for a tenth time period T10. Fig.13D ) is fed into the chamber 210. Once a positive DC bias is applied to the chuck 220, the holes move to the surface 112 of the substrate 110. Therefore, in this case, the surface 112 of the substrate 110 is positively charged.

[0115] In operation S22 of method M2, a second precursor is fed into a chamber of the manufacturing apparatus. Figure 3 and Fig.13D For example, a second precursor P2' (e.g., H2O in this case) is fed from the precursor conveyor 240 into the chamber 210. The positive charges (holes) near the surface of the substrate 110 attract the H2O molecules due to their partial negative charges (oxygen). The H2O molecules may be mostly attracted to the substrate 110 and thus mostly deposited on the substrate 110 rather than on the spacer structure 330 (and / or ILD 360). Fig.13E As shown, the H 2 O molecules are mostly absorbed on the surface 112 of the substrate 110 to form a dielectric film 372 ”. In some embodiments, there are still some H 2 O molecules absorbed on the surface of the dielectric material (ie, the spacer structure 330 and the ILD 360 in this case).

[0116] refer to Fig. 9 . After the bias applied to the suction cup 220 is turned on and before the bias is turned off, the first precursor P2' is fed into the chamber 210 for the eleventh time period T11. In some embodiments, the eleventh time period T11 is many times shorter than the tenth time period T10. In addition, after the feeding of the second precursor P2' is stopped, the bias is turned off. The twelfth time period T12 is between the start of the bias supply and the start of the second precursor feeding, and the thirteenth time period T13 is between the end of the second precursor feeding and the end of the bias supply. In some embodiments, the twelfth time period T12 is long enough to charge the substrate 110, and the thirteenth time period T13 is long enough to provide reaction time for the second precursor deposition.

[0117] In operation S18 of method M2, the bias voltage is turned off, and in operation S24 of method M2, the excess second precursor is purged from the chamber. Fig.13E As shown, the dielectric film 372" is mostly formed on the surface of the substrate 110, and the dielectric film 372" may expose a portion of the surface of the spacer structure 330 (and / or the ILD 360). That is, the selective ALD process results in no or negligible deposition of the dielectric film 372" on the spacer structure 330 and the ILD 360. Then, the method M2 proceeds to operation S16 to repeat operations S16 to S24, and another dielectric film is formed on the dielectric film 372". Fig.13F and 10F As shown, the cycle of operations S16 to S24 may be repeated multiple times to form a dielectric layer 372' in the opening 332. In operation S26 of method M2, the wafer is taken out of the chamber to perform a next manufacturing process.

[0118] Fig.14 is a perspective view of a semiconductor device according to some embodiments. In some embodiments, after forming the dielectric layer 372' (eg, Fig.11F , Fig.12F,and Fig.13F In the process shown in FIG. 1 , an isotropic etching process is performed on the dielectric layer 372' to remove the sidewall portion 372s of the dielectric layer 372' and also to thin the bottom 372b of the dielectric layer 372'. Then, a metal layer 374 and a filling layer 376 are formed in the gate trench 332 to form a metal gate structure 370. Fig.14 In the embodiment, the metal layer 374 contacts the spacer structure 330 and the gate dielectric layer 372. Fig.14 Other structural and manufacturing details of the semiconductor device in Fig.10I The semiconductor devices are similar to those in the prior art and therefore will not be described in detail hereinbelow.

[0119] FIG. 15A to FIG. 15K is a perspective view of a method for manufacturing a semiconductor structure at various stages according to some embodiments of the present disclosure. In some embodiments, FIG. 15A to FIG. 15K The semiconductor structures shown in the drawings may be intermediate devices fabricated during processing of an integrated circuit (IC) or a portion thereof, which may include static random access memory (SRAM), logic circuits, passive components such as resistors, capacitors, and inductors; and / or active components such as p-type field effect transistors (PFETs), n-type FETs (NFETs), multi-gate FETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof.

[0120] refer to Fig.15A A substrate 410 is provided. The semiconductor substrate 410 may be or include a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. In some embodiments, the semiconductor material of the semiconductor substrate 410 may include an elemental semiconductor such as silicon (Si) and germanium (Ge); a compound semiconductor; an alloy semiconductor; or a combination thereof.

[0121] Various devices may be on the semiconductor substrate 410. For example, the semiconductor substrate 410 may include field effect transistors (FETs), such as Fin FETs (FinFETs), planar FETs, vertical all-around gate FETs (VGAA FETs), etc.; diodes; capacitors; inductors; and other devices. For example, the device may be formed entirely within the semiconductor substrate 410, in a portion of the semiconductor substrate 410 and a portion of one or more overlying layers, and / or entirely in one or more overlying layers. The processes described herein may be used to form devices and / or interconnect devices to form an integrated circuit. The integrated circuit may be any circuit, such as an application specific integrated circuit (ASIC), a processor, a memory, or other circuit.

[0122] The first dielectric layer 420 is formed on the semiconductor substrate 410. The first dielectric layer 420 can be directly on the semiconductor substrate 410, or any number of other layers can be disposed between the first dielectric layer 420 and the semiconductor substrate 410. For example, the first dielectric layer 420 can be or include an intermetallic dielectric (IMD) or an interlayer dielectric (ILD). The first dielectric layer 420, for example, can be or include a low-k dielectric having a gamma-ray diffraction pattern of less than about 4.0, such as about 2.0 or even less. In some examples, the first dielectric layer 420 includes silicon oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiO x C y , silicon-carbon materials, compounds thereof, composites thereof, or combinations thereof.

[0123] Conductive component 430 is in and / or through first dielectric layer 420. Conductive component 430 may be or include a wire and / or a conductive via, a gate structure of a transistor, or contact with a gate structure of a transistor and / or a source / drain region of a transistor. In some embodiments, first dielectric layer 420 is an IMD, and conductive component 430 may include a wire and / or a conductive via (collectively or individually, "interconnect structure"). Interconnect structure may be formed by, for example, passing through the IMD and / or forming openings and / or grooves in the IMD using a damascene process. Although other processes and interconnect structures may be implemented, some examples of forming interconnect structures are further described below. In other examples, first dielectric layer 420 may include an ILD, and conductive component 430 may include, for example, a gate electrode (e.g., tungsten, cobalt, etc.) in an ILD formed using a replacement gate process. In some other embodiments, first dielectric layer 420 may be an ILD, and conductive component 430 may include a contact. A contact may be formed by forming an opening through the ILD to reach, for example, a gate electrode and / or source / drain region of a transistor formed on the semiconductor substrate 410. The contact may include an adhesion layer (e.g., Ti, etc.), a barrier layer (e.g., TiN, etc.) on the adhesion layer, and a conductive fill material (e.g., tungsten, cobalt, etc.) on the barrier layer. The contact may also be made of a metal with low diffusivity, such as tungsten, molybdenum, or ruthenium, without a barrier layer.

[0124] The second dielectric layer 440 is formed on the first dielectric layer 420 and the conductive component 430. For example, the second dielectric layer 440 can be or include an IMD. The second dielectric layer 440 is deposited on the top surface of the first dielectric layer 420 and the conductive component 430. The second dielectric layer 440, for example, can be or include a low-k dielectric having a k value less than about 4.0, such as about 2.0 or even less. In some examples, the second dielectric layer 440 includes silicon oxide, PSG, BPSG, FSG, SiO x C y , silicon-carbon materials, compounds thereof, composites thereof, or combinations thereof. The second dielectric layer 440 may be deposited using CVD such as PECVD or flowable CVD (FCVD); spin coating; or another deposition technique. In some examples, chemical mechanical planarization (CMP) or another planarization process may be performed to planarize the top surface of the second dielectric layer 440.

[0125] At least one through hole 450 is formed in the second dielectric layer 440. In some embodiments, at least one opening is formed in the second dielectric layer 440, a conductive material is filled in the opening, and a planarization process is performed to remove excess conductive material. Thus, the through hole 450 is formed and contacts the conductive component 430. The through hole 450 can be made of tungsten, aluminum, copper, or other suitable materials.

[0126] Then, an etch stop layer (ESL) 460 is formed on the second dielectric layer 440 (see Fig.15H ). The ESL 460 is formed by performing a bias-induced selective ALD process, as described in more detail below. In some embodiments, Figure 3 The manufacturing device 200 and / or the execution Figure 2 The method M1 is used to form ESL 460. Furthermore, Figure 5 The timetable in can be applied to the formation of ESL 460. It should be noted that only FIG. 15C to FIG. 15E The dimensions of the precursors shown in FIG. 1 are for reference only and do not limit the scope of the embodiments.

[0127] refer to Figure 2 , Figure 3 ,and Fig. 15B In operation S12 of method M1, a wafer is placed on a suction cup in a manufacturing device. For example, a wafer (eg, Fig.15A The structure in (a) is placed on a chuck 220 of the fabrication apparatus 200. In some embodiments, a vacuum is applied to the chamber 210 to remove oxygen and moisture and / or to raise the temperature to an acceptable level suitable for ALD deposition.

[0128] In operation S14 of method M1, a bias voltage is applied to the suction cup. Fig. 15B In this case, a negative DC bias is applied to the chuck 220. With the DC bias, since the conductivity of the through hole 450 (e.g., conductive material) is higher than the conductivity of the second dielectric layer 440 (e.g., dielectric material), charges (electrons in this case) are accumulated in the through hole 450, such that, as shown in FIG. Fig. 15B As shown, more charges are retained near the surface of the through hole 450. In some embodiments, the bias voltage may have a power greater than about 0 W and equal to or less than about 50 W, for example, about 20 W. If the power is greater than about 50 W, the gas (e.g., precursor / processing gas) in the chamber 210 may be ionized to form plasma, which may bombard the wafer to damage the structure formed thereon.

[0129] In some embodiments, Figure 5 As shown, the bias applied to the chuck 220 allows the first time period T1 to continue. The bias is applied before the precursor is fed into the chamber 210. Once the negative DC bias is applied to the chuck 220, the electrons move to the surface of the through hole 450. Therefore, in this case, the surface of the through hole 450 is negatively charged.

[0130] In operation S16 of method M1, a first precursor is fed into a chamber of a manufacturing apparatus. Figure 3 and Fig. 15CFor example, a first precursor P1 (eg, H2O in this case) is fed from a precursor conveyor 240 into the chamber 210. Fig. 15C As shown, the negative charges (electrons) near the surface of the via 450 repel the H2O molecules due to the partial negative charges (oxygen) of the H2O molecules. The H2O molecules may be mostly attracted to the second dielectric layer 440 and thus deposited on the second dielectric layer 440 instead of the via 450. Fig.15D As shown, most of the H 2 O is absorbed on the surface 442 of the second dielectric layer 440 . In some embodiments, some H 2 O is still absorbed on the surface of the via 450 .

[0131] In the second period T2, the first precursor P1' is fed into the chamber 210 (see Figure 5 ). In some embodiments, Figure 5 The third period T3 in the embodiment is long enough to charge the via 450, and Figure 5 The fourth time period T4 is long enough to provide a reaction time for the deposition of the first precursor. In addition, during operation S14 and operation S16, the plasma source 230 is turned off so that when the bias is applied to the chuck 220, there is no plasma or negligible plasma in the chamber 210. In some other embodiments, the first precursor P1 is a plasma, and the first precursor P1 is fed from the plasma source 230 into the chamber 210. During this process, the plasma comes from the plasma source 230 instead of in the chamber 210, so a bias with a lower power can be applied to the chuck 220 to perform a selective ALD process.

[0132] In operation S18 of method M1, the bias voltage is turned off, and then in operation S20 of method M1, the excess first precursor P1 is purged out of the chamber. Specifically, during time periods T2 and T4, the first precursor P1 is mostly absorbed onto the surface 442 of the second dielectric layer 440 (see FIG. Figure 5 ), and some of the first precursor P1 is absorbed onto the surface of the through hole 450. After the fourth period T4, the bias voltage is turned off so that the electrons near the surface of the through hole 450 gradually disappear. Then, the charging gas enters the chamber 210 to purge the excess first precursor P1 out of the chamber 210.

[0133] In operation S22 of method M1, a second precursor is fed into a chamber of the manufacturing apparatus. Figure 3 and Fig.15E For example, a second precursor P2 (in this case, for example, a high-k precursor) is fed from a precursor conveyor 240 into the chamber 210. Fig.15EAs shown, the second precursor P2 is attracted by the first precursor (in this case, -OH) absorbed on the second dielectric layer 440. The second precursor can be attracted by -OH and thus is mostly deposited on the second dielectric layer 440 instead of on the via 450. Fig.15F As shown, the second precursor P2 is mostly absorbed on the surface 442 of the second dielectric layer 440 and forms a dielectric film 460 ″ thereon. In some embodiments, the dielectric film 460 ″ may be a high-k dielectric layer.

[0134] exist Figure 5 In some embodiments, the second precursor P2 is charged and replaced for a fifth period T5. Figure 5 The sixth period T6 is used to neutralize the surface of the through hole 450. In some embodiments, Figure 5 The seventh time period T7 provides a reaction time for the second precursor deposition.

[0135] In operation S24 of method M1, excess second precursor is purged from the chamber. After operation S24, as Fig.15F As shown, the dielectric film 460" is mostly formed on the surface 442 of the second dielectric layer 440, and the dielectric film 460" may expose a portion of the surface of the through hole 450. That is, the selective ALD process results in no or negligible deposition of the dielectric film 460" on the through hole 450. Then, the method M1 proceeds to operation S14 to repeat operations S14 to S24, and another dielectric film is formed on the dielectric film 460". Figure 15G As shown, the cycle of operation S14 to operation S24 may be repeated multiple times to form a dielectric layer 460' on the second dielectric layer 440. Figure 15G , the dielectric layer 460' includes a thick portion 460a directly above the second dielectric layer 440 and a thin portion 460b directly above the through hole 450. The thickness t3 of the thick portion 460a is greater than the thickness t4 of the thin portion 460b.

[0136] refer to Fig.15H The dielectric layer 460' is etched to remove Figure 15G The thin portion 460b is formed and the thin portion 460a is thinned. Thus, the ESL 460 is formed. The ESL 460 exposes the through hole 450 while covering the second dielectric layer 440. In some embodiments, the sidewalls of the ESL 460 are substantially aligned with the sidewalls of the through hole 450.

[0137] refer to Fig.15IA third dielectric layer 470 is formed over ESL 460. For example, third dielectric layer 470 may be or include an IMD. Third dielectric layer 470 is deposited on a top surface of ESL 460 and in contact with via 450. Third dielectric layer 470, for example, may be or include a low-k dielectric having a k value of less than about 4.0, such as about 2.0 or even less. In some examples, third dielectric layer 470 includes silicon oxide, PSG, BPSG, FSG, SiO x C y , silicon-carbon materials, compounds thereof, composites thereof, or combinations thereof. The third dielectric layer 470 may be deposited using CVD such as PECVD or flowable CVD (FCVD); spin coating; or another deposition technique. In some examples, chemical mechanical planarization (CMP) or another planarization process may be performed to planarize the top surface of the third dielectric layer 470.

[0138] refer to Fig.15J . An opening 472 is formed in the third dielectric layer 470. The opening 472 may be formed using a photolithography and etching process, such as in a dual damascene process. For example, the photoresist may be patterned with a pattern corresponding to the opening 472, such as by forming a photoresist on the third dielectric layer 470 using spin coating, and by exposing the photoresist to light using an appropriate photomask. Then, the exposed portion or the unexposed portion of the photoresist may be removed depending on whether a positive photoresist or a negative photoresist is used. Then, the pattern of the photoresist may be transferred to the third dielectric layer 470, such as by using a suitable etching process, which forms the opening 472 in the third dielectric layer 470. The etching process may include reactive ion etching (RIE), neutral beam etching (NBE), inductively coupled plasma (ICP) etching, etc., or a combination thereof. The etching process may be anisotropic. The ESL 460 serves as an etching stop for the etching process so that the opening 472 does not expose the second dielectric layer 440, but exposes the through hole 450. The photoresist is subsequently removed, for example, in an ashing or wet stripping process.

[0139] refer to Figure 15K A conductive line 480 is formed in the opening 472. For example, a conductive material is filled in the opening 472 (see Fig.15J ). The conductive material includes at least a metal element, such as copper (Cu). The conductive material may include other suitable materials, such as Ru, W, Ti, Al, Co, or a combination thereof. Then, after forming the conductive material, a planarization process (e.g., CMP) is performed to remove the excess portion of the conductive material outside the opening 472, thereby exposing the top surface of the third dielectric layer 470 and obtaining a planarized surface. A portion of the conductive material in the opening 472 is referred to as a wire 480.

[0140] exist Figure 15K, the ESL 460 has an opening 462 directly above the through hole 450. The side 464 of the opening 462 is substantially adjacent to the side wall 452 of the through hole 450. A portion of the conductive wire 480 is in the opening 462 and in contact with the through hole 450. The conductive wire 480 is separated from the second dielectric layer 440. The ESL 460 is sandwiched between the second dielectric layer 440 and the conductive wire 480, and the conductive wire 480 is in contact with the side 464 of the ESL 460 and the top surface of the ESL 460. In addition, the interface 475 between the third dielectric layer 470 and the conductive wire 480 is retracted from the side 464 of the ESL 460. The conductive wire 480 and the second dielectric layer 440 are in contact with opposite surfaces of the ESL 460, respectively. The side wall 452 of the through hole 450 is not parallel to the side surface 464 of the ESL 460.

[0141] exist Figure 15G In the embodiment, the dielectric layer 460' is formed by performing a bias-induced selective ALD process. By providing a bias voltage on the suction cup 220, the charge has different distributions in different materials. The charge can attract or repel the precursor to increase or decrease the corresponding deposition rate. In some other embodiments, when there is a high deposition selectivity between the dielectric layer (i.e., the second dielectric layer 440) and the conductive layer (i.e., the via 450), the dielectric layer 460' can be omitted. Fig.15H In addition, self-aligned monolayers (SAMs), which may be formed using an additional deposition process and cause defect problems, may be omitted to simplify the manufacturing process.

[0142] Figure 15G The dielectric layer 460' in may be formed using other biases and / or precursors. FIG. 16A to FIG. 16G 1 is a perspective view of a method for manufacturing a semiconductor structure at various stages according to some embodiments of the present disclosure. Throughout the various views and illustrative embodiments, the same reference numerals are used to designate the same elements. This embodiment may be repeated in FIG. 15A to FIG. 15K Reference numerals and / or letters are used in the following description. This repetition is for simplicity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. In the following embodiments, the structural and material details previously described are not repeated below and only provide further information to perform the present invention. FIG. 16A to FIG. 16G In some embodiments, Figure 3 The manufacturing device 200 and / or the execution Figure 2 Method M1 in the formation Figures 16A to 16F In some embodiments, Figure 5 The timetable is also applied to FIG. 16A to FIG. 16F It should be noted that only the FIG. 16B to FIG. 16D The dimensions of the precursors shown in FIG. 1 are for reference only and do not limit the scope of the embodiments.

[0143] refer to Figure 2 , Figure 3 ,and Fig.16A In operation S12 of method M1, a wafer is placed on a suction cup of a manufacturing device. Fig.16A In this case, a positive DC bias is applied to the chuck 220. With the DC bias, since the conductivity of the through hole 450 (e.g., conductive material) is higher than the conductivity of the second dielectric layer 440 (e.g., dielectric material), charges (in this case, holes) accumulate in the through hole 450, such that, as shown in FIG. Fig.16A As shown, more charges are retained near the surface of the through hole 450. In some embodiments, the bias voltage may have a power greater than about 0 W and equal to or less than about 50 W, for example, about 20 W. If the power is greater than about 50 W, the gas (e.g., precursor / processing gas) in the chamber 210 may be ionized to form plasma, which may bombard the wafer to damage the structure formed thereon.

[0144] In some embodiments, Figure 5 As shown, the bias applied to the chuck 220 continues the first time period T1. The bias is applied before the precursor is fed into the chamber 210. Once the positive DC bias is applied to the chuck 220, the holes move to the surface of the through hole 450. Therefore, in this case, the surface of the through hole 450 is positively charged.

[0145] In operation S16 of method M1, a first precursor is fed into a chamber of a manufacturing apparatus. Figure 3 and Fig. 16B For example, a first precursor P1' (in this case, for example, a high-k precursor) is fed from a precursor conveyor 240 into the chamber 210. In some embodiments, by controlling the temperature of the chamber 210 and / or feeding a reactive gas into the chamber 210, a chemical reaction occurs to remove a substituent from the first precursor P1', so that the first precursor P1' is partially positive. The first precursor P1' having a partial positive charge is mostly repelled by the holes 450, and thus is mostly deposited on the second dielectric layer 440 rather than on the through-holes 450. As shown in FIG. Fig. 16C As shown, the first precursor P1′ is mostly absorbed on the surface 442 of the second dielectric layer 440. In some embodiments, some of the first precursor P1′ is still absorbed on the surface of the through hole 450.

[0146] In the second period T2, the first precursor P1' is fed into the chamber 210 (see Figure 5 ). In some embodiments, Figure 5 The third period T3 in the embodiment is long enough to charge the via 450, and Figure 5The fourth time period T4 is long enough to provide a reaction time for the first precursor deposition. In addition, during operation S14 and operation S16, the plasma source 230 is turned off so that when the bias is applied to the chuck 220, there is no plasma or negligible plasma in the chamber 210. In some other embodiments, the first precursor P1 is a plasma, and the first precursor P1' is fed from the plasma source 230 into the chamber 210.

[0147] In operation S18 of method M1, the bias voltage is turned off, and then in operation S20 of method M1, the excess first precursor is purged out of the chamber. In operation S22 of method M1, the second precursor is fed into the chamber of the manufacturing apparatus. Figure 3 and Fig.16D For example, a second precursor P2' (eg, an oxidant such as H2O vapor, O3, or O2 plasma in this case) is fed into the chamber 210 from a precursor conveyor 240 or a plasma source 230 (for O2 plasma oxidant). Fig.16D As shown, the second precursor P2' is attracted by the first precursor P1' absorbed on the second dielectric layer 440. The second precursor P2' may be attracted by the first precursor, so more of the second precursor P2' is deposited on the surface 442 of the second dielectric layer 440, and less of the second precursor P2' is deposited on the surface of the through hole 450. Fig.16E As shown, a dielectric film 460 is formed on the surface of the second dielectric layer 440 and the through hole 450.

[0148] exist Figure 5 In some embodiments, the second precursor P2' is charged and replaced for a fifth period T5. Figure 5 The sixth period T6 is used to neutralize the surface of the through hole 450. In some embodiments, Figure 5 The seventh time period T7 provides a reaction time for the second precursor deposition.

[0149] In operation S24 of method M1, excess second precursor is purged from the chamber. After operation S24, as Fig.16E As shown, the dielectric film 460" is mostly formed on the surface 442 of the second dielectric layer 440, and the dielectric film 460" may expose a portion of the surface of the through hole 450. That is, the selective ALD process results in no or negligible deposition of the dielectric film 460" on the through hole 450. Then, the method M1 proceeds to operation S14 to repeat operations S14 to S24, and another dielectric film is formed on the dielectric film 460". Fig.16F As shown, the cycle of operations S14 to S24 may be repeated multiple times to form a dielectric layer 460' on the second dielectric layer 440. In operation S26 of method M1, the wafer is taken out of the chamber to perform a next manufacturing process.

[0150] Then, execute FIG. 15H to FIG. 15K The process in order to form Figure 16G The semiconductor structure shown. Figure 16G The structure and formation of the semiconductor structure in Fig.15H and Figure 15K The formation of the semiconductor structure is the same or similar, and the detailed description will not be repeated in this regard.

[0151] Based on the above discussion, it can be seen that the present disclosure provides advantages. However, it should be understood that other embodiments may provide additional advantages, and not all advantages are necessarily disclosed herein, and no particular advantage is required for all embodiments. One advantage is that the selective ALD process can be performed by applying a DC and / or RF bias. Another advantage is that the bias-induced selective ALD process is an indirect induction process and can eliminate the need for a SAM or other additional layer for selective deposition that may damage the structure formed on the wafer or include additional processes. In addition, the bias-induced selective ALD process does not complicate the manufacturing process for forming semiconductor devices and / or semiconductor structures.

[0152] According to some embodiments, the method includes forming a dummy gate structure above a wafer. Gate spacers are formed on both sides of the dummy gate structure. The dummy gate structure is removed to form a gate trench between the gate spacers. A gate dielectric layer is formed in the gate trench. A gate electrode is formed above the gate dielectric layer. Forming the gate dielectric layer includes applying a first bias to the wafer. With the first bias turned on, a first precursor is fed to the wafer. The first bias is turned off. After turning off the first bias, a second precursor is fed to the wafer.

[0153] According to some embodiments, a method includes forming a mask layer over a substrate. The substrate is patterned by using the mask layer as a mask to form a trench in the substrate. An isolation structure is formed in the trench, including feeding a first precursor to the substrate. After feeding the first precursor, a bias voltage is applied to the substrate. With the bias voltage turned on, a second precursor is fed to the substrate. Feeding the first precursor, applying the bias voltage, and feeding the second precursor are repeated.

[0154] According to some embodiments, a device includes a conductive component, a first dielectric layer, a through hole, an etch stop layer (ESL), a second dielectric layer, and a wire. The first dielectric layer is above the conductive component. The through hole is in the first dielectric layer and above the conductive component. The ESL is above the first dielectric layer. The side of the ESL is adjacent to the side wall of the through hole. The second dielectric layer is above the ESL. The wire in the second dielectric layer and above the through hole. The wire contacts the side of the ESL and the top surface of the ESL.

[0155] According to one embodiment of the present application, a method for manufacturing a semiconductor device is provided, comprising: forming a dummy gate structure above a wafer; forming a gate spacer on either side of the dummy gate structure; removing the dummy gate structure to form a gate trench between the gate spacers; depositing a gate dielectric layer in the gate trench, comprising: applying a first bias to the wafer; feeding a first precursor to the wafer when the first bias is turned on; turning off the first bias; and after turning off the first bias, feeding a second precursor to the wafer; and forming a gate electrode above the gate dielectric layer. In some embodiments, the first bias is a DC bias. In some embodiments, the first bias is an RF bias. In some embodiments, the power of the first bias is greater than about 0W and equal to or less than about 50W. In some embodiments, the first bias lasts for a first period of time, and the first precursor is fed to the wafer for a second period of time less than the first period of time. In some embodiments, the first precursor is H2O. In some embodiments, the first precursor is in a plasma phase, and feeding the first precursor to the wafer comprises: generating plasma in a plasma source spaced apart from a chamber in which the wafer is located; and introducing the plasma into the chamber. In some embodiments, depositing the gate dielectric layer is performed so that the thickness of the lateral portion of the gate dielectric layer is greater than the thickness of the vertical portion of the gate dielectric layer. In some embodiments, the method of manufacturing a semiconductor device further includes: etching back the gate electrode and the gate dielectric layer to form a groove above the gate electrode; and forming a capping layer in the groove. In some embodiments, forming the capping layer is performed using a selective deposition process including the following steps: applying a second bias to the wafer; feeding a third precursor to the wafer with the second bias turned on; turning off the second bias; and feeding a fourth precursor in the groove after turning off the bias.

[0156] According to another embodiment of the present application, a method for manufacturing a semiconductor device is provided, comprising: forming a mask layer over a substrate; patterning the substrate by using the mask layer as a mask to form a groove in the substrate; and forming an isolation structure in the groove, comprising: feeding a first precursor to the substrate; applying a bias to the substrate after feeding the first precursor; feeding a second precursor to the substrate with the bias turned on; and repeatedly feeding the first precursor, applying the bias, and feeding the second precursor. In some embodiments, the bias is a positive bias. In some embodiments, the bias is a negative bias. In some embodiments, the first precursor is a silicon precursor. In some embodiments, the second precursor is H2O. In some embodiments, the power of the bias is greater than about 0W and equal to or less than about 50W.

[0157] According to another embodiment of the present application, a semiconductor device is provided, comprising: a conductive component; a first dielectric layer on the conductive component; a through hole in the first dielectric layer and on the conductive component; an etch stop layer (ESL) on the first dielectric layer, wherein the side of the ESL is in contact with the side wall of the through hole; a second dielectric layer on the ESL; and a wire in the second dielectric layer and above the through hole, the wire being in contact with the side of the ESL and the top surface of the ESL. In some embodiments, the interface between the second dielectric layer and the wire is retracted from the side of the ESL. In some embodiments, the wire is separated from the first dielectric layer by the ESL. In some embodiments, the side wall of the through hole is not parallel to the side of the ESL.

[0158] The parts of several embodiments are discussed above so that those skilled in the art can better understand various aspects of the present invention. It should be understood by those skilled in the art that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. It should also be appreciated by those skilled in the art that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a dummy gate structure over the wafer; forming gate spacers on either side of the dummy gate structure; removing the dummy gate structure to form a gate trench between the gate spacers; Depositing a gate dielectric layer in the gate trench, comprising: applying a first bias voltage to the wafer; feeding a first precursor to the wafer when the first bias voltage is turned on; Turning off the first bias voltage; and After turning off the first bias, feeding a second precursor to the wafer; and forming a gate electrode over the gate dielectric layer.

2. The method according to claim 1, wherein: The first bias voltage is a DC bias voltage.

3. The method according to claim 1, wherein: The first bias voltage is an RF bias voltage. The method according to claim 1 , wherein a power of the first bias voltage is greater than about 0 W and equal to or less than about 50 W.

5. The method according to claim 1, wherein: The first bias voltage is maintained for a first period of time, and the first precursor is fed to the wafer for a second period of time that is less than the first period of time.

6. The method according to claim 1, wherein: The first precursor is H2O.

7. The method according to claim 1, wherein: The first precursor is in a plasma phase, and feeding the first precursor to the wafer comprises: generating a plasma in a plasma source spaced apart from a chamber in which the wafer is located; and The plasma is introduced into the chamber.

8. The method according to claim 1, wherein: Depositing the gate dielectric layer is performed such that a thickness of a lateral portion of the gate dielectric layer is greater than a thickness of a vertical portion of the gate dielectric layer.

9. The method according to claim 1, further comprising: Etching back the gate electrode and the gate dielectric layer to form a recess above the gate electrode; as well as A cover layer is formed in the groove.

10. The method according to claim 9, wherein: Forming the capping layer is performed using a selective deposition process comprising the following steps: applying a second bias voltage to the wafer; feeding a third precursor to the wafer when the second bias voltage is turned on; Turning off the second bias voltage; as well as After turning off the bias, a fourth precursor is fed into the groove.

11. A method for manufacturing a semiconductor device, comprising: forming a mask layer over the substrate; patterning the substrate by using the mask layer as a mask to form trenches in the substrate; as well as forming an isolation structure in the trench, comprising: feeding a first precursor to the substrate; applying a bias voltage to the substrate after feeding the first precursor; feeding a second precursor to the substrate with the bias voltage turned on; and Feeding the first precursor, applying the bias voltage, and feeding the second precursor are repeated.

12. The method according to claim 11, wherein: The bias voltage is a positive bias voltage.

13. The method according to claim 11, wherein: The bias voltage is a negative bias voltage.

14. The method according to claim 11, wherein: The first precursor is a silicon precursor.

15. The method according to claim 11, wherein: The second precursor is H2O. The method of claim 11 , wherein a power of the bias voltage is greater than about 0 W and equal to or less than about 50 W.

17. A semiconductor device comprising: a conductive member disposed in the first dielectric layer; a second dielectric layer over the conductive member; a via in the second dielectric layer and over the conductive feature; an etch stop layer on the second dielectric layer, wherein a side of the etch stop layer is adjacent to a side wall of the through hole, and a side of the etch stop layer is aligned with the side wall of the through hole; a third dielectric layer over the etch stop layer; and A conductive line is provided in the third dielectric layer and above the through hole, the conductive line being in contact with the side surface of the etch stop layer and a top surface of the etch stop layer.

18. The device according to claim 17, wherein An interface between the third dielectric layer and the conductive line is retracted from the side surface of the etch stop layer.

19. The device according to claim 17, wherein: The conductive line is separated from the second dielectric layer by the etch stop layer.

20. The device according to claim 17, wherein The sidewall of the through hole is not parallel to the side surface of the etch stop layer.

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