Semiconductor structure and method of forming integrated circuit structure

Abstract

The present invention provides a semiconductor structure, the semiconductor structure comprising: a substrate having a front side and a back side; an active area protruding from the substrate and surrounded by an isolation part; a gate stack formed on the front side of the substrate and disposed on the active area; a first source / drain (S / D) part and a second source / drain (S / D) part formed on the active area and inserted by the gate stack; a front side contact part disposed on the top surface of the first S / D part; a back side contact part disposed on the bottom surface of the second S / D part and electrically connected to the bottom surface of the second S / D part; and a semiconductor layer disposed on the bottom surface of the first S / D part having a first thickness and the bottom surface of the gate stack having a second thickness, the second thickness being greater than the first thickness. Embodiments of the present application also relate to a method of forming an integrated circuit structure.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming integrated circuit structures. Background Art

[0002] Integrated circuits have evolved to advanced technologies with smaller component sizes (e.g., 7nm, 5nm, and 3nm). In these advanced technologies, the gate spacing (spacing) continues to shrink, and thus the gate bridging problem is caused. In addition, to enhance device performance, three-dimensional transistors, such as three-dimensional transistors formed on fin-type active areas, are generally required. Those three-dimensional field effect transistors (FETs) formed on fin-type active areas are also called FinFETs. Other three-dimensional field effect transistors include full-ring gate FETs. These FETs require narrow fin widths for short channel control, which results in a smaller source / drain area than planar FETs. This will reduce the alignment margin and cause problems of further reducing device spacing and increasing assembly density. As device size decreases, power lines are formed on the back side of the substrate. However, existing backside power rails still face various challenges, including short circuits, leakage, wiring resistance, alignment margins, layout flexibility, and assembly density. Therefore, structures and methods for fin transistors and power rails are needed to solve these problems to improve circuit performance and reliability. Summary of the invention

[0003] Some embodiments of the present application provide a method for forming an integrated circuit structure, comprising: receiving a substrate having a front surface and a back surface, wherein the substrate comprises a first semiconductor layer of a first semiconductor material and a dielectric layer embedded under the first semiconductor layer; forming a stack of first semiconductor films and second semiconductor films interlaced with each other, wherein the first semiconductor film and the second semiconductor film have different semiconductor materials; forming an isolation component in the substrate and extending to the dielectric layer, thereby defining an active area surrounded by the isolation component; forming a gate stack spanning between a first source / drain (S / D) region and a second source / drain (S / D) region on the active area; and A deep trench extending below the top surface of the isolation component is formed in the first source / drain region; a second semiconductor layer of a second semiconductor material is filled in the deep trench, the second semiconductor material being different from the first semiconductor material; a first source / drain component and a second source / drain component are formed in the first source / drain region and the second source / drain region; the first semiconductor material under the second source / drain component is selectively removed from the back side of the substrate to form a trench; the trench is filled with a dielectric material; and the second semiconductor layer is selectively removed from the back side of the substrate to form a back contact hole self-aligned with the first source / drain component.

[0004] Some other embodiments of the present application provide a method for forming an integrated circuit structure, comprising: receiving a substrate having a front surface and a back surface, wherein the substrate comprises a dielectric layer embedded therein, a first semiconductor layer of a first semiconductor material covering the dielectric layer, and a stack of a first semiconductor film and a second semiconductor film above the first substrate, wherein the first semiconductor film and the second semiconductor film have different semiconductor materials and are alternately stacked; forming an isolation component in the substrate and extending to the dielectric layer to define an active area surrounded by the isolation component; forming a first source / drain (S / D) component and a second source / drain (S / D) component on the active area; and D) a gate stack between components; forming a deep trench in the first source / drain region from the front side of the substrate and extending through the first semiconductor layer; filling the deep trench with a second semiconductor layer of a second semiconductor material, the second semiconductor material being different from the first semiconductor material; selectively removing the first semiconductor material under the second source / drain component from the back side of the substrate to form a trench; filling the trench with a dielectric material; selectively removing the second semiconductor layer from the back side of the substrate to form a back contact hole self-aligned with the first source / drain component; and forming a back contact component in the back contact hole.

[0005] Still other embodiments of the present application provide a semiconductor structure, comprising: a substrate having a front side and a back side; an active region protruding from the substrate and surrounded by an isolation structure; a gate stack formed on the front side of the substrate and disposed on the active region; a first source / drain (S / D) component and a second source / drain (S / D) component formed on the active region and inserted by the gate stack; a front side contact component disposed on a top surface of the first source / drain component; a back side contact component disposed on a bottom surface of the second source / drain component and electrically connected to a bottom surface of the second source / drain component; and a semiconductor layer disposed on a bottom surface of the first source / drain component having a first thickness and on a bottom surface of the gate stack having a second thickness, the second thickness being greater than the first thickness. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read together with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A , Figure 1B and Figure 1CA flow chart of a method of forming a semiconductor device having backside power rails and backside self-aligned vias according to various aspects of the present invention is shown.

[0008] Figure 2 and Figure 3 According to some embodiments, Figure 1A-Figure 1C A cross-sectional view of a portion of a semiconductor device during an intermediate fabrication step of an embodiment of a method.

[0009] Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A and Fig.19A A top view of a portion of a semiconductor device in accordance with some embodiments is illustrated.

[0010] Figure 4B , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 5F , Figure 5G , Figure 6B , Figure 7B , Figure 7C , Fig.7D , Fig. 7E , Figure 8B , Figure 8C , Fig.8D , Fig. 8E , Fig. 9B , Fig. 9C , Fig.9D , Fig.9E , Fig. 10B , Fig. 10C , Fig. 10D , Fig.10E , Fig. 11B , Fig. 11C , Fig.11D , Fig.11E , Fig. 12B , Fig. 12C , Fig.12D , Fig.12E , Fig. 13B , Fig. 13C , Fig.13D , Fig.13E , Fig. 14B , Fig. 14C , Fig.14D , Fig.14E , Fig. 15B , Fig. 15C , Fig.15D , Fig.15E , Fig. 16B , Fig. 16C , Fig.16D , Fig.16E , Fig. 17B , Fig. 17C , Fig.17D , Fig.17E , Fig.18B , Fig. 18C , Fig.18D , Fig.18E and Fig.19B A cross-sectional view of a portion of a semiconductor device according to some embodiments is shown.

[0011] Fig. 20A , Fig. 20B and Fig. 20C A perspective view of a portion of a semiconductor device according to some embodiments is shown.

[0012] Fig.21A , Fig.22A , Fig.23A and Fig.24A A top view of a portion of a semiconductor device in accordance with some embodiments is shown.

[0013] Fig.21B , Fig. 21C , Fig.21D , Fig.21E , Fig. 22B , Fig. 22C , Fig.22D , Fig.22E , Fig. 23B , Fig.23C , Fig.23D , Fig.23E and Fig. 24B A cross-sectional view of a portion of a semiconductor device according to some embodiments is shown.

[0014] Fig.25A , Fig.25B and Fig.25C A perspective view of a portion of a semiconductor device according to some embodiments is shown.

[0015] Fig.26 and Fig. 27 According to some embodiments, Figure 1A-Figure 1C A cross-sectional view of a portion of a semiconductor device during an intermediate fabrication step of an embodiment of a method.

[0016] Fig.28A , Fig.29A , Fig. 30A , Fig.31A , Fig.32A, Fig.33A , Fig.34A , Fig.35A , Fig.36A , Fig.37A , Fig.38A , Fig.39A , Fig.40A , Fig.41A , Fig.42A and Fig.43A A top view of a portion of a semiconductor device in accordance with some embodiments is illustrated.

[0017] Fig.28B , Fig.29B , Fig.29C , Fig.29D , Fig.29E , Fig.29F , Figure 29G , Fig. 30B , Fig.31B , Fig. 31C , Fig.31D , Fig.31E , Fig.32B , Fig.32C , Fig.32D , Fig.32E , Fig.33B , Fig.33C , Fig.33D , Fig.33E , Fig.34B , Fig.34C , Fig.34D , Fig.34E , Fig.35B , Fig.35C , Fig.35D , Fig.35E , Fig.36B , Fig.36C , Fig.36D , Fig.36E , Fig.37B , Fig.37C , Fig.37D , Fig.37E , Fig.38B , Fig.38C , Fig.38D , Fig.38E , Fig.39B , Fig.39C , Fig.39D , Fig.39E , Fig.40B , Fig.40C , Fig.40D , Fig.40E , Fig.41B , Fig.41C , Fig.41D , Fig.41E , Fig.42B , Fig.42C , Fig.42D , Fig.42E and Fig.43BA cross-sectional view of a portion of a semiconductor device according to some embodiments is shown.

[0018] Fig.44A , Fig.44B and Fig.44C A perspective view of a portion of a semiconductor device according to some embodiments is shown. DETAILED DESCRIPTION

[0019] The following disclosure provides a variety of different embodiments or examples for implementing different components of the present invention. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact.

[0020] In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not indicate the relationship between the various embodiments and / or configurations discussed in itself. In addition, in the subsequent description, forming a component on another component, connecting a component to and / or coupling it to another component may include an embodiment in which the components are directly contacted, and may also include an additional component that can form an inserted component, so that the components may not be directly contacted. In addition, for the convenience of the present invention of a component relationship with another component, spatial relative terms such as "lower", "upper", "horizontal", "vertical", "above...", "above...", "below...", "below...", "upward", "downward", "top", "bottom", etc. and their derivatives (e.g., "horizontally", "downward", "upward", etc.) are used. Spatial relative terms are intended to cover different directions of devices including components. Further, as understood by those skilled in the art, when "about", "approximately", etc. are used to describe a number or a range of numbers, the term is intended to cover numbers within a reasonable range (such as, within + / -10% of the described number or other value) including the described number. For example, the term "about 5 nm" encompasses a size range from 4.5 nm to 5.5 nm.

[0021] The present invention provides a semiconductor structure with a backside power rail and a method for manufacturing the same. The semiconductor structure also includes a backside via (also referred to as a backside via contact) component, which is arranged on the back side of the substrate and inserted between the semiconductor active area (such as a fin active area) and the backside power rail, and electrically connects the backside power rail to a device component (such as a source component of a field effect transistor (FET)) on the semiconductor active area. In particular, the backside via component is self-aligned with the device component to be electrically connected (such as the source component), thereby providing a connection without overlay shift and eliminating short circuit problems, such as a short circuit between a corresponding metal gate electrode and the backside power rail, which is connected to the source / drain component through the via component.

[0022] The semiconductor structure also includes an interconnect structure formed on the front side of the substrate. The interconnect structure also includes a front contact component electrically connected to the FET, such as a drain component bonded and connected to the transistor, so that the power rail is distributed to the front and back sides of the substrate, the number of power lines is reduced from the front side of the substrate, and more space is provided for metal wiring and processing margin on the front side of the substrate. The semiconductor structure thus formed includes a back side power rail on the back side and an interconnect structure on the front side to centrally route the power lines, for example, the drain component is connected to the corresponding power line through the interconnect structure, and the source component is connected to the corresponding power line through the back side power rail. In some embodiments, both the front side and the back side contact components include silicide to reduce contact resistance. The disclosed structure and its manufacturing method can be applied to a semiconductor structure having a FET with a three-dimensional structure (such as a fin FET (FinFET) formed on a fin active area) and a FET with multiple channels stacked vertically (such as a full surround gate (GAA) structure).

[0023] Figure 1A , Figure 1B and Figure 1C 1 is a flow chart of a method 100 for manufacturing a semiconductor device according to various aspects of the present invention. The present invention contemplates additional processing. Additional operations may be provided before, during, and after the method 100, and some of the operations described may be moved, replaced, or removed for additional embodiments of the method 100.

[0024] Combine the following Figures 2 to 44C Describing method 100, Figures 2 to 44CVarious top views, cross-sectional views, or perspective views of a semiconductor device (or semiconductor structure) 200 (or 400 or 500) at different stages of manufacture according to various embodiments are shown. In some embodiments, the semiconductor device is a portion of an IC chip, a system on a chip (SoC), or a portion thereof, which includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), FinFETs, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, memory devices, other suitable components, etc., or combinations thereof. For clarity, Figures 2 to 44C The simplification is done to better understand the inventive concept of the present invention. Other components may be added in the semiconductor device 200 (or 400 or 500), and some of the components described below may be replaced, modified, or removed in other embodiments of the semiconductor device 200 (or 400 or 500).

[0025] Figure 2 A substrate 201 is shown according to some embodiments. In the depicted embodiment, the substrate 201 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. In the depicted embodiment, the substrate 201 includes a semiconductor layer 204, an insulator 203, and a carrier 202. In an embodiment, the semiconductor layer 204 may be silicon, silicon-germanium, germanium, or other suitable semiconductors; the carrier 202 may be a portion of a silicon wafer; and the insulator 203 may be silicon oxide. The semiconductor-on-insulator substrate may be fabricated using isolation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods. In an alternative embodiment, the substrate 201 is a bulk silicon substrate (i.e., includes bulk single crystal silicon). In various embodiments, the substrate 201 may include other semiconductor materials, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof.

[0026] In some embodiments, semiconductor layer 204 may include various doped regions depending on the design requirements of device 200. For example, an N-type doped region may be formed by doping an n-type dopant such as phosphorus, arsenic, other n-type dopants, or a combination thereof; and a P-type doped region may be formed by doping a p-type dopant such as boron, indium, other p-type dopants, or a combination thereof. In some embodiments, semiconductor substrate 204 includes a doped region formed by a combination of a p-type dopant and an n-type dopant. In some embodiments, semiconductor layer 204 is not doped or is unintentionally doped with a very small amount of dopant.

[0027] In operation 101, method 100 ( Figure 1A ) forming a semiconductor layer 207 above the substrate 201, such as Figure 3 As shown. Semiconductor layer 207 is different from semiconductor layer 204. In some embodiments, semiconductor layer 204 is a silicon layer, and semiconductor layer 207 is a silicon germanium (SiGe) layer. Additional semiconductor material 208 may be further grown above semiconductor layer 207, and may be a silicon layer, such as an undoped silicon layer. In the depicted embodiment, semiconductor layer 207 of SiGe is embedded in a silicon substrate including silicon layers 204 and 208. Semiconductor layer 207 is formed by a suitable method such as epitaxial growth. According to some embodiments, semiconductor layer 207 has a thickness ranging between 20nm and 100nm, which is greater than a silicon germanium film (to be described below) in a semiconductor stack, and is therefore referred to as a thick semiconductor layer.

[0028] At operation 102, method 100 ( Figure 1A ) A stack 205 of a first semiconductor layer and a second semiconductor layer is formed over the substrate 201. According to an embodiment, the resulting structure is Figure 3. The semiconductor layer stack 205 includes a semiconductor layer 210 and a semiconductor layer 215, which are stacked vertically (e.g., along the z direction) in a staggered manner (alternating structure) with respect to the surface of the substrate 201. In some embodiments, the semiconductor layer 210 and the semiconductor layer 215 are epitaxially grown in the staggered manner and alternating structure as shown. For example, the first layer of the semiconductor layer 210 is epitaxially grown above the substrate 201, the first layer of the semiconductor layer 215 is epitaxially grown on the first layer of the semiconductor layer 210, the second layer of the semiconductor layer 210 is epitaxially grown on the first layer of the semiconductor layer 215, and so on, until the desired number of semiconductor layers 210 and semiconductor layers 215 in the semiconductor layer stack 205 is reached. In such embodiments, the semiconductor layer 210 and the semiconductor layer 215 may be referred to as epitaxial layers. In some embodiments, epitaxial growth of semiconductor layer 210 and semiconductor layer 215 is achieved by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process, a metal organic chemical vapor deposition (MOCVD) process, other appropriate epitaxial growth processes, or a combination thereof.

[0029] The composition of semiconductor layer 210 is different from the composition of semiconductor layer 215, thereby obtaining etching selectivity and / or different oxidation rates during subsequent processing. In some embodiments, the etching rate of the etchant on semiconductor layer 210 is a first etching rate, and the etching rate of the etchant on semiconductor layer 215 is a second etching rate, wherein the second etching rate is less than the first etching rate. In some embodiments, the oxidation rate of semiconductor layer 210 is a first oxidation rate, and the oxidation rate of semiconductor layer 215 is a second oxidation rate, wherein the second oxidation rate is less than the first oxidation rate. In the described embodiments, semiconductor layer 210 and semiconductor layer 215 include different materials, composition atomic percentages, composition weight percentages, thicknesses and / or properties, thereby obtaining a desired etching selectivity during an etching process (e.g., an etching process implemented to form a suspended channel layer in a channel region of device 200). For example, when semiconductor layer 210 includes silicon germanium and semiconductor layer 215 includes silicon, for a given etchant, the silicon etching rate of semiconductor layer 215 is lower than the silicon germanium etching rate of semiconductor layer 210. In some embodiments, semiconductor layer 210 and semiconductor layer 215 may include the same material, but have different composition atomic percentages to obtain etching selectivity and / or different oxidation rates. For example, semiconductor layer 210 and semiconductor layer 215 may include silicon germanium, wherein semiconductor layer 210 has a first silicon atomic percentage and / or a first germanium atomic percentage, and semiconductor layer 215 has a different second silicon atomic percentage and / or a different second germanium atomic percentage. The present invention contemplates that semiconductor layer 210 and semiconductor layer 215 include any combination of semiconductor materials that can provide a desired etching selectivity, a desired oxidation rate difference, and / or a desired performance characteristic (e.g., a material that maximizes current flow), including any semiconductor material disclosed herein.

[0030] As further described below, the semiconductor layer 215 or a portion thereof forms a channel region of the device 200. In the depicted embodiment, the semiconductor layer stack 205 includes three semiconductor layers 210 and three semiconductor layers 215, and the three semiconductor layers 210 and the three semiconductor layers 215 are configured to form three semiconductor layer pairs disposed above the substrate 201, each semiconductor layer pair having a corresponding first semiconductor layer 210 and a corresponding second semiconductor layer 215. After subsequent processing, such a structure will result in the device 200 having three channels. However, the present invention contemplates some embodiments in which the semiconductor layer stack 205 includes more or fewer semiconductor layers, for example, depending on the number of channels required for the device 200 (e.g., a GAA transistor) and / or the design requirements of the device 200. For example, the semiconductor layer stack 205 may include two to ten semiconductor layers 210 and two to ten semiconductor layers 215. In an alternative embodiment in which the device 200 is a FinFET device, the stack 205 is only a layer of semiconductor material, such as a layer of Si. As will be discussed, method 100 will process layers on both sides of substrate 201. In the present invention, the side of substrate 201 where stack 205 is located is referred to as the front side, and the side opposite the front side is referred to as the back side.

[0031] In the depicted embodiment, semiconductor layer 207 and semiconductor layer 210 include silicon germanium, but have different thicknesses and may further include different compositions. For example, the thickness of semiconductor layer 207 is greater than the thickness of each semiconductor layer 210. In another example, the germanium concentration of semiconductor layer 207 is different from the germanium concentration of semiconductor layer 210, such as a greater concentration. In yet another example, the germanium concentration of semiconductor layer 207 is different from the germanium concentration of semiconductor layer 210 and the thickness is different from the thickness of semiconductor layer 210.

[0032] At operation 104, method 100 ( Figure 1A ) Fins 218 are formed by patterning the stack 205 and the substrate 201. Figure 4A A top view of the device 200 is shown with the fins 218 oriented along the “x” direction. Figure 4B Shown partially along Figure 4A FIG. 2 is a cross-sectional view of the device 200 along line AA in FIG. Figure 4BAs shown, the fin 218 includes a patterned stack 205 (having layers 210 and 215), a patterned semiconductor layer (204 and 207), and one or more patterned hard mask layers 206. The fin 218 can be patterned by any suitable method. For example, the fin 218 can be patterned using one or more photolithography processes (including a double patterning process or a multi-patterning process). Typically, the double patterning process or the multi-patterning process combines a photolithography process with a self-alignment process, thereby being able to obtain, for example, a pattern with a smaller pitch than that otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the stack 205 and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used as mask elements for patterning the fin 218. For example, the mask element can be used to etch grooves in the stack 205 and the substrate 201, thereby leaving the fin 218 on the substrate 201. The etching process may include a dry etching process, a wet etching process, a reactive ion etching (RIE) process, and / or other suitable processes. For example, the dry etching process may employ an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. For example, the wet etching process may include etching in dilute hydrofluoric acid (DHF); a potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH); or other suitable wet etchants. Many other embodiments of the method of forming the fin 218 may be suitable.

[0033] At operation 106, method 100 ( Figure 1A ) to form various isolation structures on the substrate 201 and isolate the fins 218. This operation is performed in an embodiment of Figure 5A-5G Shown in. Figure 5A 2 shows a top view of the device 200, Figure 5B-5G The diagram shows a portion of the process along the respective steps of operation 106. Figure 5A A cross-sectional view of device 200 taken along line AA in FIG.

[0034] refer to Figure 5B, an isolation component 230 is formed above and / or in the substrate 201 to isolate the various active areas of the device 200. For example, the isolation component 230 surrounds the bottom of the fin 218 to separate and isolate the fins 218 from each other. The isolation component 230 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (for example, including silicon, oxygen, nitrogen, carbon or other suitable isolation components) or a combination thereof. The isolation component 230 may include different structures, such as a shallow trench isolation (STI) structure and / or a deep trench isolation (DTI) structure. In an embodiment, the isolation component 230 can be formed by filling the trenches between the fins 218 with a dielectric material layer (for example, by using a CVD process or a spin-on glass process), performing a chemical mechanical polishing (CMP) process to remove excess dielectric material and / or planarize the top surface of the dielectric material layer, and etching back the dielectric material layer to form the isolation component 230. In some embodiments, the isolation component 230 includes a multilayer structure, such as a silicon nitride layer disposed above a thermal oxide liner layer.

[0035] In the depicted embodiment, the isolation features 230 are formed such that a top surface of the isolation features 230 is above a top surface of the semiconductor layer 207. In the depicted embodiment, the isolation features 230 are formed such that a bottom surface of the isolation features 230 extends to the insulator 203.

[0036] refer to Figure 5C , a cladding (semiconductor) layer 231 is deposited over the top and sidewall surfaces of the fin 218 and over the isolation feature 230. In some embodiments, the cladding layer 231 includes SiGe. The cladding layer 231 may be deposited using CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), other suitable methods or combinations thereof. After depositing the cladding layer 231, operation 106 performs an etching process to remove a portion of the cladding layer 231 from over the isolation feature 230, for example, using a plasma dry etching process.

[0037] refer to Figure 5D , a dielectric liner 232 is deposited over the cladding layer 231 and on the top surface of the isolation feature 230, and then a dielectric fill layer 233 is deposited over the dielectric liner 232 and fills the gaps between the fins 218. In an embodiment, the dielectric liner 232 includes a low-k dielectric material, such as a dielectric material including Si, O, N, and C. Exemplary low-k dielectric materials include FSG, carbon-doped silicon oxide, (Applied Materials, Santa Clara, California), Xerogel, Aerogel, amorphous fluorinated carbon, parylene, BCB, SiLK (Dow Chemical, Midland, Michigan), polyimide, other low-k dielectric materials, or combinations thereof. Low-k dielectric materials generally refer to dielectric materials with low dielectric constants, such as lower than the dielectric constant of silicon oxide (k≈3.9). The dielectric liner 232 may be deposited using CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods, or combinations thereof. In an embodiment, the dielectric fill layer 233 includes silicon oxide, silicon nitride, silicon oxynitride, oxide formed by TEOS, PSG, BPSG, low-k dielectric materials, other suitable dielectric materials, or combinations thereof. The dielectric fill layer 233 may be deposited using a flowable CVD (FCVD) process that includes, for example, depositing a flowable material (such as a liquid compound) over the device 200 and converting the flowable material into a solid material by a suitable technique such as thermal annealing and / or ultraviolet radiation treatment. Other types of methods may be used to deposit the dielectric fill layer 233. After depositing layers 232 and 233, operation 106 may perform a CMP process to planarize the top surface of the device 200 and expose the cladding layer 231.

[0038] refer to Figure 5E , a dielectric helmet 234 is deposited over dielectric layers 232 and 233 and between cladding layer 231 on opposite sidewalls of fin 218. In one embodiment, dielectric helmet 234 comprises a high-k dielectric material such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x, ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba, Sr)TiO3 (BST), Si3N4, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, or combinations thereof. High-k dielectric materials generally refer to dielectric materials with high dielectric constants (e.g., higher than the dielectric constant of silicon oxide (k≈3.9)). The dielectric helmet 234 is formed by any process described herein, such as ALD, CVD, PVD, oxidation-based deposition processes, other suitable processes, or combinations thereof. In an embodiment, operation 106 includes recessing the dielectric layers 232 and 233 using a selective etching process that etches the dielectric layers 232 and 233 without (or minimally) etching the hard mask 206 and the cladding layer 231. Subsequently, operation 106 deposits one or more dielectric materials into the recesses and performs a CMP process on the one or more dielectric materials to form a dielectric helmet 234.

[0039] refer to Fig. 5F , operation 106 recesses the fin 218 (particularly removing the hard mask layer 206) and the cladding layer 231 disposed between the dielectric helmet 234. Operation 106 may apply one or more selective etching processes to the hard mask layer 206 and the cladding layer 231, while not (or minimally) etching the dielectric helmet 234. The selective etching process may be dry etching, wet etching, reactive ion etching (RIE), or other suitable etching processes.

[0040] refer to Figure 5G Operation 106 deposits a dielectric layer 235 over the surface of the fin 218 and over the dielectric helmet 234. In the present embodiment, the dielectric layer 235 is a dummy (or sacrificial) gate dielectric layer. The dummy gate dielectric 235 includes a dielectric material such as silicon oxide, a high-k dielectric material, other suitable dielectric materials, or a combination thereof, and can be deposited using any process described herein, such as ALD, CVD, PVD, other suitable processes, or a combination thereof.

[0041] In operation 108, method 100 ( Figure 1A ) to form a gate stack 240 over the dummy gate dielectric 235. According to an embodiment, the resulting structure is Figure 6A-6B Shown in. Fig. 6A 2 shows a top view of the device 200, Figure 6B Shows a portion along Fig. 6A. From the top view, the gate stack 240 is generally oriented longitudinally in the "y" direction perpendicular to the "x" direction. In the present embodiment, the gate stack 240 is a dummy (or sacrificial) gate stack and will be replaced by a functional gate stack 240'. The dummy gate stack 240 is formed by a deposition process, a photolithography process, an etching process, other suitable processes or a combination thereof. For example, a deposition process is performed to form a dummy gate electrode layer 245 above the dummy gate dielectric layer 235. In some embodiments, one or more hard mask layers 246 (such as silicon oxide films and silicon nitride films) are deposited above the dummy gate electrode layer 245. In some embodiments, the dummy gate electrode layer 245 includes polysilicon or other suitable materials, and the one or more hard mask layers 246 include silicon oxide, silicon nitride or other suitable materials. The deposition process may include CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), other appropriate methods or combinations thereof. A photolithography patterning and etching process is then performed to pattern one or more hard mask layers 246, dummy gate electrode layer 245 and dummy gate dielectric layer 235, thereby forming a dummy gate stack 240, such as Figure 6B More specifically, the photolithography process forms a patterned photoresist layer with openings, an etching process is applied to transfer the openings to the hard mask layer 246, and then another etching process is applied to the dummy gate layers 245 and 235 to transfer the openings from the hard mask layer to the dummy gate layer. The photolithography patterning process includes resist coating (e.g., spin coating), soft drying, mask alignment, exposure, post-exposure baking, developing (developing the resist), rinsing, drying (e.g., hard drying), other appropriate photolithography processes, or combinations thereof. The etching process includes a dry etching process, a wet etching process, other etching methods, or combinations thereof.

[0042] Operation 108 further forms a gate spacer 247 (eg, Figure 6B). The gate spacer 247 is formed by any suitable process and includes one or more dielectric materials. The dielectric material may include silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN)). For example, a dielectric layer including silicon and nitrogen, such as a silicon nitride layer, may be deposited over the dummy gate stack 240 and subsequently etched (e.g., anisotropically etched) to form the gate spacer 247. In some embodiments, the gate spacer 247 includes a multilayer structure, such as a first dielectric layer including silicon nitride and a second dielectric layer including silicon oxide. In some embodiments, more than one set of spacers, such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers, are formed adjacent to the dummy gate stack 240. In such an implementation, the spacers of each set may include materials having different etch rates. For example, a first dielectric layer including silicon and oxygen (e.g., silicon oxide) can be deposited and etched to form a first spacer group adjacent to the dummy gate stack 240, and a second dielectric layer including silicon and nitrogen (e.g., silicon nitride) can be deposited and etched to form a second spacer group adjacent to the first spacer group.

[0043] At operation 110, method 100 ( Figure 1A ) A source / drain (S / D) trench 250 is formed by etching the fin 218 adjacent to the gate spacer 247. According to an embodiment, the resulting structure is Figure 7A-7E Shown in. Fig. 7A 2 shows a top view of the device 200, Figure 7B , Figure 7C , Fig.7D and Fig. 7E Parts along the Fig. 7A 2 is a cross-sectional view of the device 200 along the BB line, CC line, DD line, and EE line in FIG. In particular, the DD line is cut into the source region of the transistor and is parallel to the gate stack 240, and the EE line is cut into the drain region of the transistor and is parallel to the gate stack 240. Similarly, the configuration 8A to 18A , FIG. 21A to FIG. 23A as well as FIG. 31A to FIG. 42A The DD line and EE line in.

[0044] In the depicted embodiment, the etching process completely removes the semiconductor layer stack 205 in the source / drain region of the fin 218, thereby exposing the substrate (such as semiconductor layer 208) in the source / drain region. Therefore, the source / drain trench 250 has sidewalls defined by the remaining portion of the semiconductor layer stack 205 and a bottom defined by the substrate (such as semiconductor layer 208), which is disposed in the channel region below the gate stack 240. In some embodiments, the etching process removes the semiconductor layer stack 205, so that the isolation feature 230 is exposed within the trench 250. In some embodiments, the etching process removes some (but not all) of the semiconductor layer stack 205, so that the source / drain trench 250 has a bottom defined by the semiconductor layer 210 or the semiconductor layer 215 in the source / drain region. In some embodiments, the etching process also removes some (but not all) of the substrate portion of the fin 218, so that the source / drain trench 250 extends below the topmost surface of the substrate 201. The etching process may include a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, the etching process is a multi-step etching process. For example, etchants may be used alternately in the etching process to remove the semiconductor layer 210 and the semiconductor layer 215 separately and alternately. In some embodiments, the parameters of the etching process are configured to selectively etch the semiconductor layer stack, wherein the gate stack 240 and / or the isolation component 230 are minimally (to not) etched. In some embodiments, a photolithography process, such as the photolithography process described herein, is performed to form a patterned mask layer covering the gate stack 240 and / or the isolation component 230, and the etching process uses the patterned mask layer as an etching mask.

[0045] Operation 110 further forms an inner spacer 255 inside the S / D trench 250 along the sidewall of the semiconductor layer 210 (see Figure 7B). For example, a first etching process is performed that selectively etches the semiconductor layer 210 exposed by the source / drain trench 250 while minimally (to not) etching the semiconductor layer 215, thereby forming a gap between the semiconductor layer 215 under the gate spacer 247 and between the semiconductor layer 215 and the semiconductor layer 204. A portion (edge) of the semiconductor layer 215 is thus suspended in the channel region under the gate spacer 247. In some embodiments, the gap extends partially under the dummy gate stack 240. The first etching process is configured to laterally etch (e.g., along the "x" direction) the semiconductor layer 210, thereby reducing the length of the semiconductor layer 210 along the "x" direction. The first etching process is a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. Subsequently, a deposition process forms a spacer layer over the gate structure 240 and over the components defining the source / drain trench 250 (e.g., the semiconductor layer 215, the semiconductor layer 210, and the semiconductor layer 204), such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods, or combinations thereof. The spacer layer partially (and in some embodiments completely) fills the source / drain trench 250. The deposition process is configured to ensure that the spacer layer fills the gap between the semiconductor layer 215 below the gate spacer 247 and between the semiconductor layer 215 and the substrate 201. A second etching process is then performed that selectively etches the spacer layer to form an inner spacer 255, such as Figure 7B , while minimal (to no) etching of the semiconductor layer 215, the dummy gate stack 240, and the gate spacer 247. In some embodiments, the spacer layer is removed from the sidewalls of the gate spacer 247, the sidewalls of the semiconductor layer 215, the dummy gate stack 240, and the substrate 201. The spacer layer (and the inner spacer 255) includes a material different from the material of the semiconductor layer 215 and the material of the gate spacer 247 to obtain a desired etch selectivity during the second etching process. In some embodiments, the spacer layer 255 includes a dielectric material including silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon oxycarbonitride). In some embodiments, the inner spacer layer 255 includes a low-k dielectric material, such as the low-k dielectric materials described herein. In embodiments where the device 200 is a FinFET, the inner spacer 255 is omitted.

[0046] At operation 112, method 100 ( Figure 1A ) performs additional etching on a subset of the S / D regions, such as the source region of the device 200 according to the depicted embodiment, thereby creating deep trenches in the source region. According to an embodiment, the resulting structure is Figure 8A-8E Shown in. Fig. 8A 2 shows a top view of the device 200, Figure 8B , Figure 8C , Fig.8D and Fig. 8E Parts along the Fig. 8A A cross-sectional view of the device 200 taken along the BB line, CC line, DD line and EE line in FIG.

[0047] In the depicted embodiment, operation 112 forms an etch mask 241 including a patterned hard mask 236 and a patterned resist 237. The etch mask 241 covers the device 200, except for the source region, which is exposed through the opening 238 in the etch mask 241. Subsequently, operation 112 etches the source region deep in the substrate 201, for example, through the semiconductor layer 207, until only a thin layer 204 remains in the source trench 250, thereby extending the source trench 250 into the substrate 201. The etching process may include a dry etching process, a wet etching process, a reactive ion etching process, or other suitable process. In this embodiment, the etching process is substantially anisotropic (i.e., substantially vertical). Similarly, the etching process is selectively adjusted for the material of the semiconductor layer 204, and the gate spacer 247 and the gate hard mask layer 246 are not etched (or minimally etched). The etching process in operation 112 can be similar to the etching process in operation 110. After the etching process is completed, operation 112 removes the patterned resist 237 , such as by a stripping process.

[0048] The method 100 may further include an operation 113, which is applied to the isolation features 230 in the source trench 250, making the source trench 250 wider (eg, Fig.9D ). In the depicted embodiment, operation 113 is a pre-cleaning process prior to the epitaxial growth in operation 114. The pre-cleaning process applies a cleaning chemical to clean the trench 250 and withdraw (partially remove) the isolation feature 230, so that the trench 250 is laterally expanded. In some embodiments, the cleaning chemical includes a dry etching process for cleaning the surface and partially removing the isolation feature 230 (such as silicon oxide) using an ammonia (NH3) and nitrogen trifluoride (NF3) gas mixture. The plasma energy decomposes the ammonia and nitrogen trifluoride gases into reactive species that combine in the gas phase to form highly reactive ammonium fluoride (NH4F) compounds and / or ammonium bifluoride (NH4F·HF). These molecules react with the isolation feature 230 to be cleaned. In the depicted embodiment, the trench 250 is widened so that the lateral dimension increase ranges between 1 nm and 6 nm, which will result in increasing the size of the backside through-hole feature (to be further described at a later stage) and reducing its resistance.

[0049] At operation 114, method 100 ( Figure 1A ) A semiconductor layer 239 is formed in the source trench 250. According to an embodiment, the resulting structure is Figure 9A-9E Shown in. Fig. 9A 2 shows a top view of the device 200, Fig. 9B , Fig. 9C , Fig.9D and Fig.9E Parts along the Fig. 9A A cross-sectional view of the device 200 taken along the BB line, CC line, DD line and EE line in FIG.

[0050] The semiconductor layer 239 may be deposited using an epitaxial growth process or by other suitable processes. In some embodiments, epitaxial growth of the semiconductor layer 239 is achieved by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process, a metal organic chemical vapor deposition (MOCVD) process, other suitable epitaxial growth processes, or a combination thereof. The semiconductor layer 239 includes a semiconductor material different from the semiconductor material included in the semiconductor layer 207, thereby obtaining etching selectivity during subsequent processing. For example, the semiconductor layers 239 and 207 (or the additional semiconductor layer 204) may include different materials, different composition atomic percentages, different composition weight percentages, and / or other features to obtain the desired etching selectivity during the etching process. In an embodiment, the semiconductor layer 207 includes silicon germanium, and the semiconductor layer 239 includes silicon, such as undoped silicon. By using undoped silicon, the deep portions of the source / drain features 260 for both the nFET and the pFET can share the same epitaxial process and save manufacturing costs. In an alternative embodiment, semiconductor layer 239 includes silicon doped with boron to enhance etch selectivity to an etch process used to etch silicon germanium for backside processing at a later stage. In another embodiment, both semiconductor layers 239 and 207 may include silicon germanium, but with different silicon atomic percentages. The present invention contemplates that semiconductor layers 239 and 207 include any combination of semiconductor materials that can provide the desired etch selectivity, including any semiconductor material disclosed herein. Fig.9E ) is covered by the patterned hard mask layer 236, so the semiconductor layer 239 is deposited only in the source region ( Fig.9D ). The semiconductor layer 239 is deposited to a certain thickness so that it extends upward to the bottom of the stack 205 ( Fig. 9B ) and is substantially parallel to the top surface of the isolation member 230 ( Fig.9D ). If the semiconductor layer 239 is initially grown larger than Fig. 9B and Fig.9DIf the level shown is high, operation 114 may include an etching process that recesses the semiconductor layer 239 to that level. After depositing the semiconductor layer 239, operation 114 removes the patterned hard mask layer 236 by one or more etching processes. As will be discussed below, in various embodiments, the additional etching in operation 112 and the growth of the semiconductor layer 239 in operation 114 may be performed only in the source region, only in the drain region, or in both the source region and the drain region.

[0051] At operation 116, method 100 ( Figure 1A ) epitaxially grows the semiconductor S / D component 260 in the S / D trench 250. According to an embodiment, the resulting structure is Figure 10A-10E Shown in. Fig. 10A 2 shows a top view of the device 200, Fig. 10B , Fig. 10C , Fig. 10D and Fig.10E Parts along the Fig. 10A A cross-sectional view of the device 200 taken along the BB line, CC line, DD line and EE line in FIG.

[0052] like Fig. 10B , Fig. 10D and Fig.10EAs shown, epitaxial S / D components 260 are grown from semiconductor layers (such as 208 and 239) at the bottom of S / D trench 250 and from semiconductor layer 215 at the sidewalls of S / D trench 250. The epitaxial process may use CVD deposition techniques (e.g., VPE and / or UHV-CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The epitaxial process may use gaseous and / or liquid precursors that interact with the composition of semiconductor layers 208, 239, and 215 (particularly semiconductor layer 215). Epitaxial S / D components 260 are doped with n-type dopants for n-type transistors or p-type dopants for p-type transistors, respectively. In some embodiments, for n-type transistors, epitaxial S / D components 260 include silicon and may be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., to form Si:C epitaxial source / drain components, Si:P epitaxial source / drain components, or Si:C:P epitaxial source / drain components). In some embodiments, for p-type transistors, the epitaxial S / D features 260 include silicon germanium or germanium and may be doped with boron, other p-type dopants, or combinations thereof (e.g., to form Si:Ge:B epitaxial source / drain features). In some embodiments, the epitaxial S / D features 260 include more than one epitaxial semiconductor layer, wherein the epitaxial semiconductor layers may include the same or different materials and / or dopant concentrations. Additionally, in an embodiment, the S / D features 260 (or at least the portion thereof adjacent to the semiconductor layer 239) include a different material composition than the semiconductor layer 239 to obtain etch selectivity during the backside via formation process. For example, in an embodiment, the semiconductor layer 239 includes undoped silicon and the S / D features 260' include doped silicon (n-type doped for n-type transistors and p-type doped for p-type transistors). In some embodiments, the epitaxial source / drain features 260 are doped during deposition by adding impurities to the source material of the epitaxial process. In some embodiments, the epitaxial source / drain features 260 are doped by an ion implantation process after the deposition process. In some embodiments, an annealing process (e.g., rapid thermal annealing (RTA) and / or laser annealing) is performed to activate dopants in the epitaxial source / drain features 260. In some embodiments, the epitaxial source / drain features 260 are formed in a separate processing sequence, which includes, for example, masking the p-type GAA transistor region when forming the epitaxial source / drain 260 in the n-type GAA transistor region, and masking the n-type GAA transistor region when forming the epitaxial source / drain 260 in the p-type GAA transistor region. In addition, as Fig. 10D and Fig.10EAs shown, the S / D feature 260 is formed in a polygonal shape, leaving multiple surfaces with different crystal orientations. In some embodiments, an air gap can be formed in the trench 250 and covered by the S / D feature 260. In some embodiments, the S / D feature 260 includes more than one semiconductor layer with different compositions, different dopants, different doping concentrations, or a combination thereof to achieve strain effects or other device performance advantages. In the depicted example, the S / D feature 260 also includes an epitaxially grown semiconductor layer 260' having silicon doped with boron for both nFETs and pFETs.

[0053] At operation 118, method 100 ( Figure 1B ) form a contact etch stop layer (CESL) 269 and an interlayer dielectric (ILD) layer 270.

[0054] At operation 120, method 100 ( Figure 1B ) removes the dummy gate 240 and forms a vertically stacked channel 272.

[0055] According to an embodiment, the resulting structure is Figures 11A-11E Shown in. Fig.11A 2 shows a top view of the device 200, Fig. 11B , Fig. 11C , Fig.11D and Fig.11E Parts along the Fig.11A A cross-sectional view of the device 200 taken along the BB line, CC line, DD line and EE line in FIG.

[0056] refer to Fig. 11B , Fig.11D and Fig.11E, operation 118 forms a CESL 269 and an ILD layer 270. The CESL 269 is deposited over the S / D features 260. The ILD layer 270 is deposited over the CESL 269. The CESL 269 includes a different material from the ILD layer 270 to obtain an etch selectivity and an etch stop function. The CESL 269 may include La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, or other suitable materials; and may be formed by CVD, PVD, ALD, or other suitable methods. The ILD layer 270 may include tetraethyl orthosilicate (TEOS) oxide, undoped silicon glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), phosphosilicate glass (PSG), boro-doped silicate glass (BSG), low-k dielectric materials, other suitable dielectric materials, or combinations thereof. The ILD 270 may be formed by PECVD (plasma enhanced CVD), FCVD (flow CVD), or other suitable methods. After the CESL 269 and the ILD layer 270 are deposited, a CMP process and / or other planarization process may be performed until the top (or top surface) of the dummy gate stack 240 is reached (exposed). In some embodiments, the planarization process removes the hard mask of the dummy gate stack 240 to expose the underlying dummy gate electrode 245, such as a polysilicon gate electrode layer.

[0057] refer to Fig. 11B and Fig. 11C Operation 120 removes the dummy gate stack 240 and forms a suspended channel 272. First, operation 120 includes a first etching process to remove the dummy gate stack 240 (dummy gate electrode 245 and dummy gate dielectric layer 235, see Figure 6B ). This forms the gate trench 271. The etching process may be a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, the etching process is a multi-step etching process. For example, etchants may be used alternately in the etching process to remove the various layers of the dummy gate stack 240, respectively. In some embodiments, the etching process is designed and configured to selectively etch the dummy gate stack 240, while minimally (to no) etching other components of the device 200 (such as the ILD layer 270, the gate spacer 247, the isolation component 230, the cladding layer 231, and the semiconductor layer 210).

[0058] Operation 120 also includes a second etching process to selectively remove the semiconductor layer 210 and the capping semiconductor layer 231 exposed in the gate trench 271, thereby leaving the semiconductor layer 215 suspended above the substrate 201 and connected to the S / D component 260. This process is also referred to as a channel release process, and the semiconductor layer 215 is also referred to as a channel layer. The second etching process selectively etches the semiconductor layer 210, while minimally (or even no) etching the semiconductor layer 215, and in some embodiments, minimally (or even no) etching the gate spacer 247 and / or the internal spacer 255. The second etching process can first etch and remove the capping layer 231, thereby providing a path for further etching and removing the semiconductor layer 210. In the depicted embodiment, the capping layer 231 and the semiconductor layer 210 both include silicon germanium, and the semiconductor layer 215 includes silicon, and the second etching process can be adjusted to have an etching selectivity between silicon germanium and silicon. In some embodiments, the silicon germanium can be selectively oxidized and then selectively etched away. In an embodiment where the device 200 is a FinFET, the channel release process is omitted because only the channel layer 215 but not the semiconductor layer 210 is present in the channel region.

[0059] At operation 122, method 100 ( Figure 1B ) to form a functional gate stack 240', such as a metal gate stack having a high-k dielectric material as a gate dielectric layer and a metal as a gate electrode. According to an embodiment, the resulting structure is Figure 12A-12E Shown in. Fig. 12A 2 shows a top view of the device 200, Fig. 12B , Fig. 12C , Fig.12D and Fig.12E Parts along the Fig. 12A A cross-sectional view of the device 200 taken along the BB line, CC line, DD line and EE line in FIG.

[0060] Operation 122 forms a gate dielectric layer 349 wrapped around each semiconductor layer 215, and forms a gate electrode 350 over the gate dielectric layer 349. The functional gate stack 240' includes the gate dielectric layer 349 and the gate electrode 350. The gate dielectric layer 349 may include a high-k dielectric material such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x, ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba, Sr)TiO3 (BST), Si3N4, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials or combinations thereof. High-k dielectric materials generally refer to dielectric materials having a high dielectric constant, for example, higher than the dielectric constant of silicon oxide (k≈3.9). The gate dielectric layer 349 can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD) and / or other suitable methods. In some embodiments, the gate stack 240' also includes an interface layer between the gate dielectric layer 349 and the channel 272. The interface layer can include silicon dioxide, silicon oxide or other suitable materials. In some embodiments, the gate electrode layer 350 includes an n-type work function layer or a p-type work function layer and a metal filling layer. For example, the n-type work function layer may include a metal with a sufficiently low effective work function, such as titanium, aluminum, tantalum carbide, tantalum carbide, tantalum nitride, tantalum nitride, or a combination thereof. For example, the p-type work function layer may include a metal with a sufficiently large effective work function, such as titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or a combination thereof. For example, the metal filling layer may include aluminum, tungsten, cobalt, copper, and / or other suitable materials. The gate electrode layer 350 may be formed by CVD, PVD, electroplating, and / or other suitable processes. Since the gate stack 240' includes a high-k dielectric layer and a metal layer, it is also referred to as a high-k metal gate.

[0061] Method 100( Figure 1B ) performs various operations on the front side of the device 200, including middle of the line (MEOL) processes, back end of the line (BEOL) processes, thereby bonding a carrier on the front side of the device 200. According to an embodiment, the resulting structure is Fig.13A , Fig. 13B , Fig. 13C , Fig.13D and Fig.13E Shown in. Fig.13A 2 shows a top view of the device 200, Fig. 13B , Fig.13D and Fig.13E Parts along the Fig.13A BB line, CC line, DD line and EE line of the device 200. In particular, Fig. 13B , Fig.13D and Fig.13E It is shown in a flipped view such that the front and back sides of the device 200 are flipped.

[0062] At operation 124, method 100 ( Figure 1B) to form S / D contact features 354 located on some of the S / D features 260. Operation 124 may include a photolithography process and etching a subset of the S / D features to form S / D contact holes. Operation 124 includes one or more etching processes adjusted to selectively etch the material of the ILD layer 270 without (or minimally) etching the dielectric layer 234 and the dielectric layer 232 and the CESL 269, thereby forming the contact holes. In some embodiments, the S / D features 260 may be partially etched. The etching process may be dry etching, wet etching, reactive ion etching, or other etching methods. In addition, operation 124 may further include additional etching, such as wet etching, to open the S / D features 260 and the CESL 269 so that the S / D features 260 are exposed in the contact holes. In some embodiments, the CESL 269 and the S / D features 260 form the bottom surface of the contact holes. In some embodiments, the CESL 269 , the ILD layer 270 , and the S / D features 260 form a bottom surface of the contact hole.

[0063] Operation 124 includes forming a silicide feature 352 over the S / D feature 260, and forming an S / D contact (or via) feature 354 over the silicide feature 273, such as Fig.13E Since the silicide feature 273 and the S / D contact 275 are formed on the front side of the device 200 , they are also referred to as the front side silicide feature 352 and the front side S / D contact 354 , respectively.

[0064] The process of forming the silicide feature 352 in operation 124 includes depositing one or more metals into the contact hole, performing an annealing process on the device 200 to cause a reaction between the one or more metals and the S / D feature 260 to produce the silicide feature 352, and removing an unreacted portion of the one or more metals to leave the silicide feature 352 in the contact hole. The one or more metals may include titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), erbium (Er), cobalt (Co), or a combination thereof (e.g., an alloy of two or more metals), and may be deposited using CVD, PVD, ALD, or other suitable methods. The silicide feature 352 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds.

[0065] The S / D contact component 354 may include a conductive barrier layer and a metal filling layer above the conductive barrier layer. The function of the conductive barrier layer is to prevent the metal material of the metal filling layer from diffusing into the dielectric layer adjacent to the S / D contact component 354. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru) or a conductive nitride, such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN) or a combination thereof, and the conductive barrier layer may be formed by CVD, PVD, ALD and / or other suitable processes. The metal filling layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru) or other metals, and the metal filling layer may be formed by CVD, PVD, ALD, electroplating or other suitable processes. In some embodiments, the conductive barrier layer is omitted in the S / D contact component 354. Operation 124 may perform a CMP process to remove excess material of the S / D contact component 354.

[0066] Method 100( Figure 1B ) also includes an operation 126 of performing a middle of the line (MEOL) process and a back end of the line (BEOL) process on the front side of the device 200, thereby forming an interconnect structure 360 ​​on the front side of the device 200. The interconnect structure 360 ​​has various conductive features, such as via features and metal lines in different metal layers, which are configured to couple various transistors and other IC units into functional circuits. For example, operation 126 can form a gate via feature connected to the gate stack 240', form an S / D contact via connected to the S / D contact feature 354, and form one or more interconnect layers, wherein the wiring and the via are embedded in the dielectric layer. The one or more interconnect layers connect the gate electrodes, source electrodes, and drain electrodes of the various transistors and other circuits in the device 200 to partially or fully form an integrated circuit.

[0067] In particular, if Fig. 13B As shown, operation 126 includes forming a gate via feature 362 located on the gate electrode of the gate stack 240'. The formation of the gate via feature 362 may include depositing an ILD layer 364 (and an etch stop layer below the ILD layer 364); patterning the ILD layer 364 to form an opening of the ILD layer 364 by a photolithography process and etching; and filling the opening with one or more conductive materials. In some embodiments, the formation of the gate via feature 362 may include a damascene process, such as a single damascene process or a dual damascene process.

[0068] In some embodiments, operation 126 includes forming a conductive feature 366 (such as a metal line in the first metal layer) located on the gate via feature 362, such as Fig. 13BAs shown. The formation of the conductive feature 366 may include depositing an ILD layer 368; patterning the ILD layer 368 to form an opening of the ILD layer 368 by a photolithography process and etching; and filling the opening with one or more conductive materials. In some embodiments, the formation of the conductive feature 368 may include a damascene process, such as a single damascene process or a dual damascene process.

[0069] Operation 126 may also form a passivation layer over interconnect structure 360. Fig. 13B In the example shown, layer 370 is used to represent various additional dielectric and metal layers (such as a second metal layer, a third metal layer, etc.) in interconnect structure 360 ​​; and layer 372 is used to represent various passivation layers formed on the front side of device 200 .

[0070] At operation 128, method 100 ( Figure 1B ) turns the device 200 upside down and attaches the front side of the device 200 to the carrier 374, such as Fig. 13B As shown. This allows access to the device 200 from the back side of the device 200 for further processing. Operation 128 may use any suitable attachment process, such as direct bonding, hybrid bonding, using adhesives or other bonding methods. Operation 128 may further include alignment, annealing and / or other processes. In some embodiments, carrier 374 may be a silicon wafer. Figure 13B-13E In the drawings (and in other drawings described below), the “z” direction points from the back side of the device 200 to the front side of the device 200 , while the “−z” direction points from the front side of the device 200 to the back side of the device 200 .

[0071] At operation 130, method 100 ( Figure 1C ) thinning the device 200 from the back side of the device 200 until the semiconductor layer 207 is exposed from the back side of the device 200. According to an embodiment, the resulting structure is Figure 14A-14E Shown in. Fig.14A 2 shows a top view of the device 200, Fig. 14B , Fig. 14C , Fig.14D and Fig.14E Parts along the Fig.14A 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 , 26 , 27 , 28 , 29 , 30 , 31 , 32 , 33 , 34 , 36 , 37 , 38 , 39 , 40 , 41 , 42 , 43 , 44 , 46 , 47 , 48 , 49 , 50 , 51 , 52 , 53 , 54 , 55 , 56 , 57 , 58 , 59 , 60 , 61 , 62 , 63 , 64 , 65 , 66 , 67 , 68 , 69 , 70 , 71 , 72 , 73 , 74 , 75

[0072] At operation 132, method 100 ( Figure 1C ) selectively etches the semiconductor layer 207 to form a trench 376 over the back side of the gate stack 240' and the drain feature 260. According to an embodiment, the resulting structure is Figure 15A-15E Shown in. Fig.15A 2 shows a top view of the device 200, Fig. 15B , Fig. 15C , Fig.15D and Fig.15E Parts along the Fig.15A . In the present embodiment, operation 132 applies an etching process that is adjusted to selectively etch the material of semiconductor layer 207 (e.g., SiGe in one embodiment), without etching (or minimally etching) semiconductor layer 239 (e.g., silicon in one embodiment), drain feature 260, gate stack 240' (particularly gate dielectric layer 349 and gate interface layer, if present), and isolation feature 230. It should be noted that the composition difference between semiconductor layer 239 and semiconductor layer 207 provides etching selectivity for self-alignment, and opens the drain side without opening the source side. The etching process can be dry etching, wet etching, reactive ion etching, or other etching methods. In particular, in the present embodiment, semiconductor layer 207 is etched in a self-aligned manner. In other words, operation 132 does not require the manufacture of an etching mask (e.g., an etching mask formed by a photolithography process) to etch semiconductor layer 207. Instead, it relies on the etching selectivity of materials in semiconductor layer 207 and its surrounding layers.

[0073] At operation 134, method 100 ( Figure 1C ) to form a dielectric layer 378 to fill the trench 376. According to an embodiment, the resulting structure is Figure 16A-16E Shown in. Fig.16A 2 shows a top view of the device 200, Fig. 16B , Fig. 16C , Fig.16D and Fig.16E Parts along the Fig.16A378 is a cross-sectional view of the device 200 with BB line, CC line, DD line and EE line in FIG. In an embodiment, the dielectric layer 378 includes silicon oxide. In some embodiments, the dielectric layer 378 includes other dielectric materials, such as La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Y2O3, AlON, TaCN, ZrSi or other suitable materials. The dielectric layer 378 may have a substantially uniform thickness along each surface of the groove 374 and may be formed by CVD, PVD, ALD or other suitable methods. In some embodiments, the dielectric layer 378 may include tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass or doped silicon oxide, such as borophosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), phosphosilicate glass (PSG), boro-doped silicate glass (BSG) and / or other suitable dielectric materials. The dielectric layer 378 may be formed by PECVD (Plasma Enhanced CVD), FCVD (Flow CVD), or other suitable methods. Operation 134 may further perform a CMP process to planarize the back side of the device 200 and expose the semiconductor layer 239 for further processing.

[0074] At operation 136, method 100 ( Figure 1C ) removes semiconductor layer 239 from the back side of device 200, thereby forming trenches 380 for backside vias. According to an embodiment, the resulting structure is Figure 17A-17E Shown in. Fig.17A 2 shows a top view of the device 200, Fig. 17B , Fig. 17C , Fig.17D and Fig.17E Parts along the Fig.17A2. A cross-sectional view of the device 200 along the BB line, CC line, DD line, and EE line in FIG. 1. In the present embodiment, operation 136 applies an etching process that is adjusted to selectively etch the material of the semiconductor layer 239 (such as, in one embodiment, undoped silicon) without etching (or minimally etching) the dielectric 378, the isolation feature 230, and the internal spacer 255. The etching process may partially etch the source feature 260. The etching process produces a trench 380 that exposes the source feature 260 from the back side of the device 200. The etching process may be dry etching, wet etching, reactive ion etching, or other etching methods. In particular, in the present embodiment, the semiconductor layer 239 is etched in a self-aligned manner. In other words, operation 136 does not require the manufacture of an etching mask (e.g., an etching mask formed by a photolithography process) to etch the semiconductor layer 239. Instead, it relies on the etching selectivity of the materials in the semiconductor layer 239 and its surrounding layers. This advantageously forms trench 380 to align with underlying source features 260 without misalignment, such as that introduced by photolithographic overlay shift. Using this process will produce backside source contact (or source via) features that are ideally aligned with source features 260, as will be discussed below.

[0075] At operation 138, method 100 ( Figure 1C ) to form a backside source silicide feature 382 and a backside source contact feature 284. According to an embodiment, the resulting structure is Figure 18A-18E Shown in. Fig.18A 2 shows a top view of the device 200, Fig.18B , Fig.18C , Fig.18D and Fig.18E Parts along the Fig.18A FIG. 2 is a cross-sectional view of the device 200 along the BB line, CC line, DD line and EE line in FIG. Fig.18D As shown, a silicide feature 382 is formed on the surface of the source feature 260. A backside source contact feature 384 is formed on the backside source silicide feature 280 with reduced contact resistance. In addition, the backside source contact feature 384 may include a barrier layer 386 disposed on the sidewalls of the trench 380. In some embodiments, the barrier layer 386 is a dielectric material such as silicon nitride, silicon oxide, other suitable dielectric materials, or combinations thereof. As described above with reference to Fig.17D As discussed in the self-aligned etching process, the backside source contact feature 384 is self-aligned with the source feature 260. Therefore, it is isolated from the nearby gate stack 240' by the inner spacer 255 and the barrier layer 386, as shown in FIG. Fig.18B The self-aligned backside contact feature 384 minimizes the risk of shorting between the source feature 260 and the nearby gate stack 240 ′.

[0076] In some embodiments, the process of forming the backside source silicide feature 382 is similar to the process for the frontside source silicide feature 352, and the process of forming the backside source contact feature 384 is similar to the process for the frontside source contact 354. In an embodiment, operation 138 includes depositing one or more metals into the hole 380, performing an annealing process on the device 200 to cause a reaction between the one or more metals and the source feature 260 to produce the silicide feature 382, ​​and removing an unreacted portion of the one or more metals to leave the silicide feature 382 on the surface of the source feature 260 in the trench 380. The one or more metals may include titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), erbium (Er), cobalt (Co), or a combination thereof (e.g., an alloy of two or more metals), and may be deposited using CVD, PVD, ALD, or other suitable methods. The silicide feature 280 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds. In the depicted embodiment, the source contact feature 384 may include a barrier layer 386 and a metal fill layer 388 above the barrier layer 386. The barrier layer 386 functions to prevent the metal material of the metal fill layer from diffusing into the dielectric layer (such as layer 230 and layer 376) adjacent to the source contact feature 382. The barrier layer 386 may be formed by deposition (such as CVD or ALD) and anisotropic etching to expose the silicide feature 382. Alternatively, the barrier layer 386 may be formed by other suitable methods such as selective deposition, so that the barrier layer 386 is selectively deposited on the sidewalls of the trench 380 rather than on the bottom surface. In some embodiments, the barrier layer 386 may optionally include a conductive material such as titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or a combination thereof, and the barrier layer 386 may be formed by CVD, PVD, ALD, and / or other suitable processes. The metal filling layer 388 may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or other metals, and the metal filling layer 388 may be formed by CVD, PVD, ALD, electroplating, or other suitable processes. Operation 138 may perform a CMP process to remove excess material of the source contact feature 384. Fig. 21C and Fig.18EAs shown, the gate stack 240 ′ and the drain feature 260 are protected from various deposition and etching processes in operation 138 .

[0077] In particular, the drain feature 260 ( Fig.18E ) has a first thickness T1, and the gate stack 240 ′ ( Fig.18C ) has a second thickness T2 greater than the first thickness T1. In some embodiments, the first thickness T1 is greater than about 5 nm and the second thickness T2 is greater than about 10 nm. In some embodiments, the first thickness T1 is in a range between 5 nm and 8 nm, and the second thickness T2 is in a range between 10 nm and 15 nm. In some embodiments, the thickness of the back side source contact feature 384 is greater than 20 nm. In some embodiments, the thickness of the back side source contact feature 384 is in a range between 20 nm and 30 nm.

[0078] At operation 140, method 100 ( Figure 1C ) to form a backside power rail 390 and a backside interconnect structure 392. According to an embodiment, the resulting structure is Figure 19A-19B and Figure 20A to Figure 20C Shown in. Fig.19A 2 shows a top view of the device 200, Fig.19B Shows a portion along Fig.19A A cross-sectional view of the device 200 taken along line BB in FIG. Figure 20A to Figure 20C 2 shows a perspective view of the device 200 at various stages of manufacture. Fig.19B and Fig. 20B As shown, the backside source contact feature 384 is electrically connected to the backside power rail 390. In an embodiment, the backside power rail 390 may be formed using a damascene process, a dual damascene process, a metal patterning process, or other suitable process. The backside power rail 390 may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or other metals, and may be deposited by CVD, PVD, ALD, electroplating, or other suitable processes. Although in Fig.19B390 is not shown, but the backside power rail 390 is embedded in one or more dielectric layers, and the backside interconnect structure 392 includes metal lines 394 and via features 396 embedded in one or more dielectric layers. The metal lines 394 are distributed in one or more metal layers, and the via features 396 are configured between adjacent metal layers to provide vertical connections between corresponding metal lines in adjacent metal layers. In some embodiments, the backside power rail 390 is considered to be part of the backside interconnect structure 392. Having the backside power rail 390 advantageously increases the number of metal tracks in the device 200 that can be used to directly connect to the source / drain contact features and the via features. The gate density is also increased for greater device integration than other structures without the backside power rail 390. The backside power rail 390 can have a wider dimension than the metal lines of the first metal layer (M1) on the front side of the device 200, which advantageously reduces the resistance of the backside power rail.

[0079] At operation 142, method 100 ( Figure 1C ) performs further manufacturing processes on the device 200. For example, the method 100 may form a passivation layer on the back side of the device 200, remove the carrier 374, form through silicon via (TSV) features to connect the front side interconnect structure to the back side of the device 200, and perform other BEOL processes.

[0080] In the above embodiment, the device 200 includes a thick semiconductor layer 207 disposed between the insulator 203 and the Si / SiGe stack 205. The semiconductor layer 207 is different from other semiconductor layers (e.g., 204) to provide etching selectivity. In some examples, the semiconductor layer 207 includes silicon germanium, and the semiconductor layer 204 includes silicon. The thickness of the semiconductor layer 207 is greater than any of the silicon layer and the silicon germanium layer of the Si / SiGe stack 205. The semiconductor layer substantially extends from the top surface to the bottom surface of the isolation feature 230, such as Figure 5B In addition, a semiconductor layer 239 (such as undoped silicon) is formed below the source feature 260 and substantially extends to the source feature 260. Therefore, the selective etching of the semiconductor layer 207 and the selective etching of the semiconductor layer 239 form a trench 380 self-aligned with the source feature 260, and a corresponding backside source contact feature 384 is self-aligned with the source feature 260.

[0081] In some embodiments, the source feature 260 is connected to the backside power rail 390 through the backside contact feature 384, and the drain feature 260 is connected to the frontside power rail through the frontside contact feature 354. In an alternative embodiment, the drain feature 260 is connected to the backside power rail 390 through the backside contact feature 384, and the source feature 260 is connected to the frontside power rail through the frontside contact feature 354. This can be achieved by switching the process dedicated to the source region with the process dedicated to the drain region in the above embodiments. For example, the semiconductor layer 239 can be provided in the drain region instead of in the source region.

[0082] Although not intended to be limiting, embodiments of the present invention provide one or more of the following advantages. For example, embodiments of the present invention form a silicide component that is completely wrapped around the source component, which advantageously reduces the source resistance. Moreover, embodiments of the present invention use a self-aligned process to form a backside source contact, which minimizes the risk of the source component shorting to nearby conductors including the gate stack. Embodiments of the present invention can be easily integrated into existing semiconductor manufacturing processes.

[0083] The disclosed device and method for making the same have other embodiments. The device and the method are similar except for some changes and modifications. For simplicity, similar components and processes are eliminated in the following description. Only those components and processes that are different are described below.

[0084] According to some embodiments, a device 400 and a method 100 of manufacturing the same are collectively described below.

[0085] At operation 114, method 100 ( Figure 1A ) A semiconductor layer 402 is formed in the source trench 250. According to an embodiment, the resulting structure is Figure 21A-Figure 21E Shown in. Fig.21A 4 shows a top view of the device 400, Fig. 21B , Fig. 21C , Fig.21D and Fig.21E Parts along the Fig.21A A cross-sectional view of the device 400 along the BB line, CC line, DD line and EE line in FIG.

[0086] The semiconductor layer 402 may be deposited using an epitaxial growth process or by other suitable processes. In some embodiments, epitaxial growth of the semiconductor layer 402 is achieved by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process, a metal organic chemical vapor deposition (MOCVD) process, other suitable epitaxial growth processes, or a combination thereof. The semiconductor layer 402 includes a semiconductor material different from the semiconductor material included in the semiconductor layer 207 to obtain etching selectivity during subsequent processing. For example, the semiconductor layers 402 and 207 (or the additional semiconductor layer 204) may include different materials, different composition atomic percentages, different composition weight percentages, and / or other features to obtain a desired etching selectivity during an etching process. In an embodiment, the semiconductor layer 207 includes silicon germanium, and the semiconductor layer 402 includes silicon, such as boron-doped silicon for both nFETs and pFETs to enhance etching selectivity during wet etching to remove SiGe. In the depicted embodiment, the boron doping concentration ranges from 10 20 / cm 3 and 3*10 21 / cm 3 The doped silicon can be formed by epitaxial growth and in-situ doping. During epitaxial growth, the dopant boron is introduced into the semiconductor layer 402, and the precursors for the epitaxial growth include both silicon-containing chemicals and boron-containing chemicals. If the semiconductor layer 402 is initially grown thicker than Fig. 21B and Fig.21D If the level shown is high, operation 114 may include an etching process that recesses the semiconductor layer 402 to that level. After depositing the semiconductor layer 402, operation 114 removes the patterned hard mask layer 236 by one or more etching processes. As will be discussed below, in various embodiments, the additional etching in operation 112 and the growth of the semiconductor layer 402 in operation 114 may be performed only in the source region, only in the drain region, or in both the source region and the drain region.

[0087] At operation 132, method 100 ( Figure 1C ) selectively etches the semiconductor layer 207 to form a trench 404 over the backside of the gate stack 240' and the drain feature 260. According to an embodiment, the resulting structure is Figure 22A-22E Shown in. Fig.22A 4 shows a top view of the device 400, Fig. 22B , Fig. 22C , Fig.22D and Fig.22E Parts along the Fig.22A. In the present embodiment, operation 132 applies an etching process that is adjusted to selectively etch the material of semiconductor layer 207 (e.g., SiGe in one embodiment), without etching (or minimally etching) semiconductor layer 402 (e.g., silicon in one embodiment), drain feature 260, gate stack 240' (particularly gate dielectric layer 349 and gate interface layer, if present), and isolation feature 230. It should be noted that the composition difference between semiconductor layer 402 and semiconductor layer 207 provides etching selectivity for self-alignment, and opens the drain side without opening the source side. The etching process can be dry etching, wet etching, reactive ion etching, or other etching methods. In particular, in the present embodiment, semiconductor layer 207 is etched in a self-aligned manner. In other words, operation 132 does not require the manufacture of an etching mask (e.g., an etching mask formed by a photolithography process) to etch semiconductor layer 207. Instead, it relies on the etching selectivity of materials in semiconductor layer 207 and its surrounding layers. Furthermore, the etching process includes one or more etching steps with corresponding etchants to continue etching the semiconductor layer 208 so that the gate stack 204' is exposed within the corresponding trench 402 and the drain feature 260 is exposed within the corresponding trench 404. In particular, the semiconductor layer 260' (boron-doped silicon in the present embodiment) of the drain feature 260 is exposed.

[0088] At operation 134, method 100 ( Figure 1C ) to form a dielectric layer 406 to fill the trench 402. For various features, including the front drain contact feature 354 and the back source contact feature 384 formed on the device 400 through operations 136-140, according to an embodiment, the resulting structure is Figure 23A-23E Shown in. Fig.23A 4 shows a top view of the device 400, Fig. 23B , Fig.23C , Fig.23D and Fig.23E Parts along the Fig.23A 4 is a cross-sectional view of the device 400 along the BB line, CC line, DD line and EE line in FIG. The dielectric layer 406 directly contacts the bottom surface of the gate stack 204 and the drain component 260. More specifically, the dielectric layer 406 directly contacts the semiconductor layer 260' of the drain component 260. Fig.23EAs shown, the thickness of the semiconductor layer 260' below the dielectric layer 406 is less than 3nm, such as in the range between 1nm and 2nm. In an embodiment, the dielectric layer 406 includes silicon oxide. In some embodiments, the dielectric layer 406 includes other dielectric materials, such as La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Y2O3, AlON, TaCN, ZrSi or other suitable materials. The dielectric layer 406 can have a substantially uniform thickness along each surface of the trench 404 and can be formed by CVD, PVD, ALD or other suitable methods. In some embodiments, dielectric layer 406 may include tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), phosphosilicate glass (PSG), boro-doped silicate glass (BSG), and / or other suitable dielectric materials. Operation 134 may further perform a CMP process to planarize the back side of device 400 and expose semiconductor layer 402 for further processing. It should be noted that because semiconductor layer 208 is removed and dielectric layer 406 directly contacts gate stack 240', the back side of device 400 may be planarized by dielectric layer 406. Fig. 23B The semiconductor layer 208 is not present in the device 400 in FIG.

[0089] According to an embodiment, the structure of the device is Figure 24A-24B and Figure 25A to Figure 25C Shown in. Fig.24A 4 shows a top view of the device 400, Fig. 24B Shows a portion along Fig.24A A cross-sectional view of the device 400 taken along line BB in FIG. Figure 25A to Figure 25C 4 shows a perspective view of the device 400 at various stages of manufacture. Fig. 24B and Fig.25B As shown, the backside source contact feature 384 is electrically connected to the backside power rail 390. Fig. 24B As shown, the backside interconnect structure 392 includes metal lines 394 and via features 396 embedded in one or more dielectric layers. The metal lines 394 are distributed in one or more metal layers, and the via features 396 are configured between adjacent metal layers to provide vertical connections between corresponding metal lines in adjacent metal layers. Having a backside power rail 390 advantageously increases the number of metal tracks in the device 400 that can be used to directly connect to source / drain contact features and via features. The gate density is also increased for greater device integration than other structures without the backside power rail 390. The backside power rail 390 can have a wider dimension than the metal lines of the first metal layer (M1) on the front side of the device 400, which advantageously reduces the resistance of the backside power rail.

[0090] In the above embodiment, the device 400 includes a thick semiconductor layer 207 disposed between the insulator 203 and the Si / SiGe stack 205. The semiconductor layer 207 is different from other semiconductor layers (e.g., 204) to provide etching selectivity. In some examples, the semiconductor layer 207 includes silicon germanium, and the semiconductor layer 204 includes silicon. The thickness of the semiconductor layer 207 is greater than any of the silicon layer and the silicon germanium layer of the Si / SiGe stack 205. The semiconductor layer extends substantially from the top surface to the bottom surface of the isolation feature 230. In addition, a semiconductor layer 402 (such as boron-doped silicon) is formed below the source feature 260 and substantially extends to the source feature 260. Therefore, the selective etching of the semiconductor layer 207 and the selective etching of the semiconductor layer 239 form a trench 380 that is self-aligned with the source feature 260, and the corresponding backside source contact feature 384 is self-aligned with the source feature 260.

[0091] According to some embodiments, a device 500 and a method 100 of manufacturing the same are collectively described below.

[0092] like Fig.26 As shown, in the device 500 , the semiconductor layer 207 is removed. In the depicted embodiment, the substrate 201 includes a carrier 202 , an insulator 203 , and a semiconductor layer 204 .

[0093] At operation 114, method 100 ( Figure 1A ) A semiconductor layer 502 is formed in the source trench 250. According to an embodiment, the resulting structure is Figure 33A-Figure 33E Shown in. Fig.33A 5 shows a top view of the device 500, Fig.33B , Fig.33C , Fig.33D and Fig.33E Parts along the Fig.33A A cross-sectional view of device 500 along lines BB, CC, DD, and EE in FIG.

[0094] The semiconductor layer 502 may be deposited using an epitaxial growth process or by other suitable processes. In some embodiments, epitaxial growth of the semiconductor layer 402 is achieved by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process, a metal organic chemical vapor deposition (MOCVD) process, other suitable epitaxial growth processes, or a combination thereof. The semiconductor layer 502 includes a semiconductor material different from the semiconductor material included in the semiconductor layer 207, thereby obtaining etching selectivity during subsequent processing. For example, the semiconductor layers 402 and 207 (or the additional semiconductor layer 204) may include different materials, different composition atomic percentages, different composition weight percentages, and / or other features to obtain the desired etching selectivity during the etching process. In an embodiment, for both nFET and pFET, the semiconductor layer 207 includes doped silicon germanium, and the semiconductor layer 502 includes undoped silicon germanium. The semiconductor layer 502 includes SiGe to enhance the etching selectivity during the etching process of etching silicon. In some embodiments, the germanium concentration of the semiconductor layer 502 ranges between 15% and 30% (atomic percentage). Undoped silicon germanium is used in semiconductor layer 502 so it can be applied to both nFET and pFET regions. Undoped silicon germanium can be formed by epitaxial growth and in-situ doping. Precursors for epitaxial growth include silicon-containing chemicals and germanium-containing chemicals. The germanium concentration of semiconductor layer 502 can be controlled by the partial pressure or flow rate of the germanium-containing gas during epitaxial growth. If semiconductor layer 502 is initially grown thicker than Fig.33B and Fig.33D If the level shown is high, operation 114 may include an etching process that recesses the semiconductor layer 502 to that level. After depositing the semiconductor layer 502, operation 114 removes the patterned hard mask layer 236 by one or more etching processes. In various embodiments, the additional etching in operation 112 and the growth of the semiconductor layer 502 in operation 114 may be performed only in the source region, only in the drain region, or in both the source region and the drain region.

[0095] At operation 132, method 100 ( Figure 1C ) selectively etches the semiconductor layer 204 to form a trench 404 over the backside of the gate stack 240' and the drain feature 260. According to an embodiment, the resulting structure is Figure 39A-Figure 39E Shown in. Fig.39A A top view of the device 500 is shown. Fig.39B , Fig.39C , Fig.39D and Fig.39E Parts along the Fig.39A. In the present embodiment, operation 132 applies an etching process that is adjusted to selectively etch the material of semiconductor layer 204 (e.g., silicon in one embodiment), without etching (or minimally etching) semiconductor layer 502 (e.g., undoped silicon in one embodiment), drain feature 260, gate stack 240' (particularly gate dielectric layer 349 and gate interface layer, if present), and isolation feature 230. It should be noted that the composition difference between semiconductor layer 502 and semiconductor layer 204 provides etching selectivity for self-alignment, and opens the drain side without opening the source side. The etching process can be dry etching, wet etching, reactive ion etching, or other etching methods. In particular, in the present embodiment, semiconductor layer 204 is etched in a self-aligned manner. In other words, operation 132 does not require the manufacture of an etching mask (e.g., an etching mask formed by a photolithography process) to etch semiconductor layer 204. Instead, it relies on the etching selectivity of materials in semiconductor layer 204 and its surrounding layers. Furthermore, the etching process includes one or more etching steps with corresponding etchants to continue etching the semiconductor layer 208 so that the gate stack 204′ is exposed within the corresponding trench 404 and the drain feature 260 is exposed within the corresponding trench 404. In particular, the semiconductor layer 260′ (boron-doped silicon in the present embodiment) of the drain feature 260 is exposed.

[0096] At operation 134, method 100 ( Figure 1C ) to form a dielectric layer 406 to fill the trench 402. For various features, including the front drain contact feature 354 and the back source contact feature 384 formed on the device 500 through operations 136-140, according to an embodiment, the resulting structure is Figure 40A-40E Shown in. Fig.40A 5 shows a top view of the device 500, Fig.40B , Fig.40C , Fig.40D and Fig.40E Parts along the Fig.40A 4. The dielectric layer 406 directly contacts the bottom surface of the gate stack 204' and the drain component 260. More specifically, the dielectric layer 406 directly contacts the semiconductor layer 260' of the drain component 260. Fig.23EAs shown, the thickness of the semiconductor layer 260' below the dielectric layer 406 is less than 3nm, such as in the range between 1nm and 2nm. In an embodiment, the dielectric layer 406 includes silicon oxide. In some embodiments, the dielectric layer 406 includes other dielectric materials, such as La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Y2O3, AlON, TaCN, ZrSi or other suitable materials. The dielectric layer 406 can have a substantially uniform thickness along each surface of the trench 404 and can be formed by CVD, PVD, ALD or other suitable methods. In some embodiments, the dielectric layer 406 may include tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), phosphosilicate glass (PSG), boro-doped silicate glass (BSG), and / or other suitable dielectric materials. Operation 134 may further perform a CMP process to planarize the back side of the device 500 and expose the semiconductor layer 502 for further processing. It should be noted that because the semiconductor layer 204 is removed and the dielectric layer 406 directly contacts the gate stack 240', the back side of the device 500 may be planarized. Fig.40B The semiconductor layer 204 is not present in the device 500 in FIG.

[0097] According to an embodiment, the structure of the device 500 is Figure 43A-43B and Figures 44A to 44C Shown in. Fig.43A 5 shows a top view of the device 500, Fig.43B Shows a portion along Fig.43A A cross-sectional view of the device 500 along line BB in FIG. Figures 44A to 44C 5 shows a perspective view of the device 500 at various stages of manufacture. Fig.43B and Fig.44B As shown, the backside source contact feature 384 is electrically connected to the backside power rail 390. Fig.43B As shown, the backside interconnect structure 392 includes metal lines 394 and via features 396 embedded in one or more dielectric layers. The metal lines 394 are distributed in one or more metal layers, and the via features 396 are configured between adjacent metal layers to provide vertical connections between corresponding metal lines in adjacent metal layers. Having a backside power rail 390 advantageously increases the number of metal tracks in the device 500 that can be used to directly connect to source / drain contact features and via features. The gate density is also increased for greater device integration than other structures without the backside power rail 390. The backside power rail 390 can have a wider dimension than the metal lines of the first metal layer (M1) on the front side of the device 500, which advantageously reduces the resistance of the backside power rail.

[0098] In the above embodiment, the SiGe semiconductor layer 207 is removed from the device 500. The self-aligned source contact feature 384 is still formed by the following steps: forming a deep trench on the source side by photolithography patterning and etching, filling the deep trench with a semiconductor material having etching selectivity, and subsequent selective etching.

[0099] The device 200 (or 400 or 500 ) and the method 100 for manufacturing the same may have other alternatives, extensions or modifications. For example, the source feature 260 may be optionally connected to the front metal line through the front contact feature, while the drain feature 260 is connected to the back metal line 390 through the back contact feature 384 .

[0100] The present invention provides a device structure having a backside contact feature 384 that is self-aligned with the source feature 260. The self-aligned source contact feature 384 is formed by steps including forming a deep trench on the source side by photolithographic patterning and etching, filling the deep trench with a semiconductor material having etching selectivity, and subsequent selective etching.

[0101] The disclosed structure reduces wiring resistance, increases alignment margin, increases layout flexibility, and improves assembly density. The disclosed structure provides more flexibility for circuit design layout and provides a larger process window for integrated circuit (IC) manufacturing, making the disclosed structure suitable for advanced technology nodes. The disclosed structure can be used in various applications that combine FinFETs to enhance performance. For example, FinFETs with multi-fin devices can be used to form static random access memory (SRAM) cells. In other examples, the disclosed structure can be incorporated into various integrated circuits, such as logic circuits, dynamic random access memories (DRAM), flash memory, or imaging sensors.

[0102] In one aspect, the present invention provides an embodiment of a method for forming an integrated circuit structure. The method includes: receiving a substrate having a front surface and a back surface, wherein the substrate includes a first semiconductor layer of a first semiconductor material, the first semiconductor material having a dielectric layer embedded below the first semiconductor layer; forming a stack of first semiconductor films and second semiconductor films interlaced with each other, the first semiconductor film and the second semiconductor film having different semiconductor materials; forming an isolation feature in the substrate and extending to the dielectric layer to define an active area surrounded by the isolation feature; forming a gate stack on the active area and spanning between a first source / drain (S / D) region and a second source / drain (S / D) region; and removing a gate from the substrate. A deep trench is formed in the first S / D region on the front side of the substrate and extends below the top surface of the isolation component; a second semiconductor layer of a second semiconductor material is filled in the deep trench, the second semiconductor material being different from the first semiconductor material; a first S / D component and a second S / D component are formed in the first S / D region and the second S / D region; the first semiconductor material under the second S / D component is selectively removed from the back side of the substrate to form a trench; the trench is filled with a dielectric material; and the second semiconductor layer is selectively removed from the back side of the substrate to form a back contact hole self-aligned with the first S / D component.

[0103] In some embodiments, the method further comprises forming a backside contact feature in the backside contact hole; and forming a frontside contact feature connected to the top surface of the second source / drain feature. In some embodiments, the method further comprises forming a frontside interconnect structure on the gate stack, the first source / drain feature, and the second source / drain feature from the front side, wherein the frontside interconnect structure is connected to the second source / drain feature through the frontside contact feature; and forming a backside interconnect structure on the back side of the substrate, wherein the backside interconnect structure is connected to the first source / drain feature through the backside contact feature. In some embodiments, the second semiconductor layer is an undoped silicon layer. In some embodiments, the substrate further comprises a silicon germanium layer disposed above the dielectric layer, and selectively removing the first semiconductor material comprises performing an etching process that selectively removes silicon germanium. In some embodiments, the second semiconductor layer is an undoped silicon germanium layer. In some embodiments, the second semiconductor layer is a silicon layer doped with boron. In some embodiments, the method further comprises performing another etching of the isolation feature in the deep trench before the second semiconductor layer of the second semiconductor material is filled in the deep trench. In some embodiments, selectively removing the first semiconductor material below the second source / drain region from the back side of the substrate comprises selectively etching such that a bottom surface of the second source / drain feature is exposed. In some embodiments, selectively removing the first semiconductor material comprises selectively etching the first semiconductor material such that the gate stack is exposed.

[0104] In another aspect, the present invention provides an embodiment of a method for forming an integrated circuit structure. The method includes: receiving a substrate having a front surface and a back surface, wherein the substrate includes a dielectric layer embedded therein, a first semiconductor layer of a first semiconductor material covering the dielectric layer, and a stack of a first semiconductor film and a second semiconductor film above the first substrate, the first semiconductor film and the second semiconductor film having different semiconductor materials and being alternately stacked; forming an isolation feature in the substrate and extending to the dielectric layer to define an active area surrounded by the isolation feature; forming a gate stack on the active area and spanning between a first source / drain (S / D) feature and a second source / drain (S / D) feature; / D) components; forming a deep trench in the first S / D region from the front side of the substrate and extending through the first semiconductor layer; filling a second semiconductor layer of a second semiconductor material in the deep trench, the second semiconductor material being different from the first semiconductor material; selectively removing the first semiconductor material under the second S / D component from the back side of the substrate to form a trench; filling the trench with a dielectric material; selectively removing the second semiconductor layer from the back side of the substrate to form a back contact hole self-aligned with the first S / D component; and forming a back contact component in the back contact hole.

[0105] In some embodiments, the method further comprises forming a front side contact feature connected to a top surface of the second source / drain feature. In some embodiments, the method further comprises forming a front side interconnect structure on the gate stack, the first source / drain feature, and the second source / drain feature from the front side, wherein the front side interconnect structure is connected to the second source / drain feature through the front side contact feature; and forming a back side interconnect structure on the back side of the substrate, wherein the back side interconnect structure is connected to the first source / drain feature through the back side contact feature. In some embodiments, the first semiconductor layer is a silicon germanium layer; and the second semiconductor layer is an undoped silicon layer. In some embodiments, the selectively removing the first semiconductor material comprises performing an etching process that selectively removes silicon germanium. In some embodiments, the method further comprises: bonding a carrier to the front side of the substrate; and thinning the substrate from the back side so that the isolation feature is exposed. In some embodiments, selectively removing the first semiconductor material below the second source / drain region from the back side of the substrate includes selectively etching so that a bottom surface of the second S / D component is exposed; and the selectively removing the first semiconductor material includes selectively etching the first semiconductor material so that the gate stack is exposed.

[0106] On the other hand, the present invention provides a semiconductor structure, which includes a substrate having a front side and a back side; an active area protruding from the substrate and surrounded by an isolation part; a gate stack formed on the front side of the substrate and arranged on the active area; a first source / drain (S / D) part and a second source / drain (S / D) part formed on the active area and inserted by the gate stack; a front side contact part arranged on the top surface of the first S / D part; a back side contact part arranged on the bottom surface of the second S / D part and electrically connected to the bottom surface of the second S / D part; and a semiconductor layer arranged on the bottom surface of the first S / D part having a first thickness and the bottom surface of the gate stack having a second thickness, wherein the second thickness is greater than the first thickness.

[0107] In some embodiments, the backside contact feature is surrounded by the isolation feature and directly contacts the isolation feature. In some embodiments, the semiconductor structure further comprises a plurality of channels vertically stacked and formed in the active region; an internal spacer interposed between the gate stack and one of the first source / drain feature and the second source / drain feature; and the backside contact feature laterally contacts the semiconductor layer, the internal spacer, and the isolation feature.

[0108] The features of several embodiments are summarized above. Those skilled in the art will appreciate that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present invention, and that various modifications, substitutions, and changes may be made thereto without departing from the spirit and scope of the present invention.

Claims

1. A method for forming an integrated circuit structure, comprising: receiving a substrate having a front surface and a back surface, wherein the substrate comprises a first semiconductor layer of a first semiconductor material and a dielectric layer embedded below the first semiconductor layer; forming a stack of first semiconductor films and second semiconductor films interlaced with each other, the first semiconductor films and the second semiconductor films having different semiconductor materials; forming isolation features in the substrate and extending to the dielectric layer to define an active area surrounded by the isolation features; forming a gate stack on the active region that spans between the first source / drain region and the second source / drain region; forming a deep trench extending below a top surface of the isolation feature in the first source / drain region from a front side of the substrate; A second semiconductor layer filled with a second semiconductor material in the deep trench, wherein the second semiconductor material is different from the first semiconductor material; forming a first source / drain feature and a second source / drain feature in the first source / drain region and the second source / drain region; selectively removing the first semiconductor material beneath the second source / drain feature from a back side of the substrate to form a trench; filling the trench with a dielectric material; and The second semiconductor layer is selectively removed from the back side of the substrate to form a back side contact hole self-aligned with the first source / drain features.

2. The method according to claim 1, further comprising forming a backside contact feature in the backside contact hole; and A front side contact feature connected to a top surface of the second source / drain feature is formed.

3. The method according to claim 2, further comprising A front side interconnect structure is formed from the front side on the gate stack, the first source / drain feature, and the second source / drain feature, wherein: the front side interconnect structure is connected to the second source / drain feature through the front side contact feature; as well as A backside interconnect structure is formed on the backside of the substrate, wherein the backside interconnect structure is connected to the first source / drain feature through the backside contact feature.

4. The method according to claim 1, wherein: The second semiconductor layer is an undoped silicon layer.

5. The method according to claim 1, wherein: The substrate further includes a silicon germanium layer disposed above the dielectric layer, Selectively removing the first semiconductor material includes performing an etching process that selectively removes silicon germanium.

6. The method according to claim 1, wherein: The second semiconductor layer is an undoped silicon germanium layer.

7. The method according to claim 1, wherein: The second semiconductor layer is a silicon layer doped with boron. 8 . The method of claim 1 , further comprising, before filling the second semiconductor layer of the second semiconductor material in the deep trench, performing another etching on the isolation feature in the deep trench.

9. The method according to claim 1, wherein: Selectively removing the first semiconductor material beneath the second source / drain region from the back side of the substrate includes selectively etching such that a bottom surface of the second source / drain feature is exposed.

10. The method according to claim 1, wherein: The selectively removing the first semiconductor material includes selectively etching the first semiconductor material such that the gate stack is exposed.

11. A method of forming an integrated circuit structure, comprising: receiving a substrate having a front surface and a back surface, wherein the substrate includes a dielectric layer embedded therein, a first semiconductor layer of a first semiconductor material covering the dielectric layer, and a stack of a first semiconductor film and a second semiconductor film over the first semiconductor layer, the first semiconductor film and the second semiconductor film having different semiconductor materials and being alternately stacked; forming isolation features in the substrate and extending to the dielectric layer to define an active area surrounded by the isolation features; forming a gate stack on the active region spanning between the first source / drain feature and the second source / drain feature; forming a deep trench in the first source / drain region from the front side of the substrate and extending through the first semiconductor layer; A second semiconductor layer filled with a second semiconductor material in the deep trench, wherein the second semiconductor material is different from the first semiconductor material; selectively removing the first semiconductor material beneath the second source / drain feature from a back side of the substrate to form a trench; filling the trench with a dielectric material; selectively removing the second semiconductor layer from the back side of the substrate to form a backside contact hole self-aligned with the first source / drain feature; and A backside contact feature is formed in the backside contact hole. 12 . The method of claim 11 , further comprising forming a front side contact feature connected to a top surface of the second source / drain feature.

13. The method according to claim 12, further comprising A front side interconnect structure is formed from the front side on the gate stack, the first source / drain feature, and the second source / drain feature, wherein: the front side interconnect structure is connected to the second source / drain feature through the front side contact feature; as well as A backside interconnect structure is formed on the backside of the substrate, wherein the backside interconnect structure is connected to the first source / drain feature through the backside contact feature.

14. The method according to claim 11, wherein: The first semiconductor layer is a silicon germanium layer; and The second semiconductor layer is an undoped silicon layer.

15. The method according to claim 11, wherein: The selectively removing the first semiconductor material includes performing an etching process that selectively removes silicon germanium.

16. The method according to claim 11, further comprising: bonding a carrier to the front side of the substrate; as well as The substrate is thinned from the back side such that the isolation features are exposed.

17. The method according to claim 11, wherein: Selectively removing the first semiconductor material below the second source / drain region from the back side of the substrate includes selectively etching such that a bottom surface of the second source / drain feature is exposed; and The selectively removing the first semiconductor material includes selectively etching the first semiconductor material such that the gate stack is exposed.

18. A semiconductor structure comprising: a substrate having a front side and a back side; an active region protruding from the substrate and surrounded by isolation features; a gate stack formed on the front side of the substrate and disposed on the active area; a first source / drain feature and a second source / drain feature formed on the active region and interposed by the gate stack; a front contact component disposed on a top surface of the first source / drain component; a backside contact feature disposed on and electrically connected to a bottom surface of the second source / drain feature; a first semiconductor layer having a first thickness disposed on a bottom surface of the first source / drain feature, and a second semiconductor layer having a second thickness disposed on a bottom surface of the gate stack, the second thickness being greater than the first thickness; as well as A dielectric layer is disposed below the first semiconductor layer and the second semiconductor layer and directly contacts the first semiconductor layer and the second semiconductor layer.

19. The semiconductor structure according to claim 18, wherein: The back contact component is surrounded by the isolation component and directly contacts the isolation component.

20. The semiconductor structure of claim 18, further comprising a plurality of channels vertically stacked and formed in the active region; an internal spacer interposed between the gate stack and one of the first source / drain feature and the second source / drain feature; as well as The backside contact feature laterally contacts the second semiconductor layer, the inner spacer, and the isolation feature.

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