Integrated Chip and Method for Forming the Same

Abstract

An integrated chip includes a field plate overlying an isolation structure. A gate electrode overlies a substrate between a source region and a drain region. An etch stop layer laterally extends from an upper surface of the gate electrode to a front side of the substrate. The etch stop layer overlies a drift region disposed between the source region and the drain region. The field plate is disposed within a first interlayer dielectric (ILD) layer overlying the substrate. The field plate extends from a top surface of the first ILD layer to an upper surface of the etch stop layer. The isolation structure is disposed within the substrate and extends from the front side of the substrate to a point located below the front side of the substrate. The isolation structure is laterally disposed between the gate electrode and the drain region.

Description

Technical Field

[0001] Embodiments of the present invention relate to an integrated chip and a method of forming the same. Background Art

[0002] Current integrated chips (ICs) include millions or billions of semiconductor devices formed on a semiconductor substrate (e.g., silicon). Depending on the application of the integrated chip (IC), many different types of transistor devices may be used. In recent years, the increasing market for cellular devices and radio frequency (RF) devices has led to a significant increase in the use of high voltage transistor devices. For example, since high voltage transistor devices can handle high breakdown voltages (e.g., greater than about 50 volts (V)) and high frequencies, they are often used in power amplifiers in RF transmit / receive chains. Summary of the Invention

[0003] An integrated chip according to embodiments of the present invention includes: a gate electrode overlying a substrate between a source region and a drain region; an etch stop layer laterally extending from an upper surface of the gate electrode to a front side of the substrate, wherein the etch stop layer overlies a drift region disposed between the source region and the drain region; a field plate disposed within a first interlayer dielectric (ILD) layer overlying the substrate, wherein the field plate extends from a top surface of the first ILD layer to an upper surface of the etch stop layer; and an isolation structure disposed within the substrate and extending from the front side of the substrate to a point below the front side of the substrate, wherein the isolation structure is laterally disposed between the gate electrode and the drain region, and wherein the field plate overlies the isolation structure.

[0004] An integrated chip according to an embodiment of the present invention includes: a first laterally diffused metal oxide semiconductor field effect transistor (MOSFET) (LDMOS) device, including a first gate structure overlying a substrate, wherein the first LDMOS device further includes a first source region and a first drift region disposed in the substrate; a second LDMOS device, including a second gate structure, a second source region, and a second drift region; a drain region disposed between the first LDMOS device and the second LDMOS device, wherein the first drift region is disposed between the first source region and the drain region, and wherein the second drift region is disposed between the second source region and the drain region; a first field plate laterally spaced between the drain region and the first gate structure; and a first isolation structure disposed in the substrate, wherein the first isolation structure is laterally spaced between the drain region and the first source region, wherein a first edge of the first field plate directly overlies the first isolation structure, and in a direction toward the first gate structure, a second edge of the first field plate is laterally offset from the first isolation structure by a non-zero distance.

[0005] A method of forming an integrated chip according to an embodiment of the present invention includes: forming an isolation structure in a substrate, wherein the isolation structure includes a dielectric material and the substrate includes a substrate material different from the dielectric material; performing an implantation process to form a drift region in the substrate, wherein the drift region abuts the isolation structure; forming a gate structure over the substrate, wherein the gate structure at least partially overlies the drift region; performing an implantation process to form a source region and a drain region in the substrate, wherein the drift region is laterally disposed between the source region and the drain region; forming a first interlayer dielectric (ILD) layer over the substrate; and forming a field plate over the drift region and within the ILD layer, wherein at least a portion of the field plate directly overlies the isolation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure are best understood when read in conjunction with the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A cross-sectional view showing some embodiments of a high voltage transistor device having a field plate overlying a buried isolation structure.

[0008] Figure 2 Shows Figure 1 A cross-sectional view of some alternative embodiments of the high voltage transistor shown.

[0009] Figures 3A to 3F Cross-sectional views showing various alternative embodiments of an integrated chip including a high-voltage laterally diffused metal-oxide semiconductor field-effect transistor (LDMOS) device, the high-voltage LDMOS device having a field plate overlying a buried isolation structure.

[0010] Figures 4 to 11 Cross-sectional views showing some embodiments of a method of forming an integrated chip including a high-voltage LDMOS device, the high-voltage LDMOS device having a field plate located above a buried isolation structure.

[0011] Figure 12 A method is shown in flowchart form, the flowchart showing some embodiments of a method of forming a high-voltage LDMOS device having a field plate located above a buried isolation structure. DETAILED DESCRIPTION

[0012] The present disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of illustration, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0014] High-voltage transistor devices are often configured to have field plates. A field plate is a conductive element that is placed over the drift region of a high-voltage transistor device to enhance device performance by manipulating the electric field generated by a gate electrode (e.g., reducing the peak electric field). By manipulating the electric field generated by the gate electrode, a high-voltage transistor device can achieve a higher breakdown voltage. For example, a laterally diffused metal oxide semiconductor (LDMOS) transistor device often includes a field plate that extends from a channel region to an adjacent drift region disposed between the channel region and a drain region.

[0015] To increase the number of high-voltage transistor devices disposed over / on a single substrate, the distance between the gate electrode and the drain region is reduced, such that the lateral distance of the drift region is decreased. Accordingly, more high-voltage transistor devices can be disposed adjacent to each other laterally over the single substrate. In addition, by reducing the lateral distance of the drift region, the resistance of the high-voltage transistor device can be decreased. However, as the lateral distance of the drift region is decreased, the electric field generated by the gate electrode may accumulate at the edge of the field plate adjacent to the drain region. This accumulation of the electric field may damage the crystal lattice of the substrate (e.g., cracks in the substrate), resulting in device failure and / or substantially increasing the resistance of the drift region. In addition, the accumulation of the electric field at the edge of the field plate may adversely affect the transfer of charge carriers (e.g., electrons) from the source region to the drain region, thereby reducing the performance of the high-voltage transistor device.

[0016] Accordingly, embodiments of the present disclosure relate to a high-voltage transistor device having a field plate located above a buried isolation structure disposed within a drift region. In some embodiments, the high-voltage transistor device has a gate electrode disposed over a substrate and between a source region and a drain region within the substrate. A contact etch stop layer (CESL) extends from a sidewall of the gate electrode into the drift region arranged between the gate electrode and the drain region. The field plate is located within a first inter-level dielectric (ILD) layer disposed over the substrate. The field plate is laterally disposed between a sidewall of the gate electrode and the drain region and extends in a vertical direction from the CESL to an upper surface of the first ILD layer. Additionally, the buried isolation structure is laterally disposed between a sidewall of the gate electrode and the drain region within the drift region. An edge of the field plate directly overlies the buried isolation structure such that the field plate is separated from the isolation structure by the CESL. During operation of the high-voltage transistor device, an electric field generated by the gate electrode may accumulate at an edge of the field plate overlying the buried isolation structure. The buried isolation structure is configured to mitigate and / or prevent damage to the substrate due to the accumulation of the electric field. Additionally, the buried isolation structure may mitigate and / or prevent the accumulated electric field from adversely affecting the transfer of charge carriers (e.g., electrons) from the source region to the drain region. Accordingly, the stability, durability, and / or performance of the high-voltage transistor device are improved while facilitating an increase in the number of high-voltage transistor devices that can be disposed above / on the substrate.

[0017] Figure 1 A cross-sectional view showing some embodiments of a high-voltage transistor device 100 having a field plate 124 located above an isolation structure 132, the isolation structure 132 being disposed within a substrate 102.

[0018] The high-voltage transistor device 100 includes a source region 104 and a drain region 106 disposed within the substrate 102. The substrate 102 has a first doping type (e.g., p-type), while the source region 104 and the drain region 106 each have a second doping type (e.g., n-type) and have a higher doping concentration than the substrate 102. In some embodiments, the first doping type may be p-type and the second doping type may be n-type, or vice versa.

[0019] The gate structure 116 is disposed over the substrate 102 at a position laterally arranged between the source region 104 and the drain region 106. The gate structure 116 includes a gate electrode 110 separated from the substrate 102 by a gate dielectric layer 108. When a bias voltage is received, the gate electrode 110 is configured to generate an electric field that controls the movement of charge carriers (e.g., electrons) within the channel region 112 that is laterally disposed between the source region 104 and the drain region 106. For example, during operation, a gate-source voltage can be selectively applied to the gate electrode 110 relative to the source region 104 to form a conductive channel in the channel region 112. While applying the gate-source voltage to form the conductive channel, a drain-to-source voltage is applied to cause the charge carriers to move between the source region 104 and the drain region 106 (e.g., as indicated by the arrow 105). The channel region 112 extends laterally from the source region 104 to an adjacent drift region 114 (or “drain extension region”). The drift region 114 includes a second doping type (e.g., n-type) having a relatively low doping concentration, which results in a higher resistance at high operating voltages. The gate structure 116 is disposed over the channel region 112. In some embodiments, the gate structure 116 can extend from over the channel region 112 to a position overlying a portion of the drift region 114.

[0020] An etch stop layer 122 is disposed over the upper surfaces of the gate structure 116 and the substrate 102. The etch stop layer 122 extends from the upper surface of the gate electrode 110 along the sidewalls of the gate electrode 110 and the sidewalls of the gate dielectric layer 108 to the upper surface of the substrate 102. A first interlayer dielectric (ILD) layer 118 is disposed over the substrate 102. One or more conductive structures are disposed within the first ILD layer 118. In some embodiments, the one or more conductive structures include a plurality of contacts 120 configured to provide vertical connections between the source region 104, the drain region 106, and / or the gate electrode 110 and a plurality of back-end-of-the-line (BEOL) conductive lines (not shown), the plurality of BEOL conductive lines being disposed over the contacts 120 and within a second ILD layer (not shown).

[0021] The one or more conductive structures may further include a field plate 124 disposed within the first ILD layer 118 at a position that is laterally between the drain region 106 and the gate electrode 110. In some embodiments, the field plate 124 includes a first field plate structure 126 and a second field plate structure 128. In other embodiments, the field plate 124 comprises a metal material different from that of the gate electrode 110. In yet other embodiments, the field plate 124 comprises the same metal material as the contact 120. The field plate 124 is disposed over the etch stop layer 122, where the etch stop layer 122 is configured to separate the field plate 124 from the drift region 114 and the gate electrode 110. In some embodiments, the field plate 124 may be configured to reduce the breakdown voltage of the high voltage transistor device 100 and / or reduce the resistance of the drift region 114.

[0022] In addition, an isolation structure 132 is disposed within the drift region 114 such that an upper surface of the isolation structure 132 is aligned with an upper surface of the substrate 102. In some embodiments, the isolation structure 132 comprises a dielectric material different from the material of the substrate 102 (e.g., silicon dioxide, silicon nitride, silicon carbide, another suitable dielectric material, or any combination of the foregoing). In some embodiments, the isolation structure 132 comprises or is a first material (e.g., silicon dioxide), and the etch stop layer 122 comprises or is a different second material (e.g., silicon carbide, silicon nitride, etc.). The field plate 124 overlies the isolation structure 132 and is separated from the isolation structure 132 by the etch stop layer 122. An edge 124e of the field plate 124 directly overlies the isolation structure 132, where the edge 124e is separated from the drain region 106 by a first distance. In some embodiments, the first distance is the shortest distance between the field plate 124 and the drain region 106. In other embodiments, a bottom surface of the second field plate structure 128 is laterally spaced between outer sidewalls of the isolation structure 132.

[0023] During operation, field plate 124 is configured to act on the electric field generated by gate electrode 110. Field plate 124 can be configured to change the distribution of the electric field generated by gate electrode 110 in drift region 114. This partially enhances the breakdown voltage capability of high-voltage transistor device 100. In some embodiments, the lateral distance Ld of drift region 114 is reduced to increase the number of high-voltage transistor devices that can be disposed within / above substrate 102. In such embodiments, as the lateral distance Ld of drift region 114 decreases, the electric field generated by gate electrode 110 can accumulate at edge 124e of field plate 124. This accumulation may be due to electrons tending to gather near the edges / corners of the outer surface of a conductor and / or because edge 124e is the portion of field plate 124 closest to drain region 106. Since isolation structure 132 comprises a dielectric material different from the material of substrate 102, the high electric field accumulated at and / or near edge 124e of field plate 124 may not have an adverse effect on isolation structure 132. Thus, the lateral distance Ld of drift region 114 can be reduced while preventing damage to the lattice of substrate 102. This partially increases the reliability and durability of high-voltage transistor device 100.

[0024] In other embodiments, during operation of high-voltage transistor device 100, current can flow along the shortest path between source region 104 and drain region 106 (e.g., as indicated by arrow 105). Since isolation structure 132 comprises a dielectric material different from the material of substrate 102, the current will travel around isolation structure 132. Thus, the current can flow around sidewall 132sw of isolation structure 132 and can flow parallel to lower surface 132ls of isolation structure 132. This in turn can increase the resistance of drift region 114. However, field plate 124 is configured to reduce the lateral distance Ld of drift region 114 such that the resistance of drift region 114 is reduced. In some embodiments, the increase in the resistance of drift region 114 caused by isolation structure 132 can be eliminated and / or mitigated by the reduction in the resistance of drift region 114 caused by field plate 124. Additionally, in some embodiments, since the current travels around isolation structure 132, the accumulation of electric field at edge 124e of field plate 124 may not have an adverse effect on the path (e.g., as indicated by arrow 105) and / or flow of current between source region 104 and drain region 106. This in turn can further increase the breakdown voltage of high-voltage transistor device 100.

[0025] Figure 2 A cross-sectional view showing some additional embodiments of a high-voltage transistor device including a high-voltage laterally diffused MOSFET (LDMOS) device 200 having a field plate 124 disposed over an isolation structure 132.

[0026] The LDMOS device 200 includes a source region 104 and a drain region 106 disposed within a substrate 102. In some embodiments, the substrate 102 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or some other suitable substrate. The substrate 102 has a first doping type (e.g., p-type), while the source region 104 and the drain region 106 each include a highly doped region having a second doping type (e.g., n-type) different from the first doping type. In some embodiments, the first doping type may be p-type and the second doping type may be n-type, or vice versa. In some embodiments, the source region 104 and / or the drain region 106 may each have a doping concentration of about 2.5*10 17 atoms per cubic centimeter (atoms / cm 3 )、2.88*10 17 atoms / cm 3 、5.5*10 17 atoms / cm 3 、between about 10 17 atoms / cm 3 and 10 19 atoms / cm 3 、greater than about 10 19 atoms / cm 3 , or some other suitable doping concentration. In some embodiments, the p-type dopant of the first doping type may be or may include, for example, boron, boron difluoride (e.g., BF2), indium, some other suitable p-type dopants, or any combination of the foregoing. In various embodiments, the n-type dopant of the second doping type may be or may include, for example, phosphorus, arsenic, antimony, some other suitable n-type dopants, or any combination of the foregoing.

[0027] The drain region 106 is arranged adjacent to a drift region 114 within the substrate 102. The drift region 114 includes a second doping type (e.g., n-type) having a relatively low doping concentration, which provides a high resistance when the LDMOS device 200 operates at a high voltage. In some embodiments, the drift region 114 may have a doping concentration of about 2.0*10 14 atoms / cm 3 、2.5*10 14 atoms / cm 3 、3.0*10 14 atoms / cm 3 、5.7*10 14 atoms / cm 3 or between about 10 18 atoms / cm 3 and 10 20 atoms / cm 3The doping concentration within a range. In addition, a shallow trench isolation (STI) structure 202 extends from the top surface of the substrate 102 to a point located below the top surface of the substrate 102. The drain region 106 may abut against the STI structure 202. The STI structure 202 is configured to electrically isolate the LDMOS device 200 from adjacent semiconductor devices (not shown). In some embodiments, the STI structure 202 comprises a dielectric material different from the semiconductor substrate material of the substrate 102. In other embodiments, the dielectric material may be or may include, for example, silicon dioxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, another suitable dielectric material, or any combination of the above. In still other embodiments, the semiconductor substrate material may be or may include, for example, silicon, single crystal silicon, or some other suitable semiconductor substrate material.

[0028] The gate structure 116 is disposed above the substrate 102 at a position laterally arranged between the source region 104 and the drain region 106. In some embodiments, the gate structure 116 may laterally extend from above the channel region 112 to a position covering a portion of the drift region 114. The gate structure 116 includes a gate electrode 110 separated from the substrate 102 by a gate dielectric layer 108. In some embodiments, the gate dielectric layer 108 may be or may comprise, for example, silicon dioxide, a high dielectric constant (high-k) dielectric material, etc. As used herein, a high dielectric constant dielectric material is a dielectric material having a dielectric constant greater than 3.9. In some embodiments, the gate electrode 110 comprises polysilicon and / or a metal gate material (e.g., tungsten, titanium, tantalum, and / or aluminum).

[0029] The etch stop layer 122 extends along the upper surface of the gate electrode 110, the sidewalls of the gate electrode 110, the sidewalls of the gate dielectric layer 108, and the top surface of the substrate 102. In some embodiments, the etch stop layer 122 continuously extends from the gate electrode 110 above the drift region 114 to a point beyond the sidewalls of the field plate 124. In other embodiments, the etch stop layer 122 may be or may comprise, for example, silicon nitride, silicon carbide, another suitable material, etc. In addition, a first interlayer dielectric (ILD) layer 118 covers the substrate 102 and the gate structure 116. A plurality of contacts 120 cover the substrate 102 and extend through the first ILD layer 118. In some embodiments, the first ILD layer 118 may be or may comprise, for example, silicon dioxide, a low dielectric constant dielectric material, an extremely low dielectric constant dielectric material, another suitable dielectric material, or any combination of the above. In other embodiments, the plurality of contacts 120 may be or may comprise, for example, aluminum, copper, tungsten, titanium, another suitable conductive material, or any combination of the above.

[0030] The field plate 124 extends in a vertical direction from the etch stop layer 122 to the top surface of the first ILD layer 118. In some embodiments, the top surface of the field plate 124 is aligned with the top surfaces of the plurality of contacts 120. In other embodiments, the field plate 124 may include a first field plate structure 126 and a second field plate structure 128. In some embodiments, the first field plate structure 126 and the second field plate structure 128 may be or may include the same material and / or be laterally spaced from each other by a non-zero distance. The first field plate structure 126 may directly contact the sidewall of the etch stop layer 122. The sidewalls of the field plate 124 are surrounded by the first ILD layer 118. In some embodiments, the field plate 124 may include the same material as the contacts 120. In various embodiments, the first field plate structure 126 and / or the second field plate structure 128 may be or may include, for example, aluminum, copper, tungsten, titanium, another suitable conductive material, or any combination of the foregoing.

[0031] The isolation structure 132 is disposed under the field plate 124 and within the drift region 114. The isolation structure 132 may be or may include a dielectric material different from the semiconductor substrate material of the substrate 102. In some embodiments, the isolation structure 132 includes the same dielectric material as the STI structure 202. In other embodiments, the dielectric material may be or may include, for example, silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, some other suitable dielectric material, or any combination of the foregoing. The isolation structure 132 is directly located under the second field plate structure 128 such that the isolation structure 132 is separated from the second field plate structure 128 by the etch stop layer 122. In some embodiments, the outer sidewalls of the isolation structure 132 laterally extend beyond the outer sidewalls of the etch stop layer 122. The isolation structure 132 is configured to prevent and / or mitigate damage to the substrate 102 due to the buildup of an electric field at the edges of the field plate 124. In other embodiments, the outer sidewalls of the isolation structure 132 are inclined.

[0032] Figure 3A A cross-sectional view showing some embodiments of an integrated chip 300a including a first laterally diffused metal oxide semiconductor field effect transistor (MOSFET) (LDMOS) device 316 and a second LDMOS device 318, each having a field plate 124 overlying the isolation structure 132.

[0033] The first LDMOS device 316 and the second LDMOS device 318 are disposed adjacent to each other laterally and share a drain region 106. In addition, each of the first LDMOS device 316 and the second LDMOS device 318 includes a gate structure 116 and a sidewall spacer structure 314 that laterally surrounds the sidewalls of the gate structure 116. In some embodiments, the sidewall spacer structure 314 may be or may include, for example, silicon nitride, silicon carbide, another suitable material, or any combination of the foregoing. The gate structure 116 includes a gate electrode 110 overlying a gate dielectric layer 108, and the gate dielectric layer 108 overlies a substrate 102. An etch stop layer 122 extends from the upper surface of the gate electrode 110 along the sidewalls of the sidewall spacer structure 314 to the upper surface of the substrate 102. In some embodiments, the substrate 102 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or some other suitable substrate and / or may include a first doping type (e.g., p-type). A contact region 308 is disposed within the substrate 102 and abuts a source region 104. The drain region 106 and the source region 104 each include a second doping type (e.g., n-type) opposite to the first doping type. In addition, the contact region 308 includes a first doping type (e.g., p-type), which provides an ohmic connection between the substrate 102 and an overlying contact 120.

[0034] In some embodiments, the contact region 308 may have a p-type doping concentration of approximately 10 19 atoms / cm 3 or greater than 10 19 atoms / cm 3 . The contact region 308 is disposed within a body region 306. The body region 306 has a first doping type (e.g., p-type) with a doping concentration higher than that of the substrate 102. For example, the substrate 102 may have a doping concentration in the range of between about 10 14 atoms / cm 3 to 10 16 atoms / cm 3 , while the body region 306 may have a doping concentration in the range of between approximately 10 16 atoms / cm 3 to 10 18 atoms / cm 3 . In other embodiments, the source region 104 is disposed within a shallow trench region 310, and the shallow trench region 310 may include a first doping type (e.g., p-type) and / or may have a doping concentration in the range of between about 10 16 atoms / cm 3 to 10 19 atoms / cm 3The doping concentration within a range. The shallow well region 310 abuts the source region 104 and / or the drift region 114. In some embodiments, the shallow well region 310 may be configured as a channel region, where when appropriate bias conditions are applied to the gate electrode 110, the source region 104, and / or the drain region 106, a conductive channel is formed between the source region 104 and the drift region 114.

[0035] The drift region 114 is laterally disposed between the source region 104 and the drain region 106. The drift region 114 may include a second doping type (e.g., n-type) and / or may have a doping concentration between about 10 18 atoms / cm 3 and 10 20 atoms / cm 3 within a range. The drift region 114 is disposed within the high voltage well region 304. The high voltage well region 304 may include a doping concentration between about 10 14 atoms / cm 3 and 10 16 atoms / cm 3 within a range of the second doping type (e.g., n-type). In some embodiments, the drift region 114 is part of the high voltage well region 304 such that the drift region 114 is omitted (not shown) and the high voltage well region 304 is laterally disposed between the source region 104 and the drain region 106 and serves as the drift region. The shallow well region 312 is disposed around the drain region 106 and is laterally spaced between the first LDMOS device 316 and the second LDMOS device 318. The shallow well region 312 may, for example, include a second doping type (e.g., n-type) and may have a doping concentration between about 10 14 atoms / cm 3 and 10 16 atoms / cm 3 within a range or another suitable doping concentration. In some embodiments, the drift region 114 extends continuously from the shallow well region 310 to the drain region 106 laterally such that the drift region 114 abuts the drain region 106 (not shown).

[0036] The deep well region 302 including a first doping type (e.g., p-type) is disposed within the substrate 102 and is directly disposed below the high voltage well region 304. In some embodiments, the deep well region 302 may, for example, have a doping concentration between about 10 14 atoms / cm 3 and 10 16 atoms / cm 3A doping concentration within a range or another suitable doping concentration. The deep well region 302 can be configured to enhance the formation of a depletion region within the high voltage well region 304 and / or the drift region 114, thereby reducing the magnitude of the electric field on the surface of the substrate 102. This partly helps to apply a high voltage to the first LDMOS device 316 and / or the second LDMOS device 318. The isolation structure 132 is disposed within the substrate 102 and abuts the drift region 114 and the shallow well region 312. In some embodiments, the isolation structure 132 abuts the high voltage well region 304 (not shown). The isolation structure 132 comprises a material different from the substrate 102 and is laterally disposed between the drain region 106 and the source region 104.

[0037] In addition, a first interlayer dielectric (ILD) layer 118 is disposed over the top surface of the substrate 102. A plurality of contacts 120 are disposed within the first ILD layer 118 and overlie the doped regions of the substrate 102 and / or overlie the conductive structures disposed over the top surface of the substrate 102. In some embodiments, a silicide layer (not shown) is disposed between the contacts 120 and the doped regions of the substrate 102 directly beneath the contacts 120, such that the silicide layer is configured to increase the electrical connection between the contacts 120 and the doped regions of the substrate 102. The field plate 124 includes a first field plate structure 126 that extends continuously from the top surface of the first ILD layer 118 to the top surface of the etch stop layer 122. In some embodiments, the first lower edge of the first field plate structure 126 directly overlies the isolation structure 132, and the second lower edge of the first field plate structure 126 is opposite the first lower edge and is laterally offset from the isolation structure 132 by a non-zero distance. In other embodiments, the first lower edge of the first field plate structure 126 is spaced apart from the drain region 106 by a distance such that the distance is the shortest distance between the field plate 124 and the drain region 106.

[0038] Figure 3B Shown in accordance with Figure 3A A cross-sectional view of an integrated chip 300b showing some alternative embodiments of the integrated chip 300a shown.

[0039] In some embodiments, the field plate 124 includes a first field plate structure 126 and a second field plate structure 128. In some embodiments, the second field plate structure 128 is laterally spaced between the outer sidewalls of the isolation structure 132. In other embodiments, the first edge of the first field plate structure 126 overlies the isolation structure 132 and the second edge of the first field plate structure 126 is laterally offset from the isolation structure 132 by a non-zero distance.

[0040] Figure 3C Shown in accordance with Figure 3A A cross-sectional view of an integrated chip 300c showing some alternative embodiments of the integrated chip 300a shown.

[0041] The shallow trench isolation (STI) structure 202 extends from the upper surface of the substrate 102 to a first point located below the upper surface of the substrate 102. In some embodiments, the STI structure 202 comprises the same material as the isolation structure 132. In other embodiments, the isolation structure 132 extends from the upper surface of the substrate 102 to a second point located below the upper surface of the substrate 102, wherein the first point is vertically below the second point. The STI structure 202 is configured to electrically isolate the first LDMOS device 316 and / or the second LDMOS device 318 from other semiconductor devices disposed above and / or within the substrate 102.

[0042] Figure 3D Shows according to Figure 3A A cross-sectional view of an integrated chip 300d showing some alternative embodiments of the integrated chip 300a shown.

[0043] The contacts 120 each include an internal conductor 322 surrounded by an external conductive lining 320. In some embodiments, the internal conductor 322 may be or may comprise, for example, tungsten, aluminum, copper, another suitable conductive material, or any combination of the foregoing. In other embodiments, the external conductive lining 320 may be or may comprise, for example, titanium, tantalum, titanium nitride, tantalum nitride, another suitable conductive material, or any combination of the foregoing. In various embodiments, the first field plate structure 126 of the field plate 124 may be configured as the contact 120 such that the first field plate structure 126 includes the internal conductor 322 and the external conductive lining 320. In still other embodiments, if the field plate 124 includes a second field plate structure (e.g., Figure 3B The second field plate structure 128 shown) (not shown), then the second field plate structure may include the internal conductor 322 and the external conductive lining 320.

[0044] Figure 3E Shows according to Figure 3A A cross-sectional view of an integrated chip 300e showing some alternative embodiments of the integrated chip 300a shown.

[0045] In some embodiments, the lower surface 132ls of the isolation structure 132 is vertically disposed below the drain region 106, the source region 104, and / or the contact region 308. In various embodiments, this can increase the resistance of the first LDMOS device 316 and / or the second LDMOS device 318 while further reducing the adverse effects caused by the accumulation of the electric field at the edges of the field plate 124 on the substrate 102.

[0046] Figure 3F Shows according to Figure 3A A cross-sectional view of an integrated chip 300f showing some alternative embodiments of the integrated chip 300a shown.

[0047] In some embodiments, a plurality of conductive lines 324 (e.g., comprising aluminum, copper, tungsten, titanium, tantalum, etc.) are disposed over the contact 120. The second ILD layer 321 is disposed over the first ILD layer 118, and the third ILD layer 323 is disposed over the second ILD layer 321. In some embodiments, the conductive lines 324 disposed over the contact 120 that is directly electrically coupled to the contact region 308, the source region 104, the drain region 106, and the field plate 124 are disposed within the second ILD layer 321. In other embodiments, the conductive lines 324 disposed over the contact 120 that is directly electrically coupled to the gate electrode 110 are disposed within the third ILD layer 323 and are offset a non-zero distance in a vertical direction from the second ILD layer 321. Thus, the top surface of each contact 120 (e.g., the contacts 120 disposed over the source region 104, the drain region 106, and / or the contact region 308, respectively) and the top surface of the field plate 124 are disposed within a first layer that is disposed along a first substantially straight horizontal line, wherein the top surface of each contact 120 (e.g., the contact 120 disposed over the gate electrode 110) disposed within a second layer is disposed along a second substantially straight horizontal line that is offset in a vertical direction from the first substantially straight horizontal line.

[0048] Figures 4 to 11 Cross-sectional views 400 to 1100 showing some embodiments of a method of forming an integrated chip including a high voltage LDMOS device having a field plate disposed over a buried isolation structure. Although described with reference to a method Figures 4 to 11 for the cross-sectional views 400 to 1100 shown, it should be understood that Figures 4 to 11 the structures shown are not limited to the method, but may be separate and independent of the method. Although Figures 4 to 11 described as a series of acts, it should be understood that these acts are not restrictive, the order of the acts may be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some of the acts shown and / or described may be omitted, in whole or in part.

[0049] As Figure 4As shown in the cross-sectional view 400, a substrate 102 is provided and an isolation structure 132 is formed on the front side 102f of the substrate 102. In some embodiments, the substrate 102 can be, for example, a semiconductor substrate material (e.g., silicon), a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or some other suitable substrate. In some embodiments, before forming the isolation structure 132, an implantation process is performed to dope the substrate 102 with a first doping type (e.g., p-type). In some embodiments, the process of forming the isolation structure 132 can include: forming a masking layer (not shown) over the front side 102f of the substrate; selectively etching the substrate 102 according to the masking layer to form an opening that extends from the front side 102f to a point located below the front side 102f; filling the opening with a dielectric material (e.g., by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, etc.); and performing a removal process to remove the masking layer. In some embodiments, after filling the opening with the dielectric material, a planarization process (e.g., a chemical mechanical planarization (CMP) process) can be performed on the dielectric material, thereby defining the isolation structure 132. In various embodiments, a planarization process can be performed on the dielectric material such that the planarization process continues after reaching the front side 102f of the substrate, thereby removing at least a small portion of the substrate 102. In still other embodiments, a planarization process can be performed on the dielectric material until reaching the front side 102f of the substrate 102. In some embodiments, the dielectric material is different from the semiconductor substrate material. In other embodiments, the dielectric material can be or can include, for example, silicon dioxide, silicon nitride, silicon carbide, some other suitable dielectric material, or any combination of the above. In still other embodiments, a shallow trench isolation (STI) structure (e.g., Figure 3C the shallow trench isolation structure 202 shown) (not shown) can be formed on the front side 102f of the substrate 102. In some embodiments, the STI structure can be formed simultaneously with the isolation structure 132 and / or include a dielectric material. In some embodiments, the p-type dopant of the first doping type can be or can include, for example, boron, diboron fluoride (e.g., BF2), indium, some other suitable p-type dopant, or any combination of the above.

[0050] As Figure 5As shown in the cross-sectional view 500, one or more implantation processes may be performed on the substrate 102 to form one or more doped regions within the substrate 102. In some embodiments, the one or more implantation processes may be performed to form a deep well region 302, a high voltage well region 304, a body region 306, a drift region 114, and / or a shallow well region 312. In some embodiments, the deep well region 302, the high voltage well region 304, the shallow well region 312, and / or the drift region 114 may each include a second doping type opposite to the first doping type (e.g., n-type). In some embodiments, the first doping type is p-type and the second doping type is n-type, or vice versa. In still other embodiments, the deep well region 302 and / or the body region 306 may each include the first doping type (e.g., p-type). In some embodiments, each of the one or more implantation processes may include: forming a masking layer (not shown) over the front side 102f of the substrate 102; selectively implanting dopants into the substrate 102 according to the masking layer; and performing a removal process to remove the masking layer. In some embodiments, the n-type dopant of the second doping type may be or may include, for example, phosphorus, arsenic, antimony, some other suitable n-type dopant, or any combination of the foregoing.

[0051] In some embodiments, the drift region 114 and / or the high voltage well region 304 may each have about 2.0*10 14 atoms / cm 3 、2.5*10 14 atoms / cm 3 、3.0*10 14 atoms / cm 3 、5.7*10 14 atoms / cm 3 or a doping concentration in the range of about 10 14 atoms / cm 3 to 10 15 atoms / cm 3 or some other suitable doping concentration. In some embodiments, the deep well region 302 may have about 1.5*10 14 atoms / cm 3 、1.0*10 15 atoms / cm 3 、a doping concentration in the range of about 10 14 atoms / cm 3 to 10 16 atoms / cm 3 or some other suitable doping concentration. In some embodiments, the shallow well region 312 may have about 7.0*10 14 atoms / cm 3 、1.0*10 15 atoms / cm 3 、1.12*10 15atoms / cm 3 , between about 10 14 atoms / cm 3 to 10 16 atoms / cm 3 range of doping concentration or some other suitable doping concentration. In some embodiments, the body region 306 may have about 5.0*10 14 atoms / cm 3 , 8.0*10 14 atoms / cm 3 , 1.4*10 15 atoms / cm 3 , between about 10 14 atoms / cm 3 to 10 16 atoms / cm 3 range of doping concentration or some other suitable doping concentration.

[0052] As Figure 6 shown in the cross-sectional view 600 of , a gate structure 116 is formed over the front side 102f of the substrate. In some embodiments, the gate structure 116 includes a gate dielectric layer 108 and a gate electrode 110 overlying the gate dielectric layer 108. In some embodiments, the process of forming the gate structure 116 may include: depositing a gate dielectric film over the front side 102f by, for example, CVD, PVD, ALD, or another suitable deposition process; depositing a gate electrode layer over the gate dielectric film by, for example, CVD, PVD, ALD, sputtering, or another suitable deposition or growth process; and patterning the gate dielectric film and the gate electrode layer through a masking layer (not shown) to define the gate dielectric layer 108, the gate electrode 110, and the gate structure 116. In some embodiments, the gate electrode 110 may be or may include, for example, titanium nitride, tantalum nitride, titanium, tantalum, tungsten, aluminum, copper, polysilicon, intrinsic polysilicon, doped polysilicon, another suitable conductive material, or any combination of the above. In other embodiments, the gate dielectric layer 108 may be or may include, for example, silicon dioxide, a high-k dielectric material, another suitable gate dielectric material, or any combination of the above.

[0053] As Figure 7As shown in the cross-sectional view 700, an implantation process is performed on the substrate 102 to form a shallow trench region 310 within the substrate 102. In some other embodiments, a plurality of lightly doped regions (not shown) may be formed simultaneously with the shallow trench region 310. In some embodiments, the shallow trench region 310 abuts the body region 306, the drift region 114, and / or the high-voltage well region 304. The shallow trench region 310 may include, for example, a first doping type (e.g., p-type). In some other embodiments, the implantation process includes: forming a masking layer (not shown) over the substrate 102; selectively implanting dopants into the substrate 102 according to the masking layer; and performing a removal process to remove the masking layer. In some other embodiments, the shallow trench region 310 may be configured as a channel region. In some embodiments, the shallow trench region 310 may have about 1.0*10 15 atoms / cm 3 、1.6*10 15 atoms / cm 3 、5.4*10 15 atoms / cm 3 、5.0*10 16 atoms / cm 3 、a doping concentration in the range of about 10 15 atoms / cm 3 to 10 17 atoms / cm 3 or some other suitable doping concentration.

[0054] As Figure 8 shown in the cross-sectional view 800, a sidewall spacer structure 314 is formed around the sidewalls of the gate structure 116. In some embodiments, the sidewall spacer structure 314 may be or may include, for example, silicon nitride, silicon carbide, another suitable dielectric material, or any combination of the above. In some other embodiments, the process of forming the sidewall spacer structure 314 may include: depositing (e.g., by a CVD process, a PVD process, an ALD process, or another suitable deposition process) a sidewall spacer layer over the substrate 102 and the gate structure 116; and performing a patterning process on the sidewall spacer layer to remove the sidewall spacer layer from the horizontal surface, thereby defining the sidewall spacer structure 314.

[0055] As Figure 9As shown in the cross-sectional view 900, an implantation process is performed on the substrate 102 to define a source region 104, a drain region 106, and a contact region 308 within the substrate 102. In some embodiments, the source region 104 and / or the drain region 106 may include a second doping type (e.g., n-type). In other embodiments, the contact region 308 may include a first doping type (e.g., p-type). In various embodiments, the implantation process may include: forming a masking layer (not shown) over the front side 102f of the substrate 102; selectively implanting dopants into the substrate 102 according to the masking layer; and performing a removal process to remove the masking layer. In some embodiments, the source region 104 and / or the drain region 106 may each have about 2.5*10 17 atoms / cm 3 、2.88*10 17 atoms / cm 3 、5.5*10 17 atoms / cm 3 、a doping concentration in the range of between about 10 17 atoms / cm 3 and 10 19 atoms / cm 3 、greater than about 10 19 atoms / cm 3 or some other suitable doping concentration. In some embodiments, the contact region 308 may have about 3.0*10 15 atoms / cm 3 、3.2*10 17 atoms / cm 3 、a doping concentration in the range of between about 10 15 atoms / cm 3 and 10 18 atoms / cm 3 or some other suitable doping concentration.

[0056] As Figure 10 shown in the cross-sectional view 1000, an etch stop layer 122 is formed over the gate structure 116. In some embodiments, the etch stop layer 122 extends continuously from the upper surface of the gate electrode 110 along the sidewalls of the sidewall spacer structure 314 to the front side 102f of the substrate 102. In some embodiments, the etch stop layer 122 may be or may include, for example, silicon nitride, silicon carbide, another suitable dielectric material, or any combination thereof. In other embodiments, the etch stop layer 122 may directly contact the isolation structure 132. In yet other embodiments, the etch stop layer 122 may be deposited, for example, by PVD, CVD, ALD, or another suitable deposition or growth process.

[0057] As Figure 11As shown in the cross-sectional view 1100 of FIG. 1, a first interlayer dielectric (ILD) layer 118 is formed over the substrate 102. In some embodiments, the first ILD layer 118 may be deposited, for example, by CVD, PVD, ALD, or another suitable deposition process. In other embodiments, the first ILD layer 118 may be or may include, for example, silicon dioxide, a low-k dielectric material, an ultra-low-k dielectric material, another suitable dielectric material, or any combination thereof. Additionally, after forming the first ILD layer 118, a plurality of contacts 120 and field plates 124 may be formed within the first ILD layer 118 to define a first laterally diffused metal oxide semiconductor field effect transistor (MOSFET) (LDMOS) device 316 and a second LDMOS device 318. In some embodiments, the plurality of contacts 120 and the field plates 124 may be formed simultaneously. In various embodiments, the process of forming the contacts 120 and / or the field plates 124 may include: forming a masking layer (not shown) over the first ILD layer 118; patterning the first ILD layer 118 according to the masking layer to define a plurality of openings within the first ILD layer 118; filling the plurality of openings with a conductive material (e.g., titanium, copper, aluminum, tungsten, tantalum nitride, another suitable conductive material, or any combination thereof); and performing a planarization process (e.g., a chemical mechanical planarization (CMP) process) on the conductive material to define the contacts 120 and / or the field plates 124. In other embodiments, the contacts 120 and / or the field plates 124 may each be formed by a single damascene process.

[0058] In some embodiments, the field plate 124 is formed such that it directly overlies at least a portion of the isolation structure 132. Additionally, the field plate 124 is separated from the substrate 102 and / or the isolation structure 132 by an etch stop layer 122. In various embodiments, the field plate 124 may include a first field plate structure 126 and / or a second field plate structure (not shown) (e.g., Figure 3B the second field plate structure 128 shown). In such embodiments, the first field plate structure 126 and / or the second field plate structure (not shown) (e.g., Figure 3B the second field plate structure 128 shown) may be formed simultaneously.

[0059] Figure 12Method 1200 for forming an integrated chip including an LDMOS device is shown, where the LDMOS device has a field plate overlying an isolation structure. Although method 1200 is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the shown order or actions. Thus, in some embodiments, the actions may be performed in an order different from the shown order and / or the actions may be performed simultaneously. Additionally, in some embodiments, the shown actions or events may be subdivided into multiple actions or events, which may be performed separately in multiple steps or simultaneously with other actions or sub-actions. In some embodiments, some of the shown actions or events may be omitted and other actions or events not shown may be included.

[0060] At action 1202, an isolation structure is formed in a substrate, where the isolation structure extends from a front side of the substrate to a point below the front side of the substrate. Figure 4 A cross-sectional view 400 corresponding to some embodiments of action 1202 is shown.

[0061] At action 1204, a well region, a body region, and a drift region are formed within the substrate, where the drift region abuts the isolation structure. Figure 5 A cross-sectional view 500 corresponding to some embodiments of action 1204 is shown.

[0062] At action 1206, a gate structure is formed over the substrate, where the gate structure includes a gate electrode and a gate dielectric layer under the gate electrode. The gate structure overlies at least a portion of the drift region. Figure 6 A cross-sectional view 600 corresponding to some embodiments of action 1206 is shown.

[0063] At action 1208, a source region and a drain region are formed within the substrate on opposite sides of the gate structure. The isolation structure is laterally spaced between the gate structure and the drain region. Figure 9 A cross-sectional view 900 corresponding to some embodiments of action 1208 is shown.

[0064] At action 1210, an etch stop layer is formed over the gate electrode and the substrate, where the etch stop layer extends from an upper surface of the gate electrode to an upper surface of the isolation structure. Figure 10 A cross-sectional view 1000 corresponding to some embodiments of action 1210 is shown.

[0065] At action 1212, a first interlayer dielectric (ILD) layer is formed over the substrate and the gate structure. Figure 11 A cross-sectional view 1100 corresponding to some embodiments of action 1212 is shown.

[0066] At action 1214, a plurality of contacts and field plates are formed over the substrate and within the first ILD layer, where at least a portion of the field plate directly overlies the isolation structure.Figure 11 A cross-sectional view 1100 corresponding to some embodiments of operation 1214 is shown.

[0067] Thus, in some embodiments, the present disclosure relates to a high-voltage device having a field plate that at least partially directly overlies an isolation structure disposed in a drift region.

[0068] In some embodiments, the present application provides an integrated chip, the integrated chip including: a gate electrode overlying a substrate between a source region and a drain region; an etch stop layer extending laterally from an upper surface of the gate electrode to a front side of the substrate, wherein the etch stop layer overlies a drift region disposed between the source region and the drain region; a field plate disposed within a first interlayer dielectric (ILD) layer overlying the substrate, wherein the field plate extends from a top surface of the first ILD layer to an upper surface of the etch stop layer; and an isolation structure disposed within the substrate and extending from the front side of the substrate to a point below the front side of the substrate, wherein the isolation structure is laterally disposed between the gate electrode and the drain region, and wherein the field plate overlies the isolation structure.

[0069] In some embodiments, the isolation structure comprises a first material and the substrate comprises a second material different from the first material.

[0070] In some embodiments, the first material is silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon carbonitride, and the second material is silicon.

[0071] In some embodiments, the gate electrode comprises a first conductive material and the field plate comprises a second conductive material different from the first conductive material.

[0072] In some embodiments, the integrated chip further includes: a plurality of contacts disposed within the first interlayer dielectric layer and overlying the substrate, wherein top surfaces of the plurality of contacts are aligned with a top surface of the field plate.

[0073] In some embodiments, the field plate includes: a first field plate structure extending from the top surface of the first interlayer dielectric layer to the upper surface of the etch stop layer; and a second field plate structure extending from the top surface of the first interlayer dielectric layer to the upper surface of the etch stop layer, wherein the second field plate structure is laterally offset from the first field plate structure by a non-zero distance, and wherein at least a portion of the second field plate structure directly overlies the isolation structure.

[0074] In some embodiments, in a direction toward the gate electrode, the first field plate structure is laterally offset from the isolation structure by a non-zero distance.

[0075] In some embodiments, an outer sidewall of the second field plate structure is laterally spaced between outer sidewalls of the isolation structure.

[0076] In some embodiments, the first field plate structure directly contacts a sidewall of the etch stop layer.

[0077] In some embodiments, the present application provides an integrated chip, the integrated chip including: a first laterally diffused metal oxide semiconductor field effect transistor (MOSFET) (LDMOS) device including a first gate structure overlying a substrate, wherein the first LDMOS device further includes a first source region and a first drift region disposed in the substrate; a second LDMOS device including a second gate structure, a second source region, and a second drift region; a drain region disposed between the first LDMOS device and the second LDMOS device, wherein the first drift region is disposed between the first source region and the drain region, and wherein the second drift region is disposed between the second source region and the drain region; a first field plate laterally spaced between the drain region and the first gate structure; and a first isolation structure disposed in the substrate, wherein the first isolation structure is laterally spaced between the drain region and the first source region, wherein a first edge of the first field plate directly overlies the first isolation structure, and in a direction toward the first gate structure, a second edge of the first field plate is laterally offset from the first isolation structure by a non-zero distance.

[0078] In some embodiments, the integrated chip further includes: a second field plate laterally spaced between the drain region and the second gate structure; and a second isolation structure disposed in the substrate, wherein the second isolation structure is laterally spaced between the drain region and the second source region, wherein a first edge of the second field plate directly overlies the second isolation structure.

[0079] In some embodiments, a lower surface of the first isolation structure is vertically disposed below a lower surface of the drain region.

[0080] In some embodiments, the first isolation structure directly contacts the first drift region.

[0081] In some embodiments, the integrated chip further includes: a first interlayer dielectric layer overlying the substrate; and a plurality of contacts disposed in the first interlayer dielectric layer and overlying the substrate, wherein a top surface of the plurality of contacts is aligned with a top surface of the first field plate, and wherein the contacts and the first field plate comprise the same material.

[0082] In some embodiments, the integrated chip further includes: a first etch stop layer, continuously extending from the upper surface of the first gate structure to the upper surface of the substrate, wherein the first field plate directly contacts the upper surface of the first etch stop layer.

[0083] In some embodiments, the first etch stop layer directly contacts the first drift region and directly contacts the first isolation structure.

[0084] In some embodiments, the first etch stop layer comprises a material different from that of the first isolation structure.

[0085] In some embodiments, the present application provides a method, the method comprising: forming an isolation structure in a substrate, wherein the isolation structure comprises a dielectric material and the substrate comprises a substrate material different from the dielectric material; performing an implantation process to form a drift region in the substrate, wherein the drift region abuts the isolation structure; forming a gate structure over the substrate, wherein the gate structure at least partially overlies the drift region; performing an implantation process to form a source region and a drain region in the substrate, wherein the drift region is laterally disposed between the source region and the drain region; forming a first interlayer dielectric (ILD) layer over the substrate; and forming a field plate over the drift region and within the first ILD layer, wherein at least a portion of the field plate directly overlies the isolation structure.

[0086] In some embodiments, the method further comprises: forming a plurality of contacts within the first interlayer dielectric layer and overlying the substrate, wherein the contacts are formed simultaneously with the field plate.

[0087] In some embodiments, forming the isolation structure comprises: forming a masking layer over the substrate; patterning the substrate according to the masking layer to define an opening extending from the front side of the substrate to a point below the front side of the substrate; depositing the dielectric material within the opening; and performing a planarization process on the dielectric material to form the isolation structure.

[0088] The features of several embodiments are outlined above so that those skilled in the art may better understand various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated chip, comprising: A gate electrode overlying a substrate between a source region and a drain region; An etch stop layer extending laterally from an upper surface of the gate electrode to a front side of the substrate, wherein the etch stop layer overlies a drift region disposed between the source region and the drain region; A field plate disposed within a first interlayer dielectric layer overlying the substrate, wherein the field plate extends from a top surface of the first interlayer dielectric layer to an upper surface of the etch stop layer; And An isolation structure disposed within the substrate and extending from the front side of the substrate to a point below the front side of the substrate, and the isolation structure is disposed within the drift region, wherein the isolation structure is laterally disposed between the gate electrode and the drain region, and wherein the field plate overlies the isolation structure, the field plate is laterally disposed between the drain region and the gate electrode and spaced apart from the drain region and the gate electrode, and an edge of the field plate is laterally disposed outside a first outer sidewall of the isolation structure, the field plate directly contacts a sidewall of the etch stop layer but does not extend to a top surface of the gate electrode.

2. The integrated chip according to claim 1, wherein the isolation structure comprises a first material and the substrate comprises a second material different from the first material.

3. The integrated chip according to claim 2, wherein the first material is silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride or silicon carbonitride, and the second material is silicon.

4. The integrated chip according to claim 1, wherein the gate electrode comprises a first conductive material, and the field plate comprises a second conductive material different from the first conductive material.

5. The integrated chip according to claim 1, further comprising: A plurality of contacts disposed within the first interlayer dielectric layer and overlying the substrate, wherein a top surface of the plurality of contacts is aligned with a top surface of the field plate.

6. The integrated chip according to claim 1, wherein the field plate comprises: A first field plate structure extending from the top surface of the first interlayer dielectric layer to the upper surface of the etch stop layer; And A second field plate structure extending from the top surface of the first interlayer dielectric layer to the upper surface of the etch stop layer, wherein the second field plate structure is laterally offset from the first field plate structure by a non-zero distance, and wherein at least a portion of the second field plate structure directly overlies the isolation structure.

7. The integrated chip according to claim 6, wherein in a direction towards the gate electrode, the first field plate structure is laterally offset from the isolation structure by a non-zero distance.

8. The integrated chip according to claim 6, wherein an outer sidewall of the second field plate structure is laterally spaced between the first outer sidewall and a second outer sidewall of the isolation structure.

9. The integrated chip according to claim 6, wherein the first field plate structure directly contacts the sidewall of the etch stop layer.

10. An integrated chip, comprising: A first laterally diffused metal oxide semiconductor field effect transistor device, including a first gate structure overlying a substrate, wherein the first laterally diffused metal oxide semiconductor field effect transistor device further includes a first source region and a first drift region disposed within the substrate; A second laterally diffused metal oxide semiconductor field effect transistor device, including a second gate structure, a second source region, and a second drift region; A drain region disposed between the first laterally diffused metal oxide semiconductor field effect transistor device and the second laterally diffused metal oxide semiconductor field effect transistor device, wherein the first drift region is disposed between the first source region and the drain region, and wherein the second drift region is disposed between the second source region and the drain region; A first field plate laterally spaced between the drain region and the first gate structure and spaced apart from the drain region and the first gate structure; And A first isolation structure disposed within the substrate, wherein the first isolation structure is laterally spaced between the drain region and the first source region, and the first isolation structure is disposed within the first drift region, wherein a first edge of the first field plate directly overlies the first isolation structure, and in a direction toward the first gate structure, a second edge of the first field plate is laterally disposed outside an outer sidewall of the first isolation structure, and the first field plate and the first gate structure do not overlap in a vertical direction.

11. The integrated chip according to claim 10, further including: A second field plate laterally spaced between the drain region and the second gate structure; And A second isolation structure disposed within the substrate, wherein the second isolation structure is laterally spaced between the drain region and the second source region, and a first edge of the second field plate directly overlies the second isolation structure.

12. The integrated chip according to claim 10, wherein a lower surface of the first isolation structure is disposed below a lower surface of the drain region in the vertical direction.

13. The integrated chip according to claim 10, wherein the first isolation structure directly contacts the first drift region.

14. The integrated chip according to claim 10, further including: A first interlayer dielectric layer overlying the substrate; And A plurality of contacts disposed within the first interlayer dielectric layer and overlying the substrate, wherein a top surface of the plurality of contacts is aligned with a top surface of the first field plate, and the contacts and the first field plate comprise the same material.

15. The integrated chip according to claim 10, further including: A first etch stop layer continuously extending from an upper surface of the first gate structure to an upper surface of the substrate, wherein the first field plate directly contacts an upper surface of the first etch stop layer.

16. The integrated chip according to claim 15, wherein the first etch stop layer directly contacts the first drift region and directly contacts the first isolation structure.

17. The integrated chip according to claim 15, wherein the first etch stop layer comprises a material different from that of the first isolation structure.

18. A method of forming an integrated chip, comprising: forming an isolation structure in a substrate, wherein the isolation structure comprises a dielectric material and the substrate comprises a substrate material different from the dielectric material; performing an implantation process to form a drift region in the substrate, wherein the drift region abuts the isolation structure and the isolation structure is disposed within the drift region; forming a gate structure over the substrate, wherein the gate structure at least partially overlies the drift region; performing an implantation process to form a source region and a drain region in the substrate, wherein the drift region is laterally disposed between the source region and the drain region; forming a first interlayer dielectric layer over the substrate; and forming a field plate over the drift region and within the first interlayer dielectric layer, wherein at least a portion of the field plate directly overlies the isolation structure, the field plate is laterally between the drain region and the gate structure and spaced apart from the drain region and the gate structure, and an edge of the field plate is laterally disposed outside an outer sidewall of the isolation structure, and the field plate and the gate structure do not overlap in a vertical direction.

19. The method according to claim 18, further comprising: forming a plurality of contacts within the first interlayer dielectric layer and overlying the substrate, wherein the contacts are formed simultaneously with the field plate.

20. The method according to claim 18, wherein forming the isolation structure comprises: forming a masking layer over the substrate; patterning the substrate according to the masking layer to define an opening extending from a front side of the substrate to a point below the front side of the substrate; depositing the dielectric material within the opening; and performing a planarization process on the dielectric material to form the isolation structure.

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