Optical communication O-band silicon-based high-speed semiconductor laser chip and manufacturing method thereof

Abstract

The present invention proposes an optical communication O-band silicon-based high-speed semiconductor laser chip and a manufacturing method thereof. Different buffer layers are used to form a growth surface with a low dislocation density of InP material; N-InAlGaAs is used to replace the conventional N-InAlAs electron blocking layer in the energy band structure to reduce the barrier for electrons to enter the quantum well from the N type and reduce the threshold; a superlattice structure quantum barrier is used to replace the single-layer barrier layer structure to improve the transport of heavy holes in the quantum well; and adjustments are made to the material structure to achieve an O-band high direct modulation rate semiconductor laser chip for optical communication on a silicon substrate with good reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of laser chips, and in particular to an optical communication O-band silicon-based high-speed semiconductor laser chip and a manufacturing method thereof. Background Art

[0002] High-speed optical chips are key light-emitting chips for large-capacity data centers, 5G networks, and large-capacity access networks. Compared with conventional InP substrates, silicon substrates have the advantages of good electrical and thermal conductivity, low cost, good hardness, and compatibility with conventional semiconductor processes. The preparation of InP laser chips on silicon substrates is the key to the next development and integration of optical communications; usually, due to the mismatch of lattice constants, InP material systems cannot be directly grown on silicon substrates.

[0003] In addition, the strained quantum well uses compressive strain to convert the highest hole band into a quasi-light hole band, which greatly reduces the Auger coincidence and the absorption rate between the valence band. The compressive strain can effectively reduce the effective mass and state density of the holes, thereby increasing the gain and relaxation frequency of the laser. In 1990, researchers found that compared with compressive strain, the use of tensile strain quantum wells can further reduce the laser threshold, resulting in higher light output power and relaxation frequency (Tanban-EK T et al. Performance enhancement of InGaAs / InP quantum well lasers byboth tensile and compressive strain. 21st Internal. Semicon. Laser Conf. 1990; D-3). In order to further reduce the threshold current and working current of the laser chip, tensile strain quantum wells can be used. However, in order to increase the interaction density between photons and electrons and increase the modulation frequency of the laser, high-speed laser chips usually use more quantum wells. Since the effective mass of electrons is small, a P-type electron barrier layer is usually used to limit them in the conduction band. However, the effective mass of holes is large, which can easily lead to uneven distribution problems in multi-layer quantum wells. There are usually two main ways for carriers to be transported in the energy band: one is to cross the potential barrier through thermal transition, and the other is the tunneling effect of carriers. Usually, quantum barriers cannot achieve a large proportion of tunneling for heavy holes.

[0004] In addition, since the photon and electron density of semiconductor lasers is relatively concentrated at the dissociation cavity surface, it is easy to generate heat and cause cavity surface catastrophic failure, which is a common factor of failure during laser application. Summary of the invention

[0005] In order to overcome the defects of the prior art, the present invention provides an optical communication O-band silicon-based high-speed semiconductor laser chip and a manufacturing method thereof. A transition material with similar lattice parameters is used on a silicon substrate, and the interface after growth is baked and cleaned to improve the growth interface of the InP material system and reduce dislocations. In addition, a thin layer of a multilayer superlattice is used as a quantum barrier, which is conducive to the tunneling of holes between different wells, thereby improving the uniformity and differential gain of hole injection. The method of selectively growing a PNP current blocking layer near the light-emitting and backlight end faces can block the current from flowing to the end face; on the other hand, the combined waveguide of the PNP can adjust the near field of the light spot by adjusting the thickness, reduce the end face photon density of the laser, and improve the chip reliability. Under the P-side electrode metal, an insulating InP layer doped with Fe is used to effectively improve the capacitance parameters of the chip and increase the bandwidth, and conventional BCB and other processes can be avoided.

[0006] It uses different buffer layers to form a growth surface with low dislocation density of InP material; uses N-InAlGaAs to replace the conventional N-InAlAs electron blocking layer in the energy band structure to reduce the barrier for electrons to enter the quantum well from the N type and lower the threshold; uses a superlattice structure quantum barrier to replace the single-layer barrier structure to improve the transport of heavy holes in the quantum well; and makes adjustments to the material structure to achieve an O-band high direct modulation rate semiconductor laser chip for silicon substrate optical communication with good reliability.

[0007] The present invention specifically adopts the following technical solutions:

[0008] An optical communication O-band silicon-based high-speed semiconductor laser chip is characterized by: on a Si substrate, a growth surface with low dislocation density is formed by using different buffer layers; in terms of material structure, N-InAlGaAs is used to replace the N-InAlAs electron blocking layer, and a superlattice quantum barrier structure is used.

[0009] Furthermore, the buffer layer includes: an N-GaP buffer layer, an N-GaAs buffer layer and an N-InP buffer layer.

[0010] And, an optical communication O-band silicon-based high-speed semiconductor laser chip, characterized in that: its epitaxial layer includes the following formed in sequence on a Si substrate: an N-GaP buffer layer, an N-GaAs buffer layer, an N-InP buffer layer, an N-InAlGaAs transition layer, an InAlGaAs lower waveguide layer, an InAlGaAs lower separate restriction layer, an InGaAlAs strained multiple quantum well and barrier, an InAlGaAs upper separate restriction layer, a P-InAlAs electron blocking layer, a P-InP spacer layer, a P-InGaAsP grating layer, a P-InP grating cap layer, a P-InGaAsP etching stop layer, a P-InP space layer, a P-InGaAsP transition layer, a P-InGaAs electrical contact layer, and an Fe-doped insulating InP layer.

[0011] Furthermore, the front and rear light-emitting end faces of the chip are separated in the regrown region, and the regrown region is filled with the regrown P-InP layer, N-InGaAsP layer and P-InP layer.

[0012] Furthermore, it also includes a ridge waveguide formed by etching on the epitaxial layer.

[0013] Furthermore, the ridge waveguide is etched to the P-InGaAsP etching stop layer.

[0014] Furthermore, in the InGaAlAs strained multiple quantum wells and barriers, the barrier layer is composed of a superlattice structure of three 2nm InGaAlAs barriers and two 2nm InGaAlAs wells.

[0015] And, a method for manufacturing an optical communication O-band silicon-based high-speed semiconductor laser chip, characterized in that the manufacturing process of its epitaxial layer includes the following steps:

[0016] Step S1: Buffer layer growth: Place the N-Si substrate into the MOCVD growth chamber, bake it at high temperature with nitrogen for 15 minutes, then grow a 300nm N-GaP buffer layer; bake it at high temperature with phosphine for 15 minutes, then grow a 300nm N-GaAs buffer layer; then bake it at high temperature with arsine for 15 minutes, then grow a 500nm N-InP buffer layer;

[0017] Step S2: growing a 15nm N-InAlGaAs transition layer, growing an undoped 30nm InAlGaAs lower waveguide layer; growing an undoped 20nm InAlGaAs lower separate limiting layer; growing 7 layers of 8nm-InAlGaAs tensile strain quantum wells, with a tensile strain of at least 1.3%, growing 8 layers of 10nm-InAlGaAs compressive strain quantum barriers, with a compressive strain of at least 0.4%, the quantum barriers consisting of 3 layers of 2nm-InAlGaAs barriers and 2 layers of 2nm-InAlGaAs well superlattice structures; growing a 15nm InAlGaAs upper separate limiting layer, growing a 25nm P-InAlAs electron blocking layer; growing a 50nm P-InP layer, growing a 40nm P-InGaAsP grating layer, and preparing a uniform grating;

[0018] Step S3: Deposit a 200nm SiO2 dielectric layer by PECVD, remove a 20 micron area near the front and rear light-emitting end faces of the chip by photolithography, and perform isotropic etching with a diluted bromine:hydrobromic acid solution to a depth of N-InP buffer layer; then grow 100nm P-InP, 50nm N-InGaAsP, and 100nm P-InP in sequence;

[0019] Step S4: After the PNP layer is grown, the SiO2 dielectric layer on the wafer surface is removed, the wafer is placed in an MOCVD chamber, the temperature is increased, and a 100nm P-InP grating buried layer, a 25nm P-InGaAsP etching stop layer, a 2.0 micron P-InP space layer, a 50nm P-InGaAsP transition layer, a 250nm P-InGaAs electrical contact layer, and a 300nm Fe-doped insulating InP layer are grown at high temperature to complete the epitaxial growth of the material.

[0020] Furthermore, the method also includes step S5: growing a 150nm SiO2 dielectric layer by PECVD, performing photolithography etching to form a laser ridge waveguide, removing the surface dielectric layer, growing a 4000nm SiO2 conventional passivation layer, opening a hole on the surface of the ridge waveguide, removing the Fe-doped insulating InP layer on the surface of the ridge waveguide, and performing electron beam evaporation of Ti / Pt / Au P-type electrode metal. The P-type metal is electrically isolated from the surface of the semiconductor material by the SiO2 passivation layer and the Fe-doped insulating InP layer to form a lower chip capacitance; then the mask on the back of the chip is thinned to 200 microns, and the N-side metal is evaporated; dissociation is performed to form bars, and Al2O3 / Si film system electron beam evaporation is used to form a high-reflection and high-transmittance film of the chip resonant cavity to complete the chip preparation.

[0021] The present invention and its preferred solution first grow a GaP buffer layer on a silicon substrate by MOCVD and then sequentially grow GaAs and InP buffer layers, thereby achieving a low-defect material surface that is beneficial to the epitaxial growth of subsequent laser structures.

[0022] In the epitaxial structure, N-InAlGaAs is used instead of conventional N-InAlAs to reduce the height of the potential barrier, which is beneficial to improving the transport of electrons and lowering the threshold. Then, tensile strained multiple quantum wells are used to improve the chip operating threshold and bandwidth. The quantum barrier adopts a thin-layer superlattice structure, which is beneficial to the transport of heavy holes between different quantum wells and improves their distribution uniformity.

[0023] The conventional direct dissociation process is not used on the light-emitting and backlight end faces of the laser. In the area near the light-emitting and backlight end faces, the PNP structure layer is grown in a selective area. The reverse PN junction characteristics of the PNP limit the electrons to prevent the carriers from flowing to the end face and heating with the photons, which will cause COMD (cavity surface catastrophic failure). At the same time, the PNP structure material acts as a waveguide to adjust the near-field distribution of the light spot and reduce the photon density and heating of the end face. InP / InGaAsP / InP plays the role of a combined waveguide for the light field and couples the light in the active area, adjusts the near-field distribution of the laser, improves the near-field light spot, reduces the photon density of the end face, improves the interaction between the electrons and photons on the end face, reduces the divergence angle, and improves the catastrophic failure of the chip end face.

[0024] In addition, the Fe-doped insulating InP layer grown on the epitaxial structure can play a role in electrical isolation to reduce capacitance and increase bandwidth, so there is no need for conventional BCB / PI glue and other processes, which improves the capacitance parameters of the chip and increases the working bandwidth; the present invention can realize an optical communication O-band high-speed semiconductor laser chip based on a silicon substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0026] Figure 1 A schematic diagram of the epitaxial structure of a high-speed laser chip provided in an embodiment of the present invention;

[0027] In the figure: 1 is N-Si substrate, 2 is N-GaP buffer layer, 3 is N-GaAs buffer layer, 4 is N-InP buffer layer, 5 is N-InGaAlAs transition layer, 6 is InGaAlAs lower waveguide layer, 7 is InGaAlAs lower limiting layer, 8 is InGaAlAs strained multiple quantum well and barrier, 9 is InGaAlAs upper limiting layer, 10 is P-InAlAs layer, 11 is P-InP spacer layer, 12 is P-InGaAsP grating layer, 13 is P-InP grating cap layer, 14 is P-InGaAsP etching stop layer, 15 is P-InP space layer, 16 is P-InGaAsP transition layer, 17 is P-InGaAs electrical contact layer, 18 is Fe-doped insulating InP layer, in the figure, left and right end faces are dissociation cavity faces of laser, 19, 20 and 21 are respectively P-InP, N-InGaAsP and P-InP layers for selective area regrowth.

[0028] Figure 2 Schematic diagram of the quantum well and barrier energy band structure of the conduction band in an embodiment of the present invention;

[0029] The barrier layer in the figure is composed of 3 layers of 2nm InGaAlAs barriers and 2 layers of 2nm InGaAlAs well superlattice structure, which plays a role in improving the transport of heavy holes between quantum wells. DETAILED DESCRIPTION

[0030] In order to make the features and advantages of this patent more obvious and easy to understand, the following embodiments are specifically described in detail with the accompanying drawings as follows:

[0031] like Figure 1 As shown, the specific structure of the epitaxial layer of the optical communication O-band silicon-based high-speed semiconductor laser chip and the manufacturing process of the chip provided in this embodiment are as follows:

[0032] 1. First, a 2-inch N-Si substrate 1 is placed in an MOCVD growth chamber and baked at high temperature with nitrogen for 15 minutes. The high-temperature carrier gas baking has two main functions. On the one hand, it removes surface dirty particles, and on the other hand, it utilizes the high-temperature mass transport effect to improve the surface quality of the material growth and improve the surface flatness. Then, a 300nm N-GaP buffer layer 2 is grown; at high temperature, it is baked with phosphine for 15 minutes, and then a 300nm N-GaAs buffer layer 3 is grown, and its growth lattice constant is similar to that of GaP; then, it is baked with arsine for 15 minutes at high temperature, and a 500nm N-InP buffer layer 4 is grown to complete the buffer layer growth.

[0033] 2. Then grow a 15nm N-InAlGaAs transition layer 5, grow an undoped 30nm InAlGaAs lower waveguide layer 6, the lower waveguide layer has a low barrier, which is conducive to improving the transport of electrons; grow an undoped 20nm InAlGaAs lower confinement layer 7; then form an InGaAlAs strained multiple quantum well and barrier 8, including growing 7 layers of 8nm-InAlGaAs tensile strained quantum wells, with a tensile strain of at least 1.3%, growing 8 layers of 10nm-InAlGaAs compressive strained quantum barriers, with a compressive strain of at least 0.4%, and the quantum barriers are composed of 3 layers of 2nm-InAlGaAs barriers and 2 layers of 2nm-InAlGaAs well superlattice structures, such as Figure 2 As shown, the quantum barrier is compressive strain, and the barrier layer adopts a multi-layer superlattice structure to improve the transport of holes; compared with the compressive strain quantum well, the tensile strain has a lower threshold and higher gain and bandwidth characteristics. At the same time, the quantum barrier adopts a thin layer of superlattice structure, which is more conducive to the transmission of heavy holes between quantum wells through the tunneling effect, improves the uniformity of the direct distribution of heavy holes in different quantum wells, thereby improving the differential gain and bandwidth saturation characteristics; a restriction layer 9 is grown on 15nm InAlGaAs, and a 25nm P-InAlAs electron blocking layer 10 is grown; a 50nm P-InP layer 11 is grown, and a 40nm P-InGaAsP grating layer 12 is grown, and a uniform grating is prepared.

[0034] 3. Then, a 200nm SiO2 dielectric layer is deposited by PECVD, and a 20-micron area near the front and rear light-emitting ends of the chip is removed by photolithography. A diluted bromine:hydrobromic acid solution is used for isotropic etching, and the etching depth reaches the N-InP buffer layer. Then, 100nm P-InP 19, 50nm N-InGaAsP 20, and 100nm P-InP 21 are grown in sequence. When current passes through, the PNP combination layer acts as a reverse PN junction, thereby limiting most of the current from being injected into the chip end face, improving the cavity surface catastrophic failure (COMD) caused by the large photon and electron density at the chip end face. In addition, the PNP layer can be used as a waveguide layer optically. Adjusting the thickness of the N-InGaAsP layer can optimize the distribution of the near-field of the light spot at the end face, thereby improving the photon density at the end face and reducing the heating of the chip end face.

[0035] 4. After the PNP layer is grown, the SiO2 dielectric layer on the wafer surface is removed, the wafer is placed in a MOCVD chamber, the temperature is increased, and a 100nm P-InP grating cover layer 13, a 25nm P-InGaAsP etching stop layer 14, a 2.0 micron P-InP space layer 15, a 50nm P-InGaAsP transition layer 16, a 250nm P-InGaAs electrical contact layer 17, and a 300nm Fe-doped insulating InP layer 18 are grown at high temperature to complete the epitaxial growth of the material.

[0036] 5. PECVD grows a 150nm SiO2 dielectric layer, and then photoetches it to form a laser ridge waveguide. Except for the two sides of the ridge waveguide being etched, the rest of the area on the chip remains intact; remove the surface dielectric layer, grow a 4000nm SiO2 conventional passivation layer, open a hole on the ridge waveguide surface, remove the Fe-doped insulating InP layer on the ridge waveguide surface, and electron beam evaporate Ti / Pt / Au P-type electrode metal. The P-type metal and the semiconductor material surface are electrically isolated by the SiO2 passivation layer and the Fe-doped insulating InP layer, forming a lower chip capacitance. There is no need to use BCB / PI glue and other processes, and the chip can achieve low capacitance and high bandwidth characteristics; then the chip back mask is thinned to 200 microns, and the N-side metal is evaporated. Due to the low bulk material resistance of silicon material, the thicker thinning thickness has little effect on its series resistance; dissociation forms bar strips, and Al2O3 / Si film system electron beam evaporation is used to form a high-reflection and high-transmittance film for the chip resonant cavity to complete the chip preparation.

[0037] This method uses silicon as the substrate and does not require a heat sink during the actual packaging process. High-speed laser chips can be used in large quantities in silicon photonics integration, hybrid integration, silicon photonics data centers and other fields.

[0038] This patent is not limited to the best implementation method. Anyone can derive other forms of optical communication O-band silicon-based high-speed semiconductor laser chips and their manufacturing methods under the inspiration of this patent. All equivalent changes and modifications made within the scope of the patent application of the present invention shall be covered by this patent.

Claims

1. An optical communication O-band silicon-based high-speed semiconductor laser chip, characterized by: The epitaxial layers include: N-GaP buffer layer, N-GaAs buffer layer, N-InP buffer layer, N-InAlGaAs transition layer, InAlGaAs lower waveguide layer, InAlGaAs lower separate confinement layer, InGaAlAs strained multiple quantum well and barrier, InAlGaAs upper separate confinement layer, P-InAlAs electron blocking layer, P-InP spacer layer, P-InGaAsP grating layer, P-InP grating cap layer, P-InGaAsP etching stop layer, P-InP space layer, P-InGaAsP transition layer, P-InGaAs electric contact layer and Fe-doped insulating InP layer, which are sequentially formed on a Si substrate; The front and rear light-emitting end faces of the chip are separated in the regrown area, and the regrown area is filled with the regrown P-InP layer, N-InGaAsP layer and P-InP layer; In the InGaAlAs strained multiple quantum wells and barriers, the barrier layer is composed of a superlattice structure of three 2nm InGaAlAs barriers and two 2nm InGaAlAs wells.

2. The optical communication O-band silicon-based high-speed semiconductor laser chip according to claim 1, characterized in that: It also includes a ridge waveguide formed by etching on the epitaxial layer.

3. The optical communication O-band silicon-based high-speed semiconductor laser chip according to claim 2, characterized in that: The ridge waveguide is etched to the P-InGaAsP etch stop layer.

4. A method for manufacturing an optical communication O-band silicon-based high-speed semiconductor laser chip, characterized in that: The production process of the epitaxial layer includes the following steps: Step S1: Buffer layer growth: Place the N-Si substrate into the MOCVD growth chamber, bake it at high temperature with nitrogen for 15 minutes, then grow a 300nm N-GaP buffer layer; bake it at high temperature with phosphine for 15 minutes, then grow a 300nm N-GaAs buffer layer; then bake it at high temperature with arsine for 15 minutes, then grow a 500nm N-InP buffer layer; Step S2: growing a 15nm N-InAlGaAs transition layer, growing an undoped 30nm InAlGaAs lower waveguide layer; growing an undoped 20nm InAlGaAs lower respective confinement layer; growing 7 layers of 8nm-InAlGaAs tensile strain quantum wells, with a tensile strain of at least 1.3%, growing 8 layers of 10nm-InAlGaAs compressive strain quantum barriers, with a compressive strain of at least 0.4%, the compressive strain quantum barriers consisting of 3 layers of 2nm-InAlGaAs barriers and 2 layers of 2nm-InAlGaAs well superlattice structures; growing a 15nm InAlGaAs upper respective confinement layer, growing a 25nm P-InAlAs electron blocking layer; growing a 50nm P-InP layer, growing a 40nm P-InGaAsP grating layer, and preparing a uniform grating; Step S3: Deposit a 200nm SiO2 dielectric layer by PECVD, remove a 20 micron area near the front and rear light-emitting end faces of the chip by photolithography, and perform isotropic etching with a diluted bromine:hydrobromic acid solution to a depth of N-InP buffer layer; then grow 100nm P-InP, 50nm N-InGaAsP, and 100nm P-InP in sequence; Step S4: After the PNP layer is grown, the SiO2 dielectric layer on the wafer surface is removed, the wafer is placed in an MOCVD chamber, the temperature is increased, and a 100nm P-InP grating buried layer, a 25nm P-InGaAsP etching stop layer, a 2.0 micron P-InP space layer, a 50nm P-InGaAsP transition layer, a 250nm P-InGaAs electrical contact layer, and a 300nm Fe-doped insulating InP layer are grown at high temperature to complete the epitaxial growth of the material.

5. The method for manufacturing an optical communication O-band silicon-based high-speed semiconductor laser chip according to claim 4, characterized in that: The process also includes step S5: growing a 150nm SiO2 dielectric layer by PECVD, photoetching to form a laser ridge waveguide, removing the surface dielectric layer, growing a 4000nm SiO2 conventional passivation layer, opening a hole on the ridge waveguide surface, removing the Fe-doped insulating InP layer on the ridge waveguide surface, and electron beam evaporating Ti / Pt / Au P-type electrode metal. The P-type metal is electrically isolated from the semiconductor material surface by the SiO2 passivation layer and the Fe-doped insulating InP layer to form a lower chip capacitance; then the chip back mask is thinned to 200 microns, and the N-side metal is evaporated; The chips are dissociated to form bars, and Al2O3 / Si film system is evaporated by electron beam to form high-reflection and high-transmittance films for the chip resonant cavity, thus completing the chip preparation.

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