Data drive circuit

Abstract

A data driving circuit may include a trigger circuit and a pre-driver. The trigger circuit may be configured to block the remaining signal paths except for the signal path corresponding to the currently selected driving strength among a plurality of signal paths for transmitting data. The pre-driver may be configured to drive the data transmitted through the signal path corresponding to the currently selected driving strength using an impedance determined according to a plurality of impedance control codes.

Description

Technical Field

[0001] Various embodiments may generally relate to a semiconductor circuit, and more particularly, to a data driving circuit. Background Art

[0002] The semiconductor circuit may include a data driving circuit configured to output data to an external device.

[0003] The data driving circuit may be designed to implement various impedances corresponding to the specifications of the driving strength and termination of the semiconductor device. Summary of the invention

[0004] According to one embodiment of the present disclosure, the data driving circuit may include a trigger circuit and a pre-driver. The trigger circuit may be configured to block the remaining signal paths except the signal path corresponding to the currently selected driving strength among the multiple signal paths for sending data. The pre-driver may be configured to drive the data sent through the signal path corresponding to the currently selected driving strength using an impedance determined according to multiple impedance control codes. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The above and other aspects, features and advantages of the subject matter of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0006] Figure 1 shows a data driving circuit according to an example embodiment;

[0007] Figure 2 Shows Figure 1 The trigger circuit;

[0008] Figure 3 Shows Figure 1 Pre-driver;

[0009] Figure 4 Shows Figure 3 Pre-pull-up driving unit;

[0010] Figure 5 Shows Figure 3 Pre-pull-down drive unit;

[0011] Figure 6 Shows Figure 1 The main drive;

[0012] Figure 7 Shows Figure 1 Impedance calibration circuit;

[0013] Figure 8 A data driving circuit according to one embodiment is shown;

[0014] Fig. 9 Shows Figure 8 The trigger circuit;

[0015] Fig.10 Shows Figure 8 Pre-driver;

[0016] Fig.11 Shows Fig.10 A pre-pull-up driving unit; and

[0017] Fig.12 Shows Fig.10 Pre-pull-down driver unit. DETAILED DESCRIPTION

[0018] Various embodiments of the present teachings are described in detail with reference to the accompanying drawings. The accompanying drawings are schematic representations of various embodiments (and intermediate structures). As such, variations in the illustrated configurations and shapes due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the described embodiments should not be interpreted as limited to the specific configurations and shapes shown herein, but may include deviations in configurations and shapes that do not depart from the spirit and scope of the present teachings as defined by the appended claims.

[0019] This teaching is described herein in part with reference to the cross-sectional views and / or plan views of the idealized embodiments of this teaching. However, the embodiments of this teaching should not be construed as restrictive. Although some embodiments of this teaching are shown and described, it will be appreciated by those of ordinary skill in the art that these embodiments may be changed without departing from the principles and spirit of this teaching.

[0020] Some embodiments are designed to provide a data driving circuit that can simplify logic and reduce power consumption.

[0021] Figure 1 is a diagram illustrating a data driving circuit 100 according to an example embodiment.

[0022] Reference Figure 1 The data driving circuit 100 may include a trigger circuit 101 , a pre-driver 102 and a main driver 103 .

[0023] In addition, the data driving circuit 100 of this example embodiment may further include an impedance calibration circuit 105 .

[0024] The trigger circuit 101 can latch a plurality of first data RDATA and FDATA according to a plurality of clock signals RCLKDO and FCLKDO having a phase difference to output a plurality of second data RDATAS<J:0> and FDATAS<J:0> .

[0025] The pre-driver 102 can use a plurality of drive strength control signals CONPU<K:0> and CONPD<K:0> Determine the drive strength and control code PUCODE according to multiple impedances<L:0> and PDCODE<L:0> Determine the impedance to drive the second data RDATAS<J:0> , to output multiple driving control signals PU<M:0> _<N:0> and PD<M:0> _<N:0> .

[0026] The main driver 103 can control the<M:0> _<N:0> and PD<M:0> _<N:0> To drive the output terminal DQ.

[0027] The impedance calibration circuit 105 can control the impedance control code PUCODE<L:0> and PDCODE<L:0> The resistance of the external resistor 109 connected to the external resistor pad 107 is taken as a target value.

[0028] Figure 2 It is shown Figure 1 FIG. 1 is a diagram of a trigger circuit 101 in FIG. Figure 2 shows that when the second data RDATAS<J:0> and FDATAS<J:0> Trigger circuit 101 when J is 2.

[0029] Reference Figure 2 , the trigger circuit 101 may include a first latch circuit 110, a first signal distribution circuit 111-0 to 111-2, a second latch circuit 120 and a second signal distribution circuit 121-0 to 121-2. As used herein, the tilde symbol "~" indicates a range of components. For example, "111-0 to 111-2" indicates Figure 2 The first signal distribution circuits 111-0, 111-1 and 111-2 shown in FIG.

[0030] The first latch circuit 110 may latch the first data RDATA according to the first clock signal RCLKDO of the clock signals RCLKDO and FCLKDO to generate a first latch signal RDIN.

[0031] The first signal distribution circuits 111 - 0 to 111 - 2 may distribute the first latch signal RDIN to output the second data RDATAS<2:0> among the second data RDATAS<2:0> and FDATAS<2:0>.

[0032] In example embodiments, each of the first signal distribution circuits 111 - 0 ˜ 111 - 2 may include an inverter chain.

[0033] The second latch circuit 120 may latch the first data FDATA according to a second clock signal FCLKDO among the clock signals RCLKDO and FCLKDO to generate a second latch signal FDIN.

[0034] The second signal distribution circuits 121 - 0 ˜ 121 - 2 may distribute the second latch signal FDIN to output the second data FDATAS<2:0> of the second data RDATAS<2:0> and FDATAS<2:0>.

[0035] In example embodiments, each of the second signal distribution circuits 121 - 0 ˜ 121 - 2 may include a transmission gate and an inverter.

[0036] The transmission gate may include a negative control terminal configured to receive a ground voltage and a positive control terminal configured to receive a power supply voltage.

[0037] The transmission gates may be configured to provide the same signal delay time to the second signal distribution circuits 121 - 0 ˜ 121 - 2 and the first signal distribution circuits 111 - 0 ˜ 111 - 2 .

[0038] Figure 3 It is shown Figure 1 FIG. 1 is a diagram of the pre-driver 102 in FIG.

[0039] Figure 3 shows that when the drive strength control signal CONPU<K:0> and CONPD<K:0> , Impedance control code PUCODE<L:0> and PDCODE<L:0> And the drive control signal PU<M:0> _<N:0> and PD<M:0> _<N:0> Pre-driver 102 when K, L, M and N are 4.

[0040] Reference Figure 3 , the pre-driver 102 may include a plurality of pre-driver units 201 - 0 ˜ 201 - 4 and 202 - 0 ˜ 202 - 4 .

[0041] The pre-driving units 201-0201-4 and 202-0202-4 may be classified into a plurality of pre-pull-up driving units 201-0202-4 and a plurality of pre-pull-down driving units 202-0202-4.

[0042] The first pre-pull-up driving unit 201-0 can generate a second data RDATAS <0> , the first driving strength control signal CONPU<4:0> and the first impedance control code PUCODE<4:0> to generate the first driving control signal PU <0> _<4:0>.

[0043] The second pre-pull-up driving unit 201-1 can generate a second data RDATAS <1> , the first driving strength control signal CONPU<4:0> and the first impedance control code PUCODE<4:0> to generate the first driving control signal PU <1> _<4:0>.

[0044] The third pre-pull-up driving unit 201-2 can generate a second data RDATAS <2> , the first driving strength control signal CONPU<4:0> and the first impedance control code PUCODE<4:0> to generate the first driving control signal PU <2> _<4:0>.

[0045] The fourth pre-pull-up driving unit 201-3 may be configured to drive the first pull-up driving unit 201-3 according to the second data RDATAS <2> , the first driving strength control signal CONPU<4:0> and the first impedance control code PUCODE<4:0> to generate the first driving control signal PU <3> _<4:0>.

[0046] The fifth pre-pull-up driving unit 201-4 may be configured to drive the first pre-pull-up driving unit 201-4 according to the second data RDATAS. <2> , the first driving strength control signal CONPU<4:0> and the first impedance control code PUCODE<4:0> to generate the first driving control signal PU <4> _<4:0>.

[0047] The first pre-pull-down driving unit 202-0 can use the second data FDATAS <0> , the second driving strength control signal CONPD<4:0> and the second impedance control code PDCODE<4:0> to generate the second driving control signal PD <0> _<4:0>.

[0048] The second pre-pull-down driving unit 202-1 can use the second data FDATAS <1> , the second driving strength control signal CONPD<4:0> and the second impedance control code PDCODE<4:0> to generate the second driving control signal PD <1> _<4:0>.

[0049] The third pre-pull-down driving unit 202-2 can use the second data FDATAS <2> , the second driving strength control signal CONPD<4:0> and the second impedance control code PDCODE<4:0> to generate the second driving control signal PD <2> _<4:0>.

[0050] The fourth pre-pull-down driving unit 202-3 may be configured to drive the first pull-down driving unit 202-3 according to the second data FDATAS. <2> , the second driving strength control signal CONPD<4:0> and the second impedance control code PDCODE<4:0> to generate the second driving control signal PD <3> _<4:0>.

[0051] The fifth pre-pull-down driving unit 202-4 may be configured to drive the first pull-down driving unit 202-4 according to the second data FDATAS. <2> , the second driving strength control signal CONPD<4:0> and the second impedance control code PDCODE<4:0> to generate the second driving control signal PD <4> _<4:0>.

[0052] Figure 4 It is shown Figure 3 FIG. 2 is a diagram of the fifth pull-up driving unit 201-4 in FIG.

[0053] The pre-pull-up driving units 201-0 to 201-4 may all have substantially the same configuration. Therefore, only the configuration of the fifth pre-pull-up driving unit 201-4 is shown.

[0054] Reference Figure 4 The fifth pre-pull-up driving unit 201 - 4 may include a code control circuit 210 and a driving control signal generating circuit 220 .

[0055] The code control circuit 210 may generate a first strength and impedance control signal TRIMPU<4:0> according to the first driving strength control signal CONPU<4:0> and the first impedance control code PUCODE<4:0>.

[0056] The code control circuit 210 may bypass the first impedance control code PUCODE<4:0> through the first strength and impedance control signal TRIMPU<4:0> according to the first driving strength control signal CONPU<4:0> or fix the first strength and impedance control signal TRIMPU<4:0> to a specific logic level.

[0057] The code control circuit 210 may include a plurality of code control units, ie, first to fifth code control units 211 ˜ 215 .

[0058] The first code control unit 211 can output the first driving strength control signal CONPU <0> With the first impedance control code PUCODE <0> The signal generated by AND operation is used as the first strength and impedance control signal TRIMPU <0> .

[0059] The second code control unit 212 can output the first driving strength control signal CONPU <1> With the first impedance control code PUCODE <1> The signal generated by the AND operation is used as the first strength and impedance control signal TRIMPU in the first strength and impedance control signal TRIMPU<4:0>. <1> .

[0060] The third code control unit 213 can output the first driving strength control signal CONPU <2> With the first impedance control code PUCODE <2> The signal generated by the AND operation is used as the first strength and impedance strength control signal TRIMPU<4:0> in the first strength and impedance control signal TRIMPU <2> .

[0061] The fourth code control unit 214 can output the first driving strength control signal CONPU <3> With the first impedance control code PUCODE <3> The signal generated by the AND operation is used as the first strength and impedance control signal TRIMPU in the first strength and impedance control signal TRIMPU<4:0>. <3> .

[0062] The fifth code control unit 215 can output the first driving strength control signal CONPU <4> With the first impedance control code PUCODE <4> The signal generated by the AND operation is used as the first strength and impedance control signal TRIMPU in the first strength and impedance control signal TRIMPU<4:0>. <4> .

[0063] In an example embodiment, the first to fifth code control units 211 to 215 may all have substantially the same configuration. Therefore, only the configuration of the first code control unit 211 is shown.

[0064] The first code control unit 211 may include a first logic gate 211 - 1 and a second logic gate 211 - 2 .

[0065] The first logic gate 211 - 1 may control the first driving strength control signal CONPU<4:0> in the first driving strength control signal CONPU <0> The first impedance control code PUCODE in the first impedance control code PUCODE<4:0> <0> Performs a negative AND operation.

[0066] The second logic gate 211-2 may output a signal generated by inverting the output of the first logic gate 211-1 as the first strength and impedance control signal TRIMPU <0> .

[0067] The driving control signal generating circuit 220 may generate a first strength and impedance control signal TRIMPU<4:0> and a second data RDATAS <2> To generate the first driving control signal PU <4> _<4:0>.

[0068] The driving control signal generating circuit 220 can generate a first driving control signal PU according to the first strength and impedance control signal TRIMPU<4:0>. <4> _<4:0> bypass second data RDATAS <2> Or fix the first driving control signal PU<4:0>_<4:0> to a specific logic level

[0069] The driving control signal generating circuit 220 may include a plurality of driving control signal generating units, ie, first to fifth driving control signal generating units 221 ˜ 225 .

[0070] The first driving control signal generating unit 221 may output the second data RDATAS <2> The inverted signal and the first strength and impedance control signal TRIMPU <0> The signal generated by AND operation is used as the first drive control signal PU <4> _ <0> .

[0071] The second driving control signal generating unit 222 may output the second data RDATAS <2> The inverted signal and the first strength and impedance control signal TRIMPU <1> The signal generated by AND operation is used as the first drive control signal PU <4> _ <1> .

[0072] The third driving control signal generating unit 223 may output the second data RDATAS <2> The inverted signal and the first strength and impedance control signal TRIMPU <2> The signal generated by AND operation is used as the first drive control signal PU <4> _ <2> .

[0073] The fourth driving control signal generating unit 224 may output the second data RDATAS <2> The inverted signal and the first strength and impedance control signal TRIMPU <3> The signal generated by AND operation is used as the first drive control signal PU <4> _ <3> .

[0074] The fifth driving control signal generating unit 225 may output the second data RDATAS <2> The inverted signal and the first strength and impedance control signal TRIMPU <4> The signal generated by AND operation is used as the first drive control signal PU <4> _ <4> .

[0075] In example embodiments, the first to fifth driving control signal generating units 221 to 225 may all have substantially the same configuration. Therefore, only the configuration of the first driving control signal generating unit 221 is shown.

[0076] The first driving control signal generating unit 221 may include a first logic gate 221 - 1 , a second logic gate 221 - 2 , and a third logic gate 221 - 3 .

[0077] The first logic gate 221 - 1 may be configured to convert the second data RDATAS <2> Invert and output.

[0078] The second logic gate 221-2 can combine the output of the first logic gate 221-1 with the first strength and impedance control signal TRIMPU <0> A NAND operation is performed to output the calculated signal.

[0079] The third logic gate 221 - 3 may be configured to invert the output of the second logic gate 221 - 2 to output the first driving control signal PU <4> _ <0> .

[0080] The fifth driving control signal generating unit 225 may have substantially the same configuration as that of the first driving control signal generating unit 221 except for the third logic gate 221 - 3 .

[0081] Figure 5 It is shown Figure 3 FIG. 2 is a diagram of the pre-pull-down driving unit 202 - 4 in FIG.

[0082] The pre-pull-down driving units 202-0 to 202-4 may all have substantially the same configuration. Therefore, only the configuration of the fifth pre-pull-down driving unit 202-4 is shown.

[0083] Reference Figure 5 The fifth pre-pull-down driving unit 202 - 4 may include a code control circuit 310 and a driving control signal generating circuit 320 .

[0084] The code control circuit 310 may generate a second strength and impedance control signal TRIMPD<4:0> according to the second driving strength control signal CONPD<4:0> and the second impedance control code PDCODE<4:0>.

[0085] The code control circuit 310 may bypass the second impedance control code PDCODE<4:0> or fix the second strength and impedance control signal TRIMPD<4:0> to a specific logic level according to the second driving strength control signal CONPD<4:0> through the second strength and impedance control signal TRIMPD<4:0>.

[0086] The code control circuit 310 may include a plurality of code control units, ie, first to fifth code control units 311 ˜ 315 .

[0087] The first code control unit 311 may output the second driving strength control signal CONPD<4:0> through the second driving strength control signal CONPD <0> and the second impedance control code PDCODE in the second impedance control code PDCODE<4:0> <0> The signal generated by the AND operation is used as the second strength and impedance control signal TRIMPD<4:0> in the second strength and impedance control signal TRIMPD <0> .

[0088] The second code control unit 312 may output the second driving strength control signal CONPD<4:0> through the second driving strength control signal CONPD <1> The second impedance control code PDCODE in the second impedance control code PDCODE<4:0> <1> The signal generated by the AND operation is used as the second strength and impedance control signal TRIMPD<4:0> in the second strength and impedance control signal TRIMPD <1> .

[0089] The third code control unit 313 may output the second driving strength control signal CONPD<4:0> through the second driving strength control signal CONPD <2> and the second impedance control code PDCODE in the second impedance control code PDCODE<4:0> <2> The signal generated by the AND operation is used as the second strength and impedance control signal TRIMPD<4:0> in the second strength and impedance control signal TRIMPD <2> .

[0090] The fourth code control unit 314 may output the second driving strength control signal CONPD<4:0> through the second driving strength control signal CONPD <3> and the second impedance control code PDCODE in the second impedance control code PDCODE<4:0> <3> The signal generated by the AND operation is used as the second strength and impedance control signal TRIMPD<4:0> in the second strength and impedance control signal TRIMPD <3> .

[0091] The fifth code control unit 315 may output the second driving strength control signal CONPD<4:0> through the second driving strength control signal CONPD <4> and the second impedance control code PDCODE in the second impedance control code PDCODE<4:0> <4> The signal generated by the AND operation is used as the second strength and impedance control signal TRIMPD<4:0> in the second strength and impedance control signal TRIMPD <4> .

[0092] In an example embodiment, the first to fifth code control units 311 to 315 may all have substantially the same configuration. Therefore, only the configuration of the first code control unit 311 is shown.

[0093] The first code control unit 311 may include a first logic gate 311 - 1 and a second logic gate 311 - 2 .

[0094] The first logic gate 311 - 1 may implement the second driving strength control signal CONPD<4:0> in the second driving strength control signal CONPD<4:0>. <0> The second impedance control code PDCODE in the second impedance control code PDCODE<4:0> <0> AND-NOT operation.

[0095] The second logic gate 311-2 may output a signal generated by inverting the output of the first logic gate 311-1 as the second strength and impedance control signal TRIMPD <0> .

[0096] The driving control signal generating circuit 320 may generate a second signal according to the second strength and impedance control signal TRIMPD<4:0> and the second data RDATAS <2> To generate the second driving control signal PD <4> _<4:0>.

[0097] The driving control signal generating circuit 320 can generate a second driving control signal PD according to the second strength and impedance control signal TRIMPD<4:0>. <4> _<4:0> bypass second data RDATAS <2> Or the second driving control signal PD<4:0>_<4:0> is fixed to a specific logic level.

[0098] The driving control signal generating circuit 320 may include a plurality of driving control signal generating units, ie, first to fifth driving control signal generating units 321 ˜ 325 .

[0099] The first driving control signal generating unit 321 may output the second data RDATAS <2> The inverted signal and the second intensity and impedance control signal TRIMPD <0> The signal generated by AND operation is used as the second drive control signal PD <4> _ <0> .

[0100] The second driving control signal generating unit 322 may output the second data RDATAS <2> The inverted signal and the second intensity and impedance control signal TRIMPD <1> The signal generated by AND operation is used as the second drive control signal PD <4> _ <1> .

[0101] The third driving control signal generating unit 323 may output the second data RDATAS <2> The inverted signal and the second intensity and impedance control signal TRIMPD <2> The signal generated by AND operation is used as the second drive control signal PD <4> _ <2> .

[0102] The fourth driving control signal generating unit 324 may output the second data RDATAS <2> The inverted signal and the second intensity and impedance control signal TRIMPD <3> The signal generated by AND operation is used as the second drive control signal PD <4> _ <3> .

[0103] The fifth driving control signal generating unit 325 may output the second data RDATAS <2> The inverted signal and the second intensity and impedance control signal TRIMPD <4> The signal generated by AND operation is used as the second drive control signal PD <4> _ <4> .

[0104] In an example embodiment, the first to fifth driving control signal generating units 321 to 325 may all have substantially the same configuration. Therefore, only the configuration of the first driving control signal generating unit 321 is shown.

[0105] The first driving control signal generating unit 321 may include a first logic gate 321 - 1 , a second logic gate 321 - 2 , and a third logic gate 321 - 3 .

[0106] The first logic gate 321 - 1 may be configured to convert the second data RDATAS <2> Invert and output.

[0107] The second logic gate 321 - 2 can compare the output of the first logic gate 321 - 1 with the second strength and impedance control signal TRIMPD <0> Perform a NAND operation to output the calculated signal.

[0108] The third logic gate 321 - 3 may be configured to invert the output of the second logic gate 321 - 2 to output the second driving control signal PD <4> _ <0> .

[0109] Figure 6 It is shown Figure 1 FIG. 104 is a diagram of the main drive 103 in FIG.

[0110] Reference Figure 6 , the main driver 103 may include a first driver 410 and a second driver 420 commonly connected to the output terminal DQ.

[0111] The first driver 410 may pull up the output terminal DQ to satisfy the first driving control signal PU <4> _<4:0> Determines the termination impedance and drive strength.

[0112] The second driver 420 may pull down the output terminal DQ to satisfy the second driving control signal PD <4> _<4:0> determines the termination impedance and drive strength.

[0113] The first driver 410 may include a plurality of pull-up legs 410 - 0 ˜ 410 -P.

[0114] The pull-up branches 410 - 0 ˜ 410 -P may be designed for a combination of impedance values ​​to achieve a driving strength and a termination impedance determined in the specifications of the semiconductor device.

[0115] The number of pull-up branches 410 - 0 ˜ 410 -P and the target impedance of each of the pull-up branches 410 - 0 ˜ 410 -P may be determined according to the specifications of the semiconductor device.

[0116] For the first driving control signal PU <4> _<4:0> The allocation method to the pull-up branches 410-0 to 410-P may be determined according to the specifications of the semiconductor device.

[0117] Each of the signal components of the first driving control signal PU<4:0>_<4:0> may be input to a portion of the pull-up branches 410-0~410-P in a one-to-one relationship. At least one of the signal components of the first driving control signal PU<4:0>_<4:0> may be commonly input to another portion of the pull-up branches 410-0~410-P.

[0118] The second driver 420 may include a plurality of pull-down branches 420 - 0 ˜ 420 -Q.

[0119] The pull-down branches 420 - 0 ˜ 420 -Q may be designed for a combination of impedance values ​​to achieve a driving strength and a termination impedance determined in the specifications of the semiconductor device.

[0120] The number of the pull-down branches 420 - 0 ˜ 420 -Q and the target impedance of each of the pull-down branches 420 - 0 ˜ 420 -Q may be determined according to the specifications of the semiconductor device.

[0121] The second driving control signal PD <4> _<4:0> The allocation method of the pull-down branches 420-0 to 420-Q may be determined according to the specifications of the semiconductor device.

[0122] Each of the signal components of the second driving control signal PD<4:0>_<4:0> may be input to a portion of the pull-down branches 420-0 to 420-Q in a one-to-one relationship. At least one of the signal components of the second driving control signal PD<4:0>_<4:0> may be commonly input to another portion of the pull-down branches 420-0 to 420-Q.

[0123] Figure 7 It is shown Figure 1 FIG. 1 is a diagram of an impedance calibration circuit 105 .

[0124] exist Figure 7 In the embodiment, when the resistance of the external resistor 109 may be about 300 ohm, the impedance calibration circuit 105 may be designed to achieve the driving strength and the termination impedance determined according to the specifications of the semiconductor device.

[0125] Reference Figure 7 The impedance calibration circuit 105 may include: a reference voltage generating circuit (VREF Gen) 431, a first reproduction branch 432, a first code generating circuit 433, a second reproduction branch 435, a third reproduction branch 436 and a second code generating circuit 437.

[0126] The reference voltage generating circuit 431 may be configured to generate a reference voltage VREF. For example, the reference voltage VREF may be half of the power supply voltage.

[0127] The first reproduction branch 432 may have an impedance controlled according to the first impedance control code PUCODE<4:0>.

[0128] The first reproduction branch 432 may be designed to have a first target value, ie, an impedance of about 300 ohm, which is substantially the same as the resistance of the external resistor 109 .

[0129] For example, the first reproduction branch 432 may be formed by reproducing any one of the pull-up branches 410 - 0 ˜ 410 -P.

[0130] The first reproduction branch 432 may be connected to the external resistor 109 via the external resistor pad 107 .

[0131] The first code generation circuit 433 may be configured to control a value of the first impedance control code PUCODE<4:0> according to a comparison result between a voltage of a node that may be connected to the first reproduction branch 432 and the external resistor 109 and a reference voltage VREF.

[0132] The first code generating circuit 433 may include a first comparator 433 - 1 and a first counter 433 - 2 .

[0133] The first comparator 433-1 may compare a voltage of a node connected to the first reproduction branch 432 and the external resistor 109 with a reference voltage VREF. Then, the first comparator 433-1 may output a comparison result.

[0134] The first counter 433 - 2 may control the value of the first impedance control code PUCODE<4:0> according to the output from the first comparator 433 - 1 .

[0135] The second reproduction branch 435 may have an impedance controlled according to the first impedance control code PUCODE<4:0>.

[0136] The second reproduction branch 435 may be designed to have a first target value, ie, an impedance of about 300 ohm, which is substantially the same as the resistance of the external resistor 109 .

[0137] The second reproduction branch 435 may have substantially the same configuration as that of the first reproduction branch 432 .

[0138] The third reproduction branch 436 may have an impedance controlled according to the second impedance control code PDCODE<4:0> For example, the third reproduction branch 436 may be formed by reproducing any one of the pull-down branches 420-0420-Q.

[0139] The second code generating circuit 437 may be configured to control a value of the second impedance control code PDCODE<4:0> according to a comparison result between a voltage of a node that may be connected to the second reproduction branch 435 and the third reproduction branch 436 and a reference voltage VREF.

[0140] The second code generating circuit 437 may include a second comparator 437 - 1 and a second counter 437 - 2 .

[0141] The second comparator 437-1 may compare the voltage of the node connected to the second reproduction branch 435 and the third reproduction branch 436 with the reference voltage VREF. Then, the second comparator 437-1 may output the comparison result.

[0142] The second counter 437 - 2 may control the value of the second impedance control code PDCODE<4:0> according to the output from the second comparator 437 - 1 .

[0143] Hereinafter, the operation of the impedance calibration circuit 105 may be illustrated in detail.

[0144] Since the external resistor 109 may be disposed outside the semiconductor chip, the external resistor 109 may have a constant resistance (ie, approximately 300 ohm) regardless of an internal operating environment.

[0145] Therefore, an operation for controlling the impedance of the first reproduction branch 432 to the resistance of the external resistor 109 as a target value can be performed.

[0146] The voltage of the node connected to the first reproduction branch 432 and the external resistor 109 may be compared with the reference voltage VREF. When the voltage of the node may coincide with the reference voltage VREF within an error range, the control of the first impedance control code PUCODE<4:0> may be completed.

[0147] Since the first impedance control code PUCODE<4:0> may be provided to the second reproduction branch 435 , control of the impedance of the second reproduction branch 435 may be completed simultaneously with completion of control of the first reproduction branch 432 .

[0148] An operation for controlling the impedance of the third reproduction branch 436 to be the impedance of the second reproduction branch 435 as a target value may then be performed.

[0149] The voltage of the node connected to the second reproduction branch 435 and the third reproduction branch 436 may be compared with the reference voltage VREF. When the voltage of the node may coincide with the reference voltage VREF within an error range, the control of the second impedance control code PDCODE<4:0> may be completed.

[0150] Figure 8 is a diagram illustrating a data driving circuit 500 according to an example embodiment.

[0151] Reference Figure 8 , the data driving circuit 500 may include a trigger circuit 501 , a pre-driver 502 and a main driver 503 .

[0152] In addition, the data driving circuit 500 of this example embodiment may further include an impedance calibration circuit 505 .

[0153] The trigger circuit 501 may be configured to block the remaining signal paths, among a plurality of signal paths for transmitting data, except for a signal path for corresponding to a currently selected driving strength.

[0154] The trigger circuit 501 can block the second data RDATACON<J:0> and FDATACON<J:0> The remaining signal paths except the signal path corresponding to the currently selected driving strength among the plurality of signal paths of the drive signal path. The second data RDATACON may be generated by latching the plurality of first data RDATA and FDATA according to the plurality of clock signals RCLKDO and FCLKDO having a phase difference.<J:0> and FDATACON<J:0> .

[0155] The trigger circuit 501 can control the signal CONPU according to multiple driving strengths.<K:0> and CONPD<K:0> to determine the drive strength and the signal path corresponding to the drive strength.

[0156] The pre-driver 502 may use a plurality of impedance control codes PUCODE<L:0> and PDCODE<L:0> Determines the impedance to drive the second data RDATACON<J:0> and FDATACON<J:0> The data can be sent through the signal path selected by the trigger circuit 501 to output multiple driving control signals PU<M:0> _<N:0> and PD<M:0> _<N:0> .

[0157] The main driver 503 can control the<M:0> _<N:0> and PD<M:0> _<N:0> To drive the output terminal DQ.

[0158] The impedance calibration circuit 505 can control the impedance control code PUCODE<L:0> and PDCODE<L:0> The resistance of the external resistor 109 connected to the external resistor pad 107 is taken as a target value.

[0159] Fig. 9 It is shown Figure 8 FIG. 5 is a diagram of a trigger circuit 501 in FIG.

[0160] Fig. 9 shows that when the second data RDATACON<J:0> and FDATACON<J:0> When J is 2 and the drive strength control signal CONPU<K:0> and CONPD<K:0> , Impedance control code PUCODE<L:0> and PDCODE<L:0> And the drive control signal PU<M:0> _<N:0> Trigger circuit 501 when K, L, M and N are 4.

[0161] Reference Fig. 9 The trigger circuit 501 may include a first latch circuit 510 , a first signal distribution circuit 511 , a second latch circuit 520 , and a second signal distribution circuit 521 .

[0162] The first latch circuit 510 may latch the first data RDATA according to the first clock signal RCLKDO of the clock signals RCLKDO and FCLKDO to generate a first latch signal RDIN.

[0163] In example embodiments, the first signal distribution circuit 511 may include a plurality of first signal paths 511 - 0 ˜ 511 - 4 .

[0164] The first signal distribution circuit 511 may distribute the first latch signal RDIN to output the second data RDATACON<2:0> of the second data RDATACON<2:0> and FDATACON<2:0> through only a signal path selected according to the first driving strength control signal CONPU<4:0> among the first signal paths 511 - 0 ˜ 511 - 4 .

[0165] The first signal paths 511 - 0 ˜ 511 - 4 may all have substantially the same configuration. Therefore, any one 511 - 0 of the first signal paths 511 - 0 ˜ 511 - 4 may be shown here.

[0166] When the first driving strength control signal CONPU <0> When only at a high level, the signal path 511 - 0 can invert and output the first latch signal RDIN.

[0167] When the first driving strength control signal CONPU <0> When the signal path 511-0 can be low, the second data RDATACON <0> Fixed to a high level regardless of the logic level of the first latch signal RDIN.

[0168] Signal path 511 - 0 may include a NAND gate and an inverter chain.

[0169] The NAND gate can control the first driving strength control signal CONPU <0> A NAND operation is performed with the first latch signal RDIN.

[0170] The second latch circuit 520 may latch the first data FDATA according to a second clock signal FCLKDO among the clock signals RCLKDO and FCLKDO to generate a second latch signal FDIN.

[0171] The second signal distribution circuit 521 may include a plurality of second signal paths 521 - 0 ˜ 521 - 4 .

[0172] The second signal distribution circuit 521 may distribute the second latch signal FDIN to output the second data FDATACON<2:0> of the second data RDATACON<2:0> and FDATACON<2:0> through only a signal path selected according to the second driving strength control signal CONPD<4:0> among the second signal paths 521-0 to 521-4.

[0173] The second signal paths 521-0 to 521-4 may all have substantially the same configuration. Therefore, any one 521-0 of the second signal paths 521-0 to 521-4 may be shown here.

[0174] When the second driving strength control signal CONPD <0> When the voltage level is low, the signal path 521 - 0 can invert and output the second latch signal FDIN.

[0175] When the second driving strength control signal CONPD <0> When the signal path 521-0 can be high, the second data FDATACON <0> Fixed to a high level regardless of the logic level of the second latch signal FDIN.

[0176] The signal path 521 - 0 may include a NOR gate, a transmission gate, and an inverter.

[0177] The NAND gate can control the first driving strength control signal CONPU <0> A NAND operation is performed with the first latch signal RDIN.

[0178] The NOR gate can control the second driving strength control signal CONPD <0> A NOR operation is performed with the second latch signal FDIN.

[0179] The transmission gate may include a negative control terminal configured to receive a ground voltage and a positive control terminal configured to receive a power supply voltage.

[0180] The transmission gate may be configured to provide the signal path 521 - 0 with a signal delay time substantially the same as a signal delay time of the signal path 511 - 0 of the first signal distribution circuit 511 .

[0181] The inverter can invert the output of the NOR gate to output the second data FDATACON <0> .

[0182] Fig.10 It is shown Figure 8 FIG. 5 is a diagram of the pre-driver 502 in FIG.

[0183] Reference Fig.10 , the pre-driver 502 may include a plurality of pre-driver units 601 - 0 ˜ 601 - 4 and 602 - 0 ˜ 602 - 4 .

[0184] The pre-driving units 601-0~601-4 and 602-0~602-4 may be classified into a plurality of pre-pull-up driving units 601-0~601-4 and a plurality of pre-pull-down driving units 602-0 to 602-4.

[0185] The first pre-pull-up driving unit 601-0 can be based on the second data RDATACON <0> and the first impedance control code PUCODE<4:0> to generate the first drive control signal PU <0> _<4:0>.

[0186] The second pre-pull-up driving unit 601-1 can <1> and the first impedance control code PUCODE<4:0> to generate the first drive control signal PU <1> _<4:0>.

[0187] The third pre-pull-up driving unit 601-2 can be based on the second data RDATACON <2> and the first impedance control code PUCODE<4:0> to generate the first drive control signal PU <2> _<4:0>.

[0188] The fourth pre-pull-up driving unit 601-3 can be configured to drive the first pre-pull-up driving unit 601-3 according to the second data RDATACON <2> and the first impedance control code PUCODE<4:0> to generate the first drive control signal PU <3> _<4:0>.

[0189] The fifth pre-pull-up driving unit 601-4 may be configured to drive the first pre-pull-up driving unit 601-4 according to the second data RDATACON <2> and the first impedance control code PUCODE<4:0> to generate the first drive control signal PU <4> _<4:0>.

[0190] The first pre-pull-down driving unit 602-0 can be based on the second data FDATACON <0> and the second impedance control code PDCODE<4:0> to generate the second drive control signal PD <0> _<4:0>.

[0191] The second pre-pull-down driving unit 602-1 can be based on the second data FDATACON <1> and the second impedance control code PDCODE<4:0> to generate the second drive control signal PD <1> _<4:0>.

[0192] The third pre-pull-down driving unit 602-2 can be based on the second data FDATACON <2> and the second impedance control code PDCODE<4:0> to generate the second drive control signal PD <2> _<4:0>.

[0193] The fourth pre-pull-down driving unit 602-3 can be configured to drive the first pre-pull-down driving unit 602-3 according to the second data FDATACON <2> and the second impedance control code PDCODE<4:0> to generate the second drive control signal PD <3> _<4:0>.

[0194] The fifth pre-pull-down driving unit 602-4 may be configured to drive the first pre-pull-down driving unit 602-4 according to the second data FDATACON <2> and the second impedance control code PDCODE<4:0> to generate the second drive control signal PD <4> _<4:0>.

[0195] Fig.11 It is shown Fig.10 FIG. 6 is a diagram of the fifth pre-pull-up driving unit 601-4 in FIG.

[0196] The pre-pull-up driving units 601-0 to 601-4 may all have substantially the same configuration. Therefore, only the configuration of the fifth pull-up driving unit 601-4 is shown.

[0197] Reference Fig.11 , the fifth pre-pull-up driving unit 601 - 4 may include a plurality of code control units, ie, first to fifth code control units 611 to 615 .

[0198] The first code control unit 611 can output the second data RDATACON <4> The inverted signal of the first impedance control code PUCODE<4:0> is the same as the first impedance control code PUCODE <0> The signal generated by AND operation is used as the first drive control signal PU <4> _<4:0> The first drive control signal PU <4> _ <0> .

[0199] The second code control unit 612 can output the second data RDATACON <4> The inverted signal of the first impedance control code PUCODE<4:0> is the same as the first impedance control code PUCODE <1> The signal generated by AND operation is used as the first drive control signal PU <4> _<4:0> The first drive control signal PU <4> _ <1> .

[0200] The third code control unit 613 can output the second data RDATACON <4> The inverted signal of the first impedance control code PUCODE<4:0> is the same as the first impedance control code PUCODE <2> The signal generated by AND operation is used as the first drive control signal PU <4> _<4:0> The first drive control signal PU <4> _ <2> .

[0201] The fourth code control unit 614 can output the second data RDATACON <4> The inverted signal of the first impedance control code PUCODE<4:0> is the same as the first impedance control code PUCODE <3> The signal generated by AND operation is used as the first drive control signal PU <4> _<4:0> The first drive control signal PU <4> _ <3> .

[0202] The fifth code control unit 615 can output the second data RDATACON <4> The inverted signal of the first impedance control code PUCODE<4:0> is the same as the first impedance control code PUCODE <4> The signal generated by AND operation is used as the first drive control signal PU <4> _<4:0> The first drive control signal PU <4> _ <4> .

[0203] In an example embodiment, the first to fifth code control units 611 to 615 may all have substantially the same configuration. Therefore, only the configuration of the first code control unit 611 is shown.

[0204] The first code control unit 611 may include a first logic gate 611 - 1 , a second logic gate 611 - 2 , and a third logic gate 611 - 3 .

[0205] The first logic gate 611 - 1 may be configured to convert the second data RDATACON <4> Invert and output.

[0206] The second logic gate 611 - 2 can control the output of the first logic gate 611 - 1 and the first impedance control code PUCODE <0> A NAND operation is performed to output the calculated signal.

[0207] The third logic gate 611-3 may be configured to invert the output of the second logic gate 611-2 to output the first driving control signal PU <4> _ <0> .

[0208] The fifth code control unit 615 may have substantially the same configuration as that of the first code control unit 611 except for the third logic gate 611 - 3 .

[0209] Fig.12 It is shown Fig.10 FIG. 6 is a diagram of the fifth pre-pull-down driving unit 602-4 in FIG.

[0210] The pre-pull-down driving units 602-0 to 602-4 may all have substantially the same configuration. Therefore, only the configuration of the fifth pre-pull-down driving unit 602-4 is shown.

[0211] Reference Fig.12 , the fifth pre-pull-down driving unit 602 - 4 may include a plurality of code control units, ie, first to fifth code control units 621 ˜ 625 .

[0212] The first code control unit 621 can output the second data FDATACON <4> The inverted signal of the second impedance control code PDCODE<4:0> is the same as the second impedance control code PDCODE <0> The signal generated by AND operation is used as the second drive control signal PD <4> _<4:0> The second drive control signal PD <4> _ <0> .

[0213] The second code control unit 622 can output the second data FDATACON <4> The inverted signal of the second impedance control code PDCODE<4:0> is the same as the second impedance control code PDCODE <1> The signal generated by AND operation is used as the second drive control signal PD <4> _<4:0> The second drive control signal PD <4> _ <1> .

[0214] The third code control unit 623 can output the second data FDATACON <4> The inverted signal of the second impedance control code PDCODE<4:0> is the same as the second impedance control code PDCODE <2> The signal generated by AND operation is used as the second drive control signal PD <4> _<4:0> The second drive control signal PD <4> _ <2> .

[0215] The fourth code control unit 624 can output the second data FDATACON <4> The inverted signal of the second impedance control code PDCODE<4:0> is the same as the second impedance control code PDCODE <3> The signal generated by AND operation is used as the second drive control signal PD <4> _<4:0> The second drive control signal PD <4> _ <3> .

[0216] The fifth code control unit 625 can output the second data FDATACON <4> The inverted signal of the second impedance control code PDCODE<4:0> is the same as the second impedance control code PDCODE <4> The signal generated by AND operation is used as the second drive control signal PD <4> _<4:0> The second drive control signal PD <4> _ <4> .

[0217] In an example embodiment, the first to fifth code control units 621 to 625 may all have substantially the same configuration. Therefore, only the configuration of the first code control unit 621 is shown.

[0218] The first code control unit 621 may include a first logic gate 621 - 1 , a second logic gate 621 - 2 , and a third logic gate 621 - 3 .

[0219] The first logic gate 621 - 1 may be configured to convert the second data RDATACON <4> Invert and output.

[0220] The second logic gate 621 - 2 can generate a second impedance control code PDCODE from the output of the first logic gate 621 - 1 . <0> A NAND operation is performed to output a NAND operation signal.

[0221] The third logic gate 621 - 3 may be configured to invert the output of the second logic gate 621 - 2 to output the second driving control signal PD <4> _ <0> .

[0222] In an example embodiment, the main driver 503 may have Figure 6 Therefore, for the sake of brevity, any further illustration of the main driver 503 may be omitted.

[0223] In addition, the impedance calibration circuit 505 may have Figure 7 Therefore, for the sake of brevity, any further illustration of the impedance calibration circuit 505 may be omitted.

[0224] Hereinafter, the operation of the data driving circuit 500 may be illustrated in detail.

[0225] The trigger circuit 501 can select a signal path instead of a reference Fig. 9 All of the first signal paths 511-0 to 511-4 and the second signal paths 521-0 to 521-4 shown transmit the second data RDATAS that can be generated by latching the data RDATA and FDATA according to the clock signals RCLK and FCLK.<J:0> and FDATAS<J:0> .

[0226] The trigger circuit 501 may select at least one of the signal paths 511 - 0 ˜ 511 - 4 and 521 - 0 ˜ 521 - 4 according to the driving strength control signals CONPU<4:0> and CONPD<4:0>.

[0227] Unselected signal paths among the first signal paths 511 - 0 511 - 4 and the second signal paths 521 - 0 521 - 4 may be fixed to a specific logic level to reduce current consumption.

[0228] The pre-driver 502 may apply the impedance control codes PUCODE<4:0> and PDCODE<4:0> to the second data RDATAS transmitted through the selected signal path.<J:0> and FDATA<J:0> to generate driving control signals PU<4:0>_<4:0> and PD<4:0>_<4:0>.

[0229] The main driver 503 may drive the output terminal DQ to meet the termination impedance and driving strength determined according to the driving control signals PU<4:0>_<4:0> and PD<4:0>_<4:0>.

[0230] The above embodiments of the present teachings are intended to illustrate rather than limit the present teachings. Various alternatives and equivalents are possible. The present teachings are not limited to the embodiments described herein. The present teachings are also not limited to any particular type of semiconductor device. Additions, reductions, or modifications based on the present disclosure are possible and are intended to fall within the scope of the appended claims.

[0231] CROSS-REFERENCE TO RELATED APPLICATIONS

[0232] This application claims the benefit of Korean Application No. 10-2019-0175034 filed on December 26, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A data driving circuit, the data driving circuit comprising: a trigger circuit configured to block remaining signal paths, except for a signal path corresponding to a currently selected driving strength, among a plurality of signal paths for transmitting data; as well as a pre-driver configured to drive data transmitted through the signal path corresponding to the currently selected driving strength using an impedance determined according to a plurality of impedance control codes, The trigger circuit is configured to block the remaining signal paths among multiple signal paths for sending multiple second data except the signal path corresponding to the currently selected driving strength, and the multiple second data are generated by latching multiple first data according to multiple clock signals with phase differences.

2. The data driving circuit according to claim 1, wherein: The trigger circuit comprises: a first latch circuit configured to latch any one of the first data according to the first clock signal to generate a first latch signal; a first signal distribution circuit configured to distribute the first latch signal only through a signal path selected according to a first driving strength control signal among a plurality of first signal paths among the signal paths, so as to output the distributed first latch signal as a part of a plurality of second data; a second latch circuit configured to latch another of the first data according to a second clock signal to generate a second latch signal; and a second signal distribution circuit configured to distribute the second latch signal only through a signal path selected according to a second driving strength control signal among a plurality of second signal paths among the signal paths, so as to output the distributed second latch signal as a part of the plurality of second data.

3. The data driving circuit according to claim 1, wherein: The pre-driver comprises: a plurality of pre-pull-up driving units configured to drive data transmitted through the signal path corresponding to the currently selected driving strength according to a first impedance control code among the impedance control codes; and A plurality of pre-pull-down driving units are configured to drive data transmitted through the signal path corresponding to the currently selected driving strength according to a second impedance control code among the impedance control codes. 4 . The data driving circuit according to claim 1 , further comprising a main driver configured to drive an output terminal according to an output from the trigger circuit.

5. The data driving circuit according to claim 4, wherein: The main driver comprises: a first driver configured to pull up the output terminal according to a first drive control signal in an output from the trigger circuit; and A second driver is configured to pull down the output terminal according to a second driving control signal in the output from the trigger circuit.

6. The data driving circuit according to claim 4, wherein: The main driver includes a plurality of pull-up branches and a plurality of pull-down branches commonly connected to the output terminal.

7. The data driving circuit according to claim 6, wherein: Respective signal components of the first drive control signals are input to a portion of the pull-up branch in a one-to-one relationship, and at least one of the first drive control signals is commonly input to another portion of the pull-up branch.

8. The data driving circuit according to claim 6, wherein: Respective signal components of the second drive control signals are input to a portion of the pull-down branch in a one-to-one relationship, and at least one of the second drive control signals is commonly input to another portion of the pull-down branch. 9 . The data driving circuit of claim 1 , further comprising an impedance calibration circuit configured to control the impedance control code using a resistance of an external resistor as a target value.

10. The data driving circuit according to claim 9, wherein: The impedance calibration circuit comprises: a first reproduction branch connected to the external resistor, the first reproduction branch having an impedance controlled according to a first impedance control code among the plurality of impedance control codes; a first code generating circuit configured to control a value of the first impedance control code according to a comparison result between a voltage of a first node connected to the first reproduction branch and the external resistor and a reference voltage; a second reproduction branch having an impedance controlled according to the first impedance control code; a third reproduction branch having an impedance controlled according to a second impedance control code among the plurality of impedance control codes; and A second code generating circuit configured to control a value of the second impedance control code according to a comparison result between a voltage of a second node connected to the second reproduction branch and the third reproduction branch and the reference voltage.

11. The data driving circuit according to claim 10, wherein: The first code generating circuit comprises: a comparator configured to compare the voltage of the first node with the reference voltage to output a comparison result; and A counter is configured to control a value of the first impedance control code according to an output from the comparator.

12. The data driving circuit according to claim 10, wherein: The second code generating circuit comprises: a comparator configured to compare the voltage of the second node with the reference voltage to output a comparison result; and A counter is configured to control a value of the second impedance control code according to an output from the comparator.

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