Mask pattern, semiconductor structure and forming method thereof

Abstract

A mask pattern, a semiconductor structure and a method for forming the same, wherein the mask pattern comprises: a first mask pattern, the first mask pattern comprises a plurality of first target patterns, the plurality of first target patterns are arranged along a first direction; a second mask pattern, the second mask pattern comprises a plurality of second target patterns, the plurality of second target patterns are arranged along the first direction; when the first mask pattern and the second mask pattern overlap, one first target pattern partially overlaps with one second target pattern. The pattern density of the mask pattern is good.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a mask pattern, a semiconductor structure and a forming method thereof. Background Art

[0002] At present, with the development of ultra-large-scale integrated circuits, device design sizes are getting smaller and smaller, and changes in the critical dimensions (CD) of devices have an increasing impact on device performance. For example, changes in the critical dimensions of gate structures will directly lead to changes in device operating speed.

[0003] Photolithography is a crucial technology in semiconductor manufacturing. It can transfer patterns from the mask to the surface of the silicon wafer to form semiconductor products that meet the design requirements. The photolithography process includes an exposure step, a development step after the exposure step, and an etching step after the development step.

[0004] Usually, a single photo-irradiation and etching process can meet the requirements of forming devices with larger critical dimensions. When the critical dimensions are smaller, self-aligned multiple patterning technology is required to meet the requirements of device dimensions.

[0005] However, when it is necessary to form both larger and smaller critical dimensions at the same time, when designing the mask pattern, there is not enough pattern density to meet the requirement of forming devices with smaller critical dimensions. Summary of the invention

[0006] The technical problem solved by the present invention is to provide a mask pattern, a semiconductor structure and a forming method thereof, so as to improve the pattern density in the mask pattern.

[0007] In order to solve the above technical problems, the technical solution of the present invention provides a mask pattern, including: a first mask pattern, the first mask pattern includes a plurality of first target patterns, and the first target patterns are arranged along a first direction; a second mask pattern, the second mask pattern includes a plurality of second target patterns, and the second target patterns are arranged along the first direction; when the first mask pattern and the second mask pattern overlap, one first target pattern partially overlaps with one second target pattern.

[0008] Optionally, along the first direction, each of the first target patterns has a first size, and there is a first spacing between adjacent first target patterns.

[0009] Optionally, along the first direction, each of the second target patterns has a second size, and there is a second interval between adjacent second target patterns.

[0010] Optionally, along the first direction, the second dimension ranges from 45 nanometers to 60 nanometers; and the first dimension ranges from 25 nanometers to 45 nanometers.

[0011] Optionally, along the first direction, the second dimension ranges from 100 nanometers to 200 nanometers; and the first dimension ranges from 100 nanometers to 200 nanometers.

[0012] Optionally, along the first direction, the size of the overlapping portion of the second target pattern and the first target pattern accounts for 40% to 60% of the first size, and the size of the non-overlapping portion of the second target pattern and the first target pattern accounts for 40% to 60% of the first spacing.

[0013] Optionally, along the first direction, the size of the overlapping portion of the second target pattern and the first target pattern accounts for 1 / 2 of the first size, and the size of the non-overlapping portion of the second target pattern and the first target pattern accounts for 1 / 2 of the first spacing.

[0014] Optionally, the first mask pattern further includes: a plurality of first main target patterns, and the plurality of first main target patterns are arranged along a first direction.

[0015] Optionally, the second mask pattern further includes: a plurality of second main target patterns, and the plurality of second main target patterns are arranged along the first direction.

[0016] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a sacrificial film on the substrate; providing a mask pattern, the mask pattern comprising: a first mask pattern, the first mask pattern comprising a plurality of first target patterns, the plurality of first target patterns being arranged along a first direction; a second mask pattern, the second mask pattern comprising a plurality of second target patterns, the plurality of second target patterns being arranged along the first direction; when the first mask pattern and the second mask pattern overlap, one of the first target patterns partially overlaps with one of the second target patterns; The sacrificial film is subjected to a first patterning process using the second mask pattern to form a plurality of mutually discrete sacrificial layers, and the positions and sizes of the plurality of sacrificial layers correspond to the positions and sizes of the second target pattern; a side wall is formed on the side wall surface of the sacrificial layer; after the side wall is formed, the sacrificial layer is removed; after the sacrificial layer is removed, a mask layer is formed on the substrate surface, and the top surface of the side wall and the side wall surface; the mask layer is subjected to a second patterning process using the first mask pattern to form a plurality of mutually discrete mask structures, and the positions and sizes of the plurality of mask structures correspond to the positions and sizes of the first target pattern.

[0017] Optionally, the mask structure covers at least one of the sidewalls; and there is at least one sidewall between adjacent mask structures.

[0018] Optionally, the method for forming the side wall includes: forming a side wall material film on the surface of the substrate, and the top surface and side wall surface of the sacrificial layer; etching back the side wall material film until the substrate surface and the top surface of the sacrificial layer are exposed, and forming the side wall on the side wall surface of the sacrificial layer.

[0019] Optionally, the method of performing a first patterning process on the sacrificial film using the second mask pattern includes: forming a first photoresist on the surface of the sacrificial film; performing an exposure process on the first photoresist using the second mask pattern to form an initial first patterning layer; performing a development process on the initial first patterning layer to form a first patterning layer; and performing an etching process on the sacrificial film using the first patterning layer as a mask until the substrate surface is exposed to form the sacrificial layer.

[0020] Optionally, the material of the sacrificial layer includes: amorphous silicon, amorphous carbon, polysilicon, silicon oxide, silicon oxycarbide or silicon oxyhydrogencarbide.

[0021] Optionally, the method of performing a second patterning process on the mask layer using a first mask pattern includes: forming a second photoresist on the surface of the mask layer; performing an exposure process on the second photoresist using the first mask pattern to form an initial second patterned layer; performing a development process on the initial second patterned layer to form a second patterned layer; using the second patterned layer as a mask, etching the mask layer until the substrate surface is exposed to form the mask structure.

[0022] Optionally, the material of the sidewall spacer includes silicon oxide, titanium dioxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide.

[0023] Optionally, the material of the mask layer includes: photoresist or an organic material containing carbon and oxygen.

[0024] Optionally, the method further includes: etching the substrate using the mask structure and the sidewalls as masks.

[0025] Correspondingly, the technical solution of the present invention also provides a semiconductor structure, including: a substrate; a plurality of side walls located on the substrate; a plurality of separate mask structures located on the substrate, the mask structure covers at least one of the side walls, and there is at least one side wall between adjacent mask structures.

[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0027] In a mask pattern provided by the technical solution of the present invention, the first mask pattern is used for single-shot illumination and etching process, thereby forming a device with a larger critical dimension. The second mask pattern is used for self-aligned multiple patterning process, thereby forming a device with a smaller critical dimension. Since along the first direction, the first target pattern and the second target pattern partially overlap, the space can be fully utilized, thereby satisfying that the pattern density of several first target patterns in the first mask pattern is good, and the pattern density of several second target patterns in the second mask pattern is also good.

[0028] Furthermore, since the size of the overlapping portion of the second target pattern and the first target pattern accounts for 40% to 60% of the first size, and the size of the non-overlapping portion of the second target pattern and the first target pattern accounts for 40% to 60% of the first spacing, the subsequent use of the second mask pattern for self-aligned multiple patterning to form the sidewalls, and the use of the first mask pattern for single illumination and etching processes to form the mask structure, is conducive to a portion of the sidewalls being located between adjacent mask structures, and a portion of the sidewalls overlapping the mask structure, that is, the projection of a portion of the sidewalls on the substrate surface is located within the projection of the mask structure on the substrate surface. At the same time, the pattern density of the second mask pattern is good, and the pattern density of the first mask pattern is good, so that the first patterning process is performed with the second mask pattern, and the second patterning process is performed with the first mask pattern, the pattern density formed is good, and the sidewalls located between adjacent mask structures are finally transferred to the substrate to form a device with a smaller critical size and better uniformity, and the sidewalls overlapping the mask structure are finally transferred to the substrate with the mask structure as a mask to form a device with a larger critical size and better uniformity.

[0029] In the method for forming a semiconductor structure provided by the technical solution of the present invention, since the pattern density of the first mask pattern is good, the stability of the second patterning process using the first mask pattern is good, and there are fewer defects, so that the uniformity of the formed pattern is good. Since the pattern density of the second mask pattern is good, the stability of the first patterning process using the second mask pattern is good, and there are fewer defects, so that the uniformity of the formed pattern is good, so that the performance of the formed semiconductor structure is better. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a structural schematic diagram of a mask pattern;

[0031] Figure 2 It is a schematic diagram of the structure of another mask pattern;

[0032] Figure 3 is a schematic structural diagram of a mask pattern in one embodiment of the present invention;

[0033] Figures 4 to 12 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0034] As described in the background art, the pattern density and uniformity of existing mask patterns are relatively poor.

[0035] The following is a detailed description with reference to the accompanying drawings.

[0036] Figure 1 It is a structural diagram of a mask pattern.

[0037] Please refer to Figure 1 A mask pattern 100 includes: a plurality of first target patterns 110, wherein the plurality of first target patterns 110 are arranged along a first direction X.

[0038] A single photoirradiation and etching process is performed using the mask pattern 100 to form a device with a larger feature size. In order to form a device with a smaller feature size at the same time, another mask pattern is designed on this basis, which is described in detail below with reference to the accompanying drawings.

[0039] Figure 2 It is a schematic diagram of the structure of another mask pattern.

[0040] Please refer to Figure 2 A mask pattern comprises: a first mask pattern 120, wherein the first mask pattern 120 comprises a plurality of first target patterns 121, and the plurality of first target patterns 121 are arranged along a first direction X; a second mask pattern 130, wherein the second mask pattern 130 comprises a plurality of second target patterns 131, and the plurality of second target patterns 131 are arranged along the first direction X, and the second target patterns 131 and the first target patterns 121 do not overlap.

[0041] The first mask pattern 120 is used for a single illumination and etching process to form a device with a larger critical dimension, and the second mask pattern 130 is used for a self-aligned multiple patterning process to form a device with a smaller critical dimension, thereby meeting the process requirements for forming two types of critical dimension devices.

[0042] However, the control Figure 1 and Figure 2In order to form a device with a smaller critical dimension, part of the position of the first target pattern 121 is used to form the second target pattern 131, that is, the second target pattern 131 occupies the position of the first mask pattern 120 that can be used to form the first target pattern 121, resulting in poor pattern density and uniformity in the first mask pattern 120, poor pattern density and uniformity in the second mask pattern 130, and poor stability of the etching process using the first mask pattern 120, and poor stability of the etching process using the second mask pattern 130.

[0043] In order to solve the technical problem, an embodiment of the present invention provides a mask pattern, including: a first mask pattern, the first mask pattern includes a plurality of first target patterns, and the plurality of first target patterns are arranged along a first direction; a second mask pattern, the second mask pattern includes a plurality of second target patterns, and the plurality of first target patterns are arranged along the first direction; along the first direction, one first target pattern partially overlaps with one second target pattern, and the first direction is perpendicular to the first direction. The pattern density of the mask pattern is good.

[0044] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0045] Figure 3 It is a schematic structural diagram of a mask pattern in one embodiment of the present invention.

[0046] Please refer to Figure 3 A mask pattern comprises: a first mask pattern 200, wherein the first mask pattern 200 comprises a plurality of first target patterns 210, and the plurality of first target patterns 210 are arranged along a first direction X; a second mask pattern 300, wherein the second mask pattern 300 comprises a plurality of second target patterns 310, and the plurality of second target patterns 310 are arranged along the first direction X; when the first mask pattern 200 and the second mask pattern 300 overlap, one first target pattern 210 partially overlaps with one second target pattern 310.

[0047] The first mask pattern 200 is used for single-shot illumination and etching process, thereby forming a device with a larger critical dimension. The second mask pattern 300 is used for self-aligned multiple patterning process, thereby forming a device with a smaller critical dimension. Since along the first direction X, the first target pattern 210 and the second target pattern 310 partially overlap, the space can be fully utilized, thereby satisfying that the pattern density of several first target patterns 210 in the first mask pattern 200 is good, and the pattern density of several second target patterns 310 in the second mask pattern 300 is also good.

[0048] The following is a detailed description with reference to the accompanying drawings.

[0049] Along the first direction X, each of the first target patterns 210 has a first size W1 , and a first distance L1 exists between adjacent first target patterns 210 .

[0050] Along the first direction X, each of the second target patterns 310 has a second size W2, and a second interval L2 exists between adjacent second target patterns 310 .

[0051] Along the first direction X, the size of the overlapping portion of the second target pattern 310 and the first target pattern 210 accounts for 40% to 60% of the first size, and the size of the non-overlapping portion of the second target pattern and the first target pattern accounts for 40% to 60% of the first spacing.

[0052] Since the size of the overlapping portion of the second target graphic 310 and the first target graphic 210 accounts for 40% to 60% of the first size W1, and the size of the non-overlapping portion of the second target graphic 310 and the first target graphic 210 accounts for 40% to 60% of the first spacing L1, the second mask graphic 300 is subsequently used to perform self-aligned multiple patterning to form side walls, and the first mask graphic 200 is used to perform a single illumination and etching process to form a mask structure, which is beneficial for a portion of the side wall to be located between adjacent mask structures and a portion of the side wall to overlap with the mask structure, that is, the projection of a portion of the side wall on the substrate surface is located within the projection of the mask structure on the substrate surface. At the same time, the pattern density of the second mask plate graphic 300 is better, and the pattern density of the first mask plate graphic 200 is better. Therefore, when the second mask plate graphic 310 is used for the first patterning process, and the first mask plate graphic 200 is used for the second patterning process, the pattern densities formed are both better, and the side walls located between adjacent mask structures are eventually transferred to the substrate to form devices with smaller critical dimensions and better uniformity, and the side walls overlapping with the mask structure are eventually transferred to the substrate using the mask structure as a mask to form devices with larger critical dimensions and better uniformity.

[0053] Since the size of the overlapping portion of the second target pattern 310 and the first target pattern 210 accounts for 40% to 60% of the first size W1, and the size of the non-overlapping portion of the second target pattern 310 and the first target pattern 210 accounts for 40% to 60% of the first spacing L1, the subsequent use of the second mask pattern 310 for self-aligned multiple patterning to form the sidewall is conducive to a portion of the sidewall being located within the first spacing L1, and a portion of the sidewall overlapping with the first target pattern 210, that is, a portion of the sidewall being located within the first target pattern 210. At the same time, the pattern density of the second mask pattern 300 is good, and the pattern density of the first mask pattern 200 is good, so that after a portion of the sidewall overlaps with the first target pattern 210 in the first mask pattern 200, the pattern density formed is good, so that the sidewall located within the first spacing L1 is finally transferred to the substrate to form a device with a smaller critical size and better uniformity, and the sidewall overlapping with the first target pattern 210 is finally transferred to the substrate using the first target pattern 210 as a mask to form a device with a larger critical size and better uniformity.

[0054] In this embodiment, along the first direction X, the size of the overlapping portion of the second target pattern 310 and the first target pattern 310 accounts for 1 / 2 of the first size W1, and the size of the non-overlapping portion of the second target pattern 310 and the first target pattern 210 accounts for 1 / 2 of the first spacing L1.

[0055] In this embodiment, along the first direction X, the second size W2 ranges from 100 nanometers to 200 nanometers; and the first size W1 ranges from 100 nanometers to 200 nanometers.

[0056] In another embodiment, along the first direction, the second dimension ranges from 45 nanometers to 60 nanometers; and the first dimension ranges from 25 nanometers to 45 nanometers.

[0057] The first mask pattern 200 further includes: a plurality of first main target patterns (not shown in the figure), and the plurality of first main target patterns are arranged along a first direction X.

[0058] The second mask pattern 200 further includes: a plurality of second main target patterns (not shown in the figure), and the plurality of second main target patterns are arranged along the first direction.

[0059] It should be noted that, when the first mask pattern is used for photolithography, the device formed by the first main target pattern has electrical function, while the device formed by the first target pattern does not have electrical function. The first target pattern is used to increase the pattern density of the first mask pattern.

[0060] Similarly, when the second mask pattern is used for photolithography, the device formed by the second main target pattern has electrical function, while the device formed by the second target pattern does not have electrical function. The second target pattern is used to increase the pattern density of the second mask pattern.

[0061] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure.

[0062] Figures 4 to 12 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0063] Please refer to Figure 4 , providing a substrate 400.

[0064] In this embodiment, the base 400 includes a substrate 401 and a hard mask layer 202 located on the surface of the substrate 401 .

[0065] In this embodiment, the material of the substrate 401 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0066] The material of the hard mask layer 402 includes silicon oxide, silicon nitride, titanium nitride, silicon carbon oxynitride or silicon oxynitride.

[0067] In this embodiment, the hard mask layer 402 is a single-layer structure, and the material of the hard mask layer 402 is silicon oxide.

[0068] Please refer to Figure 5 , a sacrificial film 410 is formed on the substrate 400 .

[0069] The sacrificial film 410 is used to provide material for subsequently forming a sacrificial layer.

[0070] In this embodiment, the sacrificial film 410 is formed on the surface of the hard mask layer 402 .

[0071] The material of the sacrificial film 410 includes: amorphous silicon, amorphous carbon, polysilicon, silicon oxide, silicon oxycarbide or silicon oxyhydrogencarbide.

[0072] Please refer to Figure 6 , providing any of the mask patterns described above, and using the second mask pattern 300 to perform a first patterning process on the sacrificial film 410 to form a plurality of mutually discrete sacrificial layers 420, and the positions and sizes of the plurality of sacrificial layers 420 correspond to the positions and sizes of the second target pattern 310.

[0073] The sacrificial layer 420 is used to provide support for the subsequent self-aligned multi-patterning process to form the sidewalls.

[0074] Since the pattern density of the second mask pattern 300 is better, the stability of the first patterning process using the second mask pattern 300 is better and there are fewer defects, so that the formed pattern has better uniformity, that is, the size uniformity of the formed sacrificial layer 420 is better, and then the size uniformity of the sidewalls subsequently formed on the sidewalls of the sacrificial layer 420 is also better.

[0075] The method of performing the first patterning process on the sacrificial film 410 using the second mask pattern 300 includes: forming a first photoresist (not shown in the figure) on the surface of the sacrificial film 410; performing an exposure process on the first photoresist using the second mask pattern to form an initial first patterned layer (not shown in the figure); performing a development process on the initial first patterned layer to form a first patterned layer; and performing an etching process on the sacrificial film 410 using the first patterned layer as a mask until the surface of the substrate 400 is exposed to form the sacrificial layer 420.

[0076] In this embodiment, after forming the sacrificial layer 420 , the method further includes: removing the first patterned layer.

[0077] Next, a side wall is formed on the side wall surface of the sacrificial layer. For the specific process of forming the side wall, please refer to Figures 7 and 8 .

[0078] Please refer to Figure 7 A spacer material film 430 is formed on the surface of the substrate 400 and the top surface and sidewall surface of the sacrificial layer 420 .

[0079] The spacer material film 430 is used for forming spacers later.

[0080] The material of the spacer material film 430 includes silicon oxide, titanium dioxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide, or silicon nitride oxide.

[0081] In this embodiment, the material of the spacer material film 430 is titanium dioxide.

[0082] The formation process of the spacer material film 430 includes: chemical vapor deposition process, physical vapor deposition process or atomic layer deposition process.

[0083] Please refer to Figure 8 , the sidewall material film 430 is etched back until the surface of the substrate 400 and the top surface of the sacrificial layer 420 are exposed, and the sidewall 431 is formed on the sidewall surface of the sacrificial layer 420 .

[0084] The thickness of the spacer 431 determines the size of the smaller critical dimension that is ultimately formed.

[0085] It should be noted that the thickness of the side wall 431 also needs to be smaller than the distance between the adjacent first target pattern and the second target pattern.

[0086] Since the sidewall spacer 431 is formed by etching back the sidewall material film 430 , the material of the sidewall spacer 431 includes silicon oxide, titanium dioxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide, or silicon nitride oxide.

[0087] In this embodiment, the sidewall 431 is made of titanium dioxide.

[0088] Please refer to Fig. 9 After forming the sidewall 431 , the sacrificial layer 420 is removed.

[0089] The process of removing the sacrificial layer 420 includes: a dry etching process and a wet etching process, or a combination of the two.

[0090] In this embodiment, the etching process for removing the sacrificial layer 420 is an anisotropic dry etching process.

[0091] Please refer to Fig.10 After removing the sacrificial layer 420 , a mask layer 440 is formed on the surface of the substrate 400 , and the top surface and sidewall surface of the sidewall 431 .

[0092] The top surface of the mask layer 440 is higher than or flush with the top surface of the sidewall 431 , and the mask layer 440 provides a flat surface for the subsequent second patterning process.

[0093] In this embodiment, the top surface of the mask layer 440 is higher than the top surface of the sidewall spacer 431 .

[0094] The mask layer 440 and the sidewall spacer 431 are made of different materials.

[0095] The material of the mask layer 440 includes: photoresist or organic material containing carbon and oxygen.

[0096] In this embodiment, the material of the mask layer 440 is an organic material containing carbon and oxygen, and the mask layer 440 is formed by a spin coating process.

[0097] Please refer to Fig.11 The mask layer 440 is subjected to a second patterning process using the first mask pattern 200 to form a plurality of separate mask structures 450 , and the positions and sizes of the plurality of mask structures 450 correspond to the positions and sizes of the first target pattern 210 .

[0098] Since a plurality of first target patterns 210 in the first mask pattern 200 have a first size W1 and a first spacing L1 exists between adjacent first target patterns 210 , the formed mask structure 450 has a first size W1 and a first spacing L1 exists between adjacent mask structures 450 .

[0099] The mask structure 450 covers at least one of the sidewalls 431 ; and there is at least one sidewall 431 between adjacent mask structures 450 .

[0100] In this embodiment, the mask structure 450 covers one of the sidewalls 431 ; there is a sidewall 431 between adjacent mask structures 450 .

[0101] The method of performing a second patterning process on the mask layer 440 using the first mask pattern 200 includes: forming a second photoresist (not shown in the figure) on the surface of the mask layer 440; performing an exposure process on the second photoresist using the first mask pattern 200 to form an initial second patterned layer (not shown in the figure); performing a development process on the initial second patterned layer to form a second patterned layer (not shown in the figure); using the second patterned layer as a mask, etching the mask layer 440 until the surface of the substrate 400 is exposed to form the mask structure 450.

[0102] In this embodiment, the top surface of the mask structure 450 is flush with the top surface of the spacer 431. In other embodiments, the mask structure covers the top surface of the spacer and the sidewall surface.

[0103] The mask layer 440 is subjected to a second patterning process using the first mask pattern 200 to transfer the pattern in the first mask pattern 200 to the mask layer 440 to form the mask structure 450 . The mask structure 450 and the sidewall 431 together serve as a mask for subsequent etching of the substrate 400 .

[0104] Since the pattern density of the first mask pattern 200 is good, the stability of the second patterning process using the first mask pattern 200 is good, and there are fewer defects, so that the formed pattern has good uniformity, that is, the size uniformity of the formed mask structure 450 is good. In addition, the size uniformity of the sidewall 431 is also good, which is beneficial to the stability of the pattern transfer during the second patterning process.

[0105] Please refer to Fig.12 , using the mask structure 450 and the sidewall 431 as masks, the substrate 400 is etched.

[0106] In this embodiment, the hard mask layer 402 and the portion of the substrate 401 located at the bottom of the hard mask layer 402 are etched using the mask structure 450 and the sidewall 431 as masks, thereby achieving pattern transfer and forming a semiconductor structure 460. The semiconductor structure 460 includes: a first structure (not shown in the figure) formed by pattern transfer using the sidewall 431 as a mask, the first structure having a smaller critical dimension, and a second structure (not shown in the figure) formed by pattern transfer using the mask structure 450 as a mask, the second structure having a larger critical dimension, and the semiconductor structure thus formed includes: devices of two critical dimensions.

[0107] Since the size of the overlapping portion of the second target graphic 310 and the first target graphic 210 accounts for 40% to 60% of the first size W1, and the size of the non-overlapping portion of the second target graphic 310 and the first target graphic 210 accounts for 40% to 60% of the first spacing L1, the second mask graphic 300 is used to perform self-aligned multiple patterning to form the side wall 431, and the first mask graphic 200 is used to perform a single illumination and etching process to form the mask structure 450, which is beneficial for a portion of the side wall 431 to be located between adjacent mask structures 450, and a portion of the side wall 431 overlaps with the mask structure 450, that is, the projection of a portion of the side wall 431 on the surface of the substrate 400 is located within the projection of the mask structure 450 on the surface of the substrate 400. At the same time, the pattern density of the second mask graphic 300 is better, and the pattern density of the first mask graphic 200 is better. Therefore, the first patterning process is performed with the second mask graphic 310, and the second patterning process is performed with the first mask graphic 200. The pattern densities formed are both good, and the side walls 431 located between adjacent mask structures 450 are eventually transferred to the substrate 400 to form a device with a smaller critical dimension and better uniformity. The side walls 431 overlapping with the mask structure 450 are eventually transferred to the substrate 400 using the mask structure 450 as a mask to form a device with a larger critical dimension and better uniformity.

[0108] Accordingly, the embodiment of the present invention further provides a semiconductor structure formed by the above method, please refer to Fig.11 , including: a substrate 400; a plurality of sidewalls 431 located on the substrate 400; a plurality of separate mask structures 450 located on the substrate 400, wherein the mask structure 450 covers at least one of the sidewalls 431, and there is at least one sidewall 431 between adjacent mask structures 450.

[0109] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A mask pattern, It is characterized in that include: A first mask pattern, wherein the first mask pattern includes a plurality of first target patterns, and the plurality of first target patterns are arranged along a first direction; A second mask pattern, wherein the second mask pattern includes a plurality of second target patterns, and the plurality of second target patterns are arranged along a first direction; When the first mask pattern and the second mask pattern overlap, one of the first target patterns only partially overlaps one of the second target patterns; Along the first direction, there is a first spacing between adjacent first target patterns; Along the first direction, the size of the non-overlapping portion of the second target pattern and the first target pattern is smaller than the first spacing; Along the first direction, each of the first target graphics has a first size; Along the first direction, each of the second target patterns has a second size; The thickness of the side wall is smaller than the distance between the second target pattern and the first target pattern; Along the first direction, the size of the overlapping portion of the second target pattern and the first target pattern accounts for 40% to 60% of the first size, and the size of the non-overlapping portion of the second target pattern and the first target pattern accounts for 40% to 60% of the first spacing.

2. The mask pattern according to claim 1, It is characterized in that There is a second interval between adjacent second target patterns.

3. The mask pattern according to claim 2, It is characterized in that Along the first direction, the second dimension ranges from 45 nanometers to 60 nanometers; and the first dimension ranges from 25 nanometers to 45 nanometers.

4. The mask pattern according to claim 2, It is characterized in that Along the first direction, the second dimension ranges from 100 nanometers to 200 nanometers; and the first dimension ranges from 100 nanometers to 200 nanometers.

5. The mask pattern according to claim 1, It is characterized in that Along the first direction, the size of the overlapping portion of the second target pattern and the first target pattern accounts for 1 / 2 of the first size, and the size of the non-overlapping portion of the second target pattern and the first target pattern accounts for 1 / 2 of the first spacing.

6. The mask pattern according to claim 1, It is characterized in that The first mask pattern further includes: a plurality of first main target patterns, and the plurality of first main target patterns are arranged along a first direction.

7. The mask pattern according to claim 1, It is characterized in that The second mask pattern further includes: a plurality of second main target patterns, and the plurality of second main target patterns are arranged along a first direction.

8. A method for forming a semiconductor structure, It is characterized in that include: providing a substrate; forming a sacrificial film on the substrate; Provide a mask pattern, the mask pattern including: a first mask pattern including a plurality of first target patterns arranged along a first direction; a second mask pattern including a plurality of second target patterns arranged along the first direction; when the first mask pattern and the second mask pattern overlap, one of the first target patterns only partially overlaps with one of the second target patterns; along the first direction, there is a first spacing between adjacent first target patterns; along the first direction, the size of the non-overlapping part of the second target pattern and the first target pattern is smaller than the first spacing; Use the second mask pattern to perform a first patterning process on the sacrificial film to form a plurality of discrete sacrificial layers, and the positions and sizes of the plurality of sacrificial layers correspond to the positions and sizes of the second target patterns; Form sidewalls on the sidewall surfaces of the sacrificial layers; along the first direction, each of the first target patterns has a first size; along the first direction, each of the second target patterns has a second size; The thickness of the sidewall is smaller than the distance between adjacent second target patterns and first target patterns; along the first direction, the proportion range of the size of the overlapping part of the second target pattern and the first target pattern to the first size is 40% - 60%, and the proportion range of the size of the non-overlapping part of the second target pattern and the first target pattern to the first spacing is 40% - 60%; After forming the sidewalls, remove the sacrificial layers; After removing the sacrificial layers, form a mask layer on the surface of the substrate, as well as on the top surface and sidewall surfaces of the sidewalls; Use the first mask pattern to perform a second patterning process on the mask layer to form a plurality of discrete mask structures, and the positions and sizes of the plurality of mask structures correspond to the positions and sizes of the first target patterns; The mask structures cover at least one of the sidewalls; there is at least one sidewall between adjacent mask structures; Use the mask structures and sidewalls as masks to etch the substrate.

9. The method for forming a semiconductor structure according to claim 8, wherein, The method for forming the sidewalls includes: forming a sidewall material film on the surface of the substrate, as well as on the top surface and sidewall surfaces of the sacrificial layers; back-etching the sidewall material film until the surface of the substrate and the top surface of the sacrificial layers are exposed, and forming the sidewalls on the sidewall surfaces of the sacrificial layers.

10. The method for forming a semiconductor structure according to claim 8, wherein, The method for using the second mask pattern to perform a first patterning process on the sacrificial film includes: forming a first photoresist on the surface of the sacrificial film; using the second mask pattern to perform an exposure process on the first photoresist to form an initial first patterned layer; performing a development process on the initial first patterned layer to form a first patterned layer; using the first patterned layer as a mask to etch the sacrificial film until the surface of the substrate is exposed, and forming the sacrificial layers.

11. The method for forming a semiconductor structure according to claim 8, wherein, The material of the sacrificial layer includes: amorphous silicon, amorphous carbon, polysilicon, silicon oxide, silicon oxycarbide or silicon oxyhydrogencarbide.

12. The method for forming a semiconductor structure according to claim 8, It is characterized in that The method of performing a second patterning process on the mask layer using a first mask pattern includes: forming a second photoresist on the surface of the mask layer; performing an exposure process on the second photoresist using the first mask pattern to form an initial second patterning layer; performing a development process on the initial second patterning layer to form a second patterning layer; and etching the mask layer using the second patterning layer as a mask until the substrate surface is exposed to form the mask structure.

13. The method for forming a semiconductor structure according to claim 8, It is characterized in that The mask layer and the sidewall are made of different materials; the material of the sidewall includes silicon oxide, titanium dioxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide.

14. The method for forming a semiconductor structure according to claim 8, It is characterized in that The material of the mask layer includes: photoresist or organic material containing carbon and oxygen.

15. A semiconductor structure formed by the method for forming a semiconductor structure according to any one of claims 8 to 14, It is characterized in that include: substrate; a plurality of side walls disposed on the base; A plurality of mutually separated mask structures are located on the substrate, wherein the mask structure covers at least one of the sidewalls, and at least one sidewall is provided between adjacent mask structures.

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