Three-dimensional semiconductor memory device

Abstract

A three-dimensional semiconductor memory device. The semiconductor memory device may include: a first pad layer located in a surface of a memory chip including a cell region and a step region, in which a memory cell array is connected to a plurality of row lines alternately stacked with a plurality of interlayer dielectric layers on a substrate, the step region extending from the cell region in a first direction parallel to a top surface of the substrate and including staggered step portions of the plurality of row lines, the first pad layer including a plurality of first pads connected to the step portions; a second pad layer located in a surface of a circuit chip bonded to the surface of the memory chip and having a plurality of second pads connected to a plurality of transfer transistors defined in the circuit chip; a first redistribution line disposed in the first pad layer and connecting one of the step portions and a transfer transistor; and a second redistribution line disposed in the second pad layer and connecting another step portion with another transfer transistor.

Description

Technical Field

[0001] Various embodiments relate generally to semiconductor memory devices, and more particularly to three-dimensional semiconductor memory devices. Background Art

[0002] In order to meet the demand for excellent performance and low prices required by consumers, it is necessary to increase the integration level in semiconductor devices. Since the integration level of a two-dimensional or planar semiconductor memory device is mainly determined by the area occupied by a unit memory cell, the integration level is largely affected by the level of fine pattern forming technology. However, since very expensive equipment is required to form fine patterns, the integration level of two-dimensional semiconductor memory devices is still limited despite the continuous improvement. In order to overcome such limitations, an alternative solution including a three-dimensional semiconductor memory device has been proposed, which includes memory cells arranged in three dimensions.

[0003] In a three-dimensional semiconductor memory device, the integration density can be increased by increasing the number of row lines (particularly, word lines) to be stacked. However, the number of wirings connected to the row lines increases in proportion to the number of row lines, thereby increasing the number of metal layers required to set the wirings. Summary of the invention

[0004] Various embodiments relate to a semiconductor memory device that can help reduce the number of metal layers.

[0005] In an embodiment, a semiconductor memory device may include: a first pad layer located in a surface of a memory chip including a cell area and a step area, in which a memory cell array is connected to a plurality of row lines alternately stacked with a plurality of interlayer dielectric layers on a substrate, the step area extends from the cell area in a first direction parallel to a top surface of the substrate and includes staggered step portions of the plurality of row lines, the first pad layer including a plurality of first pads connected to the step portions; a second pad layer located in a surface of a circuit chip bonded to the surface of the memory chip and having a plurality of second pads connected to a plurality of transfer transistors defined in the circuit chip; a first redistribution line disposed in the first pad layer and connecting one of the plurality of step portions and one of the plurality of transfer transistors; and a second redistribution line disposed in the second pad layer and connecting another one of the plurality of step portions and another one of the plurality of transfer transistors.

[0006] In an embodiment, a semiconductor memory device may include: a first pad layer, which is arranged in a surface of a memory chip including a cell area and a step area, in which the memory cell array is connected to a plurality of row lines alternately stacked with a plurality of interlayer dielectric layers on a substrate, and the step area extends from the cell area in a first direction parallel to the top surface of the substrate, wherein ends of the plurality of row lines protrude from the cell area into the step area at different lengths to define a plurality of staggered step portions connected to a plurality of first pads; a second pad layer, which is arranged in a surface of a circuit chip bonded to a surface of the memory chip, and a plurality of second pads are arranged in the second pad layer, and the plurality of second pads are respectively connected to a plurality of transfer transistors defined in the circuit chip; and a first redistribution line, which is arranged in the first pad layer or the second pad layer and connects one of the plurality of step portions and one of the plurality of transfer transistors.

[0007] In an embodiment, a semiconductor memory device may include: a memory chip and a circuit chip bonded to the memory chip. The memory chip includes a plurality of row lines stacked separately from each other, and includes a plurality of first pads connected to the plurality of row lines and a first redistribution line connected to one of the plurality of first pads in one surface of the memory chip bonded to the circuit chip. The circuit chip includes a plurality of transfer transistors, and includes a plurality of second pads connected to the plurality of transfer transistors and a second redistribution line connected to one of the plurality of second pads in one surface of the circuit chip bonded to the memory chip. A first pad of the plurality of first pads connected to the first redistribution line is bonded to a second pad of the plurality of second pads, and a second pad of the plurality of second pads connected to the second redistribution line is bonded to a first pad of the plurality of first pads. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram illustrating a representation of a semiconductor memory device according to an embodiment of the present disclosure.

[0009] Figure 2 is an example Figure 1 An equivalent circuit diagram of a representation of one of the memory blocks shown.

[0010] Figure 3 is an example Figure 1 A block diagram showing a portion of a row decoder is shown.

[0011] Figure 4 is a cross-sectional view illustrating an example of a semiconductor memory device according to an embodiment of the present disclosure.

[0012] Figure 5 is an example Figure 4 Top view of an example of a partial configuration.

[0013] Figure 6 is a cross-sectional view illustrating an example of a semiconductor memory device according to another embodiment of the present disclosure.

[0014] Figure 7 is an example Figure 6 Top view of an example of a partial configuration.

[0015] Figure 8 is a cross-sectional view illustrating an example of a semiconductor memory device according to still another embodiment of the present disclosure.

[0016] Fig. 9 is an example Figure 8 Top view of a representation of the partial configuration.

[0017] Fig.10 is a diagram schematically illustrating a memory system including a semiconductor memory device according to an embodiment of the present disclosure.

[0018] Fig.11 is a block diagram schematically illustrating a representation of an example of a computing system including a semiconductor memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] From the description of the exemplary embodiments described in the following text and with reference to the accompanying drawings, the advantages and features of the present disclosure and the methods for achieving them will become apparent. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but can be implemented in various different ways. The exemplary embodiments of the present disclosure convey the scope of the present disclosure to those skilled in the art.

[0020] The figures, sizes, ratios, angles, and quantities of the elements given in the drawings describing the embodiments of the present disclosure are exemplary and non-restrictive only. Throughout the specification, similar reference numerals refer to similar elements. When describing the present disclosure, when it is determined that the detailed description of the known related art may obscure the gist or clarity of the present disclosure, its detailed description will be omitted. It should be understood that the terms "including", "having", "comprising", etc. used in the specification and claims should not be interpreted as being limited to the devices listed thereafter, unless otherwise explicitly stated. In the case of using an indefinite article or a definite article (such as "one", "an", "the") when referring to a singular noun, unless otherwise explicitly stated, the article may include the plural form of the noun. When explaining the elements in the embodiments of the present disclosure, they should also be interpreted as including error tolerances, even if there is no explicit statement.

[0021] In addition, when describing the components of the present disclosure, there may be terms used like first, second, A, B, (a) and (b). These are only for the purpose of distinguishing one component from another component, and do not imply or teach the essence, order, sequence or quantity of the component. In addition, the elements in the embodiments of the present disclosure are not limited by these terms. These terms are only used to distinguish one element from another element. Therefore, as used herein, within the technical concept of the present disclosure, the first element may be the second element.

[0022] If a component is described as being “connected,” “coupled,” or “linked” to another component, it may mean that the component is not only directly “connected,” “coupled,” or “linked,” but also indirectly “connected,” “coupled,” or “linked” via a third component. When describing a positional relationship, such as “component A on component B,” “component A above component B,” “component A below component B,” and “component A next to component B,” another component C may be disposed between components A and B unless the term “directly” or “immediately thereafter” is explicitly used.

[0023] The features of the various exemplary embodiments of the present disclosure may be partially or completely connected, combined or separated. Technically, there may be various interactions and operations. The various exemplary embodiments may be implemented individually or in combination.

[0024] Hereinafter, various examples of embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 is a block diagram illustrating an example of a semiconductor memory device according to an embodiment of the present disclosure.

[0026] Reference Figure 1 , the semiconductor memory device 100 according to the embodiment of the present disclosure may include a memory cell array 110 and a logic circuit 120. The logic circuit 120 may include a row decoder (X-DEC) 121, a page buffer circuit 122, and a peripheral circuit (PERI circuit) 123.

[0027] The memory cell array 110 may include a plurality of memory blocks BLK. Although not shown, each memory block BLK may include a plurality of cell strings. Each cell string may include at least one drain select transistor, a plurality of memory cells, and at least one source select transistor connected in series. Although the following description includes an embodiment using a vertical NAND flash memory, it should be noted that the present disclosure is not limited thereto.

[0028] The memory cell array 110 may be coupled to the row decoder 121 through a plurality of row lines RL. The row lines RL may include at least one drain selection line, a plurality of word lines, and at least one source selection line. The memory cell array 110 may be coupled to the page buffer circuit 122 through a plurality of bit lines BL.

[0029] The row decoder 121 may select any one of the memory blocks BLK included in the memory cell array 110 in response to the row address X_A provided from the peripheral circuit 123. The row decoder 121 may transmit the operation voltage X_V provided from the peripheral circuit 123 to the row line RL connected to the memory block BLK selected from the memory blocks BLK included in the memory cell array 110. In order to transmit the operation voltage to the row line RL, the row decoder 121 may include a plurality of transmission transistors connected to the row line RL. The number of transmission transistors included in the row decoder 121 may be proportional to the number of memory blocks BLK and the number of row lines RL included in each memory block BLK. The operation voltage X_V as a high voltage should be provided to the word line of the selected memory block BLK. In order to transmit the high voltage, the transmission transistor may be configured by a high voltage transistor.

[0030] The page buffer circuit 122 may include a plurality of page buffers PB respectively connected to the bit lines BL. The page buffer circuit 122 may receive a page buffer control signal PB_C from the peripheral circuit 123, and may send a data signal DATA to the peripheral circuit 123 and receive the data signal DATA from the peripheral circuit 123. The page buffer circuit 122 may be a circuit that controls the bit lines BL arranged in the memory cell array 110 in response to the page buffer control signal PB_C. For example, the page buffer circuit 122 may detect the data stored in the memory cells of the memory cell array 110 by sensing the signals of the bit lines BL of the memory cell array 110 in response to the page buffer control signal PB_C, and may send the data signal DATA to the peripheral circuit 123 according to the detected data. The page buffer circuit 122 may apply a signal to the bit lines BL based on the data signal DATA received from the peripheral circuit 123 in response to the page buffer control signal PB_C, so that data may be written into the memory cells of the memory cell array 110. The page buffer circuit 122 may write data in the memory cells connected to the activated word lines or read data from the memory cells connected to the activated word lines.

[0031] The peripheral circuit 123 may receive a command signal CMD, an address signal ADD, and a control signal CTRL from outside the semiconductor memory device 100, and may send and receive a data signal DATA to and from a device (such as, for example, a memory controller) outside the semiconductor memory device 100. The peripheral circuit 123 may output a signal for writing data into or reading data from the memory cell array 110, for example, a row address X_A, a page buffer control signal PB_C, etc., based on the command signal CMD, the address signal ADD, and the control signal CTRL from outside the semiconductor memory device 100. The peripheral circuit 123 may generate various voltages including an operating voltage X_V required in the semiconductor memory device 100.

[0032] Hereinafter, in the accompanying drawings, two directions parallel to the top surface of the substrate and intersecting each other are defined as a first direction FD and a second direction SD, respectively, and a direction protruding vertically from the top surface of the substrate is defined as a third direction TD. For example, the first direction FD may correspond to the extension direction of the word line or / and the arrangement direction of the bit line, and the second direction SD may correspond to the extension direction of the bit line or / and the arrangement direction of the word line. The first direction FD and the second direction SD may cross each other substantially perpendicularly. The third direction TD may correspond to a direction perpendicular to the first direction FD and the second direction SD. In the following description, the term "vertical" or "vertical direction" will be used as having substantially the same meaning as the third direction TD. In the accompanying drawings, the direction indicated by the arrow and the direction opposite thereto represent the same direction.

[0033] Figure 2 is an example Figure 1 An equivalent circuit diagram of an example of one of the memory blocks BLK is shown.

[0034] Reference Figure 2 , the memory block BLK may include a plurality of cell strings CSTR connected between a plurality of bit lines BL and a common source line CSL. The bit lines BL may extend in the second direction SD and may be arranged in the first direction FD. A plurality of cell strings CSTR may be connected in parallel to each bit line BL. The cell strings CSTR may be commonly connected to the common source line CSL. A plurality of cell strings CSTR may be connected between a plurality of bit lines BL and a common source line CSL.

[0035] Each cell string CSTR may include a drain select transistor DST coupled to a bit line BL, a source select transistor SST coupled to a common source line CSL, and a plurality of memory cells MC coupled between the drain select transistor DST and the source select transistor SST. The drain select transistor DST, the memory cells MC, and the source select transistor SST may be coupled in series in a third direction TD.

[0036] The drain selection line DSL, the plurality of word lines WL, and the source selection line SSL may be stacked between the bit line BL and the common source line CSL in the third direction TD. Each drain selection line DSL may be connected to the gate of the corresponding drain selection transistor DST. Each word line WL may be connected to the gate of the corresponding memory cell MC. The source selection line SSL may be connected to the gate of the source selection transistor SST. The memory cells MC commonly connected to one word line WL may be configured as one page.

[0037] Figure 3 is an example Figure 1 A block diagram of an example of a portion of a row decoder is shown.

[0038] Reference Figure 3 , the row decoder 121 may include a pass transistor circuit 121A, a block decoder 121B, and a global line decoder 121C.

[0039] A pass transistor circuit 121A may be provided for each memory block BLK. Figure 1 ) collectively provide a block decoder 121B and a global line decoder 121C for a plurality of memory blocks BLK included in the memory block 121A. The transfer transistor circuit 121A may be connected to the row line RL through the local row line LRL. The local row line LRL may include at least one local drain select line LDSL, a plurality of local word lines LWL, and at least one local source select line LSSL. The local drain select line LDSL may be connected to the drain select line DSL. The local word lines LWL may be respectively connected to the word lines WL. The local source select line LSSL may be connected to the source select line SSL.

[0040] The pass transistor circuit 121A may include a plurality of pass transistors PTR, each of which is coupled to a global row line GRL. The global row line GRL may be coupled to drains of the respective pass transistors PTR, and the local row lines LRL may be coupled to sources of the pass transistors PTR, respectively.

[0041] The block decoder 121B may be connected to the pass transistor circuit 121A through the block word line BLKWL. The block decoder 121B may be provided with a peripheral circuit 123 (see, for example, Figure 1 ) and can transmit the block selection signal to the block word line BLKWL in response to a control signal from the peripheral circuit 123.

[0042] The global line decoder 121C may be coupled to the pass transistor circuit 121A through the global row line GRL. The global line decoder 121C may be provided with an operation voltage from the peripheral circuit 123, and may transmit the operation voltage to the global row line GRL in response to a control signal from the peripheral circuit 123.

[0043] The pass transistor PTR may couple the global row line GRL and the local row line LRL in response to a block selection signal of the block word line BLKWL. The pass transistor PTR may transfer an operating voltage applied to the global row line GRL to the local row line LRL and thus may provide an operating voltage to the row line RL of the memory block BLK.

[0044] Figure 4 is a cross-sectional view illustrating an example of a semiconductor memory device according to an embodiment of the present disclosure.

[0045] Reference Figure 4 , the semiconductor memory device 100 according to the embodiment of the present disclosure may include a memory chip MC and a circuit chip PC bonded to the memory chip MC. The semiconductor memory device 100 may have a POC (Periphery On Cell) structure.

[0046] The memory chip MC may include a plurality of row lines RL and a plurality of interlayer dielectric layers 20 alternately stacked on a first substrate 10. The first substrate 10 may include at least one selected from a group including a single crystal silicon layer, SOI (silicon on insulator), a silicon layer formed on a silicon germanium (SiGe) layer, a single crystal silicon layer formed on a dielectric layer, and a polysilicon layer formed on a dielectric layer. At least one layer from the bottom layer among the row lines RL may be configured with a source selection line. At least one layer from the top layer among the row lines RL may be configured with a drain selection line. The row lines RL between the source selection line and the drain selection line may be configured with a word line.

[0047] The semiconductor memory device 100 may include a cell region CAR and a step region SR extending from the cell region CAR in a first direction FD. A plurality of vertical channels CH passing through a row line RL and an interlayer dielectric layer 20 may be defined in the cell region CAR. The vertical channel CH may pass through the row line RL and the interlayer dielectric layer 20 in a third direction TD. Although not shown, each vertical channel CH may include a channel layer and a gate dielectric layer. The channel layer may include polycrystalline silicon or single crystal silicon, and may include P-type impurities such as boron (B) in some regions. The gate dielectric layer may have a stem or cylindrical shell shape surrounding the outer wall of the channel layer. The gate dielectric layer may include a tunnel dielectric layer, a charge storage layer, and a blocking layer sequentially stacked from the outer wall of the channel layer. In some embodiments, the gate dielectric layer may have an ONO (oxide-nitride-oxide) stacked structure in which an oxide layer, a nitride layer, and an oxide layer are sequentially stacked. The source select transistor may be configured where the source select line surrounds the vertical channel CH, and the memory cell may be configured where the word line surrounds the vertical channel CH. The drain select transistor may be configured where the drain select line surrounds the vertical channel CH. The source select transistor, the memory cell, and the drain select transistor may configure a memory cell array. The cell area CAR may be defined as an area where the memory cell array is located or situated.

[0048] In the step region SR, each row line RL may have a step portion SP that protrudes in the first direction from one end of another row line RL stacked thereon. For example, the row line RL may extend from the cell region CAR into the step region SR at different lengths in the first direction FD to configure a step structure in the step region SR. The length of the upper row line extending into the step region SR may be shorter than the length of the lower row line extending into the step region SR, so that the upper row line exposes the step portion SP of the lower row line. The step portion SP of the row line RL may create staggered ends in the step region SR. The step region SR may be defined as a region where the step portion SP of the row line RL is located or disposed.

[0049] A dielectric layer 30 may be defined on the first substrate 10 to cover the row lines RL, the interlayer dielectric layer 20, and the vertical channels CH. The top surface of the dielectric layer 30 may configure a surface of the memory chip MC bonded to the circuit chip PC. A plurality of metal layers ML1a and ML2a may be defined in the dielectric layer 30. The first pad layer PL1 may be defined together to the top surface of the dielectric layer 30. In the third direction TD, the metal layer ML2a may be disposed above the metal layer ML1a, and the first pad layer PL1 may be disposed above the metal layer ML2a.

[0050] In the cell region CAR, a plurality of bit lines BL may be defined in the metal layer ML1a. Bit line contacts BLC may be defined below the bit lines BL to couple the bit lines BL and the vertical channels CH. A plurality of wirings W1 may be defined in the metal layer ML1a in the step region SR. Contacts 51 may be defined below the wirings W1 to couple the wirings W1 and the step portions SP of the row lines RL. In the step region SR, a plurality of wirings W2 may be defined in the metal layer ML2a, and contacts 52 to couple the wirings W2 to the wirings W1 may be defined below the wirings W2. The contacts 52 may couple a first end of a third redistribution line RDL3 to the wirings W1 in the step region SR. The third redistribution line RDL3 may extend into the cell region CAR in the first direction FD, or may remain in the step region SR.

[0051] Figure 4 A structure in which the row line RL defined in the memory chip MC is coupled to the pass transistor PTR defined in the circuit chip PC is illustrated. A plurality of first pads PAD1 coupled to the step portion SP of the row line RL may be provided in the first pad layer PL1.

[0052] The circuit chip PC may include a plurality of pass transistors PTR defined on the second substrate 12 . Figure 4 The reference symbol S denotes a source region of each transfer transistor PTR. Although not shown, various elements configuring a logic circuit (such as, for example, Figure 1 Logic circuit 120).

[0053] The second substrate 12 may include at least one selected from the group including a single crystal silicon layer, SOI (silicon on insulator), a silicon layer formed on a silicon germanium (SiGe) layer, a single crystal silicon layer formed on a dielectric layer, and a polysilicon layer formed on a dielectric layer. The circuit chip PC and the memory chip MC are bonded to each other after being manufactured on separate wafers. The second substrate 12 may be made of the same material as the first substrate 10.

[0054] A dielectric layer 40 may be defined on the second substrate 12 to cover the transfer transistor PTR. The top surface of the dielectric layer 40 may configure a surface of the circuit chip PC that is bonded to the memory chip MC. A plurality of metal layers ML1b to ML4b may be defined in the dielectric layer 40. The second pad layer PL2 may be defined together to the top surface of the dielectric layer 40. In the third direction TD, the metal layer ML2b may be disposed above the metal layer ML1b, the metal layer ML3b may be disposed above the metal layer ML2b, and the metal layer ML4b may be disposed above the metal layer ML3b. The second pad layer PL2 may be disposed above the metal layer ML4b. A plurality of second pads PAD2 coupled to the source region S of the transfer transistor PTR may be defined in the second pad layer PL2.

[0055] The first pad PAD1 of the memory chip MC and the second pad PAD2 of the circuit chip PC may be made of, for example, copper or a copper alloy. When the memory chip MC and the circuit chip PC are bonded to each other, the first pad PAD1 and the second pad PAD2 corresponding to each other may be connected. For example, the first pad PAD1 and the second pad PAD2 are connected to each other by the following operation: a surface of the memory chip MC where the first pad PAD1 is located is brought into contact with a surface of the circuit chip PC where the second pad PAD2 is located, so that the first pad PAD1 and the second pad PAD2 are in contact with each other, and the memory chip MC and the circuit chip PC are bonded at a temperature of 300 to 400°C under a predetermined pressure.

[0056] The transfer transistor PTR may be configured by a high voltage transistor. Each high voltage transistor configuring the transfer transistor PTR requires a wider area than a low voltage transistor in order to withstand a high voltage. That is, each high voltage transfer transistor PTR needs to be manufactured in a relatively large size in order to transmit a high voltage. In order to reduce the size of the semiconductor memory device 100, it is necessary to reduce the length of the step region SR in the first direction FD. To this end, it is necessary to reduce the length of the step portion SP of each row line RL in the first direction FD. For example, the length of the step portion SP of each row line RL in the first direction FD may have a minimum feature size required for landing each contact 51. For this reason, the spacing of the step portion SP of the row line RL in the first direction FD may be smaller than the spacing of the transfer transistor PTR in the first direction FD. For example, the spacing of the step portion SP of the row line RL in the first direction FD may have a first size P1, and the spacing of the transfer transistor PTR in the first direction FD may have a second size P2, which is larger than the first size P1.

[0057] Due to the different spacings between the step portion SP and the transfer transistor PTR, when viewed from the top or in a plan view, the step portion SP of each row line RL and the transfer transistor PTR connected thereto may be spaced apart from each other in the first direction FD. The step portion SP of the row line and its corresponding transfer transistor PTR may not overlap with each other in the third direction TD. In order to connect the step portion SP and the corresponding transfer transistor PTR that do not overlap with each other in the third direction TD, a redistribution line extending in a direction parallel to the top surface of the first substrate 10 needs to be provided.

[0058] like Figure 4 As shown, a first redistribution line RDL1 may be defined in the first pad layer PL1 of the memory chip MC to connect one of the plurality of step portions SP of the plurality of row lines RL and one of the plurality of pass transistors PTR. A second redistribution line RDL2 may be defined in the second pad layer PL2 of the circuit chip PC to connect another of the plurality of step portions SP of the plurality of row lines RL and another of the plurality of pass transistors PTR.

[0059] As shown below Figure 5 , Figure 7 and Fig. 9 Further explained, the first redistribution line RDL1 may be disposed in a region remaining after the first pad PAD1 is disposed in the first pad layer PL1. The first redistribution line RDL1 may be formed in the same manufacturing step as the first pad PAD1 and may be made of the same material as the first pad PAD1.

[0060] The first end of the first redistribution line RDL1 may overlap the step portion SP in the third direction TD. A contact 53 may be defined below the first end of the first redistribution line RDL1 to connect the wiring W2 connected to the corresponding step portion SP and the first redistribution line RDL1. The first end of the first redistribution line RDL1 may be connected to the step portion SP through the wirings W1 and W2 and through the contacts 51 to 53 defined on the step portion SP. The other end of the first redistribution line RDL1 may be connected to one of the plurality of first pads PAD1. The first pad PAD1 may overlap one of the transfer transistors PTR in the third direction TD and may be connected to the source region S of one transfer transistor PTR through the second pad PAD2 and the contact 60. Although Figure 4 Only one first redistribution line RDL1 is illustrated in FIG. 2 , but it should be understood that in other embodiments, two or more first redistribution lines RDL1 are disposed in the first pad layer PL1 .

[0061] The second redistribution line RDL2 may be disposed in a remaining area of ​​the second pad layer PL2 after the second pad PAD2 is disposed. The second redistribution line RDL2 may be formed in the same manufacturing step as the second pad PAD2 and may be made of the same material as the second pad PAD2.

[0062] A first end of the second redistribution line RDL2 may overlap with a source region S of a corresponding transfer transistor PTR in the third direction TD, and may be coupled to the source region S of the transfer transistor PTR through a contact 61. The other end of the second redistribution line RDL2 may be coupled to one of a plurality of second pads PAD2. The second pad PAD2 coupled to the second redistribution line RDL2 may overlap with one of a plurality of step portions SP of a plurality of row lines RL in the third direction TD, and may be coupled to the step portion SP through the first pad PAD1, the wirings W1, W2, and the contacts 51 to 53. Although Figure 4 Only one second redistribution line RDL2 is illustrated in FIG. 2 , but it should be understood that in other embodiments, two or more second redistribution lines RDL2 are disposed in the second pad layer PL2 .

[0063] The third redistribution line RDL3 may be defined in the metal layer ML2a of the memory chip MC to connect the step portion SP of the row line RL and the source region S of the transfer transistor PTR. One end of the third redistribution line RDL3 in the step region SR may overlap the step portion SP of the row line RL and may be connected to the step portion SP of the row line RL through the wiring W1 and the contacts 51 and 52. The other end of the third redistribution line RDL3 may overlap the source region S of the transfer transistor PTR in the third direction TD and may be connected to the source region S of the transfer transistor PTR through the contact 53, the first pad PAD1, the second pad PAD2, and the contact 62. The other end of the third redistribution line RDL3 may be disposed in the step region SR or the cell region CAR.

[0064] Fourth redistribution lines RDL4a, RDL4b, and RDL4c (RDL4a to RDL4c) may be defined in metal layers ML1b to ML3b of the circuit chip PC. The fourth redistribution lines (RDL4a to RDL4c) each couple a stepped portion SP of a row line RL to a source region S of a corresponding pass transistor PTR.

[0065] One end of each of the fourth redistribution lines RDL4a to RDL4c may overlap with the stepped portion SP of the row line RL in the third direction TD, and may be coupled to the stepped portion SP of the corresponding row line RL through the contacts 71, 72, and 73, respectively, and through the second pad PAD2, the first pad PAD1, the wirings W1 and W2, and the contacts 51 to 53. The other end of each of the fourth redistribution lines RDL4a to RDL4c may overlap with the source region S of the corresponding transfer transistor PTR in the third direction TD, and may be coupled to the source region S of the transfer transistor PTR through the corresponding contact 81, 82, or 83 and at least one of the wirings W3 and W4.

[0066] The stepped portions SP coupled to the first and second redistribution lines RDL1 and RDL2 may be disposed farther from the cell region CAR in the first direction than the stepped portions SP coupled to the third redistribution lines RDL3. The stepped portions SP coupled to the first and second redistribution lines RDL1 and RDL2 may be disposed closer to the cell region CAR in the first direction than the stepped portions SP coupled to the fourth redistribution lines RDL4a to RDL4c.

[0067] Among the redistribution lines RDL1, RDL2, RDL3a, and RDL4c to RDL4c, the redistribution line having the shortest vertical distance from the second substrate 12 (i.e., in the third direction) may be coupled to the step portion SP positioned relatively farthest from the cell region CAR in the first direction FD. Among the redistribution lines RDL1, RDL2, RDL3, and RDL4a to RDL4c, the redistribution line having the longest vertical distance from the second substrate 12 may be coupled to the step portion SP positioned relatively closest to the cell region CAR in the first direction FD. For example, the fourth redistribution line RDL4a may be coupled to the step portion SP disposed farthest from the cell region CAR, and the third redistribution line RDL3 may be coupled to the step portion SP disposed closest to the cell region CAR. Such a coupling scheme may reduce a phenomenon (wiring bottleneck phenomenon) in which wiring and contacts of the step portion SP coupled to the row line RL are densely disposed in a specific area.

[0068] Figure 5 is an example including a pass transistor PTR, first and second pads PAD1 and PAD2, and some of the first and second redistribution lines RDL1 and RDL2. Figure 4 Top view of an example of a partial configuration.

[0069] Reference Figure 4 and Figure 5, the first redistribution line RDL1 may include a first landing pad portion RP1 and a first line portion RL1. The first landing pad portion RP1 may overlap the step portion SP of the row line RL in the third direction TD. The first landing pad portion RP1 may be coupled to the top end of the contact 53, and may be coupled to the step portion SP through the contacts 51, 52, and 53 and the wirings W1 and W2.

[0070] like Figure 5 As shown, the first line portion RL1 may couple the first pad PAD1 in the cell region CAR and the first landing pad portion RP1 in the step region SR. One end of the first line portion RL1 may be coupled to the first landing pad portion RP1 in the step region SR, and the other end of the first line portion RL1 may be coupled to one of the first pads PAD1 in the cell region CAR.

[0071] The second redistribution line RDL2 may include a second landing pad portion RP2 and a second line portion RL2. The second landing pad portion RP2 may overlap with the source region S of the transfer transistor PTR in the third direction TD. The second landing pad portion RP2 may be coupled to the top of the contact 61, and may be coupled to the source region S of the transfer transistor PTR through the contact 61. The second line portion RL2 may couple the second pad PAD2 and the second landing pad portion RP2. One end of the second line portion RL2 may be coupled to the second pad PAD2 in the step region SR, and the other end of the second line portion RL2 may be coupled to the second landing pad portion RP2 in the cell region CAR.

[0072] The surface of the memory chip MC in which the first redistribution line RDL1 is located or disposed in the first pad layer PL1 and the surface of the circuit chip PC in which the second redistribution line RDL2 is located or disposed in the second pad layer PL2 are bonded to each other. If the first redistribution line RDL1 and the second redistribution line RDL2 overlap each other in the third direction TD, the first redistribution line RDL1 and the second redistribution line RDL2 will be short-circuited to each other. In order to prevent the first redistribution line RDL1 and the second redistribution line RDL2 from being short-circuited to each other, the first redistribution line RDL1 and the second redistribution line RDL2 may be configured so that they do not overlap each other in the third direction TD. For example, the top surface of the first redistribution line RDL1 may be arranged to contact the top surface of the dielectric layer 40 of the circuit chip PC, and the top surface of the second redistribution line RDL2 may be arranged to contact the top surface of the dielectric layer 30 of the memory chip MC.

[0073] Refer to above Figure 4 and Figure 5The described embodiment illustrates an example in which the redistribution line is provided in both the first pad layer PL1 of the memory chip MC and the second pad layer PL2 of the circuit chip PC, but it is noted that the redistribution line may be provided in only one of the first pad layer PL1 of the memory chip MC and the second pad layer PL2 of the circuit chip PC. Figures 6 to 9 Describe this structure.

[0074] Figure 6 is a cross-sectional view illustrating an example of a semiconductor memory device according to another embodiment of the present disclosure.

[0075] Reference Figure 6 , a redistribution line RDL1 may be defined in the first pad layer PL1 of the memory chip MC. The redistribution line RDL1 may be formed in the same manufacturing step together with the first pad PAD1, and may be made of the same material as the first pad PAD1.

[0076] One end of the redistribution line RDL1 may overlap one of the plurality of step portions SP of the plurality of row lines RL in the third direction TD in the step region SR, and may be connected to the step portion SP through wirings W1, W2 and contacts 51, 52, 53. The other end of the redistribution line RDL1 may be connected to one of the plurality of first pads PAD1. The first pad PAD1 connected to the redistribution line RDL1 may overlap the source region S of the transfer transistor PTR in the third direction TD, and may be connected to the source region S of the transfer transistor PTR through the second pad PAD2 and the contact 60.

[0077] The stepped portion SP coupled to the redistribution line RDL1 may be disposed farther from the cell region CAR than the stepped portion SP coupled to the third redistribution line RDL3. The stepped portion SP coupled to the redistribution line RDL1 may be disposed closer to the cell region CAR than the stepped portion SP coupled to the fourth redistribution lines RDL4a, RDL4b, and RDL4c.

[0078] Figure 7 Examples include Figure 6 The transfer transistor PTR, the first pad PAD1 and the second pad PAD2, and some of the redistribution line RDL1, Figure 6 Top view of an example of a partial configuration.

[0079] Reference Figure 6 and Figure 7, the redistribution line RDL1 may include a landing pad portion RP1 and a line portion RL1. The landing pad portion RP1 may be arranged to overlap one of the plurality of step portions SP of the plurality of row lines RL in the third direction TD in the step region SR. The landing pad portion RP1 may be coupled to the top end of the contact 53, and may be coupled to the step portion SP through the contacts 51, 52, and 53 and the wirings W1 and W2. The line portion RL1 may couple the first pad PAD1 and the landing pad portion RP1. One end of the line portion RL1 may be coupled to the landing pad portion RP1 in the step region SR, and the other end of the line portion RL1 may be coupled to the first pad PAD1 in the cell region CAR.

[0080] Figure 8 is a cross-sectional view illustrating an example of a semiconductor memory device according to still another embodiment of the present disclosure.

[0081] Reference Figure 8 , a redistribution line RDL2 may be defined in the second pad layer PL2 of the circuit chip PC to couple the step portion SP and the source region S of the transfer transistor PTR. The redistribution line RDL2 may be formed in the same manufacturing step as the second pad PAD2 and may be made of the same material as the second pad PAD2.

[0082] One end of the redistribution line RDL2 may be connected to a second pad PAD2 of the step region SR. The second pad PAD2 connected to one end of the redistribution line RDL2 may overlap one of the plurality of step portions SP of the plurality of row lines RL in the third direction TD, and may be connected to one step portion SP through the first pad PAD1, the wirings W1 and W2, and the contacts 51, 52, and 53. The other end of the redistribution line RDL2 may overlap the source region S of the transfer transistor PTR in the third direction TD, and may be connected to the source region S of the transfer transistor PTR through the contact 61.

[0083] The stepped portion SP coupled to the redistribution line RDL2 may be disposed farther from the cell region CAR than the stepped portion SP coupled to the third redistribution line RDL3. The stepped portion SP coupled to the redistribution line RDL2 may be disposed closer to the cell region CAR than the stepped portion SP coupled to the fourth redistribution lines RDL4a, RDL4b, and RDL4c.

[0084] Fig. 9 Examples include Figure 8 The transmission transistor PTR, the first pad PAD1 and the second pad PAD2, and some of the redistribution line RDL2, Figure 8 Top view of a representation of the partial configuration.

[0085] Reference Figure 8 and Fig. 9 , the redistribution line RDL2 may include a landing pad portion RP2 and a line portion RL2. The landing pad portion RP2 may overlap the source region S of the transfer transistor PTR in the third direction TD. The landing pad portion RP2 may be coupled to Figure 8 , and may be coupled to the source region S of the transfer transistor PTR through the contact 61. The line portion RL2 may couple the second pad PAD2 and the landing pad portion RP2. One end of the line portion RL2 may be coupled to the second pad PAD2 in the step region SR, and the other end of the line portion RL2 may be coupled to the landing pad portion RP2 in the cell region CAR.

[0086] Hereinafter, effects according to the embodiments of the present disclosure will be described.

[0087] As the number of stacked row lines RL increases to provide a larger capacity and high integration in a semiconductor memory device, the number of transfer transistors PTR and the number of redistribution lines connecting the transfer transistors PTR and the row lines RL must also be increased accordingly. In order to set the redistribution lines, a method of increasing the number of metal layers in the circuit chip PC or / and the memory chip MC may be used. In this case, as the number of manufacturing steps required to form the metal layers increases, the manufacturing time and manufacturing cost increase, and the possibility of failure in the manufacturing process increases.

[0088] If the number of memory blocks is reduced, the number of row lines RL and the number of transfer transistors PTR can be reduced, and the number of redistribution lines connecting the transfer transistors PTR and the row lines RL can be reduced. However, if the number of memory blocks is reduced while maintaining the capacity of the semiconductor memory device, the number of cell strings included in each memory block increases, and the parasitic capacitance between the cell strings and the row lines RL can increase, resulting in degradation of the operating characteristics of the semiconductor memory device.

[0089] According to an embodiment of the present disclosure, by configuring a redistribution line in an extra space remaining on a pad layer of a circuit chip PC or / and a pad layer of a memory chip MC or available around a contact pad, the number of metal layers required for setting the redistribution line can be reduced without reducing the number of memory blocks. Therefore, by simplifying the process by reducing the number of manufacturing steps required to form a metal layer without deteriorating the operating characteristics of the semiconductor memory device, the manufacturing cost can be reduced, and the number of failures that may occur in the manufacturing process can be reduced.

[0090] Fig.10 is a block diagram schematically illustrating a representation of an example of a memory system including a semiconductor memory device according to an embodiment.

[0091] Reference Fig.10 , a memory system 600 according to an embodiment may include a nonvolatile memory device 610 and a memory controller 620 .

[0092] The nonvolatile memory device (NVM device) 610 may be composed of the above-mentioned semiconductor memory device and may be operated in the above-mentioned manner. The memory controller 620 may be configured to control the nonvolatile memory device 610. By the combination of the nonvolatile memory device 610 and the memory controller 620, a memory card or a solid state disk (SSD) may be provided. The SRAM (static random access memory) 621 is used as a working memory of the processing unit (e.g., CPU) 622. The host interface (host I / F) 623 includes a data exchange protocol of a host connected to the memory system 600.

[0093] The error correction code block (ECC) 624 detects and corrects errors included in data read from the nonvolatile memory device 610 .

[0094] The memory interface (memory I / F) 625 interfaces with the nonvolatile memory device 610 of the present embodiment. The processing unit 622 performs overall control operations of the memory controller 620 for data exchange.

[0095] Although not shown in the drawings, it is obvious to those skilled in the art that the memory system 600 according to the embodiment may be additionally provided with a ROM storing code data for interfacing with a host. The nonvolatile memory device 610 may be provided as a multi-chip package consisting of a plurality of flash memory chips.

[0096] As described above, the memory system 600 according to the embodiment can be set as a high-reliability storage medium with a low probability of error. Specifically, the non-volatile memory device of the present embodiment may be included in a memory system such as a solid-state disk (SSD) that is being actively studied recently. In this case, the memory controller 620 can be configured to communicate with an external (e.g., host) through one of various interface protocols such as USB (Universal Serial Bus) protocol, MMC (Multimedia Card) protocol, PCI-E (Peripheral Component Interconnect Express) protocol, SATA (Serial Advanced Technology Attachment) protocol, PATA (Parallel Advanced Technology Attachment) protocol, SCSI (Small Computer System Interface) protocol, ESDI (Enhanced Small Disk Interface) protocol, and IDE (Integrated Drive Electronics) protocol.

[0097] Fig.11 is a block diagram schematically illustrating a representation of an example of a computing system including a semiconductor memory device according to an embodiment.

[0098] Reference Fig.11 , the computing system 700 according to the embodiment may include a memory system 710 electrically connected to a system bus 760, a microprocessor (e.g., CPU) 720, a RAM 730, a user interface 740, and a modem 750 such as a baseband chipset. In the case where the computing system 700 according to the embodiment is a mobile device, a battery (not shown) for supplying an operating voltage of the computing system 700 may be additionally provided. Although not shown in the drawings, it is obvious to those skilled in the art that the computing system 700 according to the embodiment may be additionally provided with an application chipset, a camera image processor (CIS), a mobile DRAM, etc. The memory system 710 may be configured, for example, as an SSD (solid state drive / disk) that uses a non-volatile memory to store data. In addition, the memory system 710 may be configured as a fusion flash memory (e.g., OneNAND flash memory).

[0099] Although the exemplary embodiments of the present disclosure have been described for exemplary purposes, it will be understood by those skilled in the art that various modifications, additions and substitutions may be made without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered only in a descriptive sense, and not for limiting the technical scope. The technical scope of the present disclosure is not limited by the embodiments and the accompanying drawings. The spirit and scope of the present disclosure should be interpreted by the appended claims, and include all equivalents falling within the scope of the appended claims.

[0100] CROSS-REFERENCE TO RELATED APPLICATIONS

[0101] This application claims the priority of Korean Patent Application No. 10-2020-0001707 filed on January 6, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor memory device, comprising: a first pad layer in a surface of a memory chip including a cell region and a step region in which a memory cell array is coupled to a plurality of row lines alternately stacked with a plurality of interlayer dielectric layers on a substrate, the step region extending from the cell region in a first direction parallel to a top surface of the substrate and including a plurality of staggered step portions of the plurality of row lines, the first pad layer including a plurality of first pads coupled to the step portions; a second pad layer in a surface of the circuit chip bonded to the surface of the memory chip and having a plurality of second pads coupled to a plurality of pass transistors defined in the circuit chip; a first redistribution line disposed in the first pad layer and coupling one of the plurality of stepped portions and one of the plurality of pass transistors; as well as a second redistribution line disposed in the second pad layer and coupling another one of the plurality of stepped portions and another one of the plurality of pass transistors, The first redistribution line is formed on the same layer as the first pad and is made of the same material as the first pad, and The second redistribution line is formed on the same layer as the second pad and is made of the same material as the second pad.

2. The semiconductor memory device according to claim 1, wherein The first redistribution line and the second redistribution line do not overlap in a direction perpendicular to the top surface of the substrate.

3. The semiconductor memory device according to claim 1, wherein: A pitch of the stepped portions in the first direction is smaller than a pitch of the transfer transistors in the first direction.

4. The semiconductor memory device according to claim 1, wherein: The stepped portion connected to the first redistribution line and the transfer transistor do not overlap in a direction perpendicular to the top surface of the substrate, and the stepped portion connected to the second redistribution line and the transfer transistor do not overlap in a direction perpendicular to the top surface of the substrate.

5. The semiconductor memory device according to claim 1, wherein: The first redistribution line comprises: a landing portion coupled to a contact extending in a direction perpendicular to the top surface of the substrate, wherein the contact is coupled to one of the plurality of step portions; and A line portion coupling one of the plurality of first pads to the landing portion.

6. The semiconductor memory device according to claim 1, wherein: The second redistribution line comprises: a landing portion coupled to one of the plurality of pass transistors in a direction perpendicular to the top surface of the substrate; and A line portion coupling one of the plurality of second pads to the landing portion.

7. The semiconductor memory device according to claim 1, further comprising: a third redistribution line in an inner metal layer of the memory chip, the third redistribution line connecting another pass transistor of the plurality of pass transistors and another step portion of the plurality of step portions, The stepped portion coupled to the first and second redistribution lines is disposed farther from the cell region than the other stepped portion coupled to the third redistribution line.

8. The semiconductor memory device according to claim 1, further comprising: a fourth redistribution line, the fourth redistribution line being in an inner metal layer of the circuit chip, the fourth redistribution line connecting another one of the plurality of pass transistors with another one of the plurality of stepped portions, The stepped portion coupled to the first and second redistribution lines is disposed closer to the cell region than the other stepped portion coupled to the fourth redistribution line.

9. A semiconductor memory device, the semiconductor memory device comprising: a first pad layer, the first pad layer being disposed in one surface of a memory chip including a cell region and a step region, wherein a memory cell array is coupled to a plurality of row lines alternately stacked with a plurality of interlayer dielectric layers on a substrate, the step region extending from the cell region in a first direction parallel to a top surface of the substrate, and wherein ends of the plurality of row lines protrude from the cell region into the step region with different lengths to define a plurality of staggered step portions, the first pad layer comprising a plurality of first pads coupled to the step portions; a second pad layer provided in one surface of the circuit chip bonded to the one surface of the memory chip and having a plurality of second pads respectively coupled to a plurality of transfer transistors defined in the circuit chip provided therein; and a first redistribution line, the first redistribution line being disposed in the first pad layer or the second pad layer, the first redistribution line connecting one of the plurality of stepped portions and one of the plurality of transfer transistors, The first redistribution line is formed on the same layer as the first pad or the second pad, and is made of the same material as the first pad or the second pad.

10. The semiconductor memory device according to claim 9, wherein: A pitch of the plurality of stepped portions in the first direction is smaller than a pitch of the plurality of pass transistors in the first direction.

11. The semiconductor memory device according to claim 9, wherein: One of the plurality of stepped portions coupled to the first redistribution line and one of the plurality of pass transistors do not overlap each other in a second direction perpendicular to the top surface of the substrate.

12. The semiconductor memory device according to claim 9, in, The first redistribution line is disposed in the first pad layer, and Wherein, the first redistribution line comprises: a landing portion coupled to a contact extending in a second direction perpendicular to the top surface of the substrate, wherein the contact is coupled to one of the plurality of step portions; and A line portion coupling one of the plurality of first pads to the landing portion.

13. The semiconductor memory device according to claim 9, in, The first redistribution line is disposed in the second pad layer, and Wherein, the first redistribution line comprises: a landing portion coupled to a contact extending in a second direction perpendicular to the top surface of the substrate, wherein the contact is coupled to one of the plurality of pass transistors; and A line portion coupling one of the plurality of second pads to the landing portion.

14. The semiconductor memory device according to claim 9, further comprising: a second redistribution line, the second redistribution line being disposed in a metal layer inside the memory chip, the second redistribution line connecting another step portion of the plurality of step portions other than the step portion connected to the first redistribution line and another transfer transistor of the plurality of transfer transistors other than the transfer transistor connected to the first redistribution line, The stepped portion coupled to the first redistribution line is disposed farther from the cell region than the other stepped portion coupled to the second redistribution line.

15. The semiconductor memory device according to claim 9, further comprising: a second redistribution line, the second redistribution line being disposed in a metal layer inside the circuit chip, the second redistribution line connecting another transfer transistor among the plurality of transfer transistors except the transfer transistor connected to the first redistribution line and another stepped portion among the plurality of stepped portions except the stepped portion connected to the first redistribution line, The stepped portion coupled to the first redistribution line is disposed closer to the cell region than the other stepped portion coupled to the second redistribution line.

16. A semiconductor memory device, the semiconductor memory device comprising: a memory chip and a circuit chip bonded to the memory chip, wherein the memory chip includes a plurality of row lines stacked separately from each other, and includes a plurality of first pads coupled to the plurality of row lines and a first redistribution line coupled to one of the plurality of first pads in one surface of the memory chip bonded to the circuit chip, The circuit chip includes a plurality of transmission transistors, and includes a plurality of second pads connected to the plurality of transmission transistors and a second redistribution line connected to one of the plurality of second pads in one surface of the circuit chip bonded to the memory chip. wherein the one first pad among the plurality of first pads coupled to the first redistribution line is bonded to one second pad among the plurality of second pads, and the one second pad among the plurality of second pads coupled to the second redistribution line is bonded to one first pad among the plurality of first pads, The first redistribution line is formed on the same layer as the first pad and is made of the same material as the first pad, and The second redistribution line is formed on the same layer as the second pad and is made of the same material as the second pad.

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