Integrated circuit and method of manufacturing integrated circuit

Abstract

MFMIS‑FETs include MOSFETs with a three-dimensional structure that allows the MOSFET to have an effective area that is larger than the footprint of the MFM or MOSFET. In some embodiments, the gate electrode of the MOSFET and the bottom electrode of the MFM are integral. In some cases, they have equal areas. In some embodiments, the MFM and the MOSFET have nearly equal footprints. In some embodiments, the effective area of ​​the MOSFET is much larger than the effective area of ​​the MFM. These structures reduce the capacitance ratio between the MFM structure and the MOSFET without reducing the area of ​​the MFM structure in a way that would reduce the drain current. Embodiments of the present invention also relate to integrated circuits and methods of manufacturing integrated circuits.

Description

Technical Field

[0001] Embodiments of the present invention relate to integrated circuits and methods of manufacturing integrated circuits. Background Art

[0002] Many modern electronic devices contain nonvolatile memory. Nonvolatile memory is electronic memory that is able to store data in the absence of power. A promising candidate for the next generation of nonvolatile memory is ferroelectric random access memory (FeRAM). FeRAM has a relatively simple structure and is compatible with complementary metal oxide semiconductor (CMOS) logic manufacturing processes. Summary of the invention

[0003] Some embodiments of the present invention provide an integrated circuit, comprising: a substrate 175; a field effect transistor (FET) 143, comprising a gate electrode 167 and one or more channel regions 151 separated from the gate electrode 167 by an insulator 169; and a metal ferroelectric metal structure (MFM) 127, comprising a top electrode 133 and a bottom electrode separated by a ferroelectric layer 135; wherein the gate electrode 167 is coupled to the bottom electrode or is integral with the bottom electrode; the field effect transistor has an effective area related to the capacitance of the field effect transistor; the field effect transistor has a coverage area above the substrate; and the effective area of ​​the field effect transistor is larger than the coverage area of ​​the field effect transistor.

[0004] Other embodiments of the present invention provide an integrated circuit (IC) comprising: a metal ferroelectric metal structure 127, comprising a top electrode 133 and a bottom electrode separated by a ferroelectric layer 135; and a plurality of field effect transistor structures, each comprising a semiconductor source / drain region separated by a semiconductor channel region 151, a gate electrode 167 and an insulator 169 located between the gate electrode and the semiconductor channel region; wherein the gate electrode of each of the plurality of field effect transistor structures is coupled to the bottom electrode or is integral with the bottom electrode.

[0005] Still other embodiments of the present invention provide a method for manufacturing an integrated circuit (IC) including an MFMIS-FET, the method comprising: forming a semiconductor fin above a substrate; forming a dummy gate stack above the semiconductor fin; patterning the dummy gate stack to define a dummy gate; forming a sidewall spacer around the dummy gate; and replacing the dummy gate with an MFMIS-FET including a high-k dielectric, a metal gate, a ferroelectric layer, and a top electrode layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 A cross-sectional view of an integrated circuit (IC) device having an MFMIS-FET according to aspects of the present teachings is shown.

[0008] Figure 2 Shows Figure 1 A three-dimensional cross-sectional view of a portion of an IC device.

[0009] Figure 3 A cross-sectional view of an integrated circuit (IC) device having an MFMIS-FET according to some other aspects of the present teachings is shown.

[0010] Figure 4 A cross-sectional view of an integrated circuit (IC) device having an MFMIS-FET according to some other aspects of the present teachings is shown.

[0011] Figure 5 A cross-sectional view of an integrated circuit (IC) device having an MFMIS-FET according to some other aspects of the present teachings is shown.

[0012] Figure 6 to Figure 47 A series of cross-sectional views of an IC device according to some aspects of the present teachings undergoing a manufacturing process according to some aspects of the present teachings are shown. The even-numbered geometry of these figures corresponds to Figure 2 The odd geometry of these figures corresponds to Figure 2 The cross section is 220.

[0013] Fig.48 A flow chart of a manufacturing process according to some aspects of the present teachings is described. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0016] An integrated circuit (IC) device according to the present invention includes a ferroelectric random access memory (FeRAM). FeRAM has a metal / ferroelectric layer / metal (MFM) structure, in which a ferroelectric layer is arranged between two metal layers providing top and bottom electrodes. FeRAM stores data by a reversible switching process between polarization states. The polarization state can be changed using an electric field that changes the polarization maintained by the ferroelectric layer crystal structure. For example, a negative voltage bias applied to the ferroelectric layer can induce atoms to move to a first direction having a first resistance indicating a first data value (e.g., a logic "1"), while a positive voltage bias applied to the ferroelectric layer can induce atoms to move to a second direction having a second resistance indicating a second data value (e.g., a logic "0").

[0017] One type of FeRAM has a transistor connected to a capacitor, such as a 1T1C cell structured FeRAM, where the MFM is coupled to the drain of a metal oxide semiconductor field effect transistor (MOSFET or FET). Another type of FeRAM is a metal ferroelectric insulator semiconductor field effect transistor (MFIS-FET or FeFET), which is essentially a metal gate FET with a ferroelectric layer between the oxide and the gate. A third type of FeRAM is a metal ferroelectric metal insulator semiconductor field effect transistor (MFMIS-FET), where the bottom electrode of the MFM structure is coupled to the gate of the FET. The FET gate and the bottom electrode of the MFM structure act as a single floating gate. MFMIS-FETs have advantages such as lossless read, low write voltage, and high endurance.

[0018] It has been determined that in designing an MFMIS-FET, it is desirable to make the capacitance of the MFM structure much smaller than the capacitance of the FET. Reducing the capacitance of the MFM structure while fixing the capacitance of the FET structure reduces the electric field across the FET insulator while increasing the electric field across the ferroelectric layer. Reducing the electric field across the FET insulator mitigates charge trapping that can adversely affect durability. Increasing the electric field across the ferroelectric layer reduces the write voltage.

[0019] By reducing the area of ​​the MFM structure, the capacitance of the MFM structure can be reduced relative to the FET. A side effect of reducing the area of ​​the MFM structure is that the total capacitance of the MFMIS-FET is reduced. The reduction in total capacitance reduces the drain current, which can limit device performance.

[0020] According to some aspects of the present teachings, the problem of reducing the capacitance ratio between the MFM structure and the FET in the MFMIS-FET is solved by implementing the FET with a three-dimensional structure that allows the FET to have an effective area that is larger than the FET footprint. According to the present teachings, the MFM structure can have an effective area that is almost equal to the footprint of the FET structure, so the ratio between the effective area of ​​the FET and the footprint of the FET is approximately the same as the ratio between the effective area of ​​the FET and the effective area of ​​the MFM structure. Increasing the ratio reduces charge trapping and reduces write voltage. In some of these teachings, the area ratio is 4 to 1 or greater, which may be sufficient to provide satisfactory durability. In some of these teachings, the area ratio is 7 to 1 or greater, which provides good durability. In some of these teachings, the area ratio is 10 to 1 or greater, which provides near-optimal performance. In some of these teachings, the effective area of ​​the MFM structure is at least 2 / 3 of the footprint of the FET.

[0021] In some of these teachings, the FET of the MFMIS-FET includes a plurality of FET structures, each FET structure having a channel region that does not intersect with the channel regions of the other FET structures. In some of these teachings, the FET of the MFMIS-FET is implemented by one or more FinFET structures. In some of these teachings, the FET of the MFMIS-FET is implemented by a plurality of FinFET structures. In some of these teachings, the FET of the MFMIS-FET is implemented by a full-ring gate structure (such as a nanowire or hexagonal FET). In some of these teachings, the MFMIS-FET is formed below the first metallization layer.

[0022] In some of these teachings, the gate electrode of the FET provides the bottom electrode of the MFM structure. In some of these teachings, a single sidewall spacer surrounds the MFM structure and the FET. In some of these teachings, the sidewall spacer extends to or over the top of the MFM structure. These structures can be produced by a process in which the sidewall spacers formed during the replacement gate process help define and determine the size of the MFM structure.

[0023] Figure 1 A portion of an IC device 100 including an MFMIS-FET 125 is shown in accordance with some aspects of the present teachings. Figure 2A perspective view of another portion of the IC device 100 including the MFMIS-FET 125 is provided. The MFMIS-FET 125 includes an MFM 127 and a FET 143. The FET 143 includes three FET structures 145 formed around three semiconductor fins 151. Each FET structure 145 includes a different channel region 153 within a different fin 151 and shares a common gate 167. Each channel region 153 is separated from the common gate 167 by an insulator 169. The common gate 167 also provides a bottom electrode for the MFM 127. The MFM 127 also includes a top electrode 133 and a ferroelectric layer 135 located between the top electrode 133 and the common gate 167. The common gate 167 is a floating gate, is a conductive structure, and can include multiple layers of varying composition.

[0024] The MFMIS-FETs 125 are formed over a substrate 175. The substrate 175 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or any other suitable substrate. Shallow trench isolation (STI) regions 173 or similar structures may be formed in the substrate 175 to define the height of the channel regions 153. Wider STI regions 173 may provide isolation between adjacent MFMIS-FETs 125. The fins 151 may be etched from the semiconductor of the substrate 175, or may be one or more other semiconductors grown on the substrate 175.

[0025] A metal interconnect structure 191 is formed over the MFMIS-FET 125. The metal interconnect structure 191 is a product of a back-end-of-line (BEOL) process and includes etch stop layers 131, 109, metal interconnect layers 101, 111, 121 (having metal features 103 and vias 107 connecting metal features 103 in adjacent metal interconnect layers 101, 111, 121). Although only three metal interconnect layers 101, 111, 121 are shown, the metal interconnect structure 191 may have any number of metal interconnect layers and typically includes more than three. The metal features 103 and vias 107 may be, for example, copper (Cu), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), zirconium (Zi), titanium (Ti), tantalum (Ta), aluminum (Al), conductive carbides, oxides, alloys of these metals, and the like. The metal features 103 and vias 107 may be surrounded by a matrix of interlayer dielectrics 105. The etch stop layers 109 , 131 may include one or more layers of silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbide (SIOC), silicon oxycarbonitride (SiOCN), combinations thereof, or the like.

[0026] The interlayer dielectric layer 105 can be one or more low-k dielectrics or very low-k dielectrics. Low-k dielectrics are materials with a smaller dielectric constant than SiO2. SiO2 has a dielectric constant of about 3.9. Examples of low-k dielectrics include organic silicate glass (OSG) (such as carbon-doped silicon dioxide), fluorine-doped silicon dioxide (also known as fluorinated silicate glass (FSG)), organic polymer low-k dielectrics, and porous silicate glass. Very low-k dielectrics are materials with a dielectric constant of about 2.1 or less. Very low-k dielectric materials are typically low-k dielectric materials that form a porous structure. Porosity reduces the effective dielectric constant.

[0027] The MFMIS-FET 125 is surrounded by a sidewall spacer 165. In some embodiments, the sidewall spacer 165 abuts the sidewalls of the FET 143 and the sidewalls of the MFM 127. In some embodiments, the sidewall spacer 165 rises to the height of (the top of) the MFM 127 or higher. In some embodiments, the ferroelectric layer 135 rises to the height of the top electrode 133. In some embodiments, the ferroelectric layer 135 rises near the sidewall spacer 165 and can be separated from the sidewall spacer 165 by an extension of the insulator 169. These structures involve forming the MFM 127 within the space defined by the dummy gate in a replacement gate process for forming the FET 143. Adjacent sidewall spacers 165 can be separated by one or more dielectric layers, such as a contact etch stop layer (CESL) 163 and an interlayer dielectric layer (ILD0) 161. In some embodiments, the ILD0 161 is a low-k dielectric or an ultra-low-k dielectric.

[0028] MFMIS-FET 125 can have a width 123, a length 201, and a footprint of the product of width 123 and length 201. The footprint is the two-dimensional area occupied by the device above substrate 175. FET 143 and MFM 127 each have a footprint that is approximately the same as MFMIS-FET 125, but some variations may occur due to the sidewall tilt of sidewall spacer 165. In some embodiments, width 123 is in a range from 5 to 100 nm. In some embodiments, width 123 is in a range from 10 to 60 nm. In some embodiments, length 201 is in a range from 5 to 30 nm. In some embodiments, length 201 is in a range from 10 to 20 nm.

[0029] The MFM 127 has an effective area associated with capacitance that is almost the same as its footprint. The effective area associated with capacitance can be determined according to the following formula:

[0030]

[0031] Where A is the effective area, C is the capacitance, d is the thickness of the dielectric (ferroelectric layer 135 in the case of MFM 127 and insulator 169 in the case of FET 143), and ε0 is the dielectric constant or effective dielectric constant of the dielectric (if the dielectric is a multilayer composite). The effective area of ​​MFM 127 is approximately the length 203 of the top electrode 133 multiplied by the width 139 of the top electrode 133. The length 203 is approximately twice the length 201 minus the thickness of the ferroelectric layer 135. The width 139 is approximately twice the width 123 minus the thickness of the ferroelectric layer 135.

[0032] FET 143 has an effective area associated with capacitance that is greater than its footprint or the effective area of ​​MFM 127. FET 143 has a length 201 that is nearly equal to the length 203 of FET 143, but the effective area of ​​FET 143 per unit length is much greater than the effective area of ​​MFM 127 because it includes contributions from the sides and top of each of fins 151. The effective area per unit length of MFM 127 is proportional only to width 139. Therefore, the effective area A of FET 143 is FET With MFM 127 effective area A MFM The ratio R is approximately:

[0033]

[0034] Where N F is the number of fins 151, W F Fin width 147, H F is fin height 149, W M is the width 139 of MFM 127. For example, if fin width 147 is 5 nm, fin height 149 is 50 nm, width 139 is 45 nm, and there are three fins 151, the area ratio is 7 to 1. In some embodiments, fin width 147 is in a range from 1 nm to 20 nm. In some embodiments, fin width 147 is in a range from 2 nm to 10 nm. In some embodiments, fin height 149 is in a range from 10 nm to 150 nm. In some embodiments, fin height 149 is in a range from 20 nm to 100 nm. These parameters can be varied to provide a desired area ratio.

[0035] According to the present teachings, the effective area of ​​MFM 127 is relatively large. Its effective area is almost equal to the footprint of FET 143, which is essentially the same as the footprint of the entire MFMIS-FET 125. Keeping the effective area of ​​MFM 127 relatively large can prevent drain current from limiting device performance. Although the effective area of ​​MFM 127 is relatively large, it is much smaller than the effective area of ​​FET 143. The effective area of ​​FET 143 increases with structures such as fins, nanowires, and hexagonal FETS. In some embodiments, the effective area is further increased by using multiple of these structures within each MFMIS-FET 125. While maintaining the effective area of ​​MFM 127, the desired ratio between the capacitance of FET 143 and the capacitance of MFM 127 is achieved by increasing the effective area of ​​FET 143 using a three-dimensional FET structure 145.

[0036] Figure 3 An IC device 300 is shown that is similar to IC device 100, except that IC device 300 has an MFMIS-FET 325 that is different from MFMIS-FET 125, and that has an MFMIS-FET 325 that is separated from FET 143 by one or more metallization layers, such as metallization layers 111 and 121, rather than having MFM 127 formed directly over FET 143. Although MFM 327 is shown between second metallization layer 111 and third metallization layer 101, MFM 327 may be located between any pair of adjacent metallization layers in metal interconnect structure 191.

[0037] The MFM 327 includes a top electrode 335, a ferroelectric layer 333, and a bottom electrode layer 365. The thickness and composition of the top electrode 335 and the ferroelectric layer 333 may be similar to the top electrode 133 and the ferroelectric layer 135 of the MFM 127. The MFM 327 may be flanked by a first sidewall spacer 317 and a second sidewall spacer 315. Adjacent MFMs 327 are further separated by a dielectric 313. The first sidewall spacer 317, the second sidewall spacer 315, and the dielectric layer 313 may be one or more layers of a suitable dielectric, such as silicon dioxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon carbon nitride (SiCN), silicon oxycarbide (SIOC), silicon oxycarbonitride (SiOCN), and the like.

[0038] Figure 4An IC device 400 is shown that is similar to IC device 100, except that IC device 400 includes an MFMIS-FET 425 that is similar to MFMIS-FET 125, except that IC device 400 replaces FET 143 with FET 443. FET 443 includes an array of nanowire FET structures 445, each structure including a channel region 453 provided by a semiconductor nanowire 451, an insulator 469 surrounding the nanowire 451 and separating the nanowire 451 from a common gate 167. The nanowires 451 are non-intersecting.

[0039] Figure 5 An IC device 500 similar to IC device 400 is shown, except that IC device 500 includes an MFMIS-FET 525 similar to MFMIS-FET 425, except that IC device 500 uses FET 543 instead of FET 443. FET 543 includes an array of hexagonal FETs 545, each of which includes a hexagonal semiconductor structure 551, thereby providing a channel region 553 surrounded by an insulator 569 and sharing a common gate 167. FET 443 and FET 543 provide examples of full-ring gate structures. They are also examples of dividing a given channel cross section into many small and non-intersecting parts. Both of these properties contribute to increasing the area ratio R, and can contribute to achieving a desired area ratio, such as an area ratio of 10 to 1 or more.

[0040] Figure 6 to Figure 47 A series of cross-sectional views 600-4700 are provided that illustrate an integrated circuit device according to the present teachings at various stages of fabrication according to a process according to the present teachings. Figure 2 , the even numbers in these figures correspond to a cross section 210 that is perpendicular to the fin 151 along the middle of the length 201. The odd numbers in these figures correspond to a cross section 220 that passes through the middle of the fin 151. Although described with respect to a series of steps Figure 6 to Figure 47 , but it should be understood that the order of the steps can be changed in some cases, and the series of steps are applicable to structures other than the steps shown. In some embodiments, some of these steps can be omitted in whole or in part. In addition, it should be understood that Figure 6 to Figure 47 The structure shown in is not limited to the manufacturing method, but can exist independently of the method and structure.

[0041] like Figure 6 A cross-sectional view of 600 and Figure 7As shown in the cross-sectional view 700 of , the process begins by forming a photoresist mask 601 and using it to pattern a trench 603 in the substrate 175. In some embodiments, the depth 605 of the trench 603 is in the range of from 20nm to 300nm. In some embodiments, the depth 605 is in the range of from 40nm to 200nm. Figure 8 The cross-sectional view 800 and Fig. 9 As shown in the cross-sectional view 900 of , the photoresist mask 601 may be stripped and the trench 603 may be filled with a dielectric to form the STI region 173. The dielectric may be silicon dioxide (SiO2) or the like.

[0042] like Fig.10 Cross-sectional view 1000 and Fig.11 As shown in the cross-sectional view 1100 of , an etching process may be performed to recess the semiconductor between the STI regions 173 to form a trench 1001. In some embodiments, the depth 1003 of the trench 1001 is in the range of 10 nm to 150 nm. In some embodiments, the depth 1003 is in the range of 20 nm to 100 nm.

[0043] like Fig.12 The cross-sectional view 1200 and Fig.13 As shown in the cross-sectional view 1300 of FIG. 1 , a semiconductor may be deposited or grown to fill the trench 1001 and form the fin 151. The fin 151 may include multiple layers of one or more semiconductors. Suitable semiconductors for the fin 151 may include one or more of Si, SiGe, Ge, InP, InGaAs, InAs, GaSb, etc. The fin 151 may be formed by an epitaxial growth process. More generally, the fin 151 may be formed by any suitable process, including having a Figure 6 Cross-sectional view 600 to Fig.13 The cross-sectional view 1300 shows the different steps of the process.

[0044] like Fig.14 The cross-sectional view 1400 and Fig.15 As shown in the cross-sectional view 1500 of , an etching process may be performed to recess the STI region 173 around the fin 151. Fig.16 The cross-sectional view 1600 and Fig.17As shown in the cross-sectional view 1700 of FIG. 17 , a dummy gate stack 1601 may then be formed over the fin 151. The dummy gate stack 1601 includes a dielectric layer 1605 and a dummy gate layer 1603. The dielectric layer 1605 may be a deposition layer formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc., such as silicon dioxide (SiO2), etc. Optionally, the dielectric layer 1605 may be grown by oxidizing a thin layer at the surface of the fin 151. The dummy gate layer 1603 may be polysilicon, etc., formed by chemical vapor deposition (CVD), etc. In some embodiments, the thickness 1701 of the dummy gate layer 1603 on the fin 151 is in a range from 10 nm to 300 nm. In some embodiments, the thickness 1701 is in a range from 20 nm to 100 nm.

[0045] like Fig.18 Cross-sectional view 1800 and Fig.19 As shown in the cross-sectional view 1900 of , a photoresist mask 1801 can be formed and used to pattern the dummy gate layer 1603 to form the dummy gate 1803. Any suitable etching process can be used to pattern the dummy gate layer 1603, any suitable etching process, for example, dry etching (such as plasma etching), etc. The dummy gate 1803 is shown as having vertical sidewalls, but their sidewalls can have a gradually changing slope. In some embodiments, the slope is within 20° of the vertical direction.

[0046] like Fig. 20 Cross-sectional view of 2000 and Fig.21 As shown in the cross-sectional view 2100 of FIG. 1 , a spacer 165 may be formed around the dummy gate 1803. Fig.18 Cross-sectional view 1800 and Fig.19 A layer of spacer material is deposited over the structure shown in the cross-sectional view 1900 of FIG. 1 (after stripping the photoresist mask 1801), followed by an anisotropic etching process to form the spacer 165, which leaves only the spacer material on the side of the dummy gate 1803. Materials that may be suitable for the spacer 165 include, but are not limited to, silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbide (SIOC), silicon oxycarbonitride (SiOCN), and the like. Suitable processes may be chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and the like. Suitable etching processes may be dry etching processes, such as plasma etching, and the like. For ease of illustration, the spacer 165 is shown as having a uniform thickness and sharp vertical sidewalls, but in practice may be slightly tapered and narrowed near the top of the dummy gate 1803.

[0047] like Fig. 22 Cross-sectional view 2200 and Fig.23As shown in the cross-sectional view 2300 of , the areas of the fin 151 not covered by the dummy gate 1803 are doped to form source / drain regions 2301. Some of the doping may occur before forming the spacers 165, while some of the doping may occur after forming the spacers 165. The dielectric layer 1605 may be removed in the areas between the dummy gates 180 or between the spacers 165 before doping. Alternatively or additionally, an epitaxial growth process may be used to form and / or extend the source / drain regions 2301. In some embodiments, the epitaxial growth causes the source / drain regions 2301 on adjacent fins 151 of the FET 143 to merge. An annealing process may be performed on the source / drain regions 2301 before replacing the dummy gate 1803.

[0048] like Fig.24 Cross-sectional view 2400 and Fig.25 As shown in the cross-sectional view 2500 of , CESL 163 may be formed, followed by deposition of ILD0 161 and planarization to remove these materials from the top of the dummy gate 1803. CESL 163 may be, for example, silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon oxycarbide (SiOC), etc., and may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. ILD0 161 may be a low-k dielectric, an extremely low-k dielectric, or any other dielectric. ILD0 161 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or any other suitable process. Planarization may be performed by chemical mechanical polishing (CMP) or any other suitable planarization process.

[0049] like Fig.26 Cross-sectional view 2600 and Fig. 27 As shown in the cross-sectional view 2700 of FIG. 27, an etch stop layer 2701 may be formed above ILD0 161 between the dummy gates 1803. Forming the etch stop layer 2701 may include etching between the dummy gates 1803 to recess ILD0 161, depositing an etch stop material layer, and planarizing to remove the etch stop material above the dummy gates 1803. The recessing process may be dry etching, wet etching, etc. The etch stop material may be silicon nitride (Si3N4), etc., and may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. The planarization process may be CMP, etc.

[0050] like Fig.28 Cross-sectional view 2800 and Fig.29 As shown in the cross-sectional view 2900 of , a process may then be performed to remove the dummy gate 1803. The process may also remove the dielectric layer 1605. The removal process may be dry etching, wet etching, a combination thereof, or the like.

[0051] like Fig.30 Cross-sectional view of 3000 and Fig.31 As shown in the cross-sectional view 3100 of , a replacement gate can then be formed. Forming the replacement gate includes depositing an insulator 169 and a common gate 167. Insulator 169 may include multiple layers. In some embodiments, at least one of those layers is a high-k dielectric. For example, insulator 169 may include a high-k dielectric layer separated from fin 151 by an interface dielectric layer. The interface layer may be silicon dioxide (SiO2), silicon oxynitride (SiON), etc. The interface layer may be formed by oxidation of fin 151, by deposition, or due to interaction between a high-k dielectric and a semiconductor of fin 151. The interface layer may be very thin to minimize the contribution of the interface layer to the total equivalent oxide thickness of the resulting gate. The thickness may be, for example, in the range of from 1 to 20 angstroms.

[0052] High-k dielectrics are dielectrics with a higher dielectric constant than silicon dioxide (SiO2). Examples of high-k dielectrics include hafnium-based materials such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), hafnium oxide-aluminum oxide (HfO2-Al2O3) alloys, etc. Other examples of high-k dielectrics include, but are not limited to, zirconium oxide (ZrO2), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), yttrium oxide (Y2O3), lanthanum oxide (La2O3), strontium titanium oxide (SrTiO3), etc. The thickness of the high-k dielectric layer can be, for example, in the range of from 5 to 50 angstroms. The high-k dielectric layer can be formed by any suitable process. Examples of processes can be, but are not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.

[0053] The common gate 167 may include multiple layers of different compositions. Different metals may be used for different regions of the substrate 175. One or more layers may be a work function metal. Examples of work function metals include, but are not limited to, titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), tantalum carbide (TaC), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tungsten nitride (WN), molybdenum nitride (MoN), molybdenum oxynitride (MoON), etc. Additional metal layers may include, but are not limited to, tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), zirconium (Zi), titanium (Ti), tantalum (Ta), aluminum (Al), conductive carbides, oxides, and alloys of these metals, etc. The metal layer may be formed by any suitable process or combination of processes. Physical vapor deposition (PVD) is a typical process. Examples of other metal layer formation processes that may be suitable include electroplating, chemical plating, ALD, and CVD. Removal of material above the height of the etch stop layer 2701, for example, by CMP planarization leaves behind Fig.30 Cross-sectional view of 3000 and Fig.31 The structure shown in the cross-sectional view 3100. The structure includes FETs 143 each having three FET structures 145.

[0054] on the one hand, Fig.32 Cross-sectional view 3200 and Fig.33 A cross-sectional view 3300 and Fig.34 Cross-sectional view 3400 and Fig.35 The cross-sectional view 3500 of FIG. 35 provides two examples of the common gate 167 structure, the first feature is a thick work function metal 3201, and the second feature is a thin work function metal 3201. The work function metal 3201 can be, for example, titanium nitride (TiN), etc. The other metal 3401 can be tungsten (W), etc. The thick work function metal 3201 can completely fill the space between the fins 151. The thick work function metal 3201 does not completely fill the space between the fins 151. The thick work function metal 3201 can completely fill the space between the spacers 165, or it can leave some space for the other metal layer 3401. The thickness of the work function metal 3201 can be used to change the threshold voltage.

[0055] like Fig.36 Cross-sectional view 3600 and Fig.37 As shown in the cross-sectional view 3700 of FIG. 37A , a process may be performed to recess the common gate 167 below the height of the spacer 165. The process may be a wet etch, a dry etch, etc. In some embodiments, the depth 3701 is half or more of the height of the spacer 165 above the fin 151. In some embodiments, the depth 3701 is in a range from 10 nm to 150 nm. In some embodiments, the depth 3701 is in a range from 20 nm to 50 nm.

[0056] like Fig.38 Cross-sectional view of 3800 and Fig.39 As shown in the cross-sectional view 3900, it can be Fig.36 Cross-sectional view 3600 and Fig.37 A ferroelectric layer 3803 and a top electrode layer 3801 are formed above the structure shown in the cross-sectional view 3700 of to form an MFM unit stack, wherein the common gate 167 provides a bottom electrode layer. Before annealing, the material of the ferroelectric layer 3803 may or may not be a ferroelectric. If not, it will become a ferroelectric during subsequent processes. The ferroelectric layer 3803 includes an electric dipole. In some embodiments, the thickness of the ferroelectric layer 3803 is in a range from 1 nm to 15 nm. In some embodiments, the thickness of the ferroelectric layer 3803 is in a range from 1 nm to 5 nm. Examples of ferroelectric materials include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium zirconium oxide (HfZrO), aluminum oxide (Al2O3), titanium oxide (TiO2), lanthanum oxide (LaO x )、BaSrTiO x (BST), PbZrTiO x (PZT), etc. Some of these materials (such as HfO2, HfSiO x 、HfZrO x , Al2O3, TiO2 and LaO x ) include the same elements as some high-k dielectric materials, but the ratio of the elements or the crystal structure may be different. Ferroelectric materials can be formed using CVD, PVD, ALD, etc.

[0057] The top electrode layer 3801 includes one or more material layers, such as tungsten (W), titanium (Ti), tantalum (Ta), silver (Ag), aluminum (Al), nickel (Ni), their conductive alloys, etc. An annealing step may also be performed on the ferroelectric layer 3803. Annealing may be performed using thermal annealing, microwave annealing, laser annealing, or other applicable methods. The annealing temperature may be in the range of from 200°C to 600°C. The annealing may be lower in temperature or shorter in duration than the annealing used on the source / drain region 2301 (usually at least 5 seconds at 1000°C). A low annealing temperature or short duration may prevent the high-k dielectric in the insulator 169 from interacting with the metal in the common gate 167 in a manner that changes the threshold voltage.

[0058] like Fig.40 Cross-sectional view of 4000 and Fig.41As shown in the cross-sectional view 4100 of FIG. 41, a planarization process may be performed to define separate MFM 127 and MFMIS-FET 125. The planarization process may be CMP or the like. The process forms a separate ferroelectric layer 135 from the ferroelectric layer 3803, and forms a separate top electrode 133 from the top electrode layer 3801. The etch stop layer 2701 may help define the endpoint of the planarization process. In some embodiments, the planarization process removes the etch stop layer 2701.

[0059] like Fig.42 Cross-sectional view 4200 and Fig.43 As shown in the cross-sectional view 4300 of FIG. 43, a process may be performed to recess the MFM 127 below the height of the spacer 165. The process may be wet etching, dry etching, etc. Fig.44 Cross-sectional view 4400 and Fig.45 As shown in the cross-sectional view 4500 of FIG. 45, the recesses 4301 formed by the recess process can be filled to produce an etch stop layer 131 covering the MFMIS-FET 125 but not covering the ILD0 161. Filling these recesses 4301 can include depositing an etch stop material, followed by a planarization process to remove the etch stop material from above the ILD0 161. The etch stop material can be silicon nitride (Si3N4), silicon oxynitride (SiON), etc. The deposition process can be CVD, ALD, etc. The planarization process can be CMP, etc.

[0060] like Fig.46 Cross-sectional view of 4600 and Fig.47 As shown in the cross-sectional view 4700, the interlayer dielectric 105 can be deposited on Fig.44 Cross-sectional view 4400 and Fig.45 A through hole 107 may be formed through the interlayer dielectric 105 to connect to the top electrode 133. The through hole 107 may be formed by etching an opening through the interlayer dielectric 105, depositing metal, and planarizing to remove excess metal above the interlayer dielectric 105. The resulting structure is also shown in FIG. Figure 2 Additional vias (not shown) may be formed at this stage of the process to make contact with the source / drain regions 2301. Further processes, which may include damascene or dual damascene processes, may produce a corresponding Figure 1 The structure of IC 100.

[0061] Fig.48A flow chart of a process 4800 according to some aspects of the present teachings is provided. Process 4800 can be used to produce integrated circuit devices according to the present teachings. Although process 4800 is shown and described herein as a series of steps or events, it should be understood that the illustrated order of such steps or events should not be interpreted in a restrictive sense. For example, in addition to those steps or events shown and / or described herein, some steps may occur in a different order and / or occur simultaneously with other steps or events. In addition, all of the steps shown may not be required to implement one or more aspects or embodiments described herein. In addition, one or more steps described herein may be implemented in one or more separate steps and / or stages.

[0062] Process 4800 begins with step 4801, forming STI region 173, such as Figure 6 A cross-sectional view of 600 and Figure 8 The process 4800 continues with step 4803 to form the fin 151, as shown in FIG. Fig.10 Cross-sectional view 1000 and Fig.13 This may include forming a recess in a dielectric (such as STI region 173) and growing a semiconductor within the resulting recess. Alternatively, any other suitable process may be used to form fin 151.

[0063] Step 4805 is to recess the STI region 173 or remove other dielectrics around the fin 151 to expose the fin 151, such as Fig.14 Step 4807 is to form a dummy gate stack 1601 above the fin 151, as shown in FIG. Fig.16 The cross-sectional view 1600 and Fig.17 1700. Alternatively, this can be a conventional gate stack and subsequent steps associated with the replacement gate process can be eliminated. Step 4809 is to pattern the dummy gate stack 1601 to produce a dummy gate 1803, as shown in FIG. Fig.18 Cross-sectional view 1800 and Fig.19 As shown in the cross-sectional view 1900.

[0064] Step 4811 is to form a sidewall spacer 165 around the dummy gate 1803. Fig.21 Step 4813 is to form source / drain regions 2301, such as Fig.23 2300. Forming the source / drain region 2301 may include doping before and / or after step 4811 to form the sidewall spacer 165. Forming the source / drain region 2301 may also include epitaxial growth of a semiconductor.

[0065] Step 4815 is to deposit CESL 163, such as Fig.25 The cross-sectional view 2500 is shown in FIG. 4817. Step 4817 is to form ILD0 161, as shown in FIG. Fig.25 The cross-sectional view 2500 is shown. Forming ILD0 161 may include depositing a dielectric and planarizing to form the structure as shown.

[0066] Step 4819 is an etching process to recess ILD0 161 below the height of spacer 165. Step 4821 is to deposit etch stop layer 2701. Step 4823 is to planarize to leave only etch stop layer 2701 in the recess created by step 1817, as shown in FIG. Fig. 27 As shown in the cross-sectional view 2700.

[0067] Step 4825 is to remove the dummy gate 1803, such as Fig.28 Cross-sectional view 2800 and Fig.29 Steps 4829 and 4831 form a replacement high-k metal gate (HKMG) stack, such as Fig.30 Cross-sectional view of 3000 and Fig.31 3100. Step 4829 is to form an insulator 169, which may include an interfacial layer (IL) and a high-k dielectric layer. Step 4831 is to form a common gate 167, which is the gate of FET 143 and will provide the bottom electrode layer of MFM 127. Common gate 167 can also be described as a floating gate and can include Fig.32 Cross-sectional view 3200 and Fig.35 The cross-sectional view 3500 shows multiple layers of multiple materials.

[0068] Step 4833 is an etching process to recess the common gate 167 below the height of the spacer 165, such as Fig.36 Cross-sectional view 3600 and Fig.37 3700. The space (recess 3703) created by the recessing process will accommodate the ferroelectric layer 135 and the top electrode 133 of the MFM 127.

[0069] Step 4835 is to deposit the ferroelectric layer 135 and the top electrode 133 to form the MFM cell stack, such as Fig.38 Cross-sectional view 3800 and Fig.39 3900. Step 4839 is an annealing process that can be used to achieve ferroelectric properties in the ferroelectric layer 135. Step 4841 is planarization to remove the portion of the MFM unit stack outside the groove 3703. The planarization process defines the MFM 127 from the MFM unit stack, such as Fig.40 Cross-sectional view of 4000 and Fig.414100. Planarization also completes the definition of the individual MFMIS-FETs 125. Planarization can also remove the etch stop layer 2701.

[0070] Step 4843 is an etching process to recess the MFM 127 below the height of the spacer 165 forming the groove 4301, as shown in FIG. Fig.43 Step 4845 is to deposit the etch stop layer 131 and planarize it, thereby limiting the etch stop layer 131 in the groove 4301, as shown in FIG. Fig.45 As shown in the cross-sectional view 4500.

[0071] Step 4847 is to deposit a layer of interlayer dielectric 105, which can be considered as another layer of ILD0 161, such as Fig.46 Cross-sectional view of 4600 and Fig.47 4700. Step 4849 is to etch openings for vias 107 through interlayer dielectric 105, and step 4851 is to fill these openings with conductive material to form vias 107, such as Fig.46 Cross-sectional view of 4600 and Fig.47 A cross-sectional view of 4700 and Figure 2 Step 4853 includes completing the BEOL process and forming devices (such as Figure 1 The IC device 100 may further include an additional step.

[0072] Some aspects of the present teachings relate to an integrated circuit (IC) including a substrate, a field effect transistor (FET), and a metal ferroelectric metal structure (MFM). The FET includes a gate electrode and one or more channel regions separated from the gate electrode by an insulator. The MFM structure includes a top electrode and a bottom electrode separated by a ferroelectric layer. The gate electrode is coupled to the bottom electrode or is a structure essentially the same as the bottom electrode. The FET has an effective area related to the capacitance of the FET. The FET has a footprint located above the substrate. The effective area of ​​the FET is larger than the footprint of the FET.

[0073] Some aspects of the present teachings relate to an integrated circuit (IC) including a metal ferroelectric metal structure and a plurality of field effect transistor structures. The metal ferroelectric metal structure includes a top electrode and a bottom electrode separated by a ferroelectric layer. The plurality of field effect transistor structures each include a semiconductor source / drain region separated by a semiconductor channel region, a gate electrode, and an insulator between the gate electrode and the channel region. The gate electrode is coupled to or integral with the bottom electrode.

[0074] Some aspects of the present teachings relate to a method of manufacturing an integrated circuit (IC) having an MFMIS-FET. The method includes forming a semiconductor fin, forming a dummy gate stack over the semiconductor fin, patterning the dummy gate stack to define a dummy gate, forming a sidewall spacer around the dummy gate, and replacing the dummy gate with an MFMIS-FET including a high-k dielectric, a metal gate, a ferroelectric layer, and a top electrode layer.

[0075] Some aspects of the present teachings relate to an integrated circuit, including: a substrate 175; a field effect transistor (FET) 143, including a gate electrode 167 and one or more channel regions 151 separated from the gate electrode 167 by an insulator 169; and a metal ferroelectric metal structure (MFM) 127, including a top electrode 133 and a bottom electrode separated by a ferroelectric layer 135; wherein the gate electrode 167 is coupled to the bottom electrode or is integral with the bottom electrode; the field effect transistor has an effective area related to the capacitance of the field effect transistor; the field effect transistor has a footprint above the substrate; and the effective area of ​​the field effect transistor is greater than the footprint of the field effect transistor. In some embodiments, the metal ferroelectric metal structure has an effective area related to the capacitance of the metal ferroelectric metal structure; the effective area of ​​the field effect transistor is greater than the effective area of ​​the metal ferroelectric metal structure. In some embodiments, the gate electrode 167 of the field effect transistor is integral with the bottom electrode of the metal ferroelectric metal structure. In some embodiments, the metal ferroelectric metal structure has a footprint above the substrate; the field effect transistor has a footprint above the substrate; the footprint of the metal ferroelectric metal structure is equal to or greater than the footprint of the field effect transistor. In some embodiments, the integrated circuit further comprises: a sidewall spacer 165 surrounding the metal ferroelectric metal structure and the field effect transistor. In some embodiments, the integrated circuit further comprises: a sidewall spacer 165 adjacent to the field effect transistor; wherein the metal ferroelectric metal structure has a top located at or below the top of the sidewall spacer. In some embodiments, the integrated circuit further comprises: a metal interconnect structure 191 comprising a plurality of metallization layers formed above the substrate; wherein the metal ferroelectric metal structure is located below the metal interconnect structure. In some embodiments, the insulator is formed above a plurality of semiconductor fins. In some embodiments, the one or more channel regions respectively comprise one or more nanowires or respectively comprise hexagonal field effect transistors, wherein the channel regions are discontinuous with each other and are arranged in a series of rows and columns below the ferroelectric layer of the metal ferroelectric metal structure.

[0076] Other aspects of the present teachings relate to an integrated circuit (IC) comprising: a metal ferroelectric metal structure 127 including a top electrode 133 and a bottom electrode separated by a ferroelectric layer 135; and a plurality of field effect transistor structures, each including a semiconductor source / drain region separated by a semiconductor channel region 151, a gate electrode 167, and an insulator 169 located between the gate electrode and the semiconductor channel region; wherein the gate electrode of each of the plurality of field effect transistor structures is coupled to or integral with the bottom electrode. In some embodiments, the semiconductor channel regions of the plurality of field effect transistor structures are non-intersecting. In some embodiments, the semiconductor channel region of each of the plurality of field effect transistor structures has a plurality of sides; and the gate electrode is located on a plurality of sides of its corresponding semiconductor channel region. In some embodiments, each of the semiconductor channel regions is formed by a different semiconductor fin. In some embodiments, the ferroelectric layer extends over the semiconductor channel region of each of the plurality of field effect transistor structures. In some embodiments, the integrated circuit further comprises a sidewall spacer 165 surrounding the metal ferroelectric metal structure and the plurality of field effect transistor structures. In some embodiments, the sidewall spacer 165 extends from a height adjacent to the plurality of field effect transistor structures to a height at or above a top of the metallic ferroelectric metal structure.

[0077] Still other aspects of the present teachings relate to a method of manufacturing an integrated circuit (IC) including an MFMIS-FET, the method comprising: forming a semiconductor fin over a substrate; forming a dummy gate stack over the semiconductor fin; patterning the dummy gate stack to define a dummy gate; forming a sidewall spacer around the dummy gate; and replacing the dummy gate with an MFMIS-FET including a high-k dielectric, a metal gate, a ferroelectric layer, and a top electrode layer. In some embodiments, replacing the dummy gate with an MFMIS-FET including a high-k dielectric, a metal gate, a ferroelectric layer, and a top electrode layer comprises: replacing the dummy gate with a high-k dielectric and a metal gate; recessing the metal gate below the height of the sidewall spacer to form a groove; and forming a ferroelectric layer and a top electrode layer within the groove. In some embodiments, the dummy gate is formed over a plurality of semiconductor fins. In some embodiments, the method further comprises: etching the top electrode layer below the height of the sidewall spacer to form a second groove; and filling the second groove to form an etch stop layer over the top electrode.

[0078] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that this equivalent construction does not deviate from the spirit and scope of the present invention, and that they can make multiple changes, substitutions and changes herein without departing from the spirit and scope of the present invention.

Claims

1. An integrated circuit, comprising: substrate; A field effect transistor (FET) comprising a gate electrode and one or more channel regions separated from the gate electrode by an insulator; a metal-ferroelectric-metal structure (MFM) comprising a top electrode and a bottom electrode separated by a ferroelectric layer; a sidewall spacer adjacent to the field effect transistor; as well as an etch stop layer, located on the top electrode, wherein a top surface of the etch stop layer is flush with a top surface of the sidewall spacer; wherein the gate electrode is coupled to the bottom electrode or is integral with the bottom electrode; The field effect transistor has an effective area related to the capacitance of the field effect transistor; The field effect transistor has a footprint over the substrate; and The active area of ​​the field effect transistor is larger than the footprint of the field effect transistor.

2. The integrated circuit of claim 1 , wherein: The metal ferroelectric metal structure has an effective area related to the capacitance of the metal ferroelectric metal structure; The effective area of ​​the field effect transistor is larger than the effective area of ​​the metal ferroelectric metal structure.

3. The integrated circuit according to claim 1, wherein: The gate electrode of the field effect transistor is integral with the bottom electrode of the metallic ferroelectric metal structure.

4. The integrated circuit of claim 1, wherein: The metallic ferroelectric metal structure has a footprint over the substrate; The field effect transistor has a footprint over the substrate; The footprint of the metallic ferroelectric metal structure is equal to or greater than the footprint of the field effect transistor.

5. The integrated circuit according to claim 1, wherein: The sidewall spacer surrounds the metal ferroelectric metal structure and the field effect transistor.

6. The integrated circuit of claim 1, wherein: The metallic ferroelectric metal structure has a top portion located at or below a top portion of the sidewall spacer.

7. The integrated circuit of claim 1 , further comprising: a metal interconnect structure comprising a plurality of metallization layers formed over the substrate; Wherein, the metal ferroelectric metal structure is located below the metal interconnection structure.

8. The integrated circuit of claim 1, wherein: The insulator is formed over the plurality of semiconductor fins.

9. The integrated circuit of claim 1, wherein: The one or more channel regions respectively include one or more nanowires or respectively include hexagonal field effect transistors, wherein the channel regions are discontinuous with each other and are arranged in a series of rows and columns below the ferroelectric layer of the metallic ferroelectric metal structure.

10. An integrated circuit (IC), comprising: a metallic ferroelectric metal structure including a top electrode and a bottom electrode separated by a ferroelectric layer; a plurality of field effect transistor structures, each comprising semiconductor source / drain regions separated by a semiconductor channel region, a gate electrode, and an insulator between the gate electrode and the semiconductor channel region; sidewall spacers surrounding the metal ferroelectric metal structure and the plurality of field effect transistor structures; as well as an etch stop layer, located on the top electrode, wherein a top surface of the etch stop layer is flush with a top surface of the sidewall spacer; The gate electrode of each of the plurality of field effect transistor structures is coupled to the bottom electrode or is integral with the bottom electrode.

11. The integrated circuit of claim 10, wherein: The semiconductor channel regions of the plurality of field effect transistor structures are disjoint.

12. The integrated circuit of claim 10, wherein: The semiconductor channel region of each of the plurality of field effect transistor structures has a plurality of sides; and The gate electrodes are located on multiple sides of their corresponding semiconductor channel regions.

13. The integrated circuit of claim 10, wherein: Each of the semiconductor channel regions is formed of a different semiconductor fin.

14. The integrated circuit of claim 10, wherein: The ferroelectric layer extends over the semiconductor channel region of each of the plurality of field effect transistor structures.

15. The integrated circuit of claim 10, wherein: A bottom surface of the etch stop layer contacts a top surface of the ferroelectric layer.

16. The integrated circuit of claim 15, wherein: The sidewall spacers extend from a height adjacent to the plurality of field effect transistor structures to a height at or above a top of the metallic ferroelectric metal structure.

17. A method of manufacturing an integrated circuit (IC) comprising an MFMIS-FET, the method comprising: forming a semiconductor fin over the substrate; forming a dummy gate stack over the semiconductor fin; patterning the dummy gate stack to define a dummy gate; forming a sidewall spacer around the dummy gate; replacing the dummy gate with an MFMIS-FET comprising a high-k dielectric, a metal gate, a ferroelectric layer, and a top electrode layer; etching the top electrode layer below the height of the sidewall spacers to form a recess; as well as The recess is filled to form an etch stop layer over the top electrode, wherein a top surface of the etch stop layer is flush with a top surface of the sidewall spacer.

18. The method according to claim 17, wherein: Replacing the dummy gate with an MFMIS-FET including a high-k dielectric, a metal gate, a ferroelectric layer, and a top electrode layer comprises: replacing the dummy gate with a high-k dielectric and a metal gate; recessing the metal gate below the height of the sidewall spacer to form another recess; and A ferroelectric layer and a top electrode layer are formed in the other recess.

19. The method according to claim 17, wherein: The dummy gate is formed over the plurality of semiconductor fins.

20. The method according to claim 17, wherein: A bottom surface of the etch stop layer contacts a top surface of the ferroelectric layer.

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