Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a first well disposed in the substrate, a second well disposed in the substrate and adjacent to the first well, an isolation structure disposed in the first well, and a gate structure disposed on the substrate and including a first gate portion and a second gate portion, wherein the first gate portion overlaps the first well and the second well, and an opening between the first gate portion and the second gate portion exposes a portion of the isolation structure. The semiconductor structure can be effectively reduced in damage caused by hot carrier injection testing, and the reliability of the semiconductor structure can be improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor structure, and more particularly to a laterally diffused metal oxide semiconductor (LMOS). Background Art

[0002] Semiconductor devices are used in many electronic devices, such as personal computers, mobile phones, digital cameras, and other electronic devices. The manufacturing process for semiconductor devices typically involves sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers onto a substrate, and patterning the different material layers using photolithography techniques to form circuit components and electronic elements.

[0003] During semiconductor manufacturing processes, hot carrier injection (HCI) testing is performed on semiconductor devices, such as laterally diffused metal oxide semiconductor (LDMOS). However, after the HCI test, the LDMOS is damaged, resulting in leakage current. Furthermore, each HCI test causes additional damage to the LDMOS. Consequently, the leakage current becomes increasingly severe, impacting the reliability of the LDMOS device.

[0004] Although the existing LDMOS devices have generally improved some of the problems, they are not satisfactory in all aspects. Therefore, a novel semiconductor structure is still needed to meet various requirements. Summary of the Invention

[0005] An embodiment of the present invention provides a semiconductor structure and a method for forming the same. By providing a gate structure with an opening that exposes a portion of the isolation structure, damage to the semiconductor structure caused by hot carrier injection testing can be effectively reduced, thereby improving the reliability of the semiconductor structure.

[0006] According to some embodiments of the present invention, a semiconductor structure is provided. The semiconductor structure includes a substrate; a first well disposed in the substrate; a second well disposed in the substrate and adjacent to the first well; an isolation structure disposed in the first well; and a gate structure disposed on the substrate and including a first gate portion and a second gate portion, wherein the first gate portion overlaps the first well and the second well, and an opening is defined between the first gate portion and the second gate portion, exposing a portion of the isolation structure.

[0007] According to some embodiments of the present invention, a method for forming a semiconductor structure is provided. The method comprises: providing a substrate; forming a first well in the substrate; forming a second well in the substrate adjacent to the first well; forming an isolation structure in the first well; and forming a gate structure on the substrate, wherein the gate structure comprises a first gate portion and a second gate portion, the first gate portion overlapping the first well and the second well, and an opening between the first gate portion and the second gate portion exposing a portion of the isolation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following describes embodiments of the present invention in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of elements may be arbitrarily enlarged or reduced to clearly illustrate the features of the embodiments of the present invention.

[0009] Figure 1 is a cross-sectional view illustrating a stage of forming a semiconductor structure according to some embodiments of the present invention.

[0010] Figure 2 is a cross-sectional view illustrating a stage of forming a semiconductor structure according to some embodiments of the present invention.

[0011] Figure 3 is a cross-sectional view illustrating a stage of forming a semiconductor structure according to some embodiments of the present invention.

[0012] Figure 4 is a cross-sectional view illustrating a stage of forming a semiconductor structure according to some embodiments of the present invention.

[0013] Figure 5 FIG. 1 is a partial enlarged view of a semiconductor structure according to some embodiments of the present invention.

[0014] Figure 6 is a cross-sectional view illustrating a stage of forming a semiconductor structure according to some embodiments of the present invention.

[0015] Figure Number:

[0016] 10~Open mouth;

[0017] 100~Semiconductor structure;

[0018] 102~base;

[0019] 104a, 104b~isolation structure;

[0020] 106~First Well;

[0021] 108~Second Well;

[0022] 110~first doped region;

[0023] 112~ second doping region;

[0024] 114~third doping region;

[0025] 116~Gate structure;

[0026] 116a~first gate portion;

[0027] 116b~second gate portion;

[0028] 118~interlayer dielectric layer;

[0029] 120~source electrode;

[0030] 120a, 120b, 122a~contact holes;

[0031] 122~drain electrode;

[0032] D ~ distance;

[0033] L ~ length;

[0034] S1~first side wall;

[0035] E1~first end;

[0036] E2~Second end. DETAILED DESCRIPTION

[0037] The following discloses many different implementation methods or examples to implement the different features of the embodiments of the present invention. The following describes specific embodiments of components and their arrangements to illustrate the embodiments of the present invention. Of course, these embodiments are only for illustration and should not be used to limit the scope of the embodiments of the present invention. For example, when the specification mentions that a first feature is formed on a second feature, it includes an embodiment in which the first feature and the second feature are in direct contact, and also includes an embodiment in which there are other features between the first feature and the second feature, that is, the first feature and the second feature are not in direct contact. In addition, repeated numbers or marks may be used in different embodiments. These repetitions are only for the purpose of simply and clearly describing the embodiments of the present invention and do not represent a specific relationship between the different embodiments and / or structures discussed.

[0038] In addition, spatially relative terms may be used, such as "below," "beneath," "lower," "above," "upper," and similar terms. These spatially relative terms are intended to facilitate describing the relationship between one element or feature and another element or feature in the drawings. These spatially relative terms include different orientations of the device in use or operation, as well as the orientations depicted in the drawings. When the device is rotated 90 degrees or in other orientations, the spatially relative adjectives used herein will also be interpreted based on the orientation.

[0039] Here, the terms "about," "approximately," and "substantially" generally mean within + / -20% of a given value, preferably within + / -10%, and more preferably within + / -5%, or within + / -3%, or within + / -2%, or within + / -1%, or within 0.5%. The numerical values ​​given herein are approximate values, that is, in the absence of specific description of "about," "approximately," or "substantially," the given numerical value may still imply the meaning of "about," "approximately," or "substantially."

[0040] It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms, and these terms are merely used to distinguish different elements, components, regions, layers, and / or parts. Thus, a first element, component, region, layer, and / or part discussed below may be referred to as a second element, component, region, layer, and / or part without departing from the teachings of the present invention.

[0041] Although the steps in some embodiments are described as being performed in a specific order, these steps may be performed in any other logical order. In different embodiments, some of the steps described may be replaced or omitted, and other operations may be performed before, during, and / or after the steps described in the embodiments of the present invention. The high electron mobility transistors in the embodiments of the present invention may include other features. In different embodiments, some features may be replaced or omitted.

[0042] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meanings as commonly understood by one of ordinary skill in the art to which this invention belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant art and this invention, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of this invention.

[0043] Furthermore, in some embodiments of the present invention, terms such as "connect," "connect," and "interconnect," unless otherwise specified, may refer to two structures being in direct contact, or to two structures not being in direct contact, with another structure positioned between them. Furthermore, such terms may include situations where both structures are movable or both structures are fixed.

[0044] Unless otherwise specified, elements or layers with similar names may be formed using similar materials or methods.

[0045] Figures 1 to 46 are cross-sectional views illustrating different stages of forming a semiconductor structure 100 according to some embodiments of the present invention. Figure 1 As shown, a substrate 102 is provided. The substrate 102 may be a semiconductor substrate. The semiconductor substrate may be an elemental semiconductor, including silicon or germanium; a compound semiconductor, including gallium nitride (GaN), silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including silicon-germanium alloy (SiGe), gallium arsenide-phosphide alloy (GaAsP), aluminum indium arsenide alloy (AlInAs), aluminum gallium arsenide alloy (AlGaAs), gallium indium arsenide alloy (GaInAs), gallium indium phosphide alloy (GaInP), and / or gallium indium arsenide-phosphide alloy (GaInAsP), or a combination of the above materials.

[0046] In some embodiments, substrate 102 may be a single crystal substrate, a multi-layer substrate, a gradient substrate, other suitable substrates, or combinations thereof. Furthermore, substrate 102 may also be a semiconductor-on-insulator (SOI) substrate, which may include a base plate, a buried oxide layer disposed on the base plate, or a semiconductor layer disposed on the buried oxide layer. Furthermore, in some embodiments, substrate 102 is an n-type substrate. In other embodiments, substrate 102 is a p-type substrate.

[0047] Then, refer to Figure 1, isolation structures 104a and 104b are formed in substrate 102. Specifically, isolation structures 104a and 104b are embedded in substrate 102. The top surface of isolation structure 104a and the top surface of isolation structure 104b are coplanar with the top surface of substrate 102. In some embodiments, isolation structures 104a and 104b can be formed by a local oxidation of silicon (LOCOS) isolation process, a shallow trench isolation (STI) process, or a combination thereof. In some embodiments, isolation structures 104a and 104b are formed of a dielectric material. In some embodiments, the dielectric material of isolation structures 104a and 104b includes silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or a combination thereof.

[0048] Next, see Figure 2 A first well 106 and a second well 108 adjacent to the first well 106 are formed in the substrate 102. A portion of the first well 106 is disposed below the isolation structure 104a, and the second well 108 is disposed between the isolation structures 104a and 104b.

[0049] In some embodiments, the first well 106 and the second well 108 can be formed by an ion implantation process. In some embodiments, the first well 106 and the second well 108 can be formed by two separate ion implantation processes. The first well 106 and the second well 108 can have different conductivity types. In some embodiments, the first well 106 has a first conductivity type and the second well 108 has a second conductivity type opposite to the first conductivity type. Alternatively, the first well 106 has the second conductivity type and the second well 108 has the first conductivity type. Specifically, in some embodiments, the first well 106 can be a p-type well and the second well 108 can be an n-type well to serve as an n-type metal-oxide-semiconductor field-effect transistor (NMOS). In some embodiments, the first well 106 can be an n-type well and the second well 108 can be a p-type well to serve as a p-type metal-oxide-semiconductor field-effect transistor (PMOS). In some embodiments, the doping concentration of the first well 106 is between about 1×10 16 cm -3 and 1×10 18 cm -3 The doping concentration of the second well 108 is between about 1×10 16 cm -3 and 1×10 18 cm -3 .

[0050] Next, see Figure 3 , forming a first doping region 110 and a second doping region 112 in the second well 108, and forming a third doping region 114 in the first well 106. The first doping region 110 is adjacent to the second doping region 112. In some embodiments, the conductivity type of the first doping region 110 is the same as that of the second well 108, the conductivity type of the second doping region 112 is different from that of the second well 108, and the conductivity type of the third doping region 114 is the same as that of the first well 106. In some embodiments, dopants of appropriate conductivity types can be implanted by an ion implantation process to form the first doping region 110, the second doping region 112, and the third doping region 114, respectively. In some embodiments, the doping concentration of the first doping region 110 is between 1×10 18 cm -3 and 1×10 21 cm -3 The doping concentration of the second doping region 112 is between 1×10 18 cm -3 and 1×10 21 cm -3 The doping concentration of the third doping region 114 is between 1×10 18 cm -3 and 1×10 21 cm -3 In some embodiments, the doping concentrations of the first doping region 110 and the second doping region 112 are greater than that of the first well 106 , and the doping concentration of the third doping region 114 is greater than that of the second well 108 .

[0051] Next, see Figure 4 A gate structure 116 is formed on the first well 106 and the second well 108, wherein the gate structure 116 includes a first gate portion 116a and a second gate portion 116b. The first gate portion 116a partially overlaps the first well 106 and the second well 108, and the second gate portion 116b also covers a portion of the isolation structure 104a.

[0052] In some embodiments, the gate structure 116 may include a single or multiple gate dielectric layers, and a single or multiple gate electrode layers.

[0053] In some embodiments, the gate dielectric layer may comprise silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material, other suitable dielectric materials, or combinations thereof. The high-k dielectric material may comprise, but is not limited to, a metal oxide, a metal nitride, a metal silicide, a metal aluminate, a zirconium silicate, a zirconium aluminate, or combinations thereof. In some embodiments, the gate dielectric layer may be formed by a plasma enhanced chemical vapor deposition (PECVD) process, a spin coating process, other suitable processes, or combinations thereof.

[0054] In some embodiments, the gate electrode layer may include amorphous silicon, polycrystalline silicon, metal nitride, conductive metal oxide, metal, other suitable materials, or combinations thereof. The metal may include, but is not limited to, aluminum (Al), molybdenum (Mo), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), hafnium (Hf), or combinations thereof. The conductive metal oxide may include, but is not limited to, ruthenium oxide or indium tin oxide. In some embodiments, the gate electrode layer may be formed by chemical vapor deposition (CVD), sputtering, resistive heating evaporation, electron beam evaporation, pulsed laser deposition, or other suitable methods. The chemical vapor deposition method may be, for example, a low pressure chemical vapor deposition (LPCVD) process, a low temperature chemical vapor deposition (LTCVD) process, a rapid thermal chemical vapor deposition (RTCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, an atomic layer deposition (ALD) process, or other commonly used methods.

[0055] In some embodiments, the gate dielectric layer and gate electrode layer may be patterned using a patterning process to form the gate structure 116 including the first gate portion 116a and the second gate portion 116b. Specifically, a photoresist material is formed on the gate dielectric layer and the gate electrode layer using a suitable process, such as spin coating or chemical vapor deposition, atomic layer deposition, physical vapor deposition (PVD), molecular beam deposition, plasma-enhanced chemical vapor deposition, other suitable methods, or other suitable deposition methods, or a combination thereof. Photolithography, post-exposure baking, and development are then performed to remove a portion of the photoresist material to form a patterned photoresist layer. The patterned photoresist layer serves as an etch mask for etching. A double or triple layer of photoresist may be used. The gate dielectric layer and the gate electrode layer are then etched using any acceptable etching process, such as reactive ion etching, neutral beam etching, or the like, or a combination thereof, to form the first gate portion 116a and the second gate portion 116b. Then, the patterned photoresist layer is removed.

[0056] Next, see Figure 5 , which shows Figure 4A partial enlarged view of a semiconductor structure. An opening 10 is defined between the first gate portion 116a and the second gate portion 116b, exposing a portion of the isolation structure 104a. Specifically, the isolation structure 104a has a first sidewall S1 that is adjacent to the second well 108. The opening 10 between the first gate portion 116a and the second gate portion 116b overlaps with the first sidewall S1 of the isolation structure 104a in a direction perpendicular to the substrate 102. In other words, the vertical projection of the opening 10 onto the substrate 102 overlaps with the vertical projection of the first sidewall S1 of the isolation structure 104a onto the substrate 102. In some embodiments, the opening 10 overlaps with one-third of the first sidewall S1 of the isolation structure 104a in a direction perpendicular to the substrate 102. In other words, the vertical projection of the opening 10 onto the substrate 102 overlaps with one-third of the first sidewall S1 of the isolation structure 104a. Specifically, the first sidewall S1 of the isolation structure 104a has a first end E1 proximate to the top surface of the isolation structure 104a and a second end E2 opposite the first end E1. One-third of the first sidewall S1 of the isolation structure 104a is measured from the first end E1 of the first sidewall S1 of the isolation structure 104a to the second end E2 of the first sidewall S1 of the isolation structure 104a. By providing the gate structure 116 with an opening 10 that partially exposes the isolation structure 104a, damage to the semiconductor structure caused by hot carrier injection testing can be effectively reduced, thereby improving the reliability of the semiconductor structure.

[0057] In some embodiments, the first gate portion 116a does not cover the first end E1 of the first sidewall S1 of the isolation structure 104a. In some embodiments, the second gate portion 116b covers the second end E2 of the first sidewall S1 of the isolation structure 104a, ensuring that the electrical properties of the semiconductor device are not affected. Conversely, if the second gate portion 116b does not cover the second end E2 of the first sidewall S1 of the isolation structure 104a, the opening 10 will expose too much of the isolation structure 104a, thereby affecting the electrical properties of the semiconductor device and thereby affecting the intended function or use of the semiconductor device.

[0058] In the direction from the second doped region 112 toward the isolation structure 104a, the first gate portion 116a has a length L. There is a distance D between the second doped region 112 and the first well 106, where the length L is greater than the distance D. Specifically, the distance D is the perpendicular distance between the side of the second doped region 112 and the interface between the first well 106 and the second well 108. In some embodiments, the length L is greater than the distance D to ensure proper device operation. If the length L is less than the distance D, the channel will not open. In one embodiment, one side of the first gate portion 116a is substantially flush with the second doped region 112, and the first gate portion 116a extends across the interface between the first well 106 and the second well 108. The opening 10 exposes a portion of the first well 106 and a portion of the isolation structure 104a. In one embodiment, the opening 10 is approximately 0.1 micrometers (μm) to 1.0 micrometers (μm) to ensure that subsequent manufacturing processes can completely fill the opening 10, preventing subsequent ion implantation from penetrating the substrate 102 through the opening 10 and affecting device electrical properties.

[0059] Next, see Figure 6 An interlayer dielectric (ILD) layer 118 is formed on the isolation structure 104a, the isolation structure 104b, the first gate portion 116a, and the second gate portion 116b. The ILD layer 118 also covers the first doped region 110, the second doped region 112, and the third doped region 114. The ILD layer 118 may be formed of a dielectric material. In some embodiments, the material of the ILD layer 118 may include silicon oxide, silicon nitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), other suitable dielectric materials, or combinations thereof. Furthermore, in some embodiments, the interlayer dielectric layer 118 can be formed using molecular-beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), metalorganic chemical vapor deposition (MOCVD), chemical vapor deposition, atomic layer deposition, physical vapor deposition, molecular beam deposition, plasma-enhanced chemical vapor deposition, other appropriate methods, or combinations thereof. In one embodiment, the first gate portion 116 a and the second gate portion 116 b preferably have substantially the same operating potential. However, those skilled in the art may configure the first gate portion 116 a and the second gate portion 116 b to have a voltage difference, or one of the gate portions 116 b to have a floating potential, according to actual needs.

[0060] Then, a source electrode 120 and a drain electrode 122 are formed on the interlayer dielectric layer 118. The source electrode 120 and the drain electrode 122 are respectively disposed on the second well 108 and the first well 106. In some embodiments, the first gate portion 116a and the second gate portion 116b are disposed between the source electrode 120 and the drain electrode 122. In addition, in some embodiments, contact holes 120a, 120b, and 122a are formed in the interlayer dielectric layer 118. In some embodiments, the contact hole 120a penetrates the interlayer dielectric layer 118 and contacts the source electrode 120 and the first doped region 110, the contact hole 120b penetrates the interlayer dielectric layer 118 and contacts the source electrode 120 and the second doped region 112, and the contact hole 122a penetrates the interlayer dielectric layer 118 and contacts the drain electrode 122 and the third doped region 114. As mentioned above, the source electrode 120 may be electrically connected to the first doping region 110 and the second doping region 112 through the contact holes 120 a and 120 b respectively, and the drain electrode 122 may be electrically connected to the third doping region 114 through the contact hole 122 a.

[0061] The source electrode 120, the drain electrode 122, and the contact holes 120a, 120b, and 122a may be formed of polysilicon, metal, or other suitable conductive materials. In some embodiments, the materials of the source electrode 120, the drain electrode 122, and the contact holes 120a, 120b, and 122a may include copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), gold (Au), chromium (Cr), nickel (Ni), platinum (Pt), titanium (Ti), iridium (Ir), rhodium (Rh), copper alloys, aluminum alloys, molybdenum alloys, tungsten alloys, gold alloys, chromium alloys, nickel alloys, platinum alloys, titanium alloys, iridium alloys, rhodium alloys, other suitable conductive materials, or combinations thereof. In some embodiments, the materials of the source electrode 120, the drain electrode 122, and the contact holes 120a, 120b, and 122a may be different from each other.

[0062] In some embodiments, the source electrode 120, the drain electrode 122, and the contact holes 120a, 120b, and 122a can be formed by chemical vapor deposition, sputtering, resistance heating evaporation, electron beam evaporation, pulsed laser deposition, or other suitable methods. The chemical vapor deposition method may be, for example, a low-pressure chemical vapor deposition process, a low-temperature chemical vapor deposition process, a rapid temperature chemical vapor deposition process, a plasma-enhanced chemical vapor deposition process, an atomic layer deposition process, or other commonly used methods. At this point, the semiconductor structure 100 is substantially completed.

[0063] Compared to conventional technologies, the semiconductor structure and the method for forming the same provided by the embodiments of the present invention have at least one of the following advantages:

[0064] (1) By providing the gate structure with an opening that exposes a portion of the isolation structure, damage to the semiconductor structure caused by a hot carrier injection test can be effectively reduced, thereby improving the reliability of the semiconductor structure.

[0065] (2) Furthermore, since the second gate portion of the gate structure covers the second end of the first sidewall of the isolation structure, it can ensure that the electrical properties of the semiconductor device will not be affected and can still perform its intended purpose or function.

[0066] Although the embodiments of the present invention and their advantages have been disclosed above, it should be understood that any person skilled in the art may make changes, substitutions and modifications without departing from the spirit and scope of the present invention. In addition, the scope of protection of the present invention is not limited to the manufacturing processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art can understand from the disclosure of the present invention that the manufacturing processes, machines, manufacturing, material compositions, devices, methods and steps currently or in the future developed can be used according to the present invention as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein. Therefore, the scope of protection of the present invention includes the above-mentioned manufacturing processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each claim constitutes a separate embodiment, and the scope of protection of the present invention also includes the combination of each claim and embodiment.

Claims

1. A semiconductor structure, characterized in that include: a base; a first well disposed in the substrate; a second well disposed in the substrate and adjacent to the first well; an isolation structure disposed in the first well; as well as A gate structure is provided on the substrate and includes a first gate portion and a second gate portion, wherein the first gate portion overlaps with the first well and the second well, and an opening is formed between the first gate portion and the second gate portion to expose a portion of the isolation structure, wherein The isolation structure has a first sidewall close to the second well, and the first sidewall has a first end close to a top surface of the isolation structure and a second end opposite to the first end, wherein an edge of the opening is horizontally located between the first end and the second end.

2. The semiconductor structure according to claim 1, wherein: The opening between the first gate portion and the second gate portion overlaps with the first sidewall of the isolation structure in a vertical projection direction.

3. The semiconductor structure according to claim 2, wherein: The opening overlaps with one-third of the first sidewall of the isolation structure in the vertical projection direction, and one-third of the first sidewall of the isolation structure is measured from the first end of the first sidewall of the isolation structure to the second end of the first sidewall of the isolation structure.

4. The semiconductor structure according to claim 2, wherein: The first gate portion does not cover the first end of the first sidewall of the isolation structure.

5. The semiconductor structure according to claim 4, wherein: The second gate portion covers the second end of the isolation structure. The semiconductor structure according to claim 1 , wherein: The opening exposes a portion of the first well and a portion of the isolation structure.

7. The semiconductor structure according to claim 1, wherein: The first gate portion and the second gate portion have a fixed operating potential or one of them has a floating potential.

8. The semiconductor structure according to claim 1, wherein: Also includes: a first doped region disposed in the second well; as well as A second doped region is disposed in the second well and adjacent to the first doped region, wherein in a direction from the second doped region to the isolation structure, the first gate portion has a length, and there is a distance between the second doped region and the first well, and the length is greater than the distance.

9. The semiconductor structure according to claim 1, wherein: The gate structure includes at least one gate dielectric layer and at least one gate electrode layer.

10. The semiconductor structure according to claim 8, wherein: Also includes: an interlayer dielectric layer disposed on the substrate; a third doped region disposed in the first well; a source electrode passing through the interlayer dielectric layer and electrically connected to the first doped region and the second doped region; and A drain electrode passes through the interlayer dielectric layer and is electrically connected to the third doped region.

11. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a first well in the substrate; forming a second well in the substrate and adjacent to the first well; forming an isolation structure in the first well; and A gate structure is formed on the substrate, wherein the gate structure includes a first gate portion and a second gate portion, the first gate portion overlaps the first well and the second well, and an opening is formed between the first gate portion and the second gate portion to expose a portion of the isolation structure, wherein The isolation structure has a first sidewall close to the second well, and the first sidewall has a first end close to a top surface of the isolation structure and a second end opposite to the first end, wherein an edge of the opening is horizontally located between the first end and the second end.

12. The method for forming a semiconductor structure according to claim 11, wherein: The opening between the first gate portion and the second gate portion exposes the first sidewall of the isolation structure and overlaps with it in a vertical projection direction.

13. The method for forming a semiconductor structure according to claim 12, wherein: The opening between the first gate portion and the second gate portion exposes one-third of the first side wall of the isolation structure overlapping in the vertical projection direction, and one-third of the first side wall of the isolation structure is measured from the first end of the first side wall of the isolation structure to the second end of the first side wall of the isolation structure.

14. The method for forming a semiconductor structure according to claim 12, wherein: The first gate portion does not cover the first end of the first sidewall of the isolation structure.

15. The method for forming a semiconductor structure according to claim 14, wherein: The second gate portion covers the second end of the isolation structure.

16. The method for forming a semiconductor structure according to claim 11, wherein: The opening exposes a portion of the first well and a portion of the isolation structure.

17. The method for forming a semiconductor structure according to claim 11, wherein: The first gate portion and the second gate portion have a fixed operating potential or one of them has a floating potential.

18. The method for forming a semiconductor structure according to claim 11, wherein: Also includes: forming a first doped region in the second well; and A second doped region is formed in the second well and adjacent to the first doped region, wherein in a direction from the second doped region to the isolation structure, the first gate portion has a length, and there is a distance between the second doped region and the first well, and the length is greater than the distance.

19. The method for forming a semiconductor structure according to claim 11, wherein: The gate structure includes at least one gate dielectric layer and at least one gate electrode layer.

20. The method for forming a semiconductor structure according to claim 18, wherein: Also includes: forming an interlayer dielectric layer on the substrate; forming a third doped region in the first well; and forming a source electrode, passing through the interlayer dielectric layer, and electrically connected to the first doped region and the second doped region; and A drain electrode is formed, passing through the interlayer dielectric layer and electrically connected to the third doped region.

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