N-type battery structure and preparation method thereof

Abstract

The present invention discloses an N-type battery structure and its preparation method. The structure comprises an N-type silicon body material and a metal gate electrode formed on the surface of the N-type silicon body material. The structure is characterized in that the back surface of the N-type silicon body material is provided with a velvet surface portion and a polished surface portion, and the contact point between the metal gate electrode and the N-type silicon body material is located within the velvet surface portion. The velvet surface of the back metal gate electrode increases the contact area between the metal gate and the silicon, improving contact resistance. The flat surface of the polished area improves back-side passivation, reduces surface recombination velocity, and enhances internal reflection of long wavelengths, thereby increasing front-side current.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to an N-type cell structure and a preparation method thereof. Background Art

[0002] With the development of solar cell technology, cell efficiency has been increasing, primarily due to the advancement of surface passivation technology. For example, the development of aluminum back-field cells to PERC cells benefited from the development of aluminum oxide passivation technology, which greatly reduced recombination on the back surface of the cell. The development of PERC cells to TOPcon cells benefited from the passivation effect of the tunneling oxide layer and poly film structure on the metal contact, greatly reducing recombination under the back metal contact. However, as the surface recombination rate continues to decrease, the lifespan of the bulk material has gradually become a key factor restricting the improvement of cell efficiency. Compared with P-type doped silicon materials, N-type doped silicon materials have a lower doping concentration and less impurity content at the same resistivity, thus having the advantage of longer lifespan. Therefore, the proportion of N-type cells in the solar cell market is increasing.

[0003] For N-type cells, in the metallization process of electrode production, only silver paste (hereinafter referred to as Ag) is generally used as the electrode to collect electrons removed from the cell surface under light and transmit them to the external circuit. The contact resistance between Ag and silicon has always been relatively high, especially on the back side of N-type cells. In order to obtain a good surface passivation effect and increase the internal emission of long waves on the back side, thereby increasing the front current, the back side of N-type cells often adopts a polished structure to create a flat surface, which is very unfavorable for the contact of the Ag electrode. Compared with the velvet structure, the velvet has a higher specific surface area and a larger area of ​​contact with the metal, which is very conducive to contact. Therefore, the contact resistance of the velvet structure is often much smaller than that of the polished surface. Similarly, the surface of the velvet is relatively rough, which is not conducive to the passivation of the film layer. Therefore, it is difficult to take both surface passivation and surface metal contact into account, and the two are contradictory. Summary of the Invention

[0004] To address the aforementioned issues in the prior art, the present invention aims to provide an N-type battery structure and a method for preparing the same. The novel N-type battery structure provided by the present invention balances surface passivation with submetallic contact, reducing surface recombination while also lowering contact resistivity at the metal level.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] In a first aspect, the present invention provides an N-type battery structure, comprising an N-type silicon body material and a metal gate electrode formed on the surface of the N-type silicon body material, wherein the back of the N-type silicon body material is provided with a velvet portion and a polished portion, and the position where the metal gate electrode contacts the N-type silicon body material is located within the velvet portion.

[0007] The N-type cell structure of the present invention defines the contact point between the metal gate electrode and the N-type silicon body within the textured portion, while also providing a polished surface on the back side of the silicon body for film passivation. The textured structure of the back metal gate electrode increases the contact area between the metal gate and the silicon, improving contact resistance. The flat surface of the polished area improves back-side passivation, reduces the surface recombination rate, and enhances internal reflection of long wavelengths, increasing front-side current.

[0008] The velvet structure of the present invention may be, for example, a pyramid velvet structure commonly used in the art.

[0009] More preferably, the contact position between the metal gate electrode and the N-type silicon body material is a velvet surface, and the non-contact position is a polished surface, which can better achieve the above advantages of improving contact resistance and reducing surface composite plastic.

[0010] Preferably, the N-type battery further includes a pn junction layer, a passivation layer, an anti-reflection layer and a front electrode sequentially located on the front side of the N-type silicon body material, and a quantum tunneling layer, a P-doped polysilicon layer, a protective layer and a metal gate electrode sequentially located on the back side of the N-type silicon body material; wherein the front electrode contacts the passivation layer, and the metal gate electrode contacts the P-doped polysilicon layer.

[0011] In this preferred technical solution, a quantum tunneling layer, a P-doped polysilicon layer and a protective layer are provided between the back side of the N-type silicon body material and the metal gate electrode. The sum of the thicknesses of the quantum tunneling layer and the P-doped polysilicon layer is less than the height of the velvet surface, and the metal gate electrode is in contact with the P-doped polysilicon layer, so the position where the metal gate electrode contacts the N-type silicon body material is the velvet surface.

[0012] Preferably, the velvet height on the back side of the N-type silicon material is 0.5 μm to 5 μm, for example, 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.3 μm, 2.5 μm, 2.8 μm, 3 μm, 3.5 μm, 4 μm or 5 μm.

[0013] Preferably, the thickness of the quantum tunneling layer is less than 2 nm, such as 1.5 nm or 1 nm, and the thickness of the P-doped polysilicon layer is 80 nm to 120 nm, such as 80 nm, 90 nm, 95 nm, 100 nm, 110 nm, 115 nm or 120 nm.

[0014] The present invention does not limit the specific types of the front passivation layer and the anti-reflection layer. Those skilled in the art can select them as needed. For example, the passivation layer can be an aluminum oxide layer, and the anti-reflection layer can be any one of a silicon nitride layer, a silicon dioxide layer, or a silicon carbide layer.

[0015] The present invention does not limit the specific types of the quantum tunneling layer, P-doped polysilicon layer and protective layer on the back side. Those skilled in the art can select them as needed. For example, the quantum tunneling layer can be a silicon dioxide layer, the P-doped polysilicon layer can be a single crystal silicon layer, an amorphous silicon layer or a silicon carbide layer, and the protective layer can be a silicon nitride layer.

[0016] In a second aspect, the present invention provides a method for preparing the N-type battery structure as described in the first aspect, wherein the method includes a front side preparation method and a back side preparation method, wherein the front side preparation method can be prepared by referring to the method of the prior art, and the back side preparation method includes:

[0017] a. Prepare the protective layer first;

[0018] b. Then alkali etching and polishing are performed to form a velvet surface part and a polished surface part;

[0019] c. Finally, the electrode is prepared so that the electrode is formed in the suede part.

[0020] Preferably, step a comprises:

[0021] a1 Back-side single-sided phosphorus diffusion and PSG formation: The back-side N-type silicon material with back-texture is subjected to single-sided phosphorus diffusion, and phosphorus-containing silicon oxide PSG is formed on the back side;

[0022] a2. Ink grid lines are made on the back: ink slurry is used to make ink grid lines as a protective layer;

[0023] a3 Use HF solution to remove PSG not protected by the protective layer.

[0024] Preferably, the method further comprises, after step a3, performing step a4: washing away the ink;

[0025] Preferably, the method further comprises the following step after step b and before step c: removing the PSG at the ink grid line position, and the reagent used for the removal is preferably HF solution.

[0026] Preferably, the method further includes a sintering step after step c. One purpose of sintering in this step is to remove organic matter in the slurry and allow the metal slurry to condense into a good metal conductor. The second purpose is that the slurry will burn through the silicon nitride at high temperature to form a good ohmic contact between the metal and silicon.

[0027] As a preferred technical solution of the method for preparing the N-type battery structure of the present invention, the method of using ink slurry to make the gate line in step a2 includes either screen printing or inkjet printing.

[0028] Preferably, when performing step a3, the single-sided PSG removal step, that is, removing only the back PSG, a water film is used to protect the front of the battery. An exemplary method is: the laboratory uses a chain etcher. Before the silicon wafer enters the process tank (etching tank), it passes through a water shower tank. Water is sprayed on the wafer surface. Because the PSG on the front of the wafer is hydrophilic, the tension of the water forms a water film on the front surface to protect it.

[0029] Preferably, step a4 includes: using a mixture of ammonia and hydrogen peroxide to clean the ink. The mixture of ammonia and hydrogen peroxide is, for example, RCA1 solution (East Test, UP grade).

[0030] Preferably, the alkali solution in step b comprises any one of KOH solution, NaOH or TMAH, or a combination of at least two of them.

[0031] Preferably, the mass fraction of the alkali solution in step b is 2.5% to 12%, for example, 2.5%, 3.5%, 5%, 6%, 7%, 8%, 9%, 10%, 11% or 12%.

[0032] Preferably, the temperature of the alkaline solution etching and polishing in step b is 65°C to 85°C, for example, 65°C, 68°C, 70°C, 75°C, 77°C, 80°C or 85°C.

[0033] Preferably, the method for preparing the metal grid electrode in step c comprises any one of screen printing and inkjet printing.

[0034] Preferably, the type of metal grid lines prepared in step c is the same as the type of ink grid lines prepared in step a2.

[0035] Preferably, both step c and step a2 are performed by screen printing, and the screens used are of the same type, and the screen for printing ink has the same or wider grid line width than the screen for printing metal paste. Preferably, the grid line width of the screen for printing ink is wider, so as to achieve better alignment.

[0036] Preferably, the screen for printing ink is 30 μm to 500 μm wider than the grid line width of the printed metal paste, for example, 30 μm, 40 μm, 50 μm, 60 μm, 80 μm, 90 μm, 100 μm, 120 μm, 135 μm, 150 μm, 170 μm, 190 μm, 220 μm, 260 μm, 300 μm, 350 μm, 400 μm, 450 μm or 500 μm. Within this preferred range, the accuracy of the printing alignment between step (VI) and step (II) can be better guaranteed.

[0037] Preferably, the grid line width of the screen of the printing ink is in the range of 80μm to 500μm, for example, 80μm, 100μm, 125μm, 150μm, 170μm, 185μm, 200μm, 220μm, 245μm, 260μm, 300μm, 325μm, 370μm, 400μm, 450μm or 500μm, etc.

[0038] As a further preferred technical solution of the method for preparing the N-type battery structure of the present invention, the method for preparing the N-type battery structure includes:

[0039] (1) Texturing on both sides of N-type solar cells;

[0040] (2) Boron diffusion on the front side to form a pn junction;

[0041] (3) Etching the back side under the condition of water film protection on the front side;

[0042] (4) Single-sided phosphorus diffusion on the back side and forming a mask:

[0043] Performing single-side phosphorus diffusion on the back of the N-type silicon body material with back texture, and forming phosphorus-containing silicon oxide PSG on the back;

[0044] (5) Making ink grid lines on the back:

[0045] Using ink slurry to make ink grid lines as a protective layer;

[0046] (6) Under the condition of front water film protection, use HF solution to remove PSG not protected by the protective layer described in step (5);

[0047] (7) Clean off the ink;

[0048] (8) Alkali polishing:

[0049] After the battery cell is soaked in alkali solution in step (7), the position without PSG protection is polished to a polished surface, and the position with PSG protection retains a velvet surface;

[0050] (9) Soaking the cell after step (8) in HF solution to remove the PSG at the back grid line position and the boron-containing silicon dioxide BSG at the front;

[0051] (10) Passivation film coating on the front and back: The front is coated with a passivation film and an anti-reflection film in sequence, and the back is coated with a protective layer;

[0052] (11) preparing the front and back electrodes, wherein the back electrode is prepared using metal slurry, and a metal grid electrode is prepared at the position of the velvet surface in step (10);

[0053] (12) sintering;

[0054] Wherein, both step (5) and step (11) are performed by screen printing, and the screens used are of the same type, and the screen for printing ink has the same or wider width than the grid line for printing metal paste.

[0055] The key to the N-type cell structure provided by this preferred technical solution lies in creating a silicon oxide mask on the backside to protect the metal gate contact areas. After alkaline etching, the unprotected areas are polished flat, ultimately forming a selective suede structure. After printing, the suede structure is formed only below the gate lines, reducing contact resistance.

[0056] Preferably, when etching the back surface in step (3), the thinning amount is controlled to ensure that the velvet surface on the back surface is not completely etched away. The preferred thinning amount is 0.1 to 0.2 g. The thinning amount is defined as follows: m1 is weighed before etching, and m2 is weighed after etching. The difference between m1 and m2 is the thinning amount.

[0057] Compared with the prior art, the present invention has the following beneficial effects:

[0058] The present invention provides an N-type battery structure. The key to this structure is that the back of the N-type silicon body material is provided with a velvet portion and a polished portion. The position where the back metal grid electrode contacts the N-type silicon body material is located in the velvet portion, and the back of the silicon body material has a polished portion.

[0059] A selective velvet structure is made at the contact position of the metal grid electrode on the back to improve the metal contact and increase the battery filling; a polished surface part is made at the passivation position of the film layer to improve the passivation effect, reduce the surface recombination rate, increase the opening voltage, and at the same time increase the internal reflection of light and increase the current. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 Schematic diagram of the structure of the N-type battery structure of the present invention, 1-N-type silicon body material, 2-pn junction layer, 3-passivation layer, 4-antireflection layer, 5-front electrode, 6-quantum tunneling layer, 7-P-doped polysilicon layer, 8-protective layer, 9-metal gate electrode;

[0061] Figure 2 Flow chart of the preparation method of Example 1 of the present invention. DETAILED DESCRIPTION

[0062] The technical solution of the present invention will be further described below with reference to the accompanying drawings and through specific implementation methods.

[0063] Example 1

[0064] This embodiment provides an N-type battery structure (see the schematic diagram of the structure Figure 1), comprising: an N-type silicon body material 1, a pn junction layer 2, a passivation layer 3, an anti-reflection layer 4 and a front electrode 5 sequentially located on the front side of the N-type silicon body material 1,

[0065] and a quantum tunneling layer 6, a P-doped polysilicon layer 7, a protective layer 8 and a metal gate electrode 9 sequentially located on the back side of the N-type silicon body material 1;

[0066] The front electrode 5 contacts the passivation layer 3, and the metal gate electrode 9 contacts the P-doped polysilicon layer 7. The back surface of the N-type silicon body material has a selective textured structure with a partial textured surface and a partially polished surface. The contact area between the metal gate electrode and the N-type silicon body material is the textured surface, and the non-contact area is the polished surface.

[0067] The passivation layer is Al2O3 with a thickness of 5nm, the anti-reflection layer is silicon nitride with a thickness of 80nm, the quantum tunneling layer is silicon oxide with a thickness of 1.2nm, the P-doped polysilicon layer has a thickness of 120nm, the protective layer is silicon nitride with a thickness of 100nm, and the metal gate electrode is a silver electrode.

[0068] This embodiment also provides a method for preparing the N-type battery structure, which comprises the following steps (see the preparation method flow chart for details): Figure 2 ):

[0069] 1. Select conventional N-type doped cells as N-type silicon body material, with cell size of 156.75×156.75mm;

[0070] 2. Double-sided texturing: The conventional texturing process of the production line forms a velvet surface on the front and back of the battery cell.

[0071] 3. Single-sided boron diffusion on the front side: Boron diffusion is performed on the front side of the cell to form a pn junction, which is a conventional process on the production line.

[0072] 4. Backside etching: Use the production line chain etcher to perform backside etching to remove the edge pn junction and backside expansion.

[0073] The back surface was etched using a solution of hydrofluoric acid and nitric acid, with a controlled reduction of 0.12g to ensure the pyramid velvet surface was not completely etched away. A water film was applied to the front surface to protect it from damage.

[0074] 5. Single-sided phosphorus diffusion on the back: phosphorus diffusion is performed on the back of the cell to form a high-low junction on the back surface. + A layer is formed on the back of the cell to inhibit the recombination of minority carriers on the back surface and improve the minority carrier lifetime. At the same time, a thicker phosphorus-containing silicon oxide (PSG) is formed on the back of the cell to provide mask protection for step 9.

[0075] 6. Backside printing ink: Screen printing is used, using ink as a paste to print grid lines as a protective layer. The stencil used for printing ink is generally the same type as the stencil used for printing the Ag paste in step 12. For better alignment, the stencil used for printing ink is wider. The grid line width of the stencil used for printing ink is 220μm, and the grid line width of the stencil used for printing Ag paste is 40μm.

[0076] 7. Backside Silicon Oxide (PSG) Removal: Using a production line chain etcher, HF solution is used to remove the PSG on the backside of the substrate, while the front side is protected with a water film. HF does not react with ink, so the ink area printed in step 6 is protected by the ink, and the PSG beneath the ink is retained to serve as a mask for step 9. The PSG not protected by the ink will react with the HF acid and be removed.

[0077] 8. Wash off the ink: Use a tank-type cleaning machine with RCA1 liquid (East Test, UP grade) to clean the ink printed in step 6, washing away the ink and leaving only the PSG under the ink.

[0078] 9. KOH polishing: Use a tank-type cleaning machine to prepare a KOH solution and soak the cells after 8 hours. The KOH concentration is 3.7% and the soaking temperature is 70°C. PSG does not react with KOH. The areas without PSG protection are silicon materials, which will react with KOH and be polished. The areas with PSG will retain the velvet surface.

[0079] 10. Remove the oxide layer on the front and back sides (remove BSG on the front and PSG on the back). Use a tank cleaning machine to prepare HF solution, soak the battery cells after 9, remove the PSG mask at the back gate line position, and the boron-containing silicon dioxide (hereinafter referred to as BSG) on the front side.

[0080] 11. Passivation film is coated on the front and back: the front is coated with passivation film and anti-reflection film in sequence, and the back is coated with a protective layer for surface passivation.

[0081] 12. Front and back printed electrodes: Screen printing is used to prepare the front and back electrodes. For the back electrode, Ag grid lines are printed on the localized velvet surface. After printing, sintering testing and binning complete the entire battery production process.

[0082] The battery produced in Example 1 was compared with a conventional N-type battery. The results are shown in Table 1:

[0083] Table 1

[0084] Voc(V) Isc(A) FF(%) Rs(mΩ) EFF (%) Example 1 0.6891 9.849 78.92 4.15 21.92 control group 0.6876 9.805 78.29 4.61 21.61

[0085] From the above data, it can be seen that the battery efficiency is greatly increased compared with the control group by using the battery structure and process method described in the present invention.

[0086] The applicant states that the present invention is intended to illustrate the detailed methods of the present invention through the above-described embodiments, but the present invention is not limited to the above-described detailed methods, that is, it does not mean that the present invention must rely on the above-described detailed methods in order to be implemented. Those skilled in the art should understand that any improvements to the present invention, equivalent substitutions for various raw materials in the products of the present invention, addition of auxiliary ingredients, and selection of specific methods, etc., are all within the scope of protection and disclosure of the present invention.

Claims

1. A method for preparing an N-type battery structure, comprising an N-type silicon body material and a metal gate electrode formed on the surface of the N-type silicon body material, characterized in that: The preparation method of the N-type battery structure includes: (1) Texturing on both sides of N-type solar cells; (2) Boron diffusion on the front side to form a pn junction; (3) Etching the back side under the condition of water film protection on the front side; (4) Single-sided phosphorus diffusion on the back side and forming a mask: Single-sided phosphorus diffusion is performed on the back side of the N-type silicon material with back texture, and phosphorus-containing silicon oxide PSG is formed on the back side; (5) Making ink grid lines on the back: using ink slurry to make ink grid lines as a protective layer; (6) Under the condition of front water film protection, use HF solution to remove PSG not protected by the protective layer described in step (5); (7) Clean off the ink; (8) Alkali polishing: After soaking the cell in step (7), the unprotected area of ​​the cell is polished to a polished surface, while the protected area of ​​the cell retains a velvet surface. (9) Soaking the cell after step (8) in HF solution to remove the PSG at the back grid line position and the boron-containing silicon dioxide BSG at the front; (10) Passivation film coating on the front and back: The front is coated with a passivation film and an anti-reflection film in sequence, and the back is coated with a protective layer; (11) preparing the front and back electrodes, wherein the back electrode is prepared using metal slurry, and a metal grid electrode is prepared at the position of the velvet surface in step (10); (12) sintering; The back side of the N-type silicon body material is provided with a velvet surface portion and a polished surface portion, and the position where the metal gate electrode contacts the N-type silicon body material is located in the velvet surface portion; The N-type cell further includes a pn junction layer, a passivation layer, an anti-reflection layer and a front electrode sequentially located on the front surface of the N-type silicon body material. And a quantum tunneling layer, a P-doped polysilicon layer, a protective layer and a metal gate electrode are sequentially located on the back side of the N-type silicon body material.

2. The method according to claim 1, characterized in that The position where the metal gate electrode contacts the N-type silicon body material is the suede surface portion, and the position where the metal gate electrode does not contact the N-type silicon body material is the polished surface portion.

3. The method according to claim 1, characterized in that The front electrode contacts the passivation layer, and the metal gate electrode contacts the P-doped polysilicon layer.

4. The method according to claim 1, wherein The velvet height on the back side of the N-type silicon body material is 0.5 μm to 5 μm.

5. The method according to claim 3, characterized in that The thickness of the quantum tunneling layer is less than 2 nm, and the thickness of the P-doped polysilicon layer is 80 nm to 120 nm.

6. The method according to claim 3, characterized in that The passivation layer is an aluminum oxide layer.

7. The method according to claim 3, characterized in that The anti-reflection layer is any one of a silicon nitride layer, a silicon dioxide layer or a silicon carbide layer.

8. The method according to claim 3, characterized in that The quantum tunneling layer is a silicon dioxide layer.

9. The method according to claim 3, characterized in that The protective layer is a silicon nitride layer.

10. The method according to claim 1, characterized in that The metal grid line electrode is a silver electrode.

11. The method according to claim 1, wherein The method of making the grid lines using ink paste includes any one of screen printing and inkjet printing.

12. The method according to claim 1, characterized in that Use a mixture of ammonia and hydrogen peroxide to clean the ink.

13. The method according to claim 1, wherein The alkali solution includes any one of KOH solution, NaOH or TMAH, or a combination of at least two of them.

14. The method according to claim 1, wherein The mass fraction of the alkali solution is 2.5% to 12%.

15. The method according to claim 1, wherein The temperature of the alkaline solution etching and polishing is 65°C to 85°C.

16. The method according to claim 1, wherein The electrode can be prepared by screen printing or inkjet printing.

17. The method according to claim 1, wherein The type of metal grid lines prepared is the same as the type of ink grid lines prepared.

18. The method according to claim 17, characterized in that The metal grid lines and the ink grid lines are both prepared by screen printing, and the screens used are of the same type. The screen for printing ink has the same width or is wider than the screen for printing metal paste.

19. The method according to claim 18, characterized in that The screen for printing ink is 30 μm to 500 μm wider than the grid line width for printing metal paste.

20. The method according to claim 18, wherein The grid line width of the screen for printing ink is in the range of 80 μm to 500 μm.

21. The method according to claim 1, wherein When etching the back side in step (3), the thinning amount is controlled to ensure that the velvet surface on the back side is not completely etched away, and the thinning amount is 0.1 to 0.14 g.

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