Short circuit protection structure in mos gated power devices

Abstract

A short-circuit protection structure in a MOS gate-controlled power device is disclosed. A single-chip power semiconductor device (1) comprises a first load terminal (11), a second load terminal (12), a semiconductor body (10) integrated in a single chip and coupled to the first load terminal (11) and the second load terminal (12) and configured to conduct a load current along a load current path between the terminals (11, 12), a control terminal (13) and at least one control electrode (131) electrically connected to the control terminal (13), wherein the at least one control electrode (131) is electrically insulated from the semiconductor body (10) and configured to control the load current based on a control voltage (25) between the control terminal (13) and the first load terminal (11), a protection structure (15) integrated in the single chip separately from the load current path and comprising a series connection (155) of a plurality of first semiconductor regions (151) of a first conductivity type and a plurality of second semiconductor regions (152) of a second conductivity type of a plurality of pn junctions (153). The series connection (155) of the pn junctions (153) is connected in forward bias between the control terminal (13) and the first load terminal (11).

Description

Technical Field

[0001] This specification relates to embodiments of single-chip power semiconductor devices and to embodiments of methods of forming single-chip power semiconductor devices. In particular, this specification relates to embodiments of single-chip power semiconductor devices that are MOS-gated devices, such as MOSFETs, IGBTs, or MOS-gated diodes, and to embodiments of methods of forming such devices, in which protection structures are provided that limit control voltages in certain circumstances. Background Art

[0002] Modern devices in automotive, consumer, and industrial applications rely on power semiconductor devices for many functions, such as converting electrical energy and driving electric motors or machines. For example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and diodes, to name a few, have been used in a variety of applications, including but not limited to switches in power supplies and power converters.

[0003] A power semiconductor device generally includes a semiconductor body configured to conduct a forward load current along a load current path between two load terminals of the device.

[0004] Furthermore, in the case of a controllable power semiconductor device (e.g., a transistor or a so-called MOS gated diode), the load current path can be controlled by means of an insulated electrode, typically referred to as a gate electrode. For example, upon receiving a corresponding control signal from, for example, a driver unit, the control electrode can set the power semiconductor device in one of a conducting state and a blocking state. In some cases, the gate electrode can be included in a trench of the power semiconductor switch, wherein the trench can have, for example, a stripe configuration or a needle configuration.

[0005] Some controllable power semiconductor devices exhibit functionality where the load current through the semiconductor body saturates during a short circuit (SC) event, which gives an opportunity to shut down the device within a period of a few microseconds before the device is thermally damaged.

[0006] As devices evolve towards lower conduction losses, cell density and transconductance increase, resulting in higher current density and shorter permissible short-circuit durations in short-circuit mode. In some applications, the short-circuit duration is not limited for loss optimization purposes. However, in other applications, a short-circuit duration of no more than, for example, 5 to 10 μs is desirable. Limiting short-circuit capability can lead to increased power losses and application complexity.

[0007] SC events are typically detected externally to the device using load current and / or voltage measurements. Upon detection of an SC event, countermeasures may be initiated to limit the load current and / or shut down the device accordingly.

[0008] However, such SC event detection based on load current and / or voltage measurements may be too slow.

[0009] Furthermore, SC event detection based on load current and / or voltage measurements may increase the overall complexity of the device and its control. Summary of the Invention

[0010] Various aspects described herein relate to a protection structure that is integrated into the same chip as the power cell(s) of a power semiconductor device but is separate from the load current path. The protection structure is temperature responsive and thermally coupled to the load current path. During an SC event (where a high amplitude load current flows along the load current path), the device heats up, and the protection structure heats up accordingly. The resistance of the protection structure has a negative temperature coefficient and is connected in series (e.g., forward biased) between the control terminal and the load terminal of the device. Thus, during an SC event, the protection structure decreases in resistance and thereby limits the control voltage between the control terminal and the load terminal of the device.

[0011] According to an embodiment, a single-chip power semiconductor device includes: a first load terminal; a second load terminal; a semiconductor body integrated in the single chip and coupled to the first load terminal and the second load terminal and configured to conduct a load current along a load current path between the terminals; a control terminal and at least one control electrode electrically connected to the control terminal, wherein the at least one control electrode is electrically insulated from the semiconductor body and configured to control the load current based on a control voltage between the control terminal and the first load terminal; and a protection structure integrated in the single chip separately from the load current path and including a series connection of a plurality of first semiconductor regions of a first conductivity type and a plurality of second semiconductor regions of a second conductivity type, wherein the series connection of the pn junctions is connected between the control terminal and the first load terminal in a forward biased state.

[0012] According to an embodiment, a power semiconductor module includes a plurality of integrated single-chip power semiconductor devices, each of the one or more single-chip power semiconductor devices of the module including: a first load terminal; a second load terminal; a semiconductor body integrated in the single chip and coupled to the first load terminal and the second load terminal and configured to conduct a load current along a load current path between the terminals; a control terminal and at least one control electrode electrically connected to the control terminal, wherein the at least one control electrode is electrically insulated from the semiconductor body and configured to control the load current based on a control voltage between the control terminal and the first load terminal; and a protection structure integrated in the single chip separately from the load current path and including a series connection of a plurality of first semiconductor regions of a first conductivity type and a plurality of second semiconductor regions of a second conductivity type, wherein the series connection of the pn junctions is connected between the control terminal and the first load terminal in a forward biased state.

[0013] According to an embodiment, a method for forming a single-chip power semiconductor device is proposed. The single-chip power semiconductor device includes: a first load terminal; a second load terminal; a semiconductor body integrated in a single chip and coupled to the first load terminal and the second load terminal, and configured to conduct a load current along a load current path between the terminals; a control terminal and at least one control electrode electrically connected to the control terminal, wherein the at least one control electrode is electrically insulated from the semiconductor body and configured to control the load current based on a control voltage between the control terminal and the first load terminal. The method includes forming a protection structure, which is integrated in a single chip separately from the load current path and includes a series connection of a plurality of first semiconductor regions of a first conductivity type and a plurality of second semiconductor regions of a second conductivity type using a plurality of pn junctions. The series connection of the pn junctions is connected between the control terminal and the first load terminal in a forward biased state.

[0014] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The parts in the drawings are not necessarily to scale, instead emphasis is placed on illustrating the principles of the present invention. In addition, in the various figures, the same reference numerals designate corresponding parts. In the drawings:

[0016] Figure 1 schematically and exemplarily illustrate a power semiconductor module according to one or more embodiments;

[0017] Figure 2 schematically and exemplarily illustrate a protection structure of a single-chip power semiconductor device according to one or more embodiments;

[0018] Figure 3 schematically and exemplarily illustrating the vertical position of a protection structure of a single-chip power semiconductor device based on a stacking diagram according to one or more embodiments;

[0019] Figure 4 illustrates schematically and exemplarily a horizontally projected section of a single-chip power semiconductor device according to one or more embodiments;

[0020] Figures 5 to 6B each schematically and exemplarily illustrating a section of a vertical cross-section of a single-chip power semiconductor device according to some embodiments; and

[0021] 7A to 7B Both schematically and exemplarily illustrate sections of a perspective projection of a single-chip power semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0022] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.

[0023] In this regard, directional terms such as "top," "bottom," "below," "front," "back," "rear," "front," "end," "above," etc., may be used with reference to the orientation of the various figures being described. Because portions of the embodiments may be positioned in many different orientations, the directional terms are used for illustrative purposes and are in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Accordingly, the following detailed description is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

[0024] Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided by way of explanation and is not meant to limit the invention. For example, features illustrated or described as part of one embodiment may be used on other embodiments or in combination with other embodiments to produce yet further embodiments. It is intended that the invention include such modifications and variations. Examples are described using specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. For clarity, identical elements or manufacturing steps have been designated by the same reference numerals in different figures unless otherwise stated.

[0025] As used in this specification, the term "horizontal" is intended to describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or semiconductor structure. This may be, for example, the surface of a semiconductor wafer, die, or chip. For example, both the first lateral direction X and the second lateral direction Y mentioned below may be horizontal directions, wherein the first lateral direction X and the second lateral direction Y may be perpendicular to each other.

[0026] As used in this specification, the term "vertical" is intended to describe an orientation that is substantially perpendicular to a horizontal surface, i.e., parallel to the normal direction of the surface of the semiconductor wafer / chip / die. For example, the extension direction Z mentioned below may be an extension direction that is perpendicular to both the first lateral direction X and the second lateral direction Y. The extension direction Z is also referred to herein as the "vertical direction Z."

[0027] In this specification, n-doping is referred to as the “first conductivity type” and p-doping is referred to as the “second conductivity type.” Alternatively, the opposite doping relationship may be employed, whereby the first conductivity type may be p-doped and the second conductivity type may be n-doped.

[0028] In the context of this specification, the terms "ohmic contact", "electrical contact", "ohmic connection" and "electrical connection" are intended to describe the presence of a low-ohmic electrical connection or a low-ohmic current path between two regions, sections, zones, parts or components of a semiconductor device or between different terminals of one or more devices or between a terminal or metallization or electrode and a part or component of a semiconductor device. Further, in the context of this specification, the term "contact" is intended to describe the presence of a direct physical connection between two elements of the respective semiconductor device; for example, a transition between two elements that are in contact with each other may not include further intermediate elements, etc.

[0029] Furthermore, in the context of this specification, unless otherwise stated, the term "electrically insulated" is used in its generally understood context and is therefore intended to describe two or more components that are located separately from each other and that there is no ohmic connection connecting these components. However, components that are electrically insulated from each other can still be coupled to each other, for example, mechanically and / or capacitively and / or inductively. To give an example, two electrodes of a capacitor can be electrically insulated from each other and at the same time mechanically and capacitively coupled to each other, for example, by means of insulation (e.g., a dielectric).

[0030] The specific embodiments described in this specification relate to, but are not limited to, single-chip power semiconductor devices presenting, for example, a stripe cell configuration, such as single-chip power semiconductor devices that can be used in power converters or power supplies. Therefore, in an embodiment, such a single-chip power semiconductor device can be configured to carry a load current to be fed to a load and / or a load current provided by a power source, respectively. For example, a single-chip power semiconductor device can include a plurality of power semiconductor units (also referred to herein as power units), such as monolithically integrated diode units, derivatives of monolithically integrated diode units, monolithically integrated IGBT units and / or derivatives thereof, monolithically integrated MOSFET units and / or derivatives thereof. Such diode units / transistor units can be integrated in a single chip, and one or more such single chips can be integrated in a power semiconductor module. A plurality of such power units can constitute a cell field region in which active regions of monolithically integrated IGBT units and / or derivatives thereof are arranged, as will be explained in more detail below.

[0031] As used in this specification, the term "single-chip power semiconductor device" is intended to describe a power semiconductor device on a single chip having a high voltage blocking capability and / or a high current carrying capability. In other words, the embodiments of the single-chip power semiconductor device described herein are configured for high current (typically in the ampere range, e.g., up to several amperes or up to tens or hundreds of amperes) and / or high voltage (typically 100 V and above, e.g., up to at least 400 V or even higher, e.g., up to at least 3 kV, or even up to 10 kV or higher).

[0032] For example, the single-chip power semiconductor devices described below may be configured as strips or pins and configured to be employed as power components in low, medium, and / or high voltage applications. One or more single-chip power semiconductor devices may be integrated into a module to form a power semiconductor module, such as an IGBT module (or MOSFET module, or MOS gated diode module), for installation and use in low, medium, and / or high voltage applications, such as major home appliances, general-purpose drives, electric drive trains, servo drives, traction, higher power transmission facilities, and the like.

[0033] For example, the term "single-chip power semiconductor device" as used in this specification does not refer to a logic semiconductor device that is used, for example, to store data, calculate data, and / or other types of semiconductor-based data processing.

[0034] Figure 1A power semiconductor module 5 having one or more single-chip power semiconductor devices 1 according to one or more embodiments is schematically and exemplarily illustrated in a simplified manner. To describe the configuration of one or more single-chip power semiconductor devices 1, reference will also be made below to the remaining Figures 2 to 7B .

[0035] Each of the one or more single-chip power semiconductor devices 1 may include a first load terminal 11 and a second load terminal 12. The semiconductor body 10 (compare Figures 5 to 7B ) is integrated in a single chip and coupled to a first load terminal 11 and a second load terminal 12, and is configured to conduct a load current along a load current path between the terminals 11, 12. The single-chip power semiconductor device 1 further includes a control terminal 13 and at least one control electrode 131 (reference electrode 131) electrically connected to the control terminal 13. Figures 5 to 7B ), wherein the at least one control electrode 131 is electrically insulated from the semiconductor body 10 and is configured to control the load current based on a control voltage 25 between the control terminal 13 and the first load terminal 11.

[0036] Each of the one or more single-chip power semiconductor devices 1 of the module 5 may exhibit an IGBT configuration (as in Figures 5 to 7B ) or a MOSFET configuration (in this case, Figures 5 to 7B The configuration exemplarily illustrated in will simply differ in the dopant type of the semiconductor region 108) or a MOS gated diode configuration.

[0037] In an embodiment, the control terminal 13 is a gate terminal, and the first load terminal 11 is a source (or respectively emitter) terminal, and the second load terminal 12 is a drain (or respectively collector) terminal.

[0038] For example, module 5 is provided with a gate voltage V G The gate driver unit (not shown) of 24 controls the gate voltage V G 24 can be in the range of several volts, for example, in the range of -25 V ... +25 V, for example, in the range of -8 V ... +20 V or in the range of -5 V ... 16 V, or correspondingly in the range of 0 V ... 16 V, depending on the configuration of the one or more single-chip power semiconductor devices 1. Again, the range of the applied gate voltage depends on the configuration of the one or more single-chip power semiconductor devices 1. For example, the single-chip power semiconductor device can also be a SiC-MOSFET, and the range of the gate voltage is selected accordingly.

[0039] Gate voltage V GThe control voltage 24 is applied between the output 241 of the gate driver unit and the potential of the first load terminal 11, for example across the optional gate resistor 23 and the gate terminal 13, thereby providing said control voltage 25 between the control terminal 13 and the first load terminal 11. Thus, the control voltage 25 and the gate voltage 24 may be similar in magnitude, the difference between said voltages being dependent on the resistance of the optional gate resistor 23 and the control current flowing through this gate resistor 23.

[0040] In one embodiment, the gate resistor 23 may be implemented as an external resistor, such as, for example, a discrete resistor. Additionally or alternatively, at least a portion of the gate resistor 23 may be provided as an integrated resistor in the module 5 ( Figure 1 ). The gate resistor 23 may be used to limit the current flow from or to the gate driver unit providing the gate voltage 24 to the control electrode 131 , for example to adjust the current slope and / or voltage slope during switching of the module 5 .

[0041] In another embodiment, the gate driver unit may be implemented as a current source, wherein the voltage is limited to the value of the control voltage 25, for example in the range of -25 V ... 25 V, -8 V ... 20 V, or in the range of 0 ... 16 V. The gate driver may provide a control current flow to and from the control electrode 131 during switching on and / or switching off of the power semiconductor module 5. The control current may be configured to shape the current slope and / or voltage slope during switching of the module 5 by varying the current during a switching event.

[0042] For example, a first sub-range of gate voltage amplitudes is associated with an on-state of one or more single-chip power semiconductor devices 1, and a second sub-range of gate voltage amplitudes is associated with an off-state of one or more single-chip power semiconductor devices 1, as is typically the case for MOSFETs and IGBTs.

[0043] In an embodiment, the conductivity of the single-chip power semiconductor device 1 depends on the amplitude of the actual control voltage 25 ; typically, the higher the amplitude of the control voltage 25 , the higher the conductivity, and vice versa.

[0044] Therefore, by limiting the maximum amplitude of the control voltage 25 , the load current in the single-chip power semiconductor device 1 can be limited.

[0045] At least one of the one or more single-chip power semiconductor devices 1 includes a protection structure 15 integrated in the single chip separately from the load current path. The protection structure 15 includes a plurality of pn junctions 153 (compare Figure 2 ) using a plurality of first conductive type first semiconductor regions 151 (compared to Figure 2) and a plurality of second semiconductor regions 152 of the second conductivity type (reference Figure 2 ) series connection 155. The series connection 155 of pn junctions 153 is connected between the control terminal 13 and the first load terminal 11 in a forward biased direction.

[0046] As indicated above, a further optional gate resistor (not shown) may be arranged between the control terminal 13 and the connection establishing the electrical connection of the series connection 155 of the pn junctions 153 to the control terminal 13 .

[0047] As in Figure 1 As illustrated in , the series connection 155 of a plurality of pn junctions 153 (which may thus be a series connection of a corresponding plurality of diodes connected in forward bias between the control terminal 13 and the first load terminal 11) is subjected to the control voltage 25 applied between the control terminal 13 and the first load terminal 11.

[0048] In an embodiment, the protection structure 15 is thermally coupled to the load current path. For example, the thermal resistance and thermal capacitance between the protection structure 15 and the load current path in the semiconductor body 10 define a thermal time constant of no greater than 1 μs. For example, the thermal resistance is in the range of several hundred K / W (e.g., relative to 100 μm). 2 The area is within the range of 10 -11 J / K (for example, also relative to 100 μm 2 area), resulting in a thermal constant below 1 μs (e.g., below 0.5 μs or even below 0.3 μs).

[0049] In an embodiment, the protection structure 15 is configured to limit the control voltage 25 between the control terminal 13 and the first load terminal 11 to a value corresponding to the sum of the temperature-dependent built-in voltages of the pn junctions 153 by discharging the at least one control electrode 131. According to an embodiment, since the series connection 155 of the pn junctions 153 is connected in a forward biased direction between the control terminal 13 and the first load terminal 11, the control voltage 25 between the control terminal 13 and the first load terminal 11 cannot be greater than the total forward voltage of the series connection 155 of the pn junctions 153.

[0050] For example, the total forward voltage of the series connection 155 of the pn junctions 153 decreases as the temperature of the series connection 155 of the pn junctions 153 increases. For example, because the protection structure 15 is thermally coupled to the load current path, in SC events with very high load currents and high voltages, in which an increase in the temperature of the semiconductor body 10 conducting the load current is observed, the temperature of the series connection 155 of the pn junctions 153 also increases, resulting in a reduced total forward voltage of the series connection 155 of the pn junctions 153.

[0051] That is, according to an embodiment, pn junctions 153 are formed by the plurality of first semiconductor regions 151 and the plurality of second semiconductor regions 152 , wherein each pn junction 153 has a built-in voltage having a negative temperature coefficient.

[0052] For example, each of the plurality of first semiconductor regions 151 and the plurality of second semiconductor regions 152 is based on at least one of polycrystalline silicon and polycrystalline germanium. In this case, polycrystalline may also include amorphous materials and microcrystalline materials. Other materials that ensure that each pn junction 153 has a built-in voltage with a negative temperature coefficient may be used. For example, in one embodiment, each of the plurality of first semiconductor regions 151 and the plurality of second semiconductor regions 152 is based on SiC.

[0053] In an embodiment, the total number of pn junctions 153 reaches at least three. The number of pn junctions 153 actually implemented can be selected based on the control characteristics of the single-chip power semiconductor device 1. For example, in the case of a MOSFET / IGBT with a threshold voltage in the range of 4...7V, it may be desirable to limit the control voltage 25 to approximately 10 to 20V, resulting in a higher number of pn junctions 153, for example in the range of 20 to 40 pn junctions 153 (for example, each pn junction has a corresponding built-in voltage of approximately 0.7V at room temperature and a correspondingly reduced built-in voltage of, for example, 0.1V at high temperatures caused by SC events). For example, in the case of a MOSFET or IGBT exhibiting a lower threshold voltage (for example, 1...3V), it may be desirable to limit the control voltage 25 to a significantly lower value of only a few volts.

[0054] Not only a single-chip power semiconductor device 1 (some embodiments of the single-chip power semiconductor device have been described above) and a power semiconductor module 5 including many integrated single-chip power semiconductor devices (some embodiments of the power semiconductor module have been described above) are proposed here, but also a method for producing such a single-chip power semiconductor device 1 is proposed.

[0055] According to an embodiment, a method for forming a single-chip power semiconductor device is proposed. The single-chip power semiconductor device includes: a first load terminal; a second load terminal; a semiconductor body integrated in a single chip and coupled to the first load terminal and the second load terminal, and configured to conduct a load current along a load current path between the terminals; a control terminal and at least one control electrode electrically connected to the control terminal, wherein the at least one control electrode is electrically insulated from the semiconductor body and configured to control the load current based on a control voltage between the control terminal and the first load terminal. The method includes forming a protection structure, which is integrated in a single chip separately from the load current path and includes a series connection of a plurality of first semiconductor regions of a first conductivity type and a plurality of second semiconductor regions of a second conductivity type using a plurality of pn junctions. The series connection of the pn junctions is connected between the control terminal and the first load terminal in a forward biased state.

[0056] Exemplary embodiments of the method correspond to the embodiments of the single-chip power semiconductor device 1 described above.

[0057] Now about Figures 2 to 7B Further exemplary features are described, wherein these features apply similarly to each of the single-chip power semiconductor device 1 , the power semiconductor module, and the method of processing a single-chip power semiconductor device.

[0058] Figure 4 The figure shows a horizontal projection of an embodiment of a single-chip power semiconductor device 1. The single-chip power semiconductor device 1 comprises an active cell region 1-2 having one or more power cells 1-1 (compare to FIG. 1 ) integrated in a semiconductor body 10 and configured to conduct a load current. Figures 5 to 7B ); an edge termination region 1-3, which surrounds the active cell region 1-2 and is terminated by a chip edge 1-4.

[0059] As used herein, the terms "edge termination region" and "active region" are both associated with the corresponding technical meanings that a person skilled in the art typically associates with them in the context of power semiconductor devices. That is, the active regions 1-2 are primarily configured for load current conduction purposes and, if applicable, switching purposes, while the edge termination regions 1-3 primarily fulfill functions related to reliable blocking capability, appropriate guidance of the electric field, and sometimes also charge carrier discharge functions and / or further functions related to protection and appropriate termination of the active regions 1-2.

[0060] Also refer to Figures 5 to 7B, the semiconductor body 10 may have a front side 110 and a back side 120. The front side 110 and the back side 120 may terminate the semiconductor body 10 vertically. Therefore, the thickness of the semiconductor body 10 is defined as the distance between the front side 110 and the back side 120 along the vertical direction Z. In the lateral direction, the semiconductor body 10 may terminate at the chip edge 1-4. Furthermore, both the front side 110 and the back side 120 may extend laterally along both a first lateral direction X and a second lateral direction Y. For example, both the front side 110 and the back side 120 may form respective horizontal surfaces of the semiconductor body 10, and the thickness of the semiconductor body 10 may be the distance between the front side 110 and the back side 120 along the vertical direction Z in the active area 1-2 (e.g. measured at the center 1-20 of the active area 1-2).

[0061] For example, both the control terminal 13 and the first load terminal 11 are at the semiconductor body front side 110, and the second load terminal 12 is at the semiconductor body back side 120. The semiconductor body 10 is configured to conduct a load current between the first load terminal 11 and the second load terminal 12, for example if the potential at the second load terminal 12 is greater than the potential at the first load terminal 11 and the device is in an on-state.

[0062] For example, the first load terminal 11 includes a front-side metallization and / or the second load terminal 12 includes a back-side metallization. For example, the first load terminal 11 is a source (emitter) terminal and the second load terminal 12 is a drain (collector) terminal. At the front side 110, the semiconductor body 10 can be connected to the front-side metallization. At the back side 120, the semiconductor body 10 can be connected to the back-side metallization.

[0063] In an embodiment, the first load terminal 11 (e.g. the front side metallization) overlaps the active area 1-2 laterally, i.e. along the first lateral direction X and / or the second lateral direction Y and / or a combination thereof. It should be noted that the first load terminal 11 may be connected to a local contact in order to electrically contact the semiconductor body 10 at the front side 110. For example, as in Figures 5 to 7B As exemplarily illustrated in FIG, the local contact may be established by means of a contact plug 111 penetrating through the upper insulating layer 171 so as to contact the mesa portion of the power cell 1-1.

[0064] Similarly, in an embodiment, the second load terminal 12 (e.g., the backside metallization) overlaps the active regions 1-2 laterally, i.e., along the first lateral direction X and / or the second lateral direction Y and / or a combination thereof. It should be noted that the second load terminal 12 is typically not structured but rather is formed uniformly and monolithically at the semiconductor body backside 120, e.g., in order to establish a laterally uniform contact (i.e., a continuous contact surface) with the semiconductor body 10 at the backside 120. Such a uniform structure can also be implemented in regions in which the second load terminal 12 laterally overlaps the edge termination regions 1-3.

[0065] For example, the lateral boundaries of the active area 1-2 are approximately defined by the lateral boundaries of the (one or more) outermost power cells 1-1. Thus, the lateral boundaries of the active area 1-2 can be defined at the front side 110. This lateral boundary can be defined by the (one or more) outermost source regions 101 (cf. the more detailed explanation below). For example, all functional elements for enabling the conduction of a load current are present in the vertical projection of the active area 1-2 of the single-chip power semiconductor device 1, for example including at least the first load terminal 11 (e.g., its front side metal contacts, such as one or more of the contact plugs 111), (one or more) source regions 101, the body region 102, the drift region 100, the emitter region 108, and the second load terminal 12 (e.g., its back side metal), as will be explained in more detail below.

[0066] In an embodiment, the edge termination region 1 - 3 and the active region 1 - 2 may be arranged substantially symmetrically to each other, eg, about a central vertical axis spanning the center of the single-chip power semiconductor device 1 .

[0067] For example, the first load terminal 11 may include a source pad structure 115 (e.g., formed or respectively as part of the front side metallization) that laterally overlaps the active area 1-2. The control terminal 13 may include a control pad structure 135. Both the source pad structure 115 and the control pad structure 135 are arranged above the front side 110 of the semiconductor body 10. For example, both the pad structures 115 and 135 are configured to be contacted via chip-external contact components (such as bonding wires).

[0068] At least the upper insulating layer 171 of the single chip can separate both the source pad structure 115 and the control pad structure 135 from the front side 110 of the semiconductor body 10 along the vertical direction Z, as also shown in FIG. Figure 3 is schematically illustrated in Figures 5 to 7B As shown in .

[0069] As in Figure 4As further illustrated in FIG, the control pad structure 135 may include at least one of a control flow channel 1351 and a control finger 1352 separated from the source pad structure 115 by a gap region 1311. Figure 4 As shown in FIG, one or more control flow channels extend adjacent to the edge termination region 1-3, while a control finger 1352 extends through the center 1-20 of the active region 1-2. Both the control flow channel(s) 1351 and the control finger(s) 1352 are configured to provide control voltages to the plurality of power cells 1-1 in the active cell region 1-2. Both the control flow channel(s) 1351 and the control finger(s) 1352 can seamlessly merge with a control landing pad 1353 of the control pad structure 135.

[0070] In an embodiment, at least one of the one or more control flow channels 1351 and the one or more control fingers 1352 extends between two adjacent source pads 1151, 1152 of the source pad structure 115, as shown in FIG. Figure 4 As shown in FIG. Of course, source pad 1151 and control channel(s) 1351 / control finger(s) 1352 must be electrically insulated from one another. For this reason, these regions are laterally separated from one another by gap region(s) 1311. Thus, since control finger(s) 1352 may, for example, extend through the center 1-20 of active region 1-2, gap region(s) 1311 may also be adjacent to the center 1-20 of active region 1-2.

[0071] The center 1-20 of the active area 1-2 is typically also close to the maximum value of the load current density (which, of course, may depend on the actual distribution of the density of power cells 1-1 in the active area 1-2). Therefore, the center 1-20 of the active area 1-2 is typically also close to the maximum temperature of the device 1.

[0072] Now also refer to Figure 2 , Figure 2 Schematically illustrated Figure 4 In the horizontal projection of the portion 400 indicated by the dashed line in FIG, in an embodiment, the series connection 155 of the plurality of pn junctions 153, comprising the plurality of first semiconductor regions 151 and the plurality of second semiconductor regions 152, extends into a region corresponding to the vertical projection of the gap region 1311. The region corresponding to the vertical projection of the gap region 1311 can therefore be located at least partially in a central portion of the active region 1-20, e.g., laterally closer to the center 1-20 than to the chip edge 1-4. This lateral positioning of the protection structure 15 results in good thermal coupling of the series connection 155 of the plurality of pn junctions 153 to the load current path.

[0073] In an embodiment, the first protection structure contact plug 113 extends from the source pad structure 115 (eg, from the second source pad 1152) through the upper insulating layer 171 (cf. Figure 3 and Figures 5 to 7B ), and establishes an electrical connection between the source pad structure 115 and at least one first semiconductor region 151 (e.g., only the last first semiconductor region 151). Furthermore, the second protection structure contact plug 133 extends from the control pad structure 135 (e.g., from the control finger 1352) through the upper insulating layer 171, and establishes an electrical connection between the control pad structure 135 and at least one second semiconductor region 152 (e.g., only the first second semiconductor region 151). The resulting highly doped contact implant region is not separately illustrated in the figures.

[0074] For example, at least a portion of the pn junction 153 is positioned closer to a load current path, such as the active cell region 1-2 (e.g., the center 1-20 of the active cell region 1-2), than the electrical connection connecting the series connection 155 of the pn junctions 153 to the control terminal 13 (i.e., the second protection structure contact plug 133). For example, at least a portion of the pn junction 153 is positioned closer to a load current path, such as the active cell region 1-2, than an adjacent portion of the gate finger 1352.

[0075] Furthermore, as in Figure 2 As schematically illustrated in FIG, according to an embodiment, the protection structure 15 includes a plurality of short-circuit elements 154 that short-circuit np-junctions 156 formed by pairs of respective first semiconductor regions 151 and adjacent second semiconductor regions 152. The short-circuit elements 154 can be based on tungsten, for example. Other possible implementations of the short-circuit elements 154 can be based on one or more of titanium and cobalt, or respectively on highly doped polysilicon plugs optionally in combination with silicides (such as TiSi2, CoSi2, etc.).

[0076] The gap region 1311 may exhibit a thickness of a few micrometers (eg in the range of 1 μm to 100 μm (cf. also Figure 7B )) of the gap width dx. At least a portion of the first semiconductor region 151 and at least a portion of the second semiconductor region 152 may extend into a region overlapping with a portion corresponding to the vertical projection of the gap region 1311. In an embodiment, the semiconductor region 151 and the second semiconductor region 152 may not overlap with the region corresponding to the vertical projection of the control pad structure 135 and the source pad structure 115, but may be spaced apart from them in the lateral direction by distances dx1 and dx2, respectively, as shown in FIG. Figure 2 In other embodiments (control Figures 5 to 7B ), there can be overlap.

[0077] In an embodiment, the short-circuit element 154 does not overlap with a region corresponding to a vertical projection of the control pad structure 135 and the source pad structure 115 , but is laterally spaced apart therefrom.

[0078] For example, in an embodiment, each of the first semiconductor region 151 and the second semiconductor region 152 has a lateral extension (e.g., along the first lateral direction X) of at least the gap width dx. Thus, each of the first semiconductor region 151 and the second semiconductor region 152 may have a lateral extension of up to several micrometers, for example, in the range of 1 μm to 100 μm.

[0079] In an embodiment, the protection structure 15 includes two or more series connections 155, each series connection having a corresponding plurality of pn junctions 153 using a plurality of first semiconductor regions 151 and a plurality of second semiconductor regions 152, the series connections 155 being connected in parallel with each other, as in Figure 2 The larger the cross-section of each pn junction 153 and / or each short-circuit element 154, the greater the current through a single series connection 155 at a certain value of the control voltage 25. Typically, the more series connections 155 connected in parallel are provided, the faster the discharge of the control electrode 131 will occur.

[0080] With regard to the vertical position of the protective structure 15 , additional reference is made to the concept Figure 3 For example, at least the upper insulating layer 171 of the single chip separates both the source pad structure 115 and the control pad structure 135 from the front side 110 of the semiconductor body 10 along the vertical direction Z. As explained above, the protection structure 15 is integrated into the single chip, but is arranged separately from the load current path. For example, at least the lower insulating layer 172 isolates the series connection 155 of the plurality of pn junctions 153 using the plurality of first semiconductor regions 151 and the plurality of second semiconductor regions 152 from the semiconductor body 10.

[0081] In an embodiment, both the source pad structure 115 and the control pad structure 135 are arranged above the upper insulating layer 171. Furthermore, a series connection 155 of the plurality of pn junctions 153 using the plurality of first semiconductor regions 151 and the plurality of second semiconductor regions 152 is at least partially arranged below the upper insulating layer 171. In addition, a series connection 155 of the plurality of pn junctions 153 using the plurality of first semiconductor regions 151 and the plurality of second semiconductor regions 152 is completely arranged above the lower insulating layer 172. Furthermore, the power cell 1-1 can extend further along the vertical direction Z than the lower insulating layer 172.

[0082] The configuration of the lower insulating layer 172 in terms of material and size may affect thermal resistance and thermal capacitance existing between the series connection 155 of the plurality of pn junctions 153 and the load current path.

[0083] Figure 5 A section of a vertical cross section of a single-chip power semiconductor device 1 according to some embodiments is schematically and exemplarily illustrated. First, the configuration of an active cell area 1-2 having a plurality of power cells 1-1 will be briefly explained:

[0084] The single-chip power semiconductor device 1 includes a drift region 100 of a first conductivity type formed in a semiconductor body 10. A body region 102 of a second conductivity type is formed in a mesa portion of the semiconductor body 10, at least part of which is electrically connected to a first load terminal 11, for example, to a source pad structure 115. The body region 102 forms a pn junction with a subsection of a mesa portion 17 of the first conductivity type. The subsection of the mesa portion 17 may be filled with the drift region 100 or a portion of a higher-doped region of the first conductivity type.

[0085] The body region 102 can be arranged to electrically contact the first load terminal 11, for example, by means of a contact plug 111. In each power cell 1-1, at least one source region 101 of the first conductivity type can further be provided, which can also be arranged to electrically contact the first load terminal 11, for example, by means of a contact plug 111. The main part of the semiconductor body 10 is formed as a drift region 100 of the first conductivity type, which can be connected to the body region 102 and form a pn junction therewith. The body region 102 isolates the source region 101 from the drift region 100.

[0086] Further along the vertical direction Z, the drift region 100 may be connected to a field stop layer 107 of the first conductivity type, and the field stop layer 107 may be connected to an emitter region 108 coupled to the second load terminal 12. Depending on the device configuration, the emitter region 108 may be of the first conductivity type (e.g. in the case of a MOSFET configuration) or of the second conductivity type (e.g. in the case of an IGBT configuration), or may include both regions of the first conductivity type and regions of the second conductivity type (e.g. in the case of an RC IGBT configuration).

[0087] Upon receiving a corresponding control voltage provided, for example, by a gate driver unit (not shown), each control electrode 131 may induce an inversion channel in a section of the body region 102 adjacent to the corresponding control electrode 131. Therefore, each of the plurality of power cells 1-1 may be configured to conduct at least a portion of a load current between the first load terminal 11 and the second load terminal 12.

[0088] The control electrode 131 can be arranged in the trench 14 and insulated from the semiconductor body 10 by a corresponding trench insulator 142. The trench 14 can have a strip configuration or a needle configuration. The portion of the semiconductor body laterally bounded by the trench is referred to herein as a mesa portion. Not every mesa portion must include a source region 101 (or a source region 101 electrically connected to the first load terminal 11) and / or not every mesa portion must be electrically connected to the first load terminal by means of a corresponding contact plug 111, and further, not every trench 14 must include a control electrode 131, but can include a trench electrode 141 connected to another potential or electrically floating, so that various cell configurations, i.e., trench mesa patterns, can be designed for the power cell 1-1. However, the actual configuration of the power cell 1-1 is not relevant for the function of the protection structure 15 described herein.

[0089] Rather, the basic configuration of the MOS controlled power cell 1 - 1 described above is as known to those skilled in the art, and this specification employs the term “MOS controlled power cell” within the technical meaning typically associated therewith by those skilled in the art.

[0090] In an embodiment, the single-unit power semiconductor device 1 further includes a well region 109 of the second conductivity type and electrically connected to the first load terminal 11, wherein the well region 109 extends below the protection structure 15 and extends into the portion of the semiconductor body 10 corresponding to the vertical projection of the gap region 1311. For example, the well region 109 is electrically contacted by means of one or more contact plugs 111 and is therefore electrically connected to the first load terminal 11. The well region 109 may extend from the portion corresponding to the vertical projection of the gap region 1311 toward the power cell 1-1, but may be laterally separated from the power cell 1-1 by means of at least one trench 14.

[0091] In an embodiment, the protection structure 15 is arranged between the upper insulating layer 171 and the lower insulating layer 172. The lower insulating layer 172 may be in contact with the well region 109. Therefore, the well region 109 electrically connected to the first load terminal 11 (which is typically connected to a fixed potential, such as ground) can achieve an electrical shielding function by reducing capacitive coupling to a varying potential (such as the potential of the second load terminal 12).

[0092] The thermal time constant of the thermal coupling between the protection structure 15 and the load current path can be influenced by means of the material and / or dimensions (e.g., the thickness of the lower insulating layer 172). For example, a greater thickness of the lower insulating layer 172 results in a greater thermal time constant (compared to Figure 5 、 Figure 7A), and the lower thickness of the lower insulating layer 172 produces a lower thermal time constant due to the reduced thermal resistance and heat capacity (compared to Figures 6A to 6B 、 Figure 7B ).

[0093] An upper insulating layer 171, which separates both the control pad structure 135 and the source pad structure 115 from the front side 110 of the semiconductor body 10, may include a first sublayer 1711 (e.g., an intermediate oxide layer) and a second sublayer 1712 (e.g., a deposited silicon dioxide layer) thereunder. A contact plug 111 penetrates the upper insulating layer 171 to electrically connect the mesa portion to the first load terminal 11. For example, a first conductive layer 117 and a second conductive layer 137 are provided on top of the upper insulating layer 171, and the source pad structure 115 is arranged on top of (e.g., in contact with) the first conductive layer 117, while the control pad structure 135 is arranged on top of (e.g., in contact with) the second conductive layer 137. The contact plug 111 may extend from the first conductive layer 117 through the upper insulating layer 171 along a vertical direction Z and may be made of the same material as the first conductive layer 117, which may be, for example, tungsten (e.g., together with Ti and / or TiN).

[0094] Similar to the contact plugs 111, both the first protection structure contact plug 113 and the second protection structure contact plug 133, which electrically connect the series connection 155 of the pn junction 153 to the source pad structure 115 / control pad structure 135, respectively, may extend from the first conductive layer 117 (or respectively from the second conductive layer 137) through the upper insulating layer 171 along the vertical direction Z and may be made of the same material as the first conductive layer 117 or respectively the same material as the second conductive layer 137. For example, both the first protection structure contact plug 113 and the second protection structure contact plug 133 extend along the vertical direction Z by at least 1 μm, for example, in the range of 350 nm to 2300 nm.

[0095] In an embodiment, the contact plug 111 (which electrically connects the source region 101 of the power cell 1 - 1 with the first load terminal 11 ) and at least one of the first protection structure contact plug 113 and the second protection structure contact plug 133 both exhibit a common vertical extension of at least 500 nm, at least 1 μm, or at least 1.5 μm.

[0096] Furthermore, in an embodiment, the contact plug 111 (which electrically connects the source region 101 of the power cell 1-1 to the first load terminal 11) and at least one of the first protection structure contact plug 113 and the second protection structure contact plug 133 are made of the same material, which may be, for example, aluminum (Al), copper (Cu), or an alloy of aluminum or copper, such as AlSi, AlCu, or AlSiCu. According to other embodiments, the contact plug 111 may include one, two, three, or more sublayers, each of which primarily comprises at least one of nickel (Ni), titanium (Ti), silver (Ag), gold (Au), tungsten (W), platinum (Pt), tantalum (Ta), and palladium (Pd). For example, the sublayers may include a metal nitride or a metal alloy comprising Ni, Ti, Ag, Au, W, Pt, cobalt, and / or Pd.

[0097] Additionally or alternatively, the contact plug 111 (which electrically connects the source region 101 of the power cell 1 - 1 with the first load terminal 11) and at least one of the plurality of short-circuit elements 154 (which short-circuit the np-junction 156 formed by the pair of the corresponding first semiconductor region 151 and the adjacent second semiconductor region 152) also have a common vertical extension of at least 300 nm, at least 600 nm or at least 1 μm.

[0098] Furthermore, in an embodiment, the contact plug 111 (which electrically connects the source region 101 of the power cell 1-1 to the first load terminal 11) and at least one of the plurality of short-circuit elements 154 (which short-circuit the np-junction 156 formed between a corresponding pair of the first semiconductor region 151 and the adjacent second semiconductor region 152) are both made of the same material, examples of which have been identified above. In an embodiment, the materials of the short-circuit elements 154 and the contact plug 111 can be formed at least in part using the same processing steps.

[0099] In an embodiment, the short-circuit element 154 has a shorter vertical extension than the contact plug 111. This is for example Figures 5 to 7B Middle picture.

[0100] Both the source pad structure 115 and the control pad structure 135 may be at least partially covered by an insulating structure 18, which may include a first sublayer 181 (e.g., a thin dielectric film such as silicon nitride in contact with the pad structure 135) and a second sublayer 182 (e.g., a relatively thick imide layer) above the first sublayer 181. The insulating structure 18 may form an outermost insulating structure and serve as a passivation structure for the semiconductor device.

[0101] According to Figure 5In the embodiment schematically illustrated in FIG, the protection structure 15 is arranged below the first sublayer 1711 of the upper insulating layer 171 and below the second sublayer 1712. The lower insulating layer 172 may be, for example, a so-called field oxide, for example having a thickness in the range of 10 nm to 500 nm. The lower insulating layer 172 may be adjacent to the well region 109.

[0102] exist Figure 6A In the variant illustrated in FIG. B , the protection structure 15 is arranged within a first sublayer 1711 of the upper insulating layer 171 and above a second sublayer 1712. The lower insulating layer 172 may be, for example, a so-called gate oxide, for example having a thickness in the range of 5 nm to 200 nm. In this embodiment, the lower insulating layer 172 may, for example, have substantially the same thickness as the trench insulator 142.

[0103] As in Figure 6A and Figure 7A As schematically illustrated in the figure, at least one of the multiple short-circuit elements 154 (whose short circuit is an np junction 156 formed by a pair of corresponding first semiconductor regions 151 and adjacent second semiconductor regions 152) can be arranged in a portion that does not correspond to the vertical projection of the gap region 1311, for example so as to overlap laterally with at least one of the source pad structure 115 and the control pad structure 135.

[0104] As in Figure 6B and Figure 7B As schematically illustrated in the figure, each of the multiple short-circuit elements 154 (which short-circuit an np junction 156 formed by a pair of corresponding first semiconductor regions 151 and adjacent second semiconductor regions 152) is arranged in a portion corresponding to the vertical projection of the gap region 1311, for example so as not to overlap laterally with the source pad structure 115 or the control pad structure 135.

[0105] Of course, according to the described embodiments, the first protection structure contact plug 113 may laterally overlap the source pad structure 115 , and / or the second protection structure contact plug 133 may laterally overlap the control pad structure 135 .

[0106] Furthermore, it should be noted that Figures 5 to 6B Unlike the illustration in FIG, the semiconductor portion below the second protection structure contact plug 133 and laterally overlapping with the control pad structure 135 can be entirely a semiconductor region of the second conductivity type, so that the first short-circuit element 154 shown in the illustration can be omitted ("first" refers to the first short-circuit element along the extension direction of the structure 15 from the second protection structure contact plug 133 toward the first protection structure contact plug 113) because the first junction along said direction will be a pn junction rather than an np junction.

[0107] The embodiments described above include the following recognitions:

[0108] For example, compared to thyristors, IGBTs and MOSFETs have the following advantageous features: the current in a short-circuit (SC) event enters saturation, providing the opportunity to shut down the device within a few microseconds before thermal damage occurs. As devices evolve towards lower conduction losses, cell density and transconductance increase, leading to higher current densities and shorter permissible short-circuit times in short-circuit mode. In some products, the short-circuit time is not limited for loss optimization purposes. However, in some other applications, a short-circuit time of 5 to 10 μs is desirable. Limiting the short-circuit capability results in increased power losses and application costs.

[0109] According to known principles, short-circuit events can be detected externally using current and / or voltage measurements. However, this can be too slow and require additional effort in the application. For example, to limit the short-circuit current and dissipated energy, the maximum allowable gate (i.e., control) voltage may always be limited, resulting in increased turn-on and conduction-state losses. Furthermore, the channel width of the MOS control head may be limited, with the same negative impact.

[0110] According to one or more embodiments described herein, it is proposed to protect the device in the event of a short circuit by automatically limiting the control voltage at extremely high junction temperatures. The protection structure can be integrated directly next to the active cell field region and below the surface passivation of the main device and connect the gate and emitter of the main device. The protection structure can sense the high temperature in the short circuit mode and limit the short circuit current by reducing the control voltage. The protection structure can use a monolithically integrated polysilicon diode. The electrothermal response of such a diode is much faster, as compared to external current and / or voltage measurement methods, which gives more freedom to the chip design in loss optimization. On the other hand, the integrated diode does not rely on external sensors, which increases the reliability of the protection function.

[0111] For example, according to one or more embodiments described herein, the functionality of the protection structure utilizes the fact that during a short circuit the power device (IGBT, MOSFET, Si or SiC based) is rapidly heated to a temperature exceeding the maximum allowed operating junction temperature (e.g., 175° C.) The protection structure may utilize a sufficient number of integrated polysilicon diodes connected in series and connected between the gate and the source or emitter of the power device.

[0112] For example, the number of polysilicon diodes can be selected so that their leakage current is below a specific limit at the maximum permissible control voltage and the maximum permissible junction temperature. At further rising junction temperatures during a short-circuit event, the polysilicon diode's built-in voltage will drop, leading to increased current flow from the gate to the source or emitter and discharge of the gate, thus reducing the gate-source voltage and the short-circuit current. For example, a total of between approximately 3 and 80 pn junctions can be connected in series to provide functionality with today's common operating control voltages (e.g., 10...20 V, or even lower than 10 V or lower than 5 V).

[0113] For example, when switching on a highly capacitive load (such as a long cable), high and prolonged current peaks may also occur in the power devices used for the switch-on process. Conventional methods (such as DESAT, di / dt measurement, etc.) typically have the problem of distinguishing between "normal" capacitive peak currents and "real" short-circuit currents.

[0114] According to one or more embodiments described herein, the aforementioned discrimination problem is addressed by extending the response time before shutting down a power device after detecting a suspicious signal based on a protection structure. This allows the user to wait until the suspicious signal disappears on its own. However, this requires a long short-circuit withstand time, which is no longer compatible with modern power devices with high power densities.

[0115] According to one or more embodiments described herein, such a wait time prevents false triggering and / or increases the ease of use of the power device and the availability of power electronics applications. For example, one or more embodiments described herein use device temperature as a trigger, and the protection structure will automatically trigger only in the event of excessive capacitive loads or short circuits, thereby avoiding unhealthy operation of the power device. Furthermore, the availability of power devices and power electronics applications is extended to the physical limits of the power device.

[0116] In the above, embodiments related to power semiconductor devices / modules and corresponding processing methods are explained.

[0117] For example, these semiconductor devices are based on silicon (Si). Therefore, the single-crystal semiconductor region or layer (e.g., semiconductor body 10 and its regions / regions (e.g., regions, etc.)) can be a single-crystal Si region or Si layer. In other embodiments, polycrystalline silicon or amorphous silicon can be used.

[0118] However, it should be understood that the semiconductor body 10 and its regions / zones can be made of any semiconductor material suitable for manufacturing semiconductor devices. To name a few, examples of such materials include, but are not limited to: basic semiconductor materials (such as silicon (Si) or germanium (Ge)); Group IV compound semiconductor materials (such as silicon carbide (SiC) or silicon germanium (SiGe)); binary, ternary or quaternary Group III-V semiconductor materials (such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN) or indium gallium arsenide phosphide (InGaAsP)); and binary or ternary Group II-VI semiconductor materials (such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe)). The aforementioned semiconductor materials are also referred to as "homojunction semiconductor materials." When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to, aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SiC), and silicon carbide (SiC). x C 1-x ) and silicon-SiGe heterojunction semiconductor materials. For power semiconductor device applications, Si, SiC, GaAs and GaN materials are currently used.

[0119] For ease of description, spatially relative terms such as "below," "lower," "down," "above," and "upper" are used to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the corresponding device other than those depicted in the figures. Further, terms such as "first," "second," and the like are also used to describe various elements, regions, sections, and the like, and are not intended to be limiting. Throughout the description, the same terms refer to the same elements.

[0120] As used herein, the terms “having,” “comprising,” “including,” “including,” and “presenting,” etc. are open-ended terms that indicate the presence of stated elements or features but do not preclude additional elements or features.

[0121] With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.

Claims

1. A single-chip power semiconductor device (1), comprising: - a first load terminal (11); - a second load terminal (12); a semiconductor body (10) integrated in a single chip and coupled to a first load terminal (11) and a second load terminal (12), and configured to conduct a load current along a load current path between the first load terminal (11) and the second load terminal (12); a control terminal (13) and at least one control electrode (131) electrically connected to the control terminal (13), wherein the at least one control electrode (131) is electrically insulated from the semiconductor body (10) and is configured to control a load current based on a control voltage (25) between the control terminal (13) and a first load terminal (11); - a protection structure (15) which is integrated in a single chip separately from a load current path and comprises a series connection (155) of a plurality of pn junctions (153) using a plurality of first semiconductor regions (151) of a first conductivity type and a plurality of second semiconductor regions (152) of a second conductivity type, - a plurality of short-circuit elements (154), the plurality of short-circuit elements (154) short-circuiting np junctions (156) formed by pairs of corresponding first semiconductor regions (151) and adjacent second semiconductor regions (152), wherein: A series connection (155) of pn junctions (153) is connected in forward bias between the control terminal (13) and the first load terminal (11).

2. The single-chip power semiconductor device (1) according to claim 1, wherein: Each of the plurality of first semiconductor regions (151) and the plurality of second semiconductor regions (152) is based on at least one of polysilicon and polygermanium.

3. The single-chip power semiconductor device (1) according to claim 1 or 2, wherein: A pn junction (153) is formed by the plurality of first semiconductor regions (151) and the plurality of second semiconductor regions (152), and each pn junction (153) has a built-in voltage having a negative temperature coefficient.

4. The single-chip power semiconductor device (1) according to one of the preceding claims 1-2, wherein the protection structure (15) is thermally coupled to the load current path.

5. The single-chip power semiconductor device (1) according to one of the preceding claims 1-2, wherein the thermal resistance and thermal capacitance between the protection structure (15) and the load current path in the semiconductor body (10) define a thermal time constant of no more than 1 μs.

6. The single-chip power semiconductor device (1) according to any one of the preceding claims 1-2, wherein: The total forward voltage of the series connection (155) of pn junctions (153) decreases as the temperature of the series connection (155) of pn junctions (153) increases.

7. The single-chip power semiconductor device (1) according to any one of the preceding claims 1-2, wherein: The protection structure (15) is configured to limit the control voltage (25) between the control terminal (13) and the first load terminal (11) to a value corresponding to the sum of the temperature-dependent built-in voltages of the pn junctions (153) by discharging the at least one control electrode (131).

8. The single-chip power semiconductor device (1) according to any of the preceding claims 1-2, further comprising a lower insulating layer (172) isolating the series connection (155) of the plurality of pn junctions (153) using the plurality of first semiconductor regions (151) and the plurality of second semiconductor regions (152) from the semiconductor body (10).

9. The single-chip power semiconductor device (1) according to any one of the preceding claims 1-2, further comprising: an active cell region (1-2) having one or more power cells (1-1) integrated in a semiconductor body (10) and configured to conduct a load current; An edge termination region (1-3) surrounding the active cell region (1-2) and terminating at the chip edge (1-4), wherein: - the first load terminal (11) comprises a source pad structure (115) that overlaps the active cell region (1-2) in a lateral direction; - the control terminal (13) comprises a control pad structure (135), both the source pad structure (115) and the control pad structure (135) being arranged above the front side (110) of the semiconductor body (10); At least an upper insulating layer (171) of the single chip separates both the source pad structure (115) and the control pad structure (135) from the front side (110) of the semiconductor body (10) along a vertical direction (Z).

10. The single-chip power semiconductor device (1) according to claim 9, wherein: The series connection (155) of the plurality of pn junctions (153) using the plurality of first semiconductor regions (151) and the plurality of second semiconductor regions (152) is at least partially arranged below the upper insulating layer (171).

11. The single-chip power semiconductor device (1) according to claim 10, further comprising: a first protection structure contact plug (113) extending from the source pad structure (115) through the upper insulating layer (171) and establishing an electrical connection between the source pad structure (115) and the at least one first semiconductor region (151); And / or further includes: a second protection structure contact plug (133) extending from the control pad structure (135) through the upper insulating layer (171) and establishing an electrical connection between the control pad structure (135) and at least one second semiconductor region (152).

12. The single-chip power semiconductor device (1) according to claim 11, wherein: Both the first protection structure contact plug (113) and the second protection structure contact plug (133) extend at least 1 μm along the vertical direction (Z).

13. The single-chip power semiconductor device (1) according to claim 9, wherein: The control pad structure (135) includes at least one of a control channel (1351) and a control finger (1352) separated from the source pad structure (115) by a gap region (1311), wherein the series connection (155) of the plurality of pn junctions (153) using the plurality of first semiconductor regions (151) and the plurality of second semiconductor regions (152) extends to a region corresponding to a vertical projection of the gap region (1311).

14. The single-chip power semiconductor device (1) according to claim 13, wherein: At least one of the control channel (1351) and the control finger (1352) extends between two adjacent source pads (1151, 1152) of the source pad structure (115).

15. The single-chip power semiconductor device (1) according to claim 13 or 14, further comprising a well region (109) of the second conductivity type and electrically connected to the first load terminal (11), wherein The well region (109) extends below the protection structure (15) and into the region corresponding to the vertical projection of the gap region (1311).

16. The single-chip power semiconductor device (1) according to one of the preceding claims 13 to 14, wherein The region corresponding to the vertical projection of the gap region (1311) is at least partially located in a central portion that is laterally closer to the center (1-20) of the active cell region (1-2) than to the chip edge (1-4).

17. The single-chip power semiconductor device (1) according to any one of the preceding claims 1-2, wherein: At least a portion of the pn junction (153) is positioned closer to a load current path than an electrical connection connecting the series connection (155) of the pn junctions (153) to the control terminal (13).

18. A power semiconductor module (5), comprising a plurality of integrated single-chip power semiconductor devices (1) according to any one of claims 1 to 17.

19. A method for processing a single-chip power semiconductor device (1), the single-chip power semiconductor device (1) having: - a first load terminal (11); - a second load terminal (12); a semiconductor body (10) integrated in a single chip and coupled to a first load terminal (11) and a second load terminal (12), and configured to conduct a load current along a load current path between the first load terminal (11) and the second load terminal (12); a control terminal (13) and at least one control electrode (131) electrically connected to the control terminal (13), wherein the at least one control electrode (131) is electrically insulated from the semiconductor body (10) and is configured to control a load current based on a control voltage (25) between the control terminal (13) and a first load terminal (11); in, The method comprises forming a protection structure (15) which is integrated in a single chip separately from a load current path and comprises a series connection (155) of a plurality of pn junctions (153) using a plurality of first semiconductor regions (151) of a first conductivity type and a plurality of second semiconductor regions (152) of a second conductivity type, wherein the series connection (155) of the pn junctions (153) is connected in a forward biased direction between a control terminal (13) and a first load terminal (11), and wherein a plurality of short-circuit elements (154) are short-circuited to np junctions (156) formed by pairs of corresponding first semiconductor regions (151) and adjacent second semiconductor regions (152).

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