Method and system for a JFET with injection isolation

Abstract

A vertical junction field effect transistor (JFET) includes: a substrate; an active area having a plurality of semiconductor fins; a source metal layer on an upper surface of the fins; a source metal disk layer coupled to the semiconductor fins through the source metal layer; a gate area surrounding the semiconductor fins; and a body diode surrounding the gate area.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 953,059, filed on December 23, 2019, entitled “Method and System for JFET with Implant Isolation,” the disclosure of which is hereby incorporated by reference in its entirety for all purposes. Background Art

[0003] Power electronics are widely used in various applications. For example, power electronic devices are often used in power switching applications. Typical devices currently used in power applications are Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) and Insulated Gate Bipolar Transistor (IGBT). Summary of the invention

[0004] Embodiments of the present invention provide a novel vertical JFET device with a monolithically integrated source-to-drain connected body diode. Monolithic integration, rather than using a co-packaged diode, can reduce the parasitic inductance and resistance of the interconnection between the transistor and the diode terminals, and reduce the total number of parts, thereby reducing packaging cost, complexity, and board space.

[0005] The present invention achieves many benefits over conventional technologies. Embodiments of the present invention provide methods and devices for providing a vertical JFET, which includes an integrated source-to-drain connected body diode, which is desirable for various circuit applications. In a conventional structure, the JFET equivalent circuit contains a pair of diodes connected from the gate to the source and from the gate to the drain. The gate-connected diode has the possibility of being turned on and drawing current from the gate under certain conditions. The gate drive circuit will need to be able to handle this current, which is undesirable. In ordinary circuit topologies, the diode connected from the source to the drain can be used as a flywheel or freewheeling diode to prevent the accumulation of high voltages across the transistor switch in the inductive circuit. The advantage of using GaN for the body diode is that there is no minority carrier storage, which achieves fast switching and low power loss. In another embodiment, the diode is manufactured as a Schottky diode for low turn-on voltage and high switching speed. In another embodiment, the diode is manufactured as a merged pn-Schottky (Merged pn-Schottky, MPS) diode. The MPS structure can achieve a combination of low turn-on voltage and low reverse bias leakage.

[0006] According to an embodiment of the present invention, a vertical junction field effect transistor (JFET) includes: a substrate; an active area having a plurality of semiconductor fins; a source metal layer on the upper surface of the fins; a source metal pad layer coupled to the semiconductor fins through the source metal layer; a gate area surrounding the semiconductor fins; and a body diode surrounding the gate area.

[0007] According to an embodiment of the present invention, a method for manufacturing a vertical junction field effect transistor (JFET) includes: providing a semiconductor substrate of a first conductivity type and having a first surface and a second surface; forming a plurality of fins coupled to the semiconductor substrate; forming a gate layer of a second conductivity type opposite to the first conductivity type surrounding the plurality of fins; and forming an isolation region surrounding the plurality of fins, and simultaneously forming a body diode region surrounding the isolation region.

[0008] According to an embodiment of the present invention, a vertical junction field effect transistor (JFET) is provided. The vertical JFET includes: a substrate; an active region, the active region includes a plurality of semiconductor fins; and a source metal layer, the source metal layer is electrically coupled to the surface of the semiconductor fin. The vertical JFET also includes: a source metal disk layer, the source metal disk layer is coupled to the semiconductor fin through the source metal layer; a gate region, the gate region surrounds the semiconductor fin; and a body diode, the body diode surrounds the gate region.

[0009] According to another embodiment of the present invention, a method for manufacturing a vertical junction field effect transistor (JFET) is provided. The method includes: providing a semiconductor substrate of a first conductivity type and having a first surface and a second surface; and forming a plurality of fins coupled to the semiconductor substrate. The method also includes: forming a gate layer of a second conductivity type opposite to the first conductivity type surrounding the plurality of fins, and at the same time: forming an isolation region surrounding the plurality of fins and forming a body diode region surrounding the isolation region.

[0010] According to a specific embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes: a substrate including an n+GaN layer; a drift layer coupled to the substrate and including an n-GaN layer; and a plurality of fins including an n GaN material and coupled to the drift layer. The semiconductor device also includes: a gate layer including a p GaN material and surrounding the plurality of fins; an integrated diode body surrounding the plurality of fins; and an isolation region arranged between the plurality of fins and the integrated diode body.

[0011] Additional features and advantages will become apparent to those skilled in the art after reviewing the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings form a part of this disclosure describing exemplary embodiments of the present invention. Together with the description, they will explain the principles of the present invention.

[0013] Figure 1 is a cross-sectional view of a vertical fin-based field effect transistor (FinFET) device with an integrated body diode according to an embodiment of the present disclosure.

[0014] Figure 2A is a simplified plan view of a vertical fin-based field effect transistor (FinFET) device with an integrated body diode according to an embodiment of the present disclosure.

[0015] Figure 2B yes Figure 2A An enlarged view of a portion of an exemplary layout of a vertical FinFET device is shown.

[0016] include Figure 3A and Figure 3B 3 is a simplified flow chart of a method of fabricating a vertical FinFET device with an integrated body diode according to an embodiment of the present disclosure.

[0017] FIG. 4A to FIG. 4L is a cross-sectional view illustrating an intermediate stage in a method of fabricating a vertical FinFET device with an integrated body diode according to an embodiment of the present disclosure.

[0018] include Figure 5A and Figure 5B 5 is a simplified flow chart of a method of fabricating a vertical FinFET device with an MPS diode and edge termination according to an embodiment of the present disclosure.

[0019] 6A to 6H is a cross-sectional view illustrating an intermediate stage in a method of fabricating a vertical FinFET device with an integrated MPS diode according to an embodiment of the present disclosure.

[0020] include Fig. 7A and Figure 7B 7 is a simplified flow chart illustrating a method for fabricating a vertical FinFET device having an integrated merged PiN Schottky (MPS) diode and an edge termination structure of the MPS diode connected between the source and drain of the vertical FinFET device according to an embodiment of the present disclosure.

[0021] FIG. 8A to FIG. 8LA partial cross-sectional view of a vertical FinFET device structure having a source, gate, drift region, MPS diode, and edge termination structure during stages of a fabrication method according to an embodiment of the present disclosure is illustrated. DETAILED DESCRIPTION

[0022] It should be understood that the drawings are not drawn to scale, and similar reference numerals are used to represent similar elements. As used herein, the terms "example implementation", "exemplary implementation" and "present implementation" do not necessarily refer to a single implementation, although it can, and various example implementations can be easily combined and interchanged without departing from the scope or spirit of the present invention. In addition, the terms used herein are only used for the purpose of describing the example implementation, and are not intended to limit the present invention. In this regard, as used herein, the term "in ... " can include "in ... " and "on ... ", and the terms "one", "an" and "the" can include singular and plural references. In addition, as used herein, the term "by" can also mean "from", depending on the context. In addition, as used herein, the term "if" can also mean "when ... " or "when ... ", depending on the context. In addition, as used herein, the word "and / or" can refer to and cover any possible combination of one or more associated listed items.

[0023] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or segments, these elements, components, regions, layers and / or segments should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or segment from another region, layer or segment. Thus, the first element, component, region, layer or segment discussed below may be referred to as a second element, component, region, layer or segment without departing from the teachings of the present invention.

[0024] The term "horizontal" as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term "vertical" refers to a direction perpendicular to the horizontal as defined above. Prepositions such as "on", "side" (as in "sidewall"), "below", "above", "higher", "lower", "above", and "below" are defined relative to a conventional plane or surface on the top surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. It should be understood that these terms are intended to include different orientations of the device in addition to the orientations depicted in the accompanying drawings.

[0025] As mentioned above, conventional depletion-mode MOSFETs have an inherent source-to-drain connected body diode in their structure. This body diode is used in various switching circuit topologies. Junction field effect transistors (JFETs) do not have this inherent source-to-drain connected body diode in their structure. Insulated gate bipolar transistors (IGBTs) are often co-packaged with discrete diodes that provide similar functionality. Therefore, there is a need to monolithically integrate the body diode with the vertical JFET device.

[0026] Figure 1 A partial cross-sectional view of a vertical fin-based field effect transistor (FinFET) device 100 with an integrated body diode according to an embodiment of the present disclosure is illustrated. The FinFET structure (i.e., active region) is shown in region 140, and the body diode (i.e., body diode region) is shown in region 150. The body diode anode and source terminals are connected to a pad metal disposed above the FinFET device through vias. The isolation region provides electrical isolation between the FinFET active region and the body diode by disconnecting the conductive p-GaN layer between them. In one embodiment, the isolation region is formed using an ion implantation step (e.g., using nitrogen or argon) to form a trap that neutralizes the p-GaN layer. In another embodiment, the isolation region is formed by using ion implantation of n-type donor atoms to counter-dope the p-GaN layer. In another embodiment, the isolation region is formed using a plasma treatment (e.g., in a hydrogen plasma) that inactivates the doping atoms in the p-GaN layer. In another embodiment, the isolation region is a channel filled with a dielectric material. The FinFET and the diode share the same drift layer. In one embodiment, the integrated body diode is a PN diode. In other embodiments, the integrated body diode is a MPS diode.

[0027] refer to Figure 1 , the FinFET device 100 may include a semiconductor substrate 101, a drift layer 102 on the semiconductor substrate 101, and a plurality of fins 103 on the drift layer 102. In one embodiment, the semiconductor substrate 101 is an n+ doped substrate, the drift layer 102 is an n- doped layer, and the fins 103 are formed in the n- doped layer 143. The symbols "n+", "n-", and "n" indicate the relative doping relationship between the semiconductor substrate 101, the drift layer 102, and the fins 103. Typically, the semiconductor substrate 101 is more heavily doped than the fins 103, which in turn are more heavily doped than the drift layer 102. The actual doping concentration varies depending on the technology and application of the FinFET device 100. The FinFET device 100 may also include a source metal layer 104 on the upper surface of the fin 103. In one embodiment, the source metal layer 104 may be a refractory metal, a refractory metal compound, or a refractory metal alloy (e.g., TiN).

[0028] The FinFET device 100 may also include a gate layer 106 on the drift layer 102, the gate layer 106 surrounding the fin 103. In one embodiment, the gate layer 106 may be doped to form a p-type doped layer. In one embodiment, the p-type doping may be performed using ion implantation of an acceptor species and then an activation process. In one embodiment, the p-type doping may be performed by regrowing an epitaxial p-type doped GaN layer using metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). In one embodiment, the gate layer has an upper surface flush with the upper surface of the fin. In one embodiment, the gate layer is non-planar and substantially conformal to the side surface of the fin and the top of the drift layer 102. The FinFET device 100 may also include an isolation region 107 in the gate layer 106 surrounding the gate layer 106 and the fin 103. In one embodiment, the isolation region 107 may extend into the drift layer 102. In one embodiment, the isolation region 107 may terminate at the interface between the gate layer 106 and the drift layer 102.

[0029] The FinFET device 100 may further include a body diode 126 (a box indicated by a dashed line) surrounding the isolation region 107. The diode body includes a portion 106a of the p-type doped layer, which forms an anode of the diode body, and a portion 102c of the drift layer 102 below the portion 106a of the p-type doped layer, which forms a cathode of the body diode.

[0030] The FinFET device 100 may also include a gate metal layer 110, which includes a portion 110a on the gate layer 106 and a portion 110b on the anode 106a of the diode body 126. The FinFET device 100 may also include an interlayer dielectric layer 111, which covers the gate layer 106, the gate metal layer 110 (110a, 110b) and the isolation region 107. The FinFET device 100 may also include through holes (or vias) 112, which extend through the interlayer dielectric layer 111 and expose the upper surface of the source metal layer 104 and the upper surface of the portion 110b of the gate metal layer 110 associated with the body diode 126. Hereinafter, the portion 110a of the gate metal layer 110 is represented as the fin gate metal layer 110a, and the portion 110b of the gate metal layer 110 is represented as the anode metal layer 110b. In one embodiment, the through hole is filled with a metal material to form a via 113. In one embodiment, the isolation region 107 may include a channel formed in the gate layer and extending to the interface between the gate layer and the drift layer. In one embodiment, the channel of the isolation region 107 may include a dielectric material, such as silicon dioxide or silicon nitride. In one embodiment, the isolation region 107 may be formed in an n-type doped region. In one embodiment, the isolation region 107 may include a floating fin (not shown), i.e., the source of the fin is not electrically connected to any potential.

[0031] The FinFET device 100 may further include a source pad metal layer 114 on the interlayer dielectric layer 111 and electrically contacting the source metal layer 104 on the upper surface of the fin 103 through the via 113, and electrically contacting a portion 110b of the gate metal layer 108 associated with the body diode through the via 113. The FinFET device 100 may further include a drain metal layer 115 on the bottom surface of the semiconductor substrate 101. The body diode 126 is connected between the source pad metal layer 114 and the drain metal layer 115.

[0032] In some embodiments, the semiconductor substrate 101 may include an n+ doped III-nitride material, the fin 103 may include an n-doped III-nitride material, and the drift layer 102 may include an n-doped nitride material. In one embodiment, the n+ doped III-nitride material has a relative density of about 1×10 19 Atom / cm 3 The doping concentration of n-doped III-nitride materials is about 7.5×10 16 Atom / cm 3 The doping concentration of n-doped III-nitride materials is about 1×10 16 Atom / cm 3 of doping concentration.

[0033] In one embodiment, the semiconductor substrate 101 includes an n+GaN material layer, the first semiconductor layer 102 includes an n-GaN drift layer, and the gate layer 106 includes a p-type GaN layer. The fin 103 is formed in the n-GaN layer. The anode 106a is formed in the p-type GaN layer, and the doping concentration of the layer is substantially the same as the doping concentration of the gate layer 106. The cathode 102c includes a doping concentration substantially the same as the doping concentration of the drift layer 102.

[0034] Figure 2A is a simplified plan view illustrating an example layout of a vertical fin field effect transistor (FinFET) device with an integrated body diode according to an embodiment of the present disclosure. In some embodiments, the body diode is formed at the periphery of the FinFET active area, inside the edge termination. The body diode is electrically separated from the FinFET active area by an isolation region that is compatible with FET processes. In the case of a standard PN-body diode, the FinFET gate metal is used to form an ohmic contact to the p-type GaN anode of the diode, or an additional process step is used to form a merged PN-Schottky diode. The anode is connected to the source pad metal layer above through a via through the dielectric layer.

[0035] refer to Figure 2A The FinFET device 200 includes: an active region 221 having a plurality of semiconductor fins 203 arranged in parallel along a first direction (e.g., vertically); a source plate metal layer 214 formed on the semiconductor fins. A large number of vias (e.g., Figure 1 The diode region 206 is formed to surround the active region 221 and includes a large number of vias 206v ( Figure 2B The FinFET device 200 further includes an isolation ring 207 disposed between the active region 221 and the diode region 206. The FinFET device 200 further includes an edge termination region 231 adjacent to and surrounding the diode region 206.

[0036] Figure 2B for Figure 2A An enlarged view of a portion 201 of an exemplary layout of a FinFET device 200 is shown. Figure 2B, a portion of the active area 221 is shown as having: a plurality of elongated semiconductor fins 203, which are electrically in contact with the source disk metal layer 214; an isolation ring 207, which is formed below the source disk metal layer 214; an anode metal layer 210b, which is arranged in the diode region 206 and is electrically in contact with the anode 106a of the body diode 126; and a plurality of vias 206v, which electrically connect the anode metal layer 210B to the source disk metal layer 214. Figure 1 A cross-sectional view of a portion of an exemplary layout of a FinFET device 200 is shown in FIG.

[0037] FIG3 is a simplified flow chart illustrating a method 300 for fabricating a vertical fin-based FET (FinFET) device having an integrated body diode connected between a source and a drain of the vertical FinFET device according to an embodiment of the present disclosure. Referring to FIG3 , the method 300 may include providing a III-nitride substrate (310) having a first surface and a second surface opposite to the first surface. In an embodiment, the III-nitride substrate is an n+GaN substrate. For example, a first III-nitride layer is epitaxially grown on the first surface of the III-nitride substrate at a temperature between 950 degrees Celsius and 1100 degrees Celsius, and the first III-nitride layer is characterized by a first doping concentration (e.g., having a doping concentration of about 1×10 16 Atom / cm 3 In some embodiments, the first III-nitride layer is a drift layer. Method 300 further includes forming a second III-nitride epitaxial layer on the first III-nitride layer (314). In an embodiment, the second III-nitride layer is characterized by a second doping concentration that is higher than the doping concentration of the first III-nitride layer. In an embodiment, the second doping concentration is about 1×10 17 Atom / cm 3 . In an embodiment, a region having a gradient doping concentration is formed between the first III-nitride layer and the constant doping concentration region in the second III-nitride layer. In some embodiments, the second III-nitride epitaxial layer is a fin layer. Method 300 also includes: forming a patterned hard mask layer (316) on the second III-nitride layer. In one embodiment, the patterned hard mask layer is formed by depositing and patterning a dielectric material. In one embodiment, the patterned hard mask layer is composed of a source metal layer on the second III-nitride layer and a patterned hard mask layer formed on the source metal layer, the hard mask layer being used as a mask to etch the source metal layer, thereby producing a composite patterned hard mask layer. Method 300 also includes: using the patterned hard mask layer as a mask to form a plurality of semiconductor fins (318) separated by groove regions in the second III-nitride layer.

[0038] Method 300 also includes: regrowing a third III-nitride epitaxial layer (320) in the trench region. In an embodiment, the regrown III-nitride layer is a gate layer and is characterized by a conductivity type opposite to the conductivity type of the first III-nitride layer and the second III-nitride layer. Method 300 also includes: forming a source metal layer as a contact (322) on the upper surface of the n-type fin. In an embodiment, the contact is self-aligned. In an embodiment, the source metal layer of the hard mask is in electrical contact with the top of the n-type fin. Method 300 also includes: forming an isolation region (324) in the third III-nitride epitaxial layer. In an embodiment, the isolation region can be formed by performing an etching process (e.g., a reactive ion etching process) to form an isolation trench. In one embodiment, the isolation trench can be filled with an insulating material, such as a dielectric (silicon dioxide, silicon nitride). Reference Figure 1 , the isolation channel may be an isolation region 107 surrounding the fin 103. In another embodiment, the method 300 may include: selectively implanting an n-type dopant into the isolation channel to form a vertical isolation implant layer in the third III-nitride layer. In another embodiment, the method 300 may include: selectively implanting nitrogen, argon, or helium to form a well that neutralizes the p-GaN doping and forms an implanted isolation channel. In another embodiment, the method 300 may include: selectively treating the third III-nitride epitaxial layer with a plasma (e.g., a hydrogen plasma) to locally passivate the dopant in the third III-nitride epitaxial layer. In yet another embodiment, the isolation region may include a suspended fin, i.e., the suspended fin is not connected to a source disk metal layer to be formed in a subsequent process step.

[0039] The method 300 further includes forming a gate metal layer (326) on the third III-nitride epitaxial layer. Figure 1, the gate metal layer has a first portion 110a arranged on a first portion of the third III-nitride layer and a second portion 110b arranged on a second portion of the third III-nitride layer, the first portion of the third III-nitride layer is on one side of the isolation region 107 and surrounds the semiconductor fin, and the second portion of the third III-nitride layer is on the opposite side of the isolation region and does not have a semiconductor fin. Method 300 also includes: forming an interlayer dielectric layer (e.g., interlayer dielectric layer 111) (328) covering the source metal layer, the gate metal layer, and the third III-nitride epitaxial layer. Method 300 also includes: masking and etching the interlayer dielectric layer to form through holes, which expose the upper surface of the source metal layer on the second III-nitride layer and the upper surface of the second portion of the gate metal layer arranged on the opposite side of the isolation region. Thus, method 300 includes: etching the interlayer dielectric layer using the patterned hard mask layer as a mask to form through holes (330) exposing the source metal layer (source metal layer 104 on the fin 103) and the gate metal layer, and filling the through holes with a conductive material to form a plurality of vias (332) contacting the source metal layer and the gate metal layer.

[0040] Method 300 also includes: forming a source disk metal layer on the interlayer dielectric layer, the source disk metal layer electrically contacting the conductive material contacting the source metal layer, and forming a gate disk metal layer on the interlayer dielectric, the gate disk metal layer electrically contacting the conductive material contacting the gate metal layer (334); and forming a drain metal layer (336) on the second surface of the III-nitride substrate.

[0041] It should be understood that the specific steps illustrated in FIG. 3 provide a specific method for manufacturing a vertical FinFET device with an integrated body diode according to an embodiment of the present invention. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the above steps in a different order. Moreover, each of the steps illustrated in FIG. 3 may include multiple sub-steps, which may be performed in various orders suitable for each step. In addition, additional steps may be added or removed depending on the specific application. One of ordinary skill in the art will recognize that changes, modifications, and substitutions may be made.

[0042] Refer back to Figure 3 and refer to FIG. 4A to FIG. 4I , methods of fabricating vertical FinFET devices according to some embodiments of the present invention are described. Figure 4A4 is a partial cross-sectional view illustrating an n+ doped semiconductor substrate 401, an n- doped semiconductor layer 402 epitaxially grown on the n+ doped semiconductor substrate 401, and an n- doped semiconductor layer 403 epitaxially grown on the n- doped semiconductor layer 402. In one embodiment, the n- doped semiconductor layer 402 forms a drift region of the device and is doped with an n-type dopant such as silicon. In one embodiment, a patterned hard mask (474) is formed on the n- doped semiconductor layer 403. In one embodiment, a metal layer (not shown) is formed on the n- doped semiconductor layer 403, a hard mask layer (not shown) is formed on the metal layer and patterned, and an etching process is performed on the metal layer using the patterned hard mask layer as a mask to obtain a patterned hard mask and a source metal layer 404. In one embodiment, the patterned hard mask layer may include silicon dioxide or silicon nitride. In one embodiment, the patterned hard mask layer may be formed by PECVD. In another embodiment, the patterned hard mask layer may be formed using RIE with a F-based chemistry. In one embodiment, the n+ doped semiconductor substrate may be an n+ doped III-nitride substrate, wherein the n-type dopant is about 5×10 17 Atom / cm 3 To about 1×10 19 Atom / cm 3 In one embodiment, the drift region may have a value within the range of about 1×10 16 to 1×10 17 Atom / cm 3 In one embodiment, the n-doped semiconductor layer 403 may have a net n-type doping concentration in the range of about 1×10 17 Up to 1×10 18 Atom / cm 3 In one embodiment, the metal layer may include TiN. These steps correspond to steps 310 to 316 of the method 300 shown in FIG. 3 .

[0043] Figure 4B 4 is a partial cross-sectional view of the device structure after performing an etching process to obtain a plurality of semiconductor fins 403' separated by trench regions 405 (step 318). Note that after the etching process, the bottom of the trench between the fins may have a thickness similar to that of the fins. Figure 4BShapes different from the shapes shown. Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments of the invention and intermediate structures. For clarity, the thicknesses of layers and regions in the drawings may not be drawn to scale. Variations in the shapes of the figures as a result of, for example, manufacturing techniques and / or tolerances are expected. Thus, embodiments of the invention should not be construed as limited to the specific shapes of the regions illustrated herein, but rather include deviations in shape that result from manufacturing. In the following figures, the bottom of the fin is shown as having a 90 degree angle with the surface of the drift region, i.e., the fin is shown as having a cross-sectional rectangular shape. It is understood that the bottom of the fin may have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of the device, and are not intended to limit the scope of the invention. In one embodiment, the depth of the slot region 405 may be different in different regions of the device. In one embodiment, the depth of the slot region 405 may be greater in the region where the body diode is subsequently formed (e.g., see Figure 4D ).

[0044] In one embodiment, after forming the trench region 405 , a cleaning process and / or a pre-cleaning process is performed using a TMAH solution.

[0045] Figure 4C 3 is a partial cross-sectional view illustrating the device structure after epitaxially regrowing the third semiconductor layer 406 in the trench region (step 320). In one embodiment, the third semiconductor layer 406 may include a p-type III-nitride layer that is epitaxially grown in the trench region and uniformly grown to a thickness that is substantially coplanar with the bottom of the source metal layer 404. In one embodiment, the p-type III-nitride layer may be formed with about 1×10 19 Atom / cm 3 Mg is doped at a doping concentration of Mg. In one embodiment, an annealing process may be performed to activate Mg doping atoms in an amount greater than 10 wt %. In one embodiment, the patterned hard mask layer 474 is removed, which exposes the upper surface of the fin, and a source metal layer 404 is formed on the upper surface of the fin (step 322). In one embodiment, a patterned source mask layer (not shown) having an opening is formed on the exposed upper surface of the fin, and a source metal layer is formed on the upper surface of the fin through the opening of the patterned source mask layer and serves as a source contact of the fin. Thereafter, the patterned source mask layer is removed.

[0046] Figures 4D to 4G FIG. 4 is a partial cross-sectional view illustrating a device structure after an isolation region 407 is formed in the third semiconductor layer 406 (step 324 ). Figure 4DThe isolation region 407 divides the device structure into an active region 440 and a body diode region 450. In one embodiment, the isolation region 407 may be a channel formed in the third semiconductor layer 406, which extends into a portion of the second semiconductor layer 402, such as Figure 4D As shown. The channel may have a width smaller than the width of the fin 403'. In one embodiment, the isolation region 407 may be a channel filled with a dielectric material 408, such as Figure 4E In one embodiment, the isolation region 407 may be an n-type doped region 409, such as Figure 4F In one embodiment, the isolation region 407 may be a suspended fin 403f, that is, the fin 403f is not connected to a subsequently formed source pad metal as further described below. Figure 4G shown.

[0047] Figure 4H 3 is a partial cross-sectional view illustrating a device structure after forming a source metal layer 404a on the fin (step 322) and forming a gate metal layer 410 on the third semiconductor layer 406 (step 326). The gate metal layer 410 has a first portion 410a disposed on a portion of the third semiconductor layer 406 in the active region and a second portion 410b disposed on a portion of the third semiconductor layer 406 in the body diode region. Note that in Figure 4H 4, the isolation region is represented by a trench 407, however, it is understood that the isolation region can be one of a trench, a trench filled with a dielectric material, an n-type doped region, a suspended fin, a well-rich region with ion implantation for neutralization and conduction, or a plasma-treated region where the p-type dopant has been passivated. In one embodiment, the body diode region includes a portion 406a of the gate region 402 that forms an anode of the body diode and a portion 402c of the second semiconductor layer 402 that forms a cathode of the body diode. In one embodiment, the portion 402c that forms the cathode of the body diode is thinner than the semiconductor layer 402 below the active region.

[0048] Fig. 4I 3 is a partial cross-sectional view illustrating a device structure after an interlayer dielectric layer 411 is formed (step 328) on the gate metal layer 410, the third semiconductor layer 406, and the fin 403' including the source metal layer 404. In one embodiment, the interlayer dielectric layer 411 may be formed by deposition at a temperature of 300 degrees Celsius using a plasma enhanced chemical vapor deposition (PECVD) process.

[0049] Figure 4J4 is a partial cross-sectional view illustrating a device structure after a through hole (via) 412 is formed in an interlayer dielectric layer 411. For example, a patterned photoresist is formed over the interlayer dielectric layer using a photolithography process to define the location of a through hole (via) over the metal layer on the upper portion of the fin in the body diode region and the second portion 410b of the gate metal layer to be formed. After the via is formed, the patterned photoresist is removed.

[0050] Figure 4K is a partial cross-sectional view illustrating the device structure after the via hole (through hole) is filled with the conductive material 413.

[0051] Figure 4L 4 is a partial cross-sectional view illustrating the device structure after the source pad metal layer 414 is formed to be in electrical contact with the conductive material 413. Figure 4L As shown in FIG. 4 , a drain metal layer 415 is formed on the bottom surface of the n+ doped semiconductor substrate 401. The anode 406a of the body diode is connected to the source pad metal layer 414, and the cathode 402c of the body diode is connected to the drain metal layer 415. Figure 4L In the illustrated embodiment, a PN junction diode is formed. Therefore, the anode of the PN junction diode is connected to the source of the vertical FinFET device, and the cathode of the PN junction diode is connected to the drain of the vertical FinFET device. The source pad metal layer can be formed using any of a variety of processes such as sputtering, evaporation, deposition, etc. The drain metal layer can be formed using any of a variety of processes such as sputtering, evaporation, deposition, etc. The gate pad metal layer (not shown) can be formed to contact with a conductive material 413 that fills a through hole 412 connected to the gate metal in the active area.

[0052] include Figure 5A and Figure 5B FIG. 5 is a simplified flow chart illustrating a method 500 for manufacturing a vertical FinFET device having an integrated merged PiN Schottky (MPS) diode and an edge termination structure of the MPS diode according to an embodiment of the present disclosure. Referring to FIG. 5 , method 500 may include: providing a III-nitride substrate (510) of a first conductivity type and having a first surface and a second surface opposite to the first surface. In one embodiment, the III-nitride substrate is an n+GaN substrate. For example, a first III-nitride layer of a first conductivity type is epitaxially grown on the first surface of the III-nitride substrate at a temperature between 950 degrees Celsius and 1100 degrees Celsius, and the first III-nitride layer is characterized by a first doping concentration (e.g., having a doping concentration of about 1×10 16 Atom / cm 3In some embodiments, the first III-nitride layer is a drift layer. Method 500 also includes forming a second III-nitride epitaxial layer of the first conductivity type on the first III-nitride layer (514). In one embodiment, the second III-nitride layer is characterized by a second doping concentration that is higher than the doping concentration of the first III-nitride layer. In one embodiment, the second doping concentration is about 1×10 17 Atom / cm 3 . Method 500 also includes: forming a patterned hard mask layer (516) on the second III-nitride layer. In one embodiment, the patterned hard mask layer is formed by depositing and patterning a dielectric material. In one embodiment, the patterned hard mask layer is composed of a source metal layer on the second III-nitride layer and a patterned hard mask layer on the source metal layer, the hard mask layer being used to mask the source metal layer for subsequent metal etching to form a composite patterned hard mask layer. Method 500 also includes: forming a plurality of semiconductor fins separated by trench regions in the second III-nitride layer by etching using the patterned hard mask layer as a mask (518).

[0053] Method 500 also includes: epitaxially growing a third III-nitride epitaxial layer of a second conductivity type in the recess (520). In one embodiment, the regrown III-nitride layer is a gate layer having a second conductivity type, which is opposite to the first conductivity type of the first III-nitride layer and the second III-nitride layer. Method 500 also includes: removing a portion of the third III-nitride layer to form an isolation region and a plurality of openings in the third III-nitride epitaxial layer. The isolation region divides the device into an active region having a fin and a diode region having a plurality of openings, which are used to form an MPS diode and an edge termination structure (522). In one embodiment, removing a portion of the third III-nitride layer can be performed using an etching process (e.g., a reactive ion etching process) to form an isolation trench and a plurality of openings. In one embodiment, the isolation trench can be filled with an insulating material, such as a dielectric (silicon dioxide, silicon nitride), such as Figure 4E In another embodiment, the filled channel can be selectively doped by implanting a dopant of a conductivity type opposite to that of the third III-nitride layer into the channel to form a vertical isolation implant layer in the third III-nitride layer, such as Figure 4F shown.

[0054] The method 500 also includes: epitaxially regrowing a portion of the first III-nitride layer into the plurality of openings (524); forming a source metal layer contact to the top of the fin (526); and forming a gate metal layer (528) on the third III-nitride epitaxial layer. The gate metal layer has a first portion disposed on an active region of the third III-nitride layer including the semiconductor fin and a second portion disposed on a diode region including an edge termination structure. The method 500 also includes: forming an interlayer dielectric layer (530) covering the gate metal layer and the third III-nitride epitaxial layer. Method 500 also includes: masking and etching the interlayer dielectric layer to form through holes that expose the upper surface of the source metal layer on the second group III nitride layer and the upper surface of the second portion of the gate metal layer arranged on the opposite side of the isolation region; removing a portion of the interlayer dielectric layer by etching using the patterned hard mask layer as a mask to form through holes (532) that expose the source metal layer and the gate metal layer; and filling the through holes with a conductive material that is electrically in contact with the source metal layer (534).

[0055] The method 500 also includes forming a source pad metal layer (536) on the interlayer dielectric layer in electrical contact with the conductive material; and forming a drain metal layer (538) on the second surface of the III-nitride substrate.

[0056] It should be understood that the specific steps illustrated in FIG. 5 provide a specific method for manufacturing a vertical FinFET device with an integrated MPS diode and an edge termination structure of the MPS diode according to an embodiment of the present invention. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the above steps in a different order. Moreover, each of the steps illustrated in FIG. 5 may include multiple sub-steps, which may be performed in various orders suitable for each step. In addition, additional steps may be added or removed depending on the specific application. One of ordinary skill in the art will recognize that changes, modifications and substitutions may be made.

[0057] 6A to 6H A partial cross-sectional view of a vertical FinFET device structure having a source, a gate, a drift region, an MPS diode, and an edge termination structure during stages of a manufacturing method according to an embodiment of the present invention is illustrated. For simplicity, the method is described as providing a III-nitride structure having a III-nitride substrate 601, a first III-nitride layer 602 on the III-nitride substrate 601, a plurality of fins 603' on the first III-nitride layer 602, a patterned hard mask layer 604 on the fins 603', and a third III-nitride layer 606 between the fins, as shown in FIG. Fig. 6AAs shown (steps 510 to 520). In one embodiment, the third III-nitride layer 606 has an upper surface flush with the upper surface of the fin 603'. In one embodiment, the III-nitride substrate 601 is an n+GaN substrate, the first III-nitride layer 602 is an n-GaN layer used as a drift layer, the fin 603' includes an n GaN material as a second III-nitride layer on the first III-nitride layer 602, and the third III-nitride layer 606 is a p GaN layer. In one embodiment, the patterned hard mask layer 604 may include a metal, a metal alloy, or a metal compound (e.g., TiN).

[0058] Figure 6B A portion of the third III-nitride layer 606 is illustrated being removed by etching to form an isolation channel 607 and a plurality of openings 608 (step 522) exposing a surface of the first III-nitride layer 602. The isolation channel 607 divides the vertical FinFET device structure into an active region 640 and an MPS diode region 650 having an edge termination structure. Removing the portion of the third III-nitride layer 606 may be performed by etching using an etching mask (not shown). In one embodiment, the etching process may terminate at the interface between the third III-nitride layer 606 and the first III-nitride layer 602.

[0059] Figure 6C The epitaxially regrown portion of the material of the first III-nitride layer 602 in the opening 608 is illustrated to obtain an epitaxially regrown III-nitride layer 609 (step 524). In some embodiments, the height of the epitaxially regrown III-nitride layer 609 may be less than the height of the third III-nitride layer 606. In other embodiments, the height of the epitaxially regrown III-nitride layer 609 may be the same as the height of the third III-nitride layer 606. Those skilled in the art will recognize that variations, modifications, and substitutions are possible.

[0060] Fig.6DThe formation of a source metal layer 604a on the fin 603' and a gate metal layer 610 on a portion 610a of the third III-nitride layer disposed between the fins and on a portion 610b of the third III-nitride layer disposed between the epitaxially regrown III-nitride layer 609 (step 526) is illustrated. The source metal layer 604a may include the source metal layer in the composite hard mask 604 and may be one or more metal layers and / or alloy layers. The gate metal layer 610 may be one or more metal layers and / or alloy layers. The portion 610b creates a Schottky barrier layer with the epitaxially regrown III-nitride layer 609-1 and creates an ohmic contact with the region 606-1 of the third III-nitride layer 606. The remaining portion 606-2 provides junction extension and / or edge termination for the MPS diode.

[0061] Fig. 6E The device structure is illustrated after an interlayer dielectric layer 611 is formed (step 528) on the gate metal layer 610 (including 610a, 610b), the third semiconductor layer 606, the fin 603' and the patterned metal layer 604. In one embodiment, the interlayer dielectric layer 611 can be formed by depositing at a temperature of 300 degrees Celsius using a plasma enhanced chemical vapor deposition (PECVD) process.

[0062] Fig. 6F The device structure is illustrated after forming a via 612 extending through the interlayer dielectric layer 611. In one embodiment, a patterned photoresist is formed over the interlayer dielectric layer using a well-known photolithography process to define the location of the via over the metal layer on the upper portion of the fin and the second portion 410b of the gate metal layer in the MPS diode. After forming the via, the patterned photoresist is removed.

[0063] Figure 6G is a partial cross-sectional view illustrating the device structure after the via hole is filled with the conductive material 613.

[0064] Figure 6H is a partial cross-sectional view illustrating the device structure after the source pad metal layer 614 is formed to make electrical contact with the conductive material 613. Figure 6H As shown in FIG. 6 , a drain metal layer 615 is formed on the bottom surface of the n+ doped semiconductor substrate 601 .

[0065] include Fig. 7A and Figure 7BFIG. 7 is a simplified flow chart illustrating a method 700 for manufacturing a vertical FinFET device according to an embodiment of the present disclosure, the vertical FinFET device having an integrated merged PiN Schottky (MPS) diode connected between the source and drain of the vertical FinFET device and an edge termination structure of the MPS diode. Referring to FIG. 7 , method 700 may include: providing a III-nitride substrate (710) having a first surface and a second surface opposite to the first surface. In an embodiment, the III-nitride substrate is an n+GaN substrate. For example, a first III-nitride layer is epitaxially grown on the first surface of the III-nitride substrate at a temperature between 950 degrees Celsius and 1100 degrees Celsius, and the first III-nitride layer is characterized by a first doping concentration (e.g., having a doping concentration of about 1×10 16 Atom / cm 3 In some embodiments, the first III-nitride layer is a drift layer. Method 700 also includes forming a second III-nitride epitaxial layer on the first III-nitride layer (714). In an embodiment, the second III-nitride layer is characterized by a second doping concentration that is higher than the doping concentration of the first III-nitride layer. In an embodiment, the second doping concentration is about 1×10 17 Atom / cm 3 . In an embodiment, a region having a gradient doping concentration is formed between the first III-nitride layer and the constant doping concentration region in the second III-nitride layer. In some embodiments, the second III-nitride epitaxial layer is a fin layer. Method 700 also includes: forming a patterned hard mask layer (716) on the second III-nitride layer. In one embodiment, the patterned hard mask layer is formed by depositing and patterning a dielectric material. In one embodiment, the patterned hard mask layer is composed of a source metal layer on the second III-nitride layer and a patterned hard mask layer formed on the source metal layer, the hard mask layer being used as a mask to etch the source metal layer, which produces a composite patterned hard mask layer. Method 700 also includes: using the patterned hard mask layer as a mask to form a plurality of semiconductor fins separated by groove regions in the second III-nitride layer (718).

[0066] Method 700 also includes: regrowing a third III-nitride epitaxial layer (720) in the trench region. In an embodiment, the regrown III-nitride layer is a gate layer and is characterized by a conductivity type opposite to the conductivity type of the first III-nitride layer and the second III-nitride layer. Method 700 also includes: forming a contact to the top of the n-type fin (722). In an embodiment, the contact is self-aligned. In an embodiment, the source metal layer of the patterned hard mask layer is in electrical contact with the top of the n-type fin. Method 700 also includes: forming an isolation region (724) in the third III-nitride epitaxial layer. In an embodiment, the isolation region can be formed by performing an etching process (e.g., a reactive ion etching process) to form an isolation trench. In one embodiment, the isolation trench can be filled with an insulating material, such as a dielectric (silicon dioxide, silicon nitride). Reference Figure 1 , the isolation channel may be an isolation region 107 surrounding the fin 103. In another embodiment, the method 700 may include: selectively implanting an n-type dopant into the isolation channel to form a vertical isolation implant layer in the third III-nitride layer. In another embodiment, the method 700 may include: selectively implanting nitrogen, argon, or helium to form a well that neutralizes the p-GaN doping and forms an implanted isolation channel. In another embodiment, the method 700 may include: selectively treating the third III-nitride epitaxial layer with a plasma (e.g., a hydrogen plasma) to locally passivate the dopant in the third III-nitride epitaxial layer. In yet another embodiment, the isolation region may include a suspended fin, i.e., the suspended fin is not connected to a source disk layer to be formed in a subsequent process step.

[0067] The method 700 further includes forming a gate metal layer on the third III-nitride epitaxial layer (726). Figure 1, the gate metal layer has a first portion 110a arranged on a first portion of the third III-nitride layer and a second portion 110b arranged on a second portion of the third III-nitride layer, the first portion of the third III-nitride layer is on one side of the isolation region 107 and surrounds the semiconductor fin, and the second portion of the third III-nitride layer is on the opposite side of the isolation region and does not have a semiconductor fin. Method 700 also includes: forming an interlayer dielectric layer (e.g., interlayer dielectric layer 111) (728) covering the source metal layer, the gate metal layer, and the third III-nitride epitaxial layer. Method 700 also includes: masking and etching the interlayer dielectric layer to form through holes, which expose the upper surface of the source metal layer on the second III-nitride layer and the upper surface of the second portion of the gate metal layer arranged on the opposite side of the isolation region. Thus, method 700 includes: etching the interlayer dielectric layer using the patterned hard mask layer as a mask to form through holes (730) exposing the source metal layer (source metal layer 104 on the fin 103) and the gate metal layer, and filling the through holes with a conductive material to form a plurality of vias (732) contacting the source metal layer and the gate metal layer.

[0068] Method 700 also includes: forming a source disk metal layer on the interlayer dielectric layer, the source disk metal layer electrically contacting the conductive material contacting the source metal layer, and forming a gate disk metal layer on the interlayer dielectric, the gate disk metal layer electrically contacting the conductive material contacting the gate metal layer (734); and forming a drain metal layer (736) on the second surface of the III-nitride substrate.

[0069] It should be understood that the specific steps illustrated in FIG. 7 provide a specific method for manufacturing a vertical FinFET device having an integrated merged PiN Schottky (MPS) diode connected between the source and drain of the vertical FinFET device and an edge termination structure of the MPS diode according to an embodiment of the present invention. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the above steps in a different order. Moreover, each of the steps illustrated in FIG. 7 may include multiple sub-steps, which may be performed in various orders suitable for each step. In addition, additional steps may be added or removed depending on the specific application. One of ordinary skill in the art will recognize that changes, modifications, and substitutions may be made.

[0070] FIG. 8A to FIG. 8L A partial cross-sectional view of a vertical FinFET device structure having a source, gate, drift region, MPS diode, and edge termination structure during stages of a fabrication method according to an embodiment of the present disclosure is illustrated. Fig. 8A801, and n-doped semiconductor layer 803 epitaxially grown on n-doped semiconductor substrate 801. In one embodiment, n-doped semiconductor layer 802 forms a drift region of the device and is doped with an n-type dopant such as silicon. In one embodiment, a patterned hard mask layer (804) is formed on n-doped semiconductor layer 803. In one embodiment, a metal layer (not shown) is formed on n-doped semiconductor layer 803, and a hard mask layer (not shown) is formed on the metal layer and patterned, and an etching process is performed on the metal layer using the patterned hard mask layer as a mask to obtain a composite patterned hard mask including the patterned metal layer. In one embodiment, the patterned hard mask layer may include silicon dioxide or silicon nitride. In one embodiment, the patterned hard mask layer may be formed by PECVD. In another embodiment, the patterned hard mask layer may be formed using RIE with a F-based chemistry. In one embodiment, the n+ doped semiconductor substrate may be an n+ doped III-nitride substrate, wherein the n-type dopant is about 5×10 17 Atom / cm 3 To about 1×10 19 Atom / cm 3 In one embodiment, the drift region may have a value within the range of about 1×10 16 to 1×10 17 Atom / cm 3 In one embodiment, the n-doped semiconductor layer 803 may have a net n-type doping concentration in the range of about 1×10 17 Up to 1×10 18 Atom / cm 3 In one embodiment, the metal layer may include TiN. These steps correspond to steps 710 to 716 of the method 700 shown in FIG. 7 .

[0071] Figure 8B 805 is a partial cross-sectional view of the device structure after performing an etching process to obtain a plurality of semiconductor fins 803' separated by trench regions 805 (step 718). Note that after the etching process, the bottom of the trench between the fins may have a thickness similar to that of the fins. Figure 8BShapes different from the shapes shown. Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments of the invention and intermediate structures. For clarity, the thicknesses of layers and regions in the drawings may not be drawn to scale. Variations in the shapes of the figures as a result of, for example, manufacturing techniques and / or tolerances are expected. Thus, embodiments of the invention should not be construed as limited to the specific shapes of the regions illustrated herein, but rather include deviations in shape that result from manufacturing. In the following figures, the bottom of the fin is shown as having a 90 degree angle with the surface of the drift region, i.e., the fin is shown as having a cross-sectional rectangular shape. It is understood that the bottom of the fin may have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the invention. In one embodiment, the depth of the trench region 805 may be different in different regions of the device. In one embodiment, the region where the MPS diode is subsequently formed (e.g., see Fig.8D ) can be greater or less than the depth of the trench region 805 in the active region of the vertical FET. In one embodiment, the width of the fin 803" in the area where the MPS diode is subsequently formed can be wider than the fin 803' in the active region of the FinFET device.

[0072] In one embodiment, after forming the trench region 805 , a cleaning process and / or a pre-cleaning process is performed using a TMAH solution.

[0073] Figure 8C 8 is a partial cross-sectional view illustrating the device structure after epitaxially regrowing the third semiconductor layer 806 in the trench region (step 720). In one embodiment, the third semiconductor layer 806 may include a p-type III-nitride layer that is epitaxially grown in the trench region and uniformly grown to a thickness that is substantially coplanar with the bottom of the hard mask layer 804. In one embodiment, the p-type III-nitride layer may be formed with about 1×10 19 Atom / cm 3 In one embodiment, the annealing process may be performed to activate Mg doping atoms in an amount greater than 10 wt %.

[0074] Fig.8D 8 is a partial cross-sectional view illustrating a device structure after an isolation region 807 is formed in the third semiconductor layer 806 (step 724). Fig.8D The isolation region 807 divides the device structure into an active region 840 and an MPS diode region 850. In one embodiment, the isolation region 807 may be a channel formed in the third semiconductor layer 806, which extends into a portion of the second semiconductor layer 802, such as Fig.8DAs shown. The channel may have a width smaller than the width of the fin 803'. In one embodiment, the isolation region 807 may be a channel filled with a dielectric material 808, such as Fig. 8E In one embodiment, the isolation region 807 may be an n-type doped region 809, such as Fig.8F In one embodiment, the isolation region 807 may be a suspended fin 803f, i.e., the fin 803f is not connected to a subsequently formed source pad metal as further described below. Figure 8G shown.

[0075] Figure 8H is a partial cross-sectional view illustrating the device structure after a source metal layer 804a is formed on the fin (step 722) and a gate metal layer 810 is formed on the third semiconductor layer 806 (step 726). The gate metal layer 810 has a first portion 810a disposed on a portion of the third semiconductor layer 806 in the active region and a second portion 810b disposed on a portion of the third semiconductor layer 806 in the MPS diode region. The source metal layer 804a may include a source metal layer in the composite hard mask 804 and may be one or more metal layers and / or alloy layers. The gate metal layer 810 may be one or more metal layers and / or alloy layers. Portion 810b creates a Schottky barrier layer with the fin 803″ and creates an ohmic contact with the third III-nitride layer 806. Note that in Figure 8H 8, the isolation region is represented by a trench 807, however, it is understood that the isolation region can be one of a trench, a trench filled with a dielectric material, an n-type doped region, a suspended fin, a well-rich region that is ion-implanted to neutralize the conduction, or a plasma-treated region where the p-type dopant has been passivated. In one embodiment, the MPS diode region includes a portion 806a of the gate region 806 that forms an anode of the MPS diode and a portion 802c of the second semiconductor layer 802 that forms a cathode of the MPS diode. In one embodiment, the portion 802c that forms the cathode of the body diode is thinner than the semiconductor layer 802 below the active region.

[0076] Fig.8I 8 is a partial cross-sectional view illustrating a device structure after forming an interlayer dielectric layer 811 (step 728) on the gate metal layer 810, the third semiconductor layer 806, and the fin 803' including the patterned metal layer 804. In one embodiment, the interlayer dielectric layer 811 can be formed by depositing at a temperature of 300 degrees Celsius using a plasma enhanced chemical vapor deposition (PECVD) process.

[0077] Figure 8J8 is a partial cross-sectional view illustrating a device structure after forming a through hole (via) 812 in the interlayer dielectric layer. For example, a patterned photoresist is formed over the interlayer dielectric layer using a photolithography process to define the location of the through hole (via) over the metal layer on the upper portion of the fin in the MPS diode region and the second portion 810b of the gate metal layer. After forming the via, the patterned photoresist is removed.

[0078] Figure 8K is a partial cross-sectional view illustrating the device structure after the via hole (through hole) is filled with the conductive material 813.

[0079] Figure 8L 8 is a partial cross-sectional view illustrating the device structure after the source pad metal layer 814 is formed to make electrical contact with the conductive material 813. Figure 8L , a drain metal layer 815 is formed on the bottom surface of the n+ doped semiconductor substrate 801. The anode 806a of the MPS diode is connected to the source pad metal layer 814, and the cathode 802c of the MPS diode is connected to the drain metal layer 815. Therefore, the anode is connected to the source of the vertical FinFET device, and the cathode is connected to the drain of the vertical FinFET device. The source pad metal layer can be formed using any of a variety of processes such as sputtering, evaporation, deposition, etc. The drain metal layer can be formed using any of a variety of processes such as sputtering, evaporation, deposition, etc. A gate pad metal layer (not shown) can be formed to contact a conductive material 813 that fills a through hole 812 connected to a gate metal in an active area.

[0080] It should be understood that the appended claims are not limited to the precise configuration illustrated in the drawings. Those skilled in the art will recognize that various modifications, substitutions and changes may be made to the arrangements and steps of the above-described methods and apparatus without departing from the scope of the present invention.

Claims

1. A vertical junction field effect transistor (JFET), comprising: substrate; an active region including a plurality of semiconductor fins; a source metal layer electrically coupled to surfaces of the plurality of semiconductor fins; a source metal disk layer coupled to the plurality of semiconductor fins through the source metal layer; a gate region surrounding the plurality of semiconductor fins; as well as A body diode surrounds the gate region.

2. The vertical JFET according to claim 1, wherein: Also included is an isolation region disposed between the active region and the body diode.

3. The vertical JFET according to claim 2, wherein: The isolation region includes a channel.

4. The vertical JFET of claim 2, wherein: The isolation region includes a fin that is not electrically coupled to the source metal pad layer.

5. The vertical JFET of claim 2, wherein: The isolation region includes an n-type doped region.

6. The vertical JFET of claim 1, wherein: The body diode includes an anode coupled to the source metal layer and a cathode coupled to the drain of the JFET.

7. The vertical JFET of claim 1, wherein: Also included is a drift region coupled to the substrate, wherein the plurality of semiconductor fins are coupled to the drift region.

8. The vertical JFET of claim 7, wherein: The substrate includes an n+GaN layer; The drift region includes an n-GaN layer; The plurality of semiconductor fins include an n GaN layer; the body diode comprising an anode on the drift region and a cathode formed by the drift region, wherein the anode comprises a p GaN layer and is coupled to the source metal layer, and wherein the cathode is coupled to a drain of the JFET; and An edge termination region includes the p GaN layer and surrounds the body diode.

9. The vertical JFET of claim 1, wherein: The body diode is one of a PN junction diode, a Schottky diode, or a Merged PIN Schottky (MPS) diode.

10. A method of manufacturing a vertical junction field effect transistor (JFET), the method comprising: providing a semiconductor substrate of a first conductivity type and having a first surface and a second surface; forming a plurality of fins coupled to the semiconductor substrate; forming a source metal layer electrically coupled to surfaces of the plurality of fins; forming a source metal pad layer coupled to the plurality of fins through the source metal layer; forming a gate layer of a second conductivity type opposite to the first conductivity type surrounding the plurality of fins; as well as at the same time: forming an isolation region surrounding the plurality of fins; as well as A body diode region is formed surrounding the isolation region.

11. The method according to claim 10, wherein: Forming the plurality of fins includes: forming a first semiconductor epitaxial layer of the first conductivity type on the first surface of the semiconductor substrate; forming a second semiconductor epitaxial layer of the first conductivity type on the first semiconductor epitaxial layer; forming a first patterned hard mask layer on the second semiconductor epitaxial layer; Using the first patterned hard mask layer as a mask to etch a portion of the second semiconductor epitaxial layer to form the plurality of fins on the first semiconductor epitaxial layer and a trench region surrounding the plurality of fins; and The trench region is filled with the gate layer.

12. The method according to claim 11, wherein: Also includes: removing the first patterned hard mask layer; forming a second patterned hard mask layer covering the plurality of fins while exposing a surface portion of the gate layer; as well as The exposed surface portion of the gate layer is etched using the second patterned hard mask layer as a mask to form a second channel configured as the isolation region.

13. The method according to claim 11, wherein: Also includes: removing the first patterned hard mask layer; forming a second patterned hard mask layer covering the plurality of fins while exposing a surface portion of the gate layer; as well as Ion implantation is performed to implant n-type impurities into the exposed surface portion of the gate layer to form an n-type doping region configured as the isolation region.

14. The method according to claim 11, wherein: Also includes: forming a metal layer on upper portions of the plurality of fins, an upper portion of the gate layer, and an upper portion of the body diode region; forming an interlayer dielectric layer on the metal layer, the gate layer and the isolation region; forming a second patterned hard mask layer on the interlayer dielectric layer on the metal layer; etching the interlayer dielectric layer using the second patterned hard mask layer as a mask to form a plurality of vias exposing a surface portion of the metal layer on the upper portions of the plurality of fins and on the upper portion of the body diode region; as well as The plurality of through holes are filled with a conductive material to form a plurality of vias.

15. The method according to claim 14, wherein: Also includes: A drain metal layer is formed on the second surface of the semiconductor substrate, wherein the source metal layer is coupled to the plurality of vias.

16. The method according to claim 15, wherein: Forming the gate layer includes: A third semiconductor layer of the second conductivity type is epitaxially grown on the second semiconductor epitaxial layer, the third semiconductor layer having a first portion surrounding the plurality of fins and a second portion forming a portion of the body diode region on an opposite side of the isolation region.

17. The method according to claim 16, wherein: The second portion of the third semiconductor layer forms an anode of a body diode, and a portion of the first semiconductor epitaxial layer below the second portion of the third semiconductor layer forms a cathode of the body diode, the anode of the body diode is coupled to the source metal layer, and the cathode of the body diode is coupled to the drain metal layer.

18. A semiconductor device comprising: A substrate comprising an n+GaN layer; a drift layer coupled to the substrate and comprising an n-GaN layer; a plurality of fins comprising n GaN material and coupled to the drift layer; a source metal layer electrically coupled to surfaces of the plurality of fins; a source metal disk layer coupled to the plurality of fins through the source metal layer; a gate layer comprising a p GaN material and surrounding the plurality of fins; an integrated diode body surrounding the plurality of fins; as well as An isolation region is disposed between the plurality of fins and the integrated diode body.

19. The semiconductor device according to claim 18, wherein: The integrated diode body is one of a PN diode, a Schottky diode, or a merged PIN Schottky diode.

20. The semiconductor device according to claim 18, wherein The isolation region includes one of a channel, a suspended fin, or an n-type doped region.

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