Integrated circuit and capacitive transducer bias circuit

Abstract

The present invention relates to integrated circuits and capacitive transducer bias circuits. The present disclosure describes an apparatus and method for providing a DC bias voltage in a microphone assembly. Specifically, one implementation of such an apparatus can be implemented on an integrated circuit including a direct current (DC) bias circuit. The DC bias circuit can be coupled to a transducer and configured to supply a DC bias signal to the transducer. The DC bias circuit includes a multi-stage charge pump and a low pass filter (LPF) circuit. The multi-stage charge pump includes a transistor fabricated with deep trench isolation (DTI).

Description

Technical Field

[0001] The present disclosure relates generally to microphone assemblies, such as, but not limited to, microphone assemblies having microelectromechanical systems (MEMS) transducers and circuitry therefor. Background Art

[0002] Microphones with transducers that convert sound into electrical signals that are conditioned or processed by an integrated circuit are often integrated with cellular phones, personal computers, and Internet of Things (IoT) devices, among other host devices. Some of these transducers require a direct current (DC) bias voltage to operate. Increased bias voltages are needed to enable continued advancement of transducer technology. Summary of the invention

[0003] One aspect of the present invention relates to an integrated circuit, which is used to be connected to a capacitive micro-electromechanical system transducer through an interface and adjust the signal output by the capacitive micro-electromechanical system transducer, the integrated circuit comprising: a signal conditioning circuit, the input end of the signal conditioning circuit can be electrically connected to the output end of the capacitive micro-electromechanical system transducer, the signal conditioning circuit has an output end; a transducer bias circuit, the transducer bias circuit comprising: a charge pump circuit, the charge pump circuit comprising a plurality of cascaded charge pump stages between the input end and the output end of the charge pump circuit, each charge pump stage comprising a capacitor connected to a first semiconductor device, the first semiconductor device is located in a first well region, the first well region is embedded in a substrate and doped with P-type or N-type material, a first deep trench isolation barrier is arranged around the first well region to insulate at least a portion of the first well region from the substrate; a high-voltage electrostatic discharge protection circuit, the high-voltage electrostatic discharge protection circuit is connected to the output end of the charge pump circuit; and a filter, the filter is connected to the output end of the charge pump circuit.

[0004] Another aspect of the present invention relates to a capacitive transducer bias circuit, which includes: a charge pump circuit, the charge pump circuit includes a plurality of cascaded charge pump stages between an input end and an output end, the plurality of cascaded charge pump stages include a plurality of semiconductor devices, each semiconductor device is located in a P-well region or an N-well region of a substrate, the P-well region or the N-well region is electrically insulated from the substrate along the perimeter of the P-well region or the N-well region by a deep trench isolation barrier; and the plurality of cascaded charge pump stages are configured to output a DC voltage of at least 60 volts; a high-voltage electrostatic discharge protection circuit, the high-voltage electrostatic discharge protection circuit is connected to the output end of the charge pump circuit; and a filter, the filter is connected to the output end of the charge pump circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The objects, features and advantages of the present disclosure will become more fully apparent from the following description and appended claims taken in conjunction with the accompanying drawings. The drawings depict only typical embodiments and therefore are not to be considered limiting of the scope of the present disclosure, the description of which includes additional specificity and details.

[0006] Figure 1 is a cross-sectional view of a microphone assembly.

[0007] Figure 2 is a schematic diagram of the audio circuit.

[0008] Figure 3 is a schematic diagram of an example of a charge pump stage.

[0009] Figure 4 is a schematic diagram of an example of a low-pass filter circuit.

[0010] Figure 5 is a schematic diagram of an example of an electrostatic discharge circuit.

[0011] Figure 6 is a side cross-sectional view of a first transistor process including deep trench isolation (DTI).

[0012] Figure 7 Is from Figure 6 A top view of the substrate.

[0013] Figure 8 yes Figure 6 Including from Figure 3 A top view of a substrate of multiple transistors of a charge pump stage.

[0014] Fig. 9 is a side cross-sectional view of a transistor process including DTI and buried insulating layer.

[0015] Fig.10 is a side cross-sectional view of a transistor process including DTI and buried well.

[0016] Fig.11 is a side cross-sectional view of a transistor process including shared DTI.

[0017] Fig.12 is a top view of a substrate including a transistor process with shared DTI.

[0018] Fig.13 is a side cross-sectional view of a transistor process including multiple wells within a DTI ring.

[0019] Fig.14 is a top view of a substrate of a transistor process including multiple wells within a DTI ring. DETAILED DESCRIPTION

[0020] The present disclosure describes microphone assemblies and other devices and methods thereof, which microphone assemblies and other devices include a DC bias circuit having a deep trench isolation (DTI) and an output end connected to the input end of a transducer of a microphone or other device. There is an increasing need for microphone assemblies with smaller and smaller footprints. A microphone assembly including a small microelectromechanical (MEMS) module (e.g., a transducer) with low mechanical compliance can allow the MEMS module to exhibit desired characteristics (such as force balance and / or extreme miniaturization). However, low mechanical compliance may limit the sensitivity and signal-to-noise ratio (SNR) of the microphone assembly. In order to improve the sensitivity and SNR, the DC bias voltage can be increased so that the electric field in the microphone is also increased. However, increasing the DC bias voltage is limited by the breakdown voltage of the transistors in the DC bias circuit and the available space in the microphone assembly. Therefore, the present disclosure describes a DC bias circuit that can output a voltage in excess of 50 volts while maintaining a small footprint.

[0021] The DC bias circuit may include a plurality of transistors. Each of the transistors is formed, arranged or generated in an N-well or a P-well in a substrate (e.g., a P-type substrate). The breakdown voltage of the transistor (e.g., the breakdown voltage of the N-well and the P-well between the substrate) imposes a limit on how high a voltage the charge pump can be designed to generate. The limit is imposed because a voltage higher than the breakdown voltage will result in excessive leakage to the substrate, which will reduce the output voltage of the charge pump and / or damage the circuit on the integrated circuit. Deep trench isolation achieves better horizontal and vertical insulation between the N-well and the P-well and increases the breakdown voltage. The apparatus and method disclosed herein can be used to increase the DC bias voltage of the DC bias circuit to a voltage higher than 50 volts in order to improve the sensitivity and signal-to-noise ratio (SNR) of a microphone assembly having a transducer with low mechanical compliance.

[0022] Figure 1 1 is a cross-sectional view of a microphone assembly 100 in which a DC bias circuit with DTI is implemented. The microphone assembly 100 generally includes an electroacoustic transducer 102, which is coupled to a circuit 103 disposed within a housing 110. The transducer is configured to generate an electrical signal in response to sensing acoustic activity. The transducer may be a capacitive device, a piezoelectric device, or other transducer device manufactured using a microelectromechanical system (MEMS) or other known or future technology. The circuit may be implemented by one or more integrated circuits (e.g., an application specific integrated circuit (ASIC) having analog and digital circuits and a discrete discrete digital signal processor (DSP) that performs audio processing (e.g., keyword / command detection, noise suppression, authentication, etc.)).

[0023] The housing 110 includes a substrate 116 and a cover 118 coupled to an upper surface 120 of the substrate 116. The cover 118 is secured to the substrate 116 along a perimeter of the cover 118. The cover 118 and the substrate 116 together define an interior portion 122 (e.g., a cavity, etc.). The cover 118 may include an atmospheric equalization vent 126 (e.g., an opening, a hole, etc.) that provides fluid communication between the environment surrounding the housing 110 and the interior portion 122. The atmospheric equalization vent 126 prevents damage to the housing 110 and / or other components of the microphone assembly 110 that may otherwise occur due to extreme temperature and / or pressure fluctuations in the environment surrounding the microphone assembly 110.

[0024] Substrate 116 includes an acoustic port 128 that is aligned with MEMS transducer 100 such that MEMS transducer 100 is exposed to pressure changes through acoustic port 128. In various exemplary embodiments, the relative position between MEMS transducer 100 and acoustic port 128 may be different. For example, acoustic port 128 may be formed in cover 118 instead of substrate 116, and transducer 102 may be adjacent to acoustic port 128. In these cases, transducer 102 may be aligned with acoustic port 128. Figure 1 The opposite is true of the situation shown in .

[0025] The transducer 102 generates an electrical signal based on a pressure change transmitted to the transducer 102 through the acoustic port 128 (e.g., through the movement or displacement of the diaphragm 108). The pressure change can be a change in the surrounding atmospheric pressure (e.g., the pressure of the environment surrounding the microphone assembly 110) and / or a pressure change caused by an acoustic stimulus such as sound. The circuit 103 is connected to the transducer 102 via leads and traces 130 to form an electrical connection between them. The circuit 103 is configured to receive and process the signal generated by the transducer 102. The signal from the transducer 102 can be processed by the circuit 103 into an output signal representing the sensed acoustic activity. The circuit 103 may include a signal conditioning circuit, a clock circuit, a direct current (DC) bias circuit, one or more low-pass filters, and a controller, examples of which are described below. In some embodiments, the DC bias is applied to the first terminal of the transducer from the circuit 103 via the leads and traces 130. In some implementations, the signal conditioning circuit is configured to condition the electrical signal obtained from the transducer 102 when the circuit 103 is coupled to the transducer 102 .

[0026] The housing 110 may include an acoustic port 128 and an external device interface 113 having contacts (e.g., for power, data, ground, control, external signals, etc.) connected to the circuit 103. The external device interface 113 is configured for surface or other mounting to a host device (e.g., by reflow soldering). In some embodiments, the host device may be an amplifying device configured to use the electrical signal generated by the transducer 102 to amplify the audio signal and extend the audio signal to a distant place. In some embodiments, the host device may include a personal computer, a cellular phone, a mobile device, a headset, a headphone device, and / or a hearing aid device. In some implementations, the circuit 103 includes acoustic signal and atmospheric signal processing circuits and / or software to interpret the electrical signal from the MEMS transducer 102.

[0027] Figure 2 is a schematic diagram showing an audio circuit 200. The audio circuit 200 generally includes a DC bias circuit 201, a transducer 102, and an amplifier circuit 203. In some embodiments, the DC bias circuit 201 and the amplifier circuit 203 are integrated into the circuit 103. In some embodiments, the amplifier circuit 203 can be part of a host device. In some embodiments, the amplifier circuit 203 can be a signal conditioning circuit that includes a buffer, a high pass filter, and / or an analog-to-digital converter (e.g., in a digital microphone).

[0028] The DC bias circuit 201 is arranged to provide a DC bias signal to the converter 102. In some embodiments, the DC bias circuit 201 includes a multi-stage charge pump circuit 210 and a low pass filter (LPF) circuit 211. In some embodiments, the DC bias circuit 201 also includes an electrostatic discharge (ESD) circuit 212, which is coupled to the output terminal of the DC bias circuit 201 and a ground (e.g., a second voltage) and is configured to discharge static charge.

[0029] In some embodiments, the DC bias circuit 201 may include other types of DC amplification circuits in addition to or in place of the multi-stage charge pump circuit 210. The multi-stage charge pump 210 is configured to convert a DC voltage into an output DC voltage of a higher magnitude. For example, the multi-stage charge pump circuit 210 may have an input of approximately 5 volts from a battery or other power source, and the output of the multi-stage charge pump circuit 210 may have an output of 50 volts or more. In some embodiments, the increase in DC voltage from the input to the output of the multi-stage charge pump circuit 210 is based on the charge pump stage CP. 1-Nor other DC amplification circuits within the multi-stage charge pump circuit 210. The LPF 211 is arranged to receive a signal from the output of the multi-stage charge pump circuit 210 and output a DC bias signal to a first terminal of the transducer 102. In some embodiments where the mechanical compliance of the transducer 102 is small, the output voltage of the DC bias circuit 201 can be increased to provide the microphone assembly with improved sensitivity and SNR.

[0030] The transducer 102 is arranged to receive a DC bias signal from a DC bias circuit 201 and generate an electrical signal indicative of the sensed acoustic energy. The electrical signal is generated with the DC bias signal as a reference voltage. For example, the DC bias signal may be 55 volts (V), and the electrical signal generated by the transducer 102 may be a signal in the range of a few millivolts (mV) to several hundred millivolts (e.g., 0.001 mV-100 mV). The electrical signal is then provided to an amplifier circuit 203 (or circuit 103). As an example, the electrical signal may be amplified by the amplifier circuit 203 and passed on for further processing by an analog-to-digital converter, such as to create a digital representation of the electrical signal and the acoustic activity represented by the electrical signal.

[0031] Figure 3 is a schematic diagram of an example of a charge pump stage 300. In some embodiments, the charge pump stage 300 may be implemented as Figure 2 The DC bias circuit 201 has multiple charge pump stages CP 1-N In some embodiments, the charge pump stage may be implemented using one or more capacitors and one or more semiconductor devices. In some embodiments, the one or more semiconductor devices may include one or more diodes and / or one or more transistors.

[0032] The charge pump stage 300 includes an input terminal v in , a plurality of transistors M 1-6 , the first capacitor C1, the second capacitor C2 and the output terminal v out The charge pump stage 300 is configured to charge the battery via the first terminal and the second terminal The clock circuit is used to drive the charge pump stage 300. In some embodiments, the clock circuit generates a two-phase non-overlapping signal, one of which is configured to be supplied to the first terminal. and the second phase is configured to supply to the second terminal In other embodiments, more than two phases may be implemented. The charge pump stage 300 has an input terminal v in receives an input DC voltage at the output terminal v outIn some implementations, the output terminal v of the charge pump stage 300 is out can be connected to the input terminal of the second charge pump stage 300 so that the charge pump stages are cascaded and the output DC voltage of the plurality of charge pump stages can reach a higher voltage.

[0033] Figure 4 is a schematic diagram of an example of an LPF circuit 400. In some embodiments, the LPF circuit 400 can be implemented as Figure 2 It will be appreciated that in other embodiments, other types or forms of low pass filters or sub-circuits thereof may be implemented in addition to or in place of the LPF circuit 400.

[0034] The LPF circuit 400 includes an input terminal 401 configured to be coupled to an output terminal of the multi-stage charge pump circuit and an output terminal 402 configured to be coupled to a first terminal of the transducer 102. The LPF circuit 400 is configured to provide a DC bias voltage v to the transducer 102. bias . The LPF circuit 400 may have a first LPF stage 410 and a second LPF stage 411. In some embodiments, the LPF circuit 400 may have only one LPF stage. In some embodiments, the LPF circuit 400 may have more than two LPF stages. The LPF circuit 400 includes a first capacitor C1 coupled between an input terminal 401 and ground (e.g., a second voltage), a second capacitor C2 coupled between a connection of the first LPF stage 410 and the second LPF stage 411 and ground (e.g., a second voltage), and a third capacitor coupled between an output terminal 402 and ground (e.g., a second voltage). In some embodiments, the capacitor C1 may be selected based on a desired, predetermined cutoff frequency of the LPF circuit 400. 1-3 The value of .

[0035] The first LPF stage 410 includes a transistor 480 connected in parallel with a pair of reverse polarity connected diodes 481. The reverse polarity connected diode 481 includes a first diode, the anode terminal of the first diode is connected to the cathode terminal of the second diode, and the cathode terminal of the first diode is connected to the anode terminal of the second diode. The transistor 480 has a control terminal (e.g., a gate terminal) connected to the second terminal 483 of the first LPF stage 410 and the first terminal of the transistor 480. The second LPF stage 411 includes a transistor 490 connected in parallel with a pair of reverse polarity connected diodes 491. The reverse polarity connected diode 491 includes a first diode, the anode terminal of the first diode is connected to the cathode terminal of the second diode, and the cathode terminal of the first diode is connected to the anode terminal of the second diode. The transistor 490 has a control terminal (e.g., a gate terminal) connected to the output 402 of the LPF circuit 400 and the first terminal of the transistor 490.

[0036] Figure 5 is a schematic diagram of an example of an electrostatic discharge (ESD) circuit 500. In some embodiments, the ESD circuit 500 can be implemented as Figure 2 It will be appreciated that in other embodiments, other types or forms of ESD circuits or sub-circuits thereof may be implemented in addition to or in place of ESD circuit 500.

[0037] The ESD circuit 500 includes a first terminal 501 configured to be connected to the output of the multi-stage charge pump circuit and a second terminal 502 configured to be connected to ground (e.g., a second voltage). The ESD circuit 500 may include a plurality of transistors 510a-510d stacked between the first terminal 502 and the ground. A plurality of transistors 510a-510d may be stacked by connecting each of the plurality of transistors 510a-510d in series between the first terminal 501 and the second terminal 502. In some embodiments, each of the plurality of transistors has a control terminal (e.g., a gate terminal) connected to a corresponding first terminal. In some embodiments, each of the plurality of transistors 510a-510d is a PMOS transistor. In some embodiments, each of the plurality of transistors 510a-510d includes a signal inversion (e.g., a NOT gate) on a corresponding control terminal. In this way, when the voltage on the first terminal drops by a predetermined voltage or is lower than a predetermined voltage, each of the plurality of transistors 510a-510d of the ESD circuit 500 begins to conduct, thereby discharging the first terminal 501. In some embodiments, each transistor in the plurality of transistors 510a-510d is an NMOS transistor. The number of the plurality of transistors 510a-510d used or stacked together will depend on the specific implementation and design of the DC bias circuit. As described herein, each transistor in the plurality of transistors 510a-510d can be manufactured in various P-wells or N-wells. In some embodiments, the plurality of transistors 510a-510d is manufactured to have a DTI around each transistor (e.g., or around each N-well or P-well) so that the transistor has a breakdown voltage sufficient to ensure that the ESD circuit 500 does not break down or does not generate leakage current when the microphone assembly is operating.

[0038] Now, overall reference Figures 6 to 14 , depicting several different views of multiple transistor processes. Figure 6 , Fig. 9 , Fig.11 and Fig.13 A side cross-sectional view of the corresponding transistor process is depicted. Figures 7 and 8 , Fig.10 , Fig.12 and Fig.14 A top view of the corresponding transistor process is depicted. Figure 3 The example charge pump stage 300 discussed is similar to Figures 6 to 14 The description is cited together with Figure 6 , Fig. 9 and Fig.11 In some embodiments, the P-well region may refer to a region doped with a P-type material embedded in a substrate, and the N-well region may refer to a region doped with an N-type material embedded in a substrate.

[0039] Reference now Figure 6 , depicting a transistor process 600 with deep trench isolation (DTI). The transistor process 600 with DTI includes a P-type substrate 601 with a P-well 602 and an N-well 603. A first transistor M1 having a first N+ pad 620 and a second N+ pad 621 is formed in the P-well 602, and the first N+ pad 620 and the second N+ pad 621 are arranged at a certain distance in the P-well 602 and connected by a polysilicon (poly) substrate 622. A second transistor M3 having a first P+ pad 630 and a second P+ pad 631 is formed in the N-well 603, and the first P+ pad 630 and the second P+ pad 631 are arranged at a certain distance in the N-well 603 and connected by a polysilicon substrate 633. Alternatively or additionally, the first transistor M1 and the second transistor M3 can be configured such that the second transistor M3 is formed in the P-well 602, and the first transistor M1 is formed in the N-well. In addition, in some embodiments, the P-type substrate 601 can be implemented as an N-type substrate. Figure 6 The explanation of the various components is intended to be illustrative, and in alternative embodiments, other doping configurations and additional or fewer configurations of the various components are possible. The P+ pad and the N+ pad may refer to a range or region within a corresponding N-well region and a P-well region doped in a P-type material or an N-type material, respectively.

[0040] exist Figure 6 In the embodiment, the transistor process 600 with deep trench isolation (DTI) further includes a first deep N-well 640, a second deep N-well 641, a first DTI 643, and a second DTI 644. The first deep N-well 640 is adjacent to the P-well 602 and is located between one side of the P-well 602 and the P-type substrate 601. The first DTI 643 is disposed around the perimeter of the P-well 602 and is located between the P-well 602 and the P-type substrate 601. In some embodiments, the first DTI 643 is also disposed around the perimeter of the first deep N-well 640, so that the perimeter of the first deep N-well 640 is separated from the P-type substrate 601 by the first DTI 643. The second deep N-well 641 is adjacent to the N-well 603 and is located between one side of the N-well 603 and the P-type substrate 601. The second DTI 644 is disposed around the perimeter of the N-well 603 and is located between the N-well 603 and the P-type substrate 601. In some embodiments, the second DTI 644 is also disposed around the perimeter of the second deep N well 641 , such that the perimeter of the first deep N well 640 is separated from the P-type substrate 601 by the second DTI 644 .

[0041] In other words, the first DTI 643 is disposed around or near the first transistor M1, and the second DTI 644 is disposed around or near the second transistor M2. The first DTI 643 prevents the voltage on the first transistor M1 (e.g., the voltage on the first pad 620 or the second pad 621) from breaking down to the P-type substrate 601. The second DTI 644 prevents the voltage on the second transistor M2 (e.g., the voltage on the first pad 630 or the second pad 631) from breaking down to the P-type substrate 601. In other words, the first DTI 643 and the second DTI 644 increase the electrical insulation around the corresponding transistors, which increases the threshold of the breakdown voltage of the corresponding transistors (e.g., the breakdown voltage of the P-well 602 and the N-well 603). The breakdown voltage of the P-well 602 and the N-well 603 imposes a limit on how high a voltage the charge pump can be designed to generate. Thus, the DTI disposed around or near the respective transistors M1 and M2 allows for the generation of a higher DC voltage (eg, 50 volts-200 volts), which can be used to increase the sensitivity and SNR of the microphone assembly.

[0042] Similar to the transistors depicted in charge pump stage 300, a first terminal (eg, first pad 620) of first transistor M1 may be electrically coupled to an input terminal v of charge pump stage 300 via connection 691. in In addition, the second terminal of the first transistor M1 (e.g., the second pad 621) can be electrically coupled to the first terminal of the second transistor M3 (e.g., the first pad 630) and the first terminal of the first capacitor C1 via connection 692. The second terminal of the second transistor M3 (e.g., the second pad 631) can be electrically coupled to the output terminal v of the charge pump stage 300 via connection 693. out In some embodiments, the third transistor M2 is formed similarly to the first transistor M1 , and the fourth transistor M4 , the fifth transistor M5 , and the sixth transistor M6 are formed similarly to the second transistor.

[0043] The first capacitor C1 can be formed or manufactured using any known process, or formed or manufactured as any type of capacitor. In some embodiments, the first capacitor C1 includes a first terminal 681 configured to be connected to one phase of a clock. The first capacitor C1 also includes a first metal plate 682 and a second metal plate 683 electrically coupled to the first terminal 681. The first metal plate 682 is disposed between a third metal plate 684 and a fourth metal plate 685, with a dielectric therebetween. The second metal plate 683 is disposed between an outer edge and the fourth metal plate 685, with a dielectric therebetween. The third metal plate 684 and the fourth metal plate 685 are electrically coupled to a second terminal 688 of the first capacitor C1. In some embodiments, the second capacitor C2 of the charge pump stage 300 can be formed or manufactured similarly to the first capacitor C1.

[0044] Reference now Figure 7 , showing a similar Figure 6 700 of a transistor process of the process depicted. For example, the top view of the transistor process 700 with DTI includes a P-type substrate 601 having a P-well 602 and an N-well 603. A first transistor M1 is disposed or formed in the P-well 602, and a second transistor M3 is disposed or formed in the N-well 603. A first DTI 643 is disposed around or near the first transistor M1 (e.g., and the P-well 602) to electrically insulate the P-well 602 from the P-type substrate. A second DTI 644 is disposed around or near the second transistor M3 to electrically insulate the N-well 603 from the P-type substrate.

[0045] Figure 8 Depicts a similar Figure 6 8 is a top view of a transistor process 800 of a process depicted in FIG. 8 and including a plurality of transistors from a charge pump stage 300. The transistor process 800 includes a P-type substrate 601, a P-well 602, and an N-well 603. Transistors M1 and M2 are disposed or formed within the P-well 602 region, and transistors M3, M4, M5, and M6 are disposed or formed within the N-well 603. A first DTI 643 is disposed around the entire N-well (e.g., both transistors M1 and M2). A second DTI 644 is disposed around the entire P-well (e.g., around all transistors M3, M4, M5, and M6). Alternatively or additionally, in some embodiments, each transistor M 1-6 There may be corresponding DTIs disposed around or near each transistor, respectively.

[0046] Reference now Fig. 9 , depicting a second transistor process 900 with deep trench isolation (DTI). The second transistor process 900 is similar to the reference Figure 6The transistor process 600 described above. However, the second transistor process 900 includes a buried insulating layer 901 in the P-type substrate 601. The buried insulating layer 901 can be disposed in the P-type substrate 601 and extend horizontally under the first transistor M1 and the second transistor M3 as a continuous material. In some embodiments, the buried insulating layer 901 can include a plurality of different portions, each of which is arranged to insulate the corresponding P-well or N-well. The buried insulating layer 901 can include a buried oxide layer, silicon oxide, or other electrically insulating material. The buried insulating layer 901 is positioned adjacent to the first deep N-well 640 and is arranged to contact the first DTI 643 when the first DTI extends around the P-well 602 to electrically insulate the P-well 602 from the P-type substrate. In addition, the buried insulating layer 901 is positioned adjacent to the second deep N-well 641 and is arranged to contact the second DTI 644 when the second DTI extends around the N-well 603 to electrically insulate the N-well 603 from the P-type substrate. In other words, the buried insulating layer 901 is configured to increase the breakdown voltage of the transistor.

[0047] Reference now Fig.10 , depicting a third transistor process 1000 with deep trench isolation (DTI). The third transistor process 1000 is similar to the reference Figure 6 The transistor process 600 described. The third transistor process 1000 includes buried wells to increase electrical insulation between the P-well 602 and the substrate and between the N-well 603 and the substrate. The buried well includes a buried P-well 1001 disposed or formed on a side of the first deep N-well 640 opposite to a side of the first deep N-well 640 abutting the P-well 602. The buried well also includes a buried N-well 1002 disposed or formed on a side of the buried P-well 1001 opposite to a side of the buried P-well 1001 abutting the deep N-well 640. The first DTI 643 is configured to extend deep enough into the P-type substrate 601 so that when the first DTI 643 extends around the P-well 602 (e.g., and the first transistor M1), the buried P-well 1001 and the buried N-well 1002 are in contact with the first DTI 643.

[0048] The buried well also includes a buried P-well 1011 disposed or formed on a side of the second deep N-well 641 opposite to a side of the second deep N-well 641 abutting the N-well 603. The buried well also includes a buried N-well 1012 disposed or formed on a side of the buried P-well 1011 opposite to a side of the buried P-well 1011 abutting the second deep N-well 641. The second DTI 644 is configured to extend sufficiently deep into the P-type substrate 601 so that the buried P-well 1011 and the buried N-well 1012 are in contact with the second DTI 643 as the second DTI 644 extends around the N-well 603 (e.g., and the second transistor M3).

[0049] Reference now Fig.11 , depicting a fourth transistor process 1100 with deep trench isolation (DTI). The fourth transistor process 1100 is similar to the reference Figure 6 The fourth transistor process 1100 includes a P-well 602 and an N-well 603 that share a portion of a DTI 1101. The shared portion of the DTI 1101 may include portions of the P-well 602 and the N-well 603 that are adjacent to each other. In some embodiments, the thickness of the shared portion of the DTI 1101 is the same as the thickness of the unshared portions of the DTI 643 and the DTI 644. In some embodiments, the thickness of the shared portion of the DTI 1101 is greater than the thickness of the unshared portions of the DTI 643 and the DTI 644.

[0050] Fig.12 A top view of a similar fourth transistor process 1100 is depicted, and includes multiple transistors from the charge pump stage 300. The top view of the fourth transistor process 1100 depicts a P-type substrate 601 having an N-well 602 and a P-well 603. The P-well 602 is surrounded by a combination of a first DTI 643 and a shared portion of the DTI 1101. The N-well 603 is surrounded by a combination of a second DTI and a shared portion of the DTI 1101. That is, on one side (e.g., portion) of the P-well 602 and the N-well 603 that are adjacent, the P-well 602 and the N-well 603 share the DTI 1101. In some embodiments, a third DTI 1201 can be disposed or formed around the outside of both the first DTI ring 643 and the second DTI ring 644. The third DTI 1201 can also be used to increase the breakdown voltage of the transistor.

[0051] Reference now Fig.13 , shows a side cross-sectional view of a fifth transistor process 1300 including multiple wells within a DTI ring. The fifth transistor process 1300 is similar to the reference Figure 6The transistor process 600 described. The fifth transistor process 1300 includes a P-well 602 and an N-well 603, wherein a DTI ring 1301 is disposed around the P-well 602 and the N-well 603 (e.g., disposed around a first well region including one or more P-well regions and / or N-well regions). That is, in some embodiments, the DTI 1301 may be disposed in a ring including one or more P-wells 602 and one or more N-wells 603 (e.g., around the first well region). In some embodiments, one or more P-wells 602 and one or more N-wells 603 may have a shallow trench isolation (STI) barrier disposed between the corresponding N-well 603 and the P-well 602. In some embodiments, one or more P-wells 602 and one or more N-wells 603 do not have an STI or DTI barrier between adjacent N-wells 603 and / or P-wells 602. In some embodiments, the size, location, and positioning configuration of each of the one or more P-wells 602 and one or more N-wells 603 within the DTI ring 1301 may vary depending on the specific application or configuration or type of circuitry implemented within the microphone assembly.

[0052] The fifth transistor process 1300 further includes a deep N-well region 1340 extending along a first side of the N-well region 603 and the P-well region 602. The deep N-well region 1340 is disposed between the substrate 601 and the N-well region 602 and the P-well region 603. In some embodiments, additional deep well regions or oxide layers may also be used or stacked to reduce leakage current and / or increase a breakdown voltage of a corresponding transistor (e.g., by electrically insulating the transistor and the corresponding well from the substrate 601).

[0053] Reference now Fig.14, a top view of a substrate of a transistor process 1400 including multiple wells within a DTI ring is shown. The top view of the transistor process 1400 including multiple wells within a DTI ring depicts a P-type substrate 601 having a P-well region 602 and an N-well region 603 positioned adjacent to each other. The P-type substrate also includes a DTI barrier 1301 disposed around or near the P-well region 602 and the N-well region 603. That is, the DTI barrier 1301 extends around a portion of the perimeter of the P-well region 602 and a portion of the perimeter of the N-well region 603. The DTI barrier 1301 is configured to electrically insulate the P-well region 602 and the N-well region 603 from the P-type substrate 601 (e.g., in combination with a buried layer such as a deep N-well layer 1340). The N-well region 603 may have one or more transistors 1401 (e.g., or diodes) located within the N-well region 603, and the P-well region 604 may have one or more transistors 1402 located within the P-well region 602. The DTI barrier 1301 increases the breakdown voltage of the transistors 1401 and 1402 and allows higher voltages (e.g., greater than 55 volts) to be effectively reached or used on the transistors.

[0054] In some embodiments, the DTI barrier 1301 may extend around or near a region including a plurality of discrete P-well regions 602 and / or a plurality of discrete N-well regions 603. The plurality of P-well regions 602 and the plurality of N-well regions 603 may be positioned, arranged, or arranged in any particular geometry. In some embodiments, each of the plurality of P-well regions 602 and the plurality of N-well regions 603 may have one or more transistors (e.g., or diodes) located in the corresponding region. In some embodiments, one or more of the plurality of P-well regions 602 and the plurality of N-well regions 603 may also have another or corresponding DTI barrier or DTI ring disposed around the corresponding region. In some embodiments, the P-well region 602 and the N-well region 603 may not have a barrier or shallow trench isolation barrier between them.

[0055] The subject matter described in this article sometimes illustrates different components contained in or connected to different other components. It will be understood that the architecture depicted in this way is merely exemplary, and in fact, many other architectures that obtain the same function can be implemented. In a conceptual sense, any arrangement of components for achieving the same function is effectively "associated" to achieve the desired function. Thus, any two components combined in this article to obtain a specific function can be regarded as "associated" with each other to achieve the desired function, regardless of the architecture or intermediate components. Similarly, any two components associated in this way can also be regarded as "connected at work" or "connected at work" to achieve the desired function, and any two components that can be associated in this way can also be regarded as being able to "connect at work" to each other to achieve the desired function. Specific examples of connection at work include, but are not limited to, physically compatible and / or physically interacting components and / or wirelessly interactive and / or wirelessly interactive components and / or logically interactive and / or logically interactive components.

[0056] Regarding the use of plural and / or singular terms herein, those skilled in the art can translate from plural to singular and / or from singular to plural when appropriate, depending on the context and / or application. For clarity, various singular / plural permutations may be explicitly set forth herein.

[0057] Those skilled in the art will understand that, in general, the terms used herein, and especially in the appended claims (e.g., the bodies of the appended claims), are generally intended to be “open” terms (e.g., the term “including” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least,” the term “comprising” should be interpreted as “including but not limited to,” etc.).

[0058] Although the drawings and descriptions can illustrate a particular order of method steps, unless otherwise specified above, the order of these steps may be different from the steps depicted and described. In addition, unless otherwise specified above, two or more steps may be performed simultaneously or partially simultaneously. Such variations may, for example, depend on the selected software and hardware systems and the designer's choice. All of these variations are within the scope of the present disclosure. Similarly, software implementations of the described methods may be accomplished using standard programming techniques with rule-based logic and other logic to accomplish various connection steps, processing steps, comparison steps, and decision steps.

[0059] Those skilled in the art will further understand that if a specific number of a recited claim is intended to be stated, such intent will be explicitly stated in the claim, and in the absence of such a statement, no such intent exists. For example, to aid understanding, the following appended claims may contain the use of the introductory phrases "at least one" and "one or more" to introduce claim statements. However, the use of these phrases should not be interpreted as implying that the reference to a claim by the indefinite article "a" or "an" will limit any particular claim containing such a recited claim statement to an invention containing only one such statement, even if the same claim includes the introductory phrases "one or more" or "at least one", and an indefinite article such as "a" or "an" (e.g., "a" and / or "an" should generally be interpreted as meaning "at least one" or "one or more"); the same is true for the use of definite articles used to refer to claim statements. In addition, even if a specific number of recited claim statements is explicitly stated, those skilled in the art will recognize that such a statement should generally be interpreted as meaning at least the stated number (e.g., a detailed statement of "two statements" without other modifiers generally means at least two statements, or two or more statements).

[0060] Furthermore, in those cases where a convention similar to “at least one of A, B, and C, etc.” is used, generally speaking, such construction is intended in the sense that one skilled in the art would understand the convention (e.g., “a system having at least one of A, B, and C” would include, but is not limited to, systems having A alone, B alone, C alone, A and B together, A and C together, B and C together, and / or A, B, and C together, etc.). In those cases where a convention similar to “at least one of A, B, or C, etc.” is used, generally speaking, such construction is intended in the sense that one skilled in the art would understand the convention (e.g., “a system having at least one of A, B, or C” would include, but is not limited to, systems having A alone, B alone, C alone, A and B together, A and C together, B and C together, and / or A, B, and C together, etc.). One skilled in the art would further understand that any disjunctive words and / or phrases that actually present two or more alternative terms, whether in the specification, claims, or drawings, should be understood to contemplate the possibility of including one, either, or both of these terms. For example, the phrase "A or B" will be understood to include the possibilities of "A" or "B" or "A and B."

[0061] Additionally, use of the terms "approximately," "about," "approximately," "substantially," etc. means plus or minus ten percent unless otherwise indicated.

[0062] The foregoing description of exemplary embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or limited to the precise form disclosed, and modifications and variations may be made in light of the above teachings or may be acquired from practice of the disclosed embodiments. The scope of the invention is intended to be defined by the appended claims and their equivalents.

Claims

1. An integrated circuit, the integrated circuit being used to interface with a capacitive micro-electro-mechanical system transducer and adjust a signal output by the capacitive micro-electro-mechanical system transducer, the integrated circuit comprising: a signal conditioning circuit, the input end of the signal conditioning circuit being electrically connectable to the output end of the capacitive MEMS transducer, the signal conditioning circuit having an output end; A transducer bias circuit, the transducer bias circuit comprising: A charge pump circuit, the charge pump circuit comprising a plurality of cascaded charge pump stages between an input terminal and an output terminal of the charge pump circuit, each charge pump stage comprising a capacitor connected to a first semiconductor device, the first semiconductor device being located in a first well region, the first well region being embedded in a substrate and doped with a P-type or N-type material, a first deep trench isolation barrier being disposed around the first well region to insulate at least a portion of the first well region from the substrate; a high-voltage electrostatic discharge protection circuit, the high-voltage electrostatic discharge protection circuit being connected to an output end of the charge pump circuit; and A filter is coupled to an output terminal of the charge pump circuit.

2. The integrated circuit according to claim 1, wherein: The capacitor is connected to a second semiconductor device, which is connected to the first semiconductor device. The second semiconductor device is located in a second well region, which is embedded in the substrate and doped with a P-type or N-type material complementary to the P-type or N-type material of the first well region, and a second deep trench isolation barrier is arranged around at least a portion of the second well region.

3. The integrated circuit according to claim 2, wherein: The capacitor is connected to a second semiconductor device, the second semiconductor device is connected to the first semiconductor device, the second semiconductor device is located in a second well region, the second well region is embedded in the substrate and is doped with a P-type or N-type material complementary to the P-type or N-type material of the first well region, and the first deep trench isolation barrier is arranged around at least a portion of the second well region.

4. An integrated circuit according to claim 2 or 3, wherein: The first semiconductor device or the second semiconductor device includes a diode or a transistor.

5. The integrated circuit according to claim 1, wherein: The first deep trench isolation barrier is disposed around the periphery of the first well region, and a deep well is embedded in the substrate below the first well region. 6 . The integrated circuit of claim 1 , further comprising an oxide layer buried in the substrate below the first well region and connected to at least a portion of the first deep trench isolation barrier. 7 . The integrated circuit of claim 1 , further comprising an outer deep trench isolation barrier disposed around the first deep trench isolation barrier.

8. The integrated circuit of claim 1, wherein: The transducer bias circuit is configured to output a DC voltage of at least 60 volts when the transducer bias circuit is connected to a power source that supplies a DC voltage of 3 volts to 6 volts.

9. A capacitive transducer bias circuit, the capacitive transducer bias circuit comprising: A charge pump circuit, the charge pump circuit comprising a plurality of cascaded charge pump stages between an input terminal and an output terminal, the plurality of cascaded charge pump stages comprising a plurality of semiconductor devices, each semiconductor device being located in a P-well region or an N-well region of a substrate, the P-well region or the N-well region being electrically insulated from the substrate along a perimeter of the P-well region or the N-well region by a deep trench isolation barrier; and the plurality of cascaded charge pump stages are configured to output a DC voltage of at least 60 volts; a high-voltage electrostatic discharge protection circuit, the high-voltage electrostatic discharge protection circuit being connected to the output end of the charge pump circuit; as well as A filter is coupled to the output of the charge pump circuit.

10. The capacitive transducer bias circuit according to claim 9, wherein: The N-well region is electrically insulated from the substrate by the deep trench isolation barrier and the deep N-well region.

11. The capacitive transducer bias circuit according to claim 10, wherein: The P-well region is electrically insulated from the substrate by a second deep trench isolation barrier and the deep N-well region.

12. The capacitive transducer bias circuit according to claim 9, wherein: The deep trench isolation barrier is connected to a buried oxide layer, wherein the buried oxide layer and the deep trench isolation barrier electrically isolate the P-well region from the substrate and electrically isolate the N-well region from the substrate. 13 . The capacitive transducer bias circuit of claim 9 , further comprising an outer deep trench isolation barrier disposed around the deep trench isolation barrier.

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