Method for manufacturing semiconductor device

Abstract

The present disclosure provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes forming a first semiconductor layer on a substrate, forming a second semiconductor layer on the first semiconductor layer, and forming a sacrificial film on the first semiconductor layer and the second semiconductor layer. The sacrificial film fills the area between the first semiconductor layer and the second semiconductor layer. The method also includes forming a spacer in the sacrificial film between the first semiconductor layer and the second semiconductor layer and removing the sacrificial film.

Description

Technical Field

[0001] An embodiment of the present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a multi-layer stack. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are generally manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that should be solved. Summary of the invention

[0004] An object of the embodiments of the present disclosure is to provide a method for manufacturing a semiconductor device to solve at least one of the above problems.

[0005] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, comprising: forming a multilayer stack in a channel region, the multilayer stack comprising alternating layers of a first multilayer and a second multilayer, the first multilayer comprising a first semiconductor material, and the second multilayer comprising a second semiconductor material; removing the second multilayer from the multilayer stack, the remaining first multilayer comprising a first semiconductor layer of the first semiconductor material and a second semiconductor layer of the first semiconductor material; forming a sacrificial film on the first semiconductor layer and the second semiconductor layer, the sacrificial film filling an area between the first semiconductor layer and the second semiconductor layer; forming a gap in the sacrificial film between the first semiconductor layer and the second semiconductor layer; removing the sacrificial film; and forming a gate stack on the channel region.

[0006] Other embodiments of the present disclosure provide a method for manufacturing a semiconductor device, comprising: forming a first multilayer stack in a first region on a substrate, and forming a second multilayer stack in a second region on the substrate, the first multilayer stack including various layers of the second semiconductor layer, and the second multilayer stack including various layers of the first semiconductor layer; forming and removing a sacrificial film, wherein the steps of forming and removing the sacrificial film include: depositing a sacrificial film on the first multilayer stack and the second multilayer stack, wherein the sacrificial film fills a first gap between the various second semiconductor layers of the first multilayer stack, and fills a second gap between the various second semiconductor layers of the first multilayer stack; forming a first plurality of intervals in the sacrificial film between the various second semiconductor layers of the first multilayer stack, and forming a second plurality of intervals between the various first semiconductor layers of the second multilayer stack; forming a mask layer on the sacrificial film; patterning and removing the mask layer in the first region; removing the sacrificial film on the first multilayer stack; removing the mask layer in the second region; and removing the sacrificial film on the second multilayer stack; and forming separate gate electrodes on the first multilayer stack and the second multilayer stack.

[0007] Still other embodiments of the present disclosure provide a method for manufacturing a semiconductor device, comprising: forming a semiconductor layer stack in a channel region; forming a gate dielectric around each semiconductor layer of the semiconductor layer stack; depositing a sacrificial layer on the semiconductor layer stack, the sacrificial layer comprising Al2O3; forming a gap in the sacrificial layer between each semiconductor layer of the semiconductor layer stack; removing the sacrificial layer; and forming a work function adjustment layer around the gate dielectric, the work function adjustment layer comprising La or TiN, the work function adjustment layer having Al2O3 remaining in the sacrificial layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are only used for illustration. In fact, the size of the unit may be arbitrarily enlarged or reduced to clearly show the features of the present disclosure.

[0009] Figure 1 A three-dimensional view of an example nanostructure field effect transistor (nano-FET) is shown, according to some embodiments.

[0010] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B, Fig.11A , Fig. 11B , Fig. 11C , Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.13A , Fig. 13B , Fig. 13C , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig. 20C , Fig.21A , Fig.21B , Fig.22A , Fig. 22B , Fig.23A , Fig. 23B , Fig.24A , Fig. 24B , Fig.25A , Fig.25B , Fig.26A , Fig.26B , Fig.27A , Fig.27B , Fig.27C , Fig.27D , Fig.28A , Fig.28B , Fig.28C , Fig.29A , Fig.29B , Fig.29C , Fig. 30A , Fig. 30B as well as Fig. 30C is a cross-sectional view of a nanostructure field effect transistor at an intermediate stage of fabrication according to some embodiments.

[0011] The reference numerals are as follows:

[0012] 50:Substrate

[0013] 51: Anti-penetration (APT) area

[0014] 52: First semiconductor layer (nanostructure)

[0015] 53: Separator

[0016] 54: Second semiconductor layer (nanostructure)

[0017] 55: Nanostructure

[0018] 64: Multi-layer stacking

[0019] 66: Fins (Nanostructure)

[0020] 68: Isolation Area (STI Area)

[0021] 70: dummy dielectric layer

[0022] 71: dummy gate dielectric

[0023] 72: Virtual gate layer

[0024] 74: Mask layer

[0025] 76: dummy gate

[0026] 78: Mask

[0027] 80: spacer layer

[0028] 81: Spacer

[0029] 82: Spacer layer

[0030] 83: Spacer

[0031] 86: Notch

[0032] 88: Notch

[0033] 90: Internal spacer

[0034] 92: epitaxial source / drain region

[0035] 94: Contact Etch Stop Layer

[0036] 96: Gate dielectric layer

[0037] 96: Interlayer dielectric

[0038] 98: Notch

[0039] 100: Gate dielectric layer

[0040] 102: Gate electrode

[0041] 104: Gate mask

[0042] 106: Interlayer dielectric

[0043] 108: Notch

[0044] 110: Silicide region

[0045] 112: Contact

[0046] 200: Sacrificial film

[0047] 202: Area

[0048] 204: Area

[0049] 206: Area

[0050] 208: Area

[0051] 300: Heat treatment

[0052] 350: Gap

[0053] 400: Blowing

[0054] 450: Porosity

[0055] 500: Photoresist

[0056] 100A: Silicon oxide layer

[0057] 100B: Metal oxide / silicate layer

[0058] 102A: Gate electrode layer

[0059] 102B: Gate electrode layer

[0060] 102C: Filling material

[0061] 500A: Photoresist layer

[0062] 500B: Middle layer

[0063] 500C: Middle layer

[0064] 500D: bottom layer

[0065] 50N: Area

[0066] 50P: Area

[0067] 52A: first semiconductor layer

[0068] 52B: first semiconductor layer

[0069] 52C: first semiconductor layer

[0070] 54A: Second semiconductor layer

[0071] 54B: Second semiconductor layer

[0072] 54C: Second semiconductor layer

[0073] 92A: first semiconductor material layer

[0074] 92B: Second semiconductor material layer

[0075] 92C: third semiconductor material layer

[0076] A-A': Cross section

[0077] B-B': Cross section

[0078] C-C': Cross section DETAILED DESCRIPTION

[0079] The following content provides many different embodiments or examples to implement different components of the embodiments of the present disclosure. Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present disclosure. For example, in the following description, it is mentioned that a first component is formed above or on a second component, which may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the embodiments of the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and is not itself used to specify the relationship between the various embodiments and / or configurations discussed.

[0080] Furthermore, spatially relative terms such as "under", "below", "lower", "above", "upper" and the like may be used to facilitate description of the relationship between one component or feature and another component or feature in the drawings. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the orientation after the rotation.

[0081] For example, embodiments discussed in the present disclosure provide gap filling techniques, such as atomic layer deposition (ALD) processes to form sacrificial films, which are used to fill gaps in the channel region to prevent infiltration of subsequently formed mask layers. Embodiments can reduce over-etching that may occur during the removal process of the sacrificial film, which may cause unexpected and undesirable damage to the main structure of the device. As described in the present disclosure, deposition processes such as ALD processes provide gap filling techniques, which assist by forming internal gaps such as voids or pores in the sacrificial film. In this way, the etching process margin (window) can be increased. The formation of internal voids can help increase the contact area of ​​the etching chemical, which can increase the etching rate. Some embodiments provide the formation of internal voids to facilitate the removal process of the sacrificial film, the self-formation of the voids by applying thermal treatment, and / or the self-formation of the internal pores by precursor purging (purge). The formation of internal voids can facilitate the removal process of the sacrificial film while maintaining the gap filling characteristics of the sacrificial film. The embodiments can be incorporated into the semiconductor process flow with little or no impact on the integration process.

[0082] Figure 1 According to some embodiments, a three-dimensional view of an example nanostructure field effect transistor (nano-FETs), for example, a nanowire, a nanosheet, a gate-all-around (GAA), etc. is shown. The nano-FETs or GAAFETs include a p-type nanostructure 52 and an n-type nanostructure 54 (collectively referred to as a nanostructure 55) above a fin 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 serves as a channel region of the nano-FETs. An isolation region 68 is disposed between adjacent fins 66, and the fin protrudes above and between adjacent isolation regions 56. Although the isolation region 68 is described / illustrated as being separated from the substrate 50, as used in the present disclosure, the term "substrate" may refer to a separate semiconductor substrate or a semiconductor substrate combined with an isolation region. In addition, although the bottom of the fin 66 and the substrate 50 are shown as a single continuous material, the bottom of the fin 66 and / or the substrate 50 may include a single material or multiple materials. In the present disclosure, the fin 66 refers to a portion extending between adjacent isolation regions 68.

[0083] The gate dielectric layer 96 is disposed over the top surface of the fin 66 and along the top surface, sidewalls, and bottom surface of the p-type nanostructure 52 and the n-type nanostructure 54. The gate electrode 102 is over the gate dielectric layer 96. The epitaxial source / drain regions 92 are on the fin 66 and on both sides of the gate dielectric layer 96 and the gate electrode 102.

[0084] Figure 1Reference cross sections used in subsequent figures are further illustrated. Cross section AA' is along the longitudinal axis of the gate electrode 102 and, for example, perpendicular to the direction of current flow between the epitaxial source / drain regions 92 of the nano-FET. Cross section BB' is perpendicular to cross section AA' and along the longitudinal axis of the fin 66 in the PMOS region of the nano-FET and, for example, along the direction of current flow between the epitaxial source / drain regions 92 of the nano-FET. Cross section CC' is parallel to cross section AA' and extends through the epitaxial source / drain regions of the nano-FET. For clarity, subsequent figures refer to these reference cross sections.

[0085] Some embodiments described in the present disclosure are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments refer to planar devices, such as planar FETs or fin field-effect transistors (FinFETs).

[0086] Figures 2 to 30C is a cross-sectional view of an intermediate stage in the fabrication of nano-FETs according to some embodiments. Figures 2 to 5 , Fig. 6A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A , Fig.21A , Fig.22A , Fig.23A , Fig.24A , Fig.25A , Fig.26A , Fig.27A , Fig.27C , Fig.28A , Fig.29A as well as Fig. 30A For along Figure 1 The reference section AA' is shown. Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 11C , Fig. 12B , Fig.12D , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B , Fig.21B , Fig. 22B , Fig. 23B , Fig. 24B , Fig.25B , Fig.26B , Fig.27B , Fig.27D , Fig.28B , Fig.29B as well as Fig. 30B For along Figure 1 The reference section BB' is shown. Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig. 12C , Fig. 13C , Fig.28C , Fig.29C as well as Fig. 30C For along Figure 1 The reference section CC' is shown.

[0087] exist Figure 2 In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type dopants or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally speaking, an SOI substrate is a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is typically disposed on a substrate, such as a silicon substrate or a glass substrate. Other substrates, such as a multilayer substrate or a gradient substrate, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon (Si), germanium (Ge); compound semiconductors including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) and / or indium antimonide (InSb); alloy semiconductors including silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP) and / or gallium indium arsenide phosphide (GaInAsP); or combinations thereof.

[0088] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor (e.g., an n-type nano-FETs). The p-type region 50P can be used to form a p-type device, such as a PMOS transistor (e.g., a p-type nano-FETs). The n-type region 50N can be physically separated from the p-type region 50P (as shown by the separator symbol 53), and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be arranged between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0089] The substrate 50 may be lightly doped with p-type or n-type impurities. An anti-punch-through (APT) implant may be performed on the upper portion of the substrate 50 to form an APT region 51. During the APT implant, dopants may be implanted into the n-type region 50N and the p-type region 50P. The conductivity type of the dopant may be opposite to the conductivity type of the source / drain region to be formed in each of the n-type region 50N and the p-type region 50P. The APT region 51 may extend below the source / drain region to be subsequently formed in the resulting nano-FETs, which will be formed in subsequent processes. The APT region 51 may be used to reduce leakage current from the source / drain region to the substrate 50. In some embodiments, the doping concentration in the APT region 51 may be approximately 1x10 18 Atom / cm 3 Up to about 1x10 19 Atom / cm 3 For the sake of simplicity and clarity, the APT region 51 is not shown in subsequent figures.

[0090] Further in Figure 2In the embodiment of the present invention, a multilayer stack 64 is formed over a substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 52A-C (collectively referred to as first semiconductor layers 52) and second semiconductor layers 54A-C (collectively referred to as second semiconductor layers 54). For purposes of example, as discussed in more detail below, the second semiconductor layer 54 will be removed and the first semiconductor layer 52 will be patterned to form a channel region for nano-FETs in the p-type region 50P, and the first semiconductor layer 52 will be removed and the second semiconductor layer 54 will be patterned to form a channel region for nano-FETs in the n-type region 50N. However, in some embodiments, the first semiconductor layer 52 may be removed and the second semiconductor layer 54 may be patterned to form a channel region for nano-FETs in the n-type region 50N, and the second semiconductor layer 54 may be removed and the first semiconductor layer 52 may be patterned to form a channel region for nano-FETs in the p-type region 50P.

[0091] For the purpose of illustration, the multilayer stack 64 is shown as including three layers of each of the first semiconductor layer 52 and the second semiconductor layer 54. In some embodiments, the multilayer stack 64 may include any number of the first semiconductor layer 52 and the second semiconductor layer 54. Each layer of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc., and has a thickness of about 2 nanometers to about 15 nanometers. In various embodiments, the first semiconductor layer 52 may be formed of a first semiconductor material suitable for p-type nano-FETs, such as silicon germanium, and the second semiconductor layer 54 may be formed of a second semiconductor material suitable for n-type nano-FETs, such as silicon, silicon carbon, etc. For the purpose of illustration, the multilayer stack 64 is shown as the bottommost semiconductor layer being suitable for p-type nano-FETs. In some embodiments, the multilayer stack 64 may be formed so that the bottommost layer is a semiconductor layer suitable for n-type nano-FETs.

[0092] The first semiconductor material and the second semiconductor material may be materials having high etching selectivity to each other. Thus, the first semiconductor layer 52 of the first semiconductor material may be removed without significantly removing the second semiconductor layer 54 of the second semiconductor material in the n-type region 50N, thereby allowing the second semiconductor layer 54 to be patterned to form a channel region of n-type nano-FETs. Similarly, the second semiconductor layer 54 of the second semiconductor material may be removed without significantly removing the first semiconductor layer 52 of the first semiconductor material in the p-type region 50P, thereby allowing the first semiconductor layer 52 to be patterned to form a channel region of p-type nano-FETs.

[0093] refer to Figure 3 According to some embodiments, fins 66 are formed in the multilayer stack 64 and the substrate 50. In some embodiments, fins 66 can be formed in the multilayer stack 64 and the substrate 50 by etching trenches in the multilayer stack 64 and the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching can be anisotropic etching.

[0094] The fins 66 can be patterned by any suitable method. For example, one or more photolithography processes can be used to pattern the fins 66, including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine photolithography processes with self-alignment processes, allowing for the creation of patterns, for example, with a pitch that is smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, after which the remaining spacers can be used to pattern the fins 66.

[0095] Fin 66 may have a width of about 20 nanometers to about 100 nanometers. For purposes of illustration, Figure 3 The fins 66 in the n-type region 50N and the p-type region 50P are shown to have substantially equal widths. In some embodiments, the width of the fins 66 in the n-type region 50N may be greater or less than the width of the fins 66 in the p-type region 50P.

[0096] exist Figure 4In the embodiment shown, a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material over the substrate 50 and the fin 66 and between adjacent fins 66. The insulating material can be an oxide, such as silicon oxide, nitride, etc., or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), etc., or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the embodiment shown, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed as an excess of insulating material to cover the fin 66. Although the insulating material is shown as a single layer, some embodiments may utilize multiple layers of insulating material. For example, in some embodiments, a liner (not shown separately) can be first formed along the surface of the substrate 50 and the fin 66. Thereafter, a filling material, such as the material discussed above, can be formed over the liner.

[0097] A removal process is applied to the insulating material to remove excess insulating material above the fin 66. In some embodiments, a planarization process may be used, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. The planarization process exposes the fin 66 so that after the planarization process is completed, the fin 66 and the top surface of the insulating material are flush.

[0098] Thereafter, the insulating material is etched back to form STI regions 68. The insulating material is etched back so that the upper portions of the fins 66 in regions 50N and 50P protrude from between adjacent STI regions 68. For example, in some embodiments, the insulating material is etched back so that a portion of the substrate below the bottom layer of the first semiconductor layer 52A is exposed. In addition, the top surface of the STI region 68 may have a flat surface, a convex surface, a concave surface (e.g., a dished surface), or a combination thereof as shown. The top surface of the STI region 68 may be formed into a flat, convex and / or concave top surface by appropriate etching. The STI region 68 may be etched back using an acceptable etching process, such as an etching process that is selective to the material of the insulating material (e.g., an etching process that etches the material of the insulating material at a faster rate than etching the material of the fin 66). For example, oxide removal such as dilute hydrofluoric (dHF) may be used.

[0099] The above about Figures 2 to 4The process described is merely one example of how fin 66 may be formed. In some embodiments, the fin may be formed by utilizing a mask and an epitaxial growth process. For example, a dielectric layer may be formed above the top surface of substrate 50, and a groove may be etched through the dielectric layer to expose substrate 50 below. An epitaxial structure may be epitaxially grown in the groove, and the dielectric layer may be recessed so that the epitaxial structure protrudes from the dielectric layer to form fin 66. The epitaxial structure may include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments of an epitaxially grown epitaxial structure, the epitaxially grown material may be doped in situ during the growth process, which may eliminate the need for prior and subsequent implantation, although in situ and implantation doping may be used together.

[0100] In addition, for the purpose of illustration only, the first semiconductor layer 52 and the second semiconductor layer 54 are shown and discussed herein as including the same material in the p-type region 50P and the n-type region 50N. As such, in some embodiments, one or both of the first semiconductor layer 52 and the second semiconductor layer 54 may be different materials, or may be formed in a different order in the p-type region 50P and the n-type region 50N.

[0101] In addition, Figure 4 In some embodiments with different well types, a photoresist or other mask (not shown separately) may be used to implement different implantation steps for the n-type region 50N and the p-type region 50P. For example, a photoresist may be formed over the fin 66 and the STI region 68 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P of the substrate 50. The photoresist may be formed by using a spin coating technique, and the photoresist may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, an n-type dopant implantation may be performed in the p-type region 50P, and the photoresist may be used as a mask to substantially prevent the n-type dopant from being implanted into the n-type region 50N. The n-type dopant may be phosphorus, arsenic, antimony, etc., implanted into its region, and the dopant concentration may be about 10 13 Atom / cm 3 Up to about 10 14 Atom / cm 3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0102] After the p-type region 50P is implanted, a photoresist is formed over the fins 66 and STI regions 68 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N of the substrate 50. The photoresist may be formed by using a spin coating technique, and the photoresist may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type dopant implant may be performed in the n-type region 50N, and the photoresist may be used as a mask to substantially prevent the p-type dopant from being implanted into the p-type region 50P. The p-type dopant may be boron, boron fluoride, indium, etc., implanted into its region, and the dopant concentration may be about 10 13 Atom / cm 3 Up to about 10 14 Atom / cm 3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0103] After implantation of n-type region 50N and p-type region 50P, annealing may be performed to repair implantation damage and activate implanted p-type and / or n-type dopants. In some embodiments, the growth material of the epitaxial fins may be in-situ doped during growth, which may avoid implantation, although in-situ doping and implantation doping may be used together.

[0104] exist Figure 5 In the embodiment of the present invention, a dummy dielectric layer 70 is formed on the fin 66. The dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and may be deposited or thermally grown by an acceptable technique. A dummy gate layer 72 is formed above the dummy dielectric layer 70, and a mask layer 74 is formed above the dummy gate layer 72. The dummy gate layer 72 may be deposited above the dummy dielectric layer 70, and then planarized, for example, by CMP. The mask layer 74 may be deposited above the dummy gate layer 72. The dummy gate layer 72 may be a conductive material or a non-conductive material, and may be selected from a group including amorphous silicon, polysilicon, polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art for depositing selected materials. The dummy gate layer 72 may be formed of other materials having high etch selectivity to the etching of the isolation region. The mask layer 74 may include, for example, silicon nitride, silicon oxynitride, etc. In the example, a single dummy gate layer 72 and a single mask layer 74 are formed to span the n-type region 50N and the p-type region 50P. It should be noted that the dummy dielectric layer 70 is shown to cover only the fin 66 for the purpose of illustration only. In some embodiments, the dummy dielectric layer 70 may be deposited so that the dummy dielectric layer 70 covers the STI region 68 and extends between the dummy gate layer 72 and the STI region 68.

[0105] exist Fig. 6A and Figure 6B In the embodiment, the mask layer 74 (see Figure 5 ) is patterned to form a mask 78. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 to form a dummy gate 76, and the pattern of the mask 78 can be transferred to the dummy dielectric layer 70 to form a dummy gate dielectric 71. The dummy gates 76 cover the respective channel regions of the fins 66. The pattern of the mask 78 can be used to physically separate each dummy gate 76 from adjacent dummy gates 76. The dummy gates 76 can also have a lengthwise direction that is substantially perpendicular to the lengthwise direction of the respective fins 66.

[0106] exist Fig. 7A and Figure 7B In Fig. 6A and Figure 6B A first spacer layer 80 and a second spacer layer 82 are formed on the structure shown. The first spacer layer 80 and the second spacer layer 82 are then patterned to form spacers for self-aligned source / drain regions. Fig. 7A and Figure 7B In the embodiment of the present invention, a first spacer layer 80 is formed on the top surface of the STI region 68, on the top surface and sidewalls of the nanostructure 66 and the mask 78, and on the sidewalls of the substrate 50, the dummy gate 76, and the dummy gate dielectric 71. A second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, etc., and may be formed using a technique such as thermal oxidation, or may be deposited by CVD, ALD, etc. The second spacer layer 82 may be formed of a material having a different etching rate from the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and may be deposited by CVD, ALD, etc.

[0107] After forming the first spacer layer 80 and before forming the second spacer layer 82, implantation for lightly doped source / drain (LDD) regions (not shown separately) may be performed. Figure 4As discussed in the implantation, a mask, such as a photoresist, may be formed over the n-type region 50N while exposing the p-type region 50P, and an impurity of a suitable type (e.g., p-type) may be implanted into the nanostructure 66 and substrate 50 exposed in the p-type region 50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region 50P while exposing the n-type region 50N, and an impurity of a suitable type (e.g., n-type) may be implanted into the nanostructure 55 and substrate 50 exposed in the n-type region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities discussed previously, and the p-type impurity may be any of the p-type impurities discussed previously. The lightly doped source / drain regions may have a doping capacity of about 10 15 Atom / cm 3 to about 10 19 Atom / cm 3 Annealing can be used to repair implant damage and activate implanted impurities.

[0108] exist Fig. 8A and Figure 8B , the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacer 81 and the second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 have the function of self-aligning the subsequently formed source and drain regions, as well as protecting the sidewalls of the nanostructure 66 during subsequent processes. The first spacer layer 80 and the second spacer layer 82 can be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), etc. In some embodiments, the material of the second spacer layer 82 has a different etching rate from the material of the first spacer layer 80, so that the first spacer layer 80 can serve as an etching stop layer when patterning the second spacer layer 82, and the second spacer layer 82 can serve as a mask when patterning the first spacer layer 80. For example, the second spacer layer 82 can be etched using an anisotropic etching process, wherein the first spacer layer 80 serves as an etching stop layer, and wherein the remaining portion of the second spacer layer 82 forms the second spacer 83, such as Fig. 8A Afterwards, the second spacer 83 is used as a mask to simultaneously etch the exposed portion of the first spacer layer 80, thereby forming the first spacer 81, as shown in FIG. Fig. 8A shown.

[0109] like Fig. 8A As shown, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the nanostructure 66 and the substrate 50. Figure 8BAs shown, the second spacer layer 82 may be removed from over the first spacer layer 80 adjacent to the mask 78 , the dummy gate 76 , and the dummy gate dielectric 71 , and the first spacer 81 may be disposed on the sidewalls of the mask 78 , the dummy gate 76 , and the dummy gate dielectric 71 .

[0110] It should be noted that the above disclosure describes a process for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used (e.g., the first spacer 81 may be formed before forming the second spacer 83), additional spacers may be formed and removed, and / or the like. In addition, different structures and steps may be used to form n-type and p-type devices.

[0111] exist Fig. 9A and Fig. 9B In some embodiments, a first recess 86 is formed in the nanostructure 66 and the substrate 50. An epitaxial source / drain region will subsequently be formed in the first recess 86. The first recess 86 may extend through the first semiconductor layer 52 and the second semiconductor layer 54 and into the substrate 50. Fig. 9A As shown, the top surface of the STI region 68 can be flush with the top surface of the substrate 50. In various embodiments, the first recess 86 can extend to the top surface of the substrate 50 without etching the substrate 50; the substrate 50 can be etched so that the bottom surface of the first recess 86 is disposed below the top surface of the STI region 68; or similar arrangements. The nanostructure 55 and the substrate 50 can be etched to form the first recess 86 by using an anisotropic etching process such as RIE, NBE, etc. During the etching process for forming the first recess 86, the first spacer 81, the second spacer 83 and the mask 78 shield portions of the nanostructure 66 and the substrate 50. Each layer of the nanostructure 66 can be etched using a single etching process or multiple etching processes. The etching of the first recess 86 can be stopped using a timed etching process after the first recess 86 reaches the desired depth.

[0112] exist Fig. 10A and Fig. 10B In the embodiment, the sidewall portions of each layer of the multilayer stack 64 formed of the first semiconductor material (e.g., the first semiconductor layer 52) exposed by the first recess 86 are etched to form a sidewall recess 88 in the n-type region 50N, and the sidewall portions of each layer of the multilayer stack 64 formed of the second semiconductor material (e.g., the second semiconductor layer 54) exposed by the first recess 86 are etched to form a sidewall recess 88 in the p-type region 50P. Fig. 10BThe sidewalls of the first semiconductor layer 52 and the second semiconductor layer 54 in the recess 88 are shown as straight, but these sidewalls can be concave or convex. The sidewalls can be etched using an isotropic etching process, such as wet etching, etc. A mask (not shown) can be used to protect the p-type region 50P, while the first semiconductor layer 52 is etched using an etchant selective to the first semiconductor material, so that the second semiconductor layer 54 and the substrate 50 remain relatively unetched compared to the first semiconductor layer 52 in the n-type region 50N. Similarly, a mask (not shown) can be used to protect the n-type region 50N, while the second semiconductor layer 54 is etched using an etchant selective to the second semiconductor material, so that the first semiconductor layer 52 and the substrate 50 remain relatively unetched compared to the second semiconductor layer 54 in the p-type region 50P. In an embodiment where the first semiconductor layer 52 includes, for example, SiGe and the second semiconductor layer 54 includes, for example, Si or SiC, the sidewalls of the first semiconductor layer 52 in the n-type region 50N can be etched using a dry etching process with tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., and the sidewalls of the second semiconductor layer 54 in the p-type region 50P can be etched using a dry etching process with hydrogen fluoride, another fluorine-based gas, high-temperature H2SO4, H2PO3, etc., or a combination thereof.

[0113] exist Figure 11A-11C 10A and 10B, a first inner spacer 90 is formed in the sidewall recess 88. The first inner spacer 90 can be formed by depositing an inner spacer layer (not shown separately) on the structure shown in FIGS. 10A and 10B. The first inner spacer 90 serves as an isolation member between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in the recess 86, and the first semiconductor layer 52 in the n-type region 50N and the second semiconductor layer 54 in the p-type region 50P will be replaced by the corresponding gate structure.

[0114] The inner spacer layer may be deposited by a conformal deposition process such as CVD, ALD, etc. The inner spacer layer may include a material such as silicon nitride or silicon oxynitride, although any suitable material may be used, such as a low-k material having a dielectric constant less than about 3.5. The inner spacer layer may then be anisotropically etched to form a first inner spacer 90. Although the outer sidewalls of the first inner spacer 90 are shown flush with the sidewalls of the second semiconductor layer 54 in the n-type region 50N and flush with the sidewalls of the first semiconductor layer 52 in the p-type region 50P, the outer sidewalls of the first inner spacer 90 may extend beyond the sidewalls of the second semiconductor layer 54 and / or the first semiconductor layer 52, respectively, or be recessed from the sidewalls of the second semiconductor layer 54 and / or the first semiconductor layer 52.

[0115] In addition, despite the Fig. 11B , the outer sidewall of the first inner spacer 90 is shown as straight, but the outer sidewall of the first inner spacer 90 may be concave or convex. For example, Fig. 11C The embodiment shown, wherein the sidewalls of the first semiconductor layer 52 are recessed, the outer sidewalls of the first inner spacer 90 are recessed, and the first inner spacer is recessed from the sidewalls of the second semiconductor layer 54 in the n-type region 50N. The present disclosure also shows some embodiments, wherein the sidewalls of the second semiconductor layer 54 are recessed, the outer sidewalls of the first inner spacer 90 are recessed, and the first inner spacer is recessed from the sidewalls of the first semiconductor layer 52 in the p-type region 50P. The inner spacer layer can be etched by an anisotropic etching process such as RIE, NBE, etc. The first inner spacer 90 can be used to prevent a subsequent etching process (such as an etching process for forming a gate structure) from affecting a subsequently formed source / drain region (such as described below with respect to Figure 12A-12C Damage to the epitaxial source / drain regions 92) in question.

[0116] exist Figure 12A-12C In the embodiment, an epitaxial source / drain region 92 is formed in the first recess 86 to apply stress to the second semiconductor layer 54 of the nanostructure 66 in the n-type region 50N and to the first semiconductor layer 52 of the nanostructure 66 in the p-type region 50P, thereby improving performance. Fig. 12BAs shown, epitaxial source / drain regions 92 are formed in the first recess 86 so that each dummy gate 76 is disposed between respective adjacent pairs of epitaxial source / drain regions 92. In some embodiments, the first spacer 81 is used to separate the epitaxial source / drain regions 92 from the dummy gates 72 by an appropriate lateral distance so that the epitaxial source / drain regions 92 do not short-circuit with the gates of subsequently formed nano-FETs. The first internal spacer 90 can be used to separate the epitaxial source / drain regions 92 from the first semiconductor layer 52A-52C by an appropriate lateral distance to prevent short-circuiting between the epitaxial source / drain regions 92 and the gates of subsequently formed nano-FETs.

[0117] The epitaxial source / drain region 92 in the n-type region 50N (e.g., NMOS region) can be formed by shielding the p-type region 50P (e.g., PMOS region). Thereafter, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 in the n-type region 50N. The epitaxial source / drain region 92 may include any acceptable material suitable for n-type nano-FETs. For example, if the second semiconductor layer 54 is silicon, the epitaxial source / drain region 92 may include a material that applies tensile strain to the second semiconductor layer 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide (SiCP), silicon phosphide, etc. The epitaxial source / drain region 92 may have a surface that is elevated from a corresponding surface of the multilayer stack 64 and may have facets.

[0118] The epitaxial source / drain region 92 in the p-type region 50P (e.g., a PMOS region) can be formed by shielding the n-type region 50N (e.g., an NMOS region). Thereafter, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 in the p-type region 50P. The epitaxial source / drain region 92 may include any acceptable material suitable for p-type nano-FETs. For example, if the first semiconductor layer 52 is silicon germanium (SiGe), the epitaxial source / drain region 92 may include a material that applies compressive strain to the first semiconductor layer 52, such as silicon germanium, boron-doped silicon germanium (SiGeB), germanium, germanium tin, etc. The epitaxial source / drain region 92 may have a surface that is elevated from a corresponding surface of the multilayer stack 64 and may have a facet.

[0119] The epitaxial source / drain regions 92, the first semiconductor layer 52, the second semiconductor layer 54 and / or the substrate 50 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions followed by annealing. The impurity concentration of the source / drain regions may be approximately 10 19 Atom / cm 3 Up to about 10 21 Atom / cm 3The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 may be doped in-situ during growth.

[0120] As an epitaxial process for forming epitaxial source / drain regions 92 in n-type region 50N and p-type region 50P, the upper surface of the epitaxial source / drain region has facets, and the facets extend laterally outward beyond the sidewalls of nanostructure 66. In some embodiments, these facets merge adjacent epitaxial source / drain regions 92 of the same nano-FETs, such as Fig. 12A In other embodiments, as shown in Fig. 12C As shown, after the epitaxial process is completed, the adjacent epitaxial source / drain regions 92 remain separated. Fig. 12A However, the process and structure shown therein are also applicable to Fig. 12C In the embodiment of Fig. 12A as well as Fig. 12C In the illustrated embodiment, the first spacer 81 is formed to cover a portion of the sidewalls of the nanostructure 66 and a portion of the sidewalls of the substrate, and its sidewalls extend over the STI region 68 to block epitaxial growth. In some other embodiments, the spacer etch used to form the first spacer 81 can be adjusted to remove the spacer material to allow the epitaxial growth area to extend to the surface of the STI region 68.

[0121] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped to different dopant concentrations. In some embodiments, the dopant concentration of the first semiconductor material layer 92A may be less than the dopant concentration of the second semiconductor material layer 92B, and greater than the dopant concentration of the third semiconductor material layer 92C. In an embodiment where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited on the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited on the second semiconductor material layer 92B.

[0122] Fig.12DAn embodiment is shown in which the sidewalls of the first semiconductor layer 52 in the n-type region 50N and the sidewalls of the second semiconductor layer 54 in the p-type region 50P are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed from the sidewalls of the second semiconductor layer 54 and the first semiconductor layer 52, respectively. Fig.12D As shown, the epitaxial source / drain regions 92 may be formed to contact the first inner spacer 90 and may extend beyond the sidewalls of the second semiconductor layer 54 in the n-type region 50N and may extend beyond the sidewalls of the first semiconductor layer 52 in the p-type region 50P.

[0123] exist Figure 13A-13C In Fig. 6A , Fig. 12B and Fig. 12A A first interlayer dielectric (ILD) 96 is deposited on the structure shown in FIG. Figures 7A-12D The process does not change Fig. 6A ). The first ILD 96 may be formed of a dielectric material and may be deposited by any suitable method such as CVD, plasma-enhanced CVD (PECVD) or FCVD (flowable CVD). The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain regions 92, the mask 74, and the first spacer 81. The CESL 94 may include a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, etc., whose etching rate is different from the etching rate of the material of the overlying first ILD 96.

[0124] exist Fig.14A and Fig. 14BIn the process, a planarization process such as CMP may be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76 and the portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, within process variations, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 are flush. Therefore, the top surface of the dummy gate 76 is exposed through the first ILD 96. In some embodiments, the mask 78 may be retained, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surface of the mask 78 and the first spacer 81.

[0125] exist Fig.15A and Fig. 15B In the embodiment of the present invention, the dummy gate 76 and the mask 78 (if present) are removed in one or more etching steps, thereby forming a second recess 98. A portion of the dummy dielectric layer 71 in the second recess 98 may also be removed. In some embodiments, the dummy gate 76 and the dummy dielectric layer 71 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas, the reactive gas selectively etches the dummy gate 76 at a faster rate than the first ILD 96 or the first spacer 81. Each second recess 98 exposes and / or covers a portion of the multilayer stack 64, which serves as a channel region in the subsequently completed nano-FETs. The portion of the multilayer stack 64 as a channel region is disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, when etching the dummy gate 76, the dummy dielectric layer 71 may serve as an etch stop layer. The dummy dielectric layer 71 may then be removed after removing the sacrificial gate 76, for example using dilute HF.

[0126] exist Fig.16A 16 , the first semiconductor layer 52 in the n-type region 50N and the second semiconductor layer 54 in the p-type region 50P are removed, thereby extending the second recess 98. The first semiconductor layer 52 can be removed by forming a mask (not shown) over the p-type region 50P and performing an isotropic etching process, such as a wet etching process, which uses an etchant that is selective to the material of the first semiconductor layer 52, while the second semiconductor layer 54, the substrate 50, and the STI region 68 remain relatively unetched compared to the first semiconductor layer 52. In an embodiment where the first semiconductor layer 52 includes, for example, SiGe, and the second semiconductor layers 54A-54C include, for example, Si or SiC, the first semiconductor layer 52 in the n-type region 50N can be removed using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like.

[0127] The second semiconductor layer 54 may be removed by forming a mask (not shown) over the n-type region 50N and performing an isotropic etching process, such as a wet etching process, which uses an etchant that is selective to the material of the second semiconductor layer 54, while the first semiconductor layer 52, the substrate 50, and the STI region 68 remain relatively unetched compared to the second semiconductor layer 54. In embodiments where the second semiconductor layer 54 includes, for example, silicon, silicon carbon, etc., and the first semiconductor layer 52 includes, for example, silicon, etc., dilute hydrofluoric acid, etc., may be used to remove the second semiconductor layer 54 in the p-type region 50P.

[0128] exist Fig.17A and Fig. 17B In the embodiment of the present invention, a gate dielectric layer 100 is formed to replace the gate. The gate dielectric layer 100 is conformally deposited in the second recess 98. In the n-type region 50N, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50, and the top surface, sidewalls, and bottom surface of the second semiconductor layer 54, and in the p-type region 50P, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50, and the top surface, sidewalls, and bottom surface of the first semiconductor layer 52. The gate dielectric layer 100 may also be deposited on the top surfaces of the first ILD 96, the CESL 94, the first spacer 81, and the STI region 68.

[0129] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, etc. or combinations thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer 100A (see below). Fig.18A ) and a metal oxide or silicate layer 100B on the silicon oxide layer (see below Fig.18A ). In some embodiments, the gate dielectric layer 100 includes a high dielectric constant material, and in these embodiments, the gate dielectric layer 100 may have a dielectric constant value greater than about 7.0, and may include a metal oxide or silicate layer 100B of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. The formation method of the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0130] The gate dielectric layer 100 may be formed in the n-type region 50N and the p-type region 50P at the same time, so that the gate dielectric layer 100 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region may be formed by different processes, so that the gate dielectric layer 100 may be different materials. When using different processes, various mask steps may be used to shield and expose appropriate regions.

[0131] FIG. 18A to FIG. 27D A gate electrode 102 is shown formed over the gate dielectric layer 100 . Fig.18A , Fig.19A , Fig. 20A , Fig.21A , Fig.22A , Fig.23A , Fig.24A , Fig.25A , Fig.26A as well as Fig.27C Show Fig.17A A detailed view of the intermediate stages of the process in regions 202 and 204, Fig.18B , Fig.19B , Fig. 20B , Fig.21B , Fig. 22B , Fig. 23B , Fig. 24B , Fig.25B , Fig.26B as well as Fig.27D Show Fig. 17B Detailed view of regions 206 and 208 at an intermediate stage of the process.

[0132] The gate electrode 102 may be formed simultaneously so that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate electrode 102 in each region may be formed by different processes so that the gate electrode 102 may be of different materials. When using different processes, various masking steps may be used to shield and expose appropriate regions.

[0133] like Fig.18A and Fig.18BAs shown, a first gate electrode layer 102A, such as a liner or work function adjustment layer, is formed over the gate dielectric layer 100 and around the first semiconductor layer 52 and / or the second semiconductor layer 54. The first gate electrode layer 102A may be on the top surface, sidewalls, and bottom surface of the second semiconductor layer 54 and / or over the gate dielectric layer 100 on the top surface, sidewalls, and bottom surface of the first semiconductor layer 52. In some embodiments, any number of other layers, such as liner layers or work function adjustment layers, may be formed over the gate dielectric layer 100 before forming the first gate electrode layer 102A. The work function of the gate electrode may be adjusted to the band edge of silicon, SiGe, or other underlying semiconductor material. For NMOS devices, the work function may be adjusted to be close to the conduction band of silicon or SiGe, while for PMOS devices, the work function may be adjusted to be close to the valence band of silicon or SiGe to improve transistor performance.

[0134] In some embodiments, the first gate electrode layer 102A includes TiN, GaN, La, etc. and / or a combination thereof. The first gate electrode layer 102A may be formed by deposition, such as a conformal deposition method such as ALD, CVD, PVD, etc. The thickness of the first gate electrode layer 102A may be in the range of about 100 nanometers to about 500 nanometers.

[0135] exist Fig.19A and Fig.19B In the embodiment of the present invention, a sacrificial film 200 is formed on the first gate electrode layer 102A. The sacrificial film 200 may be formed by a suitable deposition process, such as ALD. The sacrificial film 200 may be used to fill the gap between the semiconductor layer 52 and / or the semiconductor layer 54 so as to suppress the formation of a photoresist (see below). Fig.21A ) fills the above-mentioned gap because the photoresist may be more difficult to remove from the gap between the semiconductor layer 52 and / or the semiconductor layer 54. The sacrificial film 200 also fills the recess 98. In some embodiments, the sacrificial film 200 includes a metal oxide, such as Al2O3, ZrO2, etc. or a combination thereof. In some embodiments, trimethylaluminium (TMA) is used as a precursor for forming the sacrificial film 200.

[0136] In some embodiments, the sacrificial film 200 is formed at a low temperature, such as in a range of about 30° C. to about 350° C. The sacrificial film 200 may be formed to a thickness of about 2 nanometers to about 15 nanometers, which may be beneficial for filling the gaps between the semiconductor layers 52 and / or 54. A sacrificial film 200 thickness of less than about 2 nanometers may not be sufficient to fill the gaps between the semiconductor layers 52 and / or 54, and may allow other materials, such as photoresist, to infiltrate the gaps in subsequent processes. A sacrificial film 200 thickness greater than about 15 nanometers may interfere with subsequent processes, such as the formation of photoresist (see below). Fig.21A In some embodiments, the sacrificial film 200 is formed without any seams or voids between the semiconductor layers 52 and / or 54 .

[0137] Fig. 20A , Fig. 20B and Fig. 20C The sacrificial film 200 is shown to be formed with spaces, such as voids and / or pores, between the semiconductor layers 52 and / or 54. The formation of the internal spaces can facilitate the subsequent removal process of the sacrificial film 200 (see below). Figure 23A-23B and Figure 25A-25B ), for example by increasing the etching chemical contact area. In some embodiments, the spacers do not open through the outer surface of the sacrificial film 200, which allows the sacrificial film 200 to maintain its gap filling properties and inhibit the subsequent formation of materials, such as photoresist (see below Fig.21A ) enters the gap between semiconductor layers 52 and 54.

[0138] According to some embodiments, Fig. 20A and Fig. 20B A void 350 is shown formed in the sacrificial film 200 between the semiconductor layers 52 and 54 by applying a heat treatment 300. The heat treatment 300 may be performed using an annealing tool at a temperature in a range of about 180° C. to about 900° C., such as about 200° C. to about 800° C., or about 400° C. to about 800° C., which may be beneficial in shrinking the volume of the sacrificial film 200 by a range of about 5% to about 50%, thereby forming the void 350 in the sacrificial film 200 between the semiconductor layers 52 and 54. Performing the heat treatment 300 at a temperature less than about 180° C. may not cause the sacrificial film 200 to shrink sufficiently to produce the void 350. Performing the heat treatment 300 at a temperature greater than about 900° C. may produce a void through the outer surface of the sacrificial film 200, which may allow subsequently formed materials, such as photoresist (see below) to shrink. Fig.21A) into the void between semiconductor layers 52 and 54. Void 350 can have a length measured in the horizontal direction in a range of about 1 nanometer to about 7 nanometers, and a thickness measured in the vertical direction in a range of about 0.1 nanometer to about 1 nanometer.

[0139] In some embodiments, Fig. 20C As shown, a controlled precursor purge 400 is performed to form a pore 450 in the sacrificial film 200 between the semiconductor layers 52 and 54. The pore 450 may have a diameter of about 10 nm. 3 to about 100nm 3 In some embodiments, 0 to 10 pores are formed between each pair of semiconductor layers 52 and 54. The controlled purge 400 can result in the self-formation of the pores 450 because the reduced H2O purge flow can result in early merging of the sacrificial film 200 at the entrance of the lateral gap between the semiconductor layers 52 and / or 54. The early merging can result in a volume reduction of the sacrificial film 200 in the range of less than about 15%.

[0140] The controlled purge 400 includes H2O purge, N2 purge, He purge, Ar purge, etc. or a combination thereof. In some embodiments, the controlled purge includes H2O purge, which is performed at a flow rate of about 100 sccm to about 1000 sccm and a duration in the range of about 0.1 seconds to about 100 seconds, which is beneficial to cause shrinkage of the sacrificial film 200 to form the pores 450. Performing the H2O purge at a flow rate of less than about 80 sccm may not produce sufficient shrinkage in the sacrificial film 200 to form the pores 450. Performing the H2O purge at a flow rate greater than about 2000 sccm may cause the pores 450 to break through the outer surface of the sacrificial film 200, which may allow subsequently formed materials, such as photoresist (see below) to form the pores 450. Fig.21A ) enters the gap between semiconductor layers 52 and 54.

[0141] In some embodiments, the controlled purge includes an N2 purge performed at a flow rate of about 100 sccm to about 1000 sccm and for a duration ranging from about 0.1 seconds to about 100 seconds, which is beneficial for causing shrinkage of the sacrificial film 200 to form the pores 450. Performing the N2 purge at a flow rate of less than about 80 sccm may not produce sufficient shrinkage in the sacrificial film 200 to form the pores 450. Performing the N2 purge at a flow rate greater than about 2000 sccm may cause the pores 450 to break through the outer surface of the sacrificial film 200, which may allow subsequently formed materials, such as photoresist (see below) to form the pores 450. Fig.21A ) enters the gap between semiconductor layers 52 and 54.

[0142] In some embodiments, the heat treatment 300 is performed to form the voids 350 in the sacrificial film 200, and the controlled purge 400 is not performed. In some embodiments, the controlled purge 400 is performed to form the pores 450 in the sacrificial film 200, and the heat treatment 300 is not performed. In some embodiments, both the heat treatment 300 and the controlled purge 400 are performed, which can form a space including the voids 350 and the pores 450 in the sacrificial film 200. Any suitable number and / or order of performing the heat treatment 300 and / or the controlled purge 400 is included within the scope of the present disclosure. In some embodiments, the sacrificial film 200 (see above) is performed. Fig.19A and Fig.19B ) and subsequent multiple cycles of thermal treatment 300 and / or controlled purging 400.

[0143] Fig.21A and Fig.21B Continue Fig. 20A , Fig. 20B and Fig. 20C , and a photoresist 500 is shown to be formed over the first semiconductor layer 52 in the p-type region 50P and over the second semiconductor layer 54 in the n-type region 50N. Fig.21A Show according to Fig. 20A Although the embodiment shown has a void 350, it should be understood that embodiments having a void 450 instead of the void 350 or having the void 450 in addition to the void 350 are all included in the scope of the embodiment according to FIGS. 21A and 21B. When performing subsequent processes on the semiconductor layer 54, such as etching of the first gate electrode layer 102A (see below), Fig.24A ), a photoresist 500 is formed to shield the semiconductor layer 52.

[0144] Fig.21A Four mask layers or photoresist 500 are shown formed over sacrificial film 200 and semiconductor layers 52 and 54. However, it should be understood that mask layer 500 or photoresist 500 may include any suitable number of film layers and materials. In some embodiments, three layers of photoresist 500 may be formed. In some embodiments, four layers of photoresist 500 include multiple mask layers, which may be sequentially blanket deposited using, for example, a spin coating process. In other embodiments, one or more of the multiple mask layers may be deposited using processes such as CVD, ALD, etc. Fig.21A As shown, the four-layer photoresist 500 includes a first photoresist layer 500A, a first intermediate layer 500B, a second intermediate layer 500C, and a bottom layer 500D. However, any suitable process and any suitable process combination may be used to deposit the film layers of the four-layer photoresist 500. Any suitable thickness may be used for the four-layer photoresist 500.

[0145] like Fig.21A As further shown, the four-layer photoresist 500 includes an underlayer 500D formed above the sacrificial film 200. Since the sacrificial film 200 fills the gap between the semiconductor layers 52 and 54, the underlayer 500D may not be formed between the semiconductor layers 52 and 54. By subsequently removing the underlayer 500D (see below), Fig.22A and Fig.25A ), increasing the etching process margin (window), which is beneficial to process efficiency. In some embodiments, the bottom layer 500D can be formed of a polymer. The bottom layer 500D can be a bottom anti-reflective coating (BARC). In some embodiments, the bottom layer 500D is formed using a spin coating process and is composed of, for example, C x H y O z However, any suitable material and any suitable process may be used to form the bottom layer 500D. The bottom layer 500D may be deposited to any suitable thickness.

[0146] The four-layer photoresist 500 further includes a second intermediate layer 500C formed on the bottom layer 500D. The second intermediate layer 500C may be made of, for example, Si x H y C z O w The second intermediate layer 500C may be formed of a material, silicon or metal oxide, and formed using one or more deposition processes such as spin coating, CVD, ALD, etc. However, any suitable material and process may be used to form the second intermediate layer 500C. In some embodiments, the material composition of the second intermediate layer 500C may be determined to provide high etching selectivity relative to some film layers, such as the bottom layer 500D and / or the sacrificial film 200 or other film layers, which may provide etching stop capability corresponding to the patterned second intermediate layer 500C. The second intermediate layer 500C may include more than one layer and may include more than one material. The second intermediate layer 500C may have any suitable thickness.

[0147] The four-layer photoresist 500 also includes a first intermediate layer 500B formed above the second intermediate layer 500C. The first intermediate layer 500B can be formed by one or more deposition processes such as spin coating, CVD, ALD, etc. However, any suitable process can be used to form the first intermediate layer 500B. In some embodiments, the material composition of the first intermediate layer 500B can be determined to provide high etching selectivity relative to other film layers, such as the bottom layer 500D, the second intermediate layer 500C or other film layers (e.g., photoresist materials), which can provide etching stop capabilities corresponding to the patterned first intermediate layer 500B. The first intermediate layer 500B may include an inorganic material, which may be a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), an oxide (e.g., silicon oxide), etc. However, any suitable material can be used to form the first intermediate layer 500B. In addition, the first intermediate layer 500B may include more than one layer, and may include more than one material. The first intermediate layer 500B can have any suitable thickness.

[0148] The four-layer photoresist 500 also includes a first photoresist layer 500A above the first intermediate layer 500B. The first photoresist layer 500A can be formed by a photoresist (e.g., a photosensitive material) including an organic material, and can be a positive photosensitive material or a negative photosensitive material. The first photoresist layer 500A can be formed by one or more deposition processes such as spin coating. However, any suitable process can be used to form the first photoresist layer 500A. The first photoresist layer 500A can have any suitable thickness.

[0149] Fig.22A and Fig. 22B The patterning of the photoresist 500 is shown (e.g., using a photolithographic mask and an etching process). Once deposited, the photoresist layer 500 can be patterned to expose portions of the sacrificial film 200 above the semiconductor layer 54 (e.g., in the n-type region 50N) while continuing to shield the semiconductor layer 52 (e.g., in the p-type region 50P). However, any suitable area can be exposed and / or shielded. Because the sacrificial film 200 fills the gaps between the semiconductor layers 54, the patterning of the photoresist layer 500 can be more easily performed because the photoresist 500 does not penetrate into the gaps between the semiconductor layers 54. In some embodiments, the photoresist layer 500 can be patterned to expose portions of the sacrificial film 200 above the semiconductor layer 52 (e.g., in the p-type region 50P) while continuing to shield the semiconductor layer 54 (e.g., in the n-type region 50N). However, any suitable area can be exposed and / or shielded.

[0150] Fig.23A and Fig. 23BThe sacrificial film 200 above the semiconductor layer 54 is shown being removed while shielding the semiconductor layer 52. The sacrificial film 200 can be removed by any suitable process, such as an etching process. The efficiency of the removal can be improved by having spaces between the semiconductor layers 54, such as gaps 350 and / or pores 450, such as by increasing the etching chemical contact area. This can increase the etching process margin by 50%. Increasing the etching process margin can avoid over-etching that may damage the main device structure, such as the gate dielectric layer 100 or the semiconductor layer 54. In some embodiments, the sacrificial film 200 is removed using an etching process including dilute hydrofluoric acid, and the etching time is about 10 seconds to about 60 seconds. In some embodiments, the sacrificial film 200 above the semiconductor layer 52 is removed while shielding the semiconductor layer 54.

[0151] Fig.24A and Fig. 24B It is shown that a portion of the first gate electrode layer 102A above the semiconductor layer 54 is recessed while the semiconductor layer 52 is masked. In some embodiments, the thickness of the first gate electrode layer 102A is reduced so that the work function adjustment layer subsequently formed on the semiconductor layer 54 can have a different thickness than the work function adjustment layer subsequently formed on the semiconductor layer 52, which is beneficial, for example, when the semiconductor layer 54 and the semiconductor layer 52 are used to form n-type nano-FETs and p-type nano-FETs, respectively. However, for any suitable purpose, the disclosed process can be used to establish film layers of different thicknesses in different areas. The first gate electrode layer 102A can be recessed by a suitable process, such as etching including diluted HF, H2SO4, etc. or a combination thereof. In some embodiments, a portion of the first gate electrode layer 102A above the semiconductor layer 54 is removed. In some embodiments, a portion of the first gate electrode layer 102A above the semiconductor layer 52 is recessed or removed while the semiconductor layer 54 is masked.

[0152] Fig.25A and Fig.25B The photoresist 500 and sacrificial film 200 are shown removed over the semiconductor layer 52. The photoresist 500 and sacrificial film 200 may be removed so that subsequent layers of the gate electrode 102 may be formed on the semiconductor layers 52 and 54 (see below). Figures 26A-27D ). The photoresist 500 may be removed by any suitable process, such as ashing. The sacrificial film 200 may be removed by the same method as described above. FIG. 23A to FIG. 23BThe removal process is substantially similar to the above. The removal efficiency can be improved by having spaces between the semiconductor layer 52, such as the gaps 350 and / or the pores 450, for example, by increasing the contact area of ​​the etching chemical. This can increase the etching process margin by 50% and can avoid over-etching that may damage the main device structure, such as the gate dielectric layer 100 or the semiconductor layer 52. In some embodiments, the residue of the sacrificial film 200 remains on the first gate electrode layer 102A or diffuses into the first gate electrode layer 102A. In some embodiments, the sacrificial film 200 includes Al2O3, and the residue of Al2O3 is about 2g / cm 3 Up to about 4g / cm 3 The density of MgO remains in the first gate electrode layer 102A.

[0153] Fig.26A and Fig.26B A second gate electrode layer 102B, such as a liner or work function adjustment layer, is shown formed on the semiconductor layers 52 and 54. Due to the recessed etching or removal of a portion of the first gate electrode layer 102A on the semiconductor layer 54 (see above Fig.24A and Fig. 24B ), the work function adjustment layers on the semiconductor layers 52 and 54 can have different thicknesses and / or compositions. This can allow the work function of the gate electrodes on the semiconductor layers 52 and 54 to be adjusted relative to different underlying semiconductor materials (e.g., Si and SiGe), or relative to forming different devices (e.g., NMOS and PMOS devices). For NMOS devices, the work function can be adjusted to be close to the conduction band of silicon or SiGe, while for PMOS devices, the work function can be adjusted to be close to the valence band of silicon or SiGe to improve the performance of the transistor.

[0154] In some embodiments, the second gate electrode layer 102B includes TiN, GaN, La, etc. and / or a combination thereof. The second gate electrode layer 102B may be formed by deposition, such as a conformal deposition method such as ALD, CVD, PVD, etc. The thickness of the second gate electrode layer 102B may be in the range of about 20 nanometers to about 500 nanometers. FIG. 18A to FIG. 26B The process shown in FIG. 5 is repeated for a plurality of cycles, which can form gate electrode layers, such as work function adjustment layers, having different thicknesses on the semiconductor layer 52 and the semiconductor layer 54 .

[0155] Fig.27A , Fig.27B , Fig.27C and Fig.27D FIG. 27C shows a process of forming a gate electrode filling material 102C (also referred to as a filling material 102C) on the first and / or second gate electrode layers 102A and 102B, thereby forming the gate electrode 102. Fig.27A A detailed view of regions 202 and 204, Fig.27D Show Fig.27B Detailed views of regions 206 and 208 of the gate electrode 100 are shown in FIG. 1 . The gate electrode filling material 102C is deposited over the gate dielectric layer 100 and the previously formed gate electrode layers (e.g., 102A and 102B), respectively, filling the remainder of the second recess 98 and forming the gate electrode 102. The gate electrode filling material 102 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, etc., combinations thereof, or multilayers thereof. Any combination of film layers constituting the gate electrode 102 may be deposited in the n-type region 50N between adjacent second semiconductor layers 54 and between the second semiconductor layer 54A and the substrate 50, and any combination of film layers constituting the gate electrode 102 may be deposited in the p-type region 50P between adjacent first semiconductor layers 52 and between the first semiconductor layer 52A and the substrate 50. Individual layers of the gate electrode filling material 102 and / or filling materials may be formed separately in each region, such as the n-type region 50N and the p-type region 50P. When using different processes to form the various layers and / or filling materials of the gate electrode filling material 102 in each region, various masking steps may be used, such as those described above with reference to FIG. 19A to FIG. 24B Describe the steps to mask and uncover the appropriate areas.

[0156] The gate dielectric layer 100 may be formed in the n-type region 50N and the p-type region 50P at the same time, so that the gate dielectric layer 100 in each region is formed of the same material, and the gate electrode 102 may be formed at the same time, so that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region may be formed by different processes, so that the gate dielectric layer 100 may be a different material and / or have a different number of film layers, and / or the gate electrode 102 in each region may be formed by different processes, so that the gate electrode 102 may be a different material and / or have a different number of film layers. When using different processes, various masking steps may be used to shield and expose appropriate regions.

[0157] After filling the second recess 98, a planarization process such as CMP may be performed to remove excess portions of the gate dielectric layer 100 and the gate electrode 102 material that are above the top surface of the first ILD 96. The gate electrode 102 and the remaining portions of the gate dielectric layer 100 material thus form a replacement gate structure for the resulting nano-FETs. The gate electrode 102 and the gate dielectric layer 100 may be collectively referred to as a "gate structure."

[0158] exist Figure 28A-28CIn the embodiment, the second ILD 106 is deposited over the first ILD 96. In some embodiments, the second ILD 106 is a flowable film formed by a flow-type CVD method. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD, PECVD, etc. According to some embodiments, before forming the second ILD 106, the gate stack (including the gate dielectric layer 100 and the corresponding overlying gate electrode 102) is recessed so that a recess is formed directly above the gate structure and between the two side portions of the first spacer 81. A gate mask 104 including one or more layers of dielectric material (such as silicon nitride, silicon oxynitride, etc.) is filled in the above-mentioned recess, and then a planarization process is performed to remove the excess portion of the dielectric material extending over the first ILD 96. A subsequently formed gate contact (eg, contact 112 , discussed below with respect to FIGS. 30A and 30B ) passes through the gate mask 104 to contact the recessed top surface of the gate electrode 102 .

[0159] exist Figure 29A-29C In the embodiment of the present invention, the second ILD 106, the first ILD 96, the CESL 94, and the gate mask 104 are etched to form a third recess 108, and the third recess 108 exposes the surface of the epitaxial source / drain region 92 and / or the gate structure. The third recess 108 can be formed by using an anisotropic etching process such as RIE, NBE, etc. In some embodiments, the third recess 108 can be etched through the second ILD 106 and the first ILD 96 using a first etching process, and then the third recess 108 can be etched through the CESL 94 using a second etching process. A mask, such as a photoresist, can be formed on the second ILD 106 and patterned, and mask portions of the second ILD 106 during the first etching process and the second etching process. In some embodiments, the etching process may over-etch, so that the third recess 108 extends into the epitaxial source / drain region 92, and the bottom of the third recess 108 may be flush with the epitaxial source / drain region 92 (e.g., at the same height, or the same distance from the substrate), or lower than the epitaxial source / drain region 92 (e.g., closer to the substrate).

[0160] After forming the third recess 108, a silicide region 110 is formed above the epitaxial source / drain region 92. In some embodiments, the step of forming the silicide region 110 includes: first, by depositing a metal (not shown) that can react with the semiconductor material (e.g., silicon, silicon germanium, germanium) of the underlying epitaxial source / drain region 92, to form a silicide or germanide region on the exposed portion of the epitaxial source / drain region 92, and then performing a thermal annealing process to form the silicide region 110, the above metal is, for example, nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals or alloys thereof. Thereafter, the unreacted portion of the deposited metal is removed, for example, by an etching process. Although the silicide region 110 is referred to as a silicide region, the silicide region 110 may also be a germanide region or a silicon germanide region (e.g., a region including silicide and germanide). In one embodiment, the silicide region 110 includes TiSi and has a thickness between about 2 nanometers and about 10 nanometers.

[0161] Continue, in Figure 30A-Figure 30C In the third recess 108, a contact 112 (also referred to as a contact plug) is formed. The contact 112 may include one or more layers, such as a barrier layer, a diffusion layer, and a filling material. For example, in some embodiments, the contact 112 includes a barrier layer and a conductive material, and is electrically coupled to the conductive component below (for example, in the embodiment shown, the gate structure 102 and / or the silicide region 110). The contact 112 electrically coupled to the gate structure 102 may be referred to as a gate contact, and the contact 112 electrically coupled to the silicide region 110 may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 106.

[0162] Some embodiments of the present disclosure can achieve some advantages. For example, the embodiments discussed above provide gap filling techniques, such as atomic layer deposition (ALD) processes to form sacrificial films, and can reduce over-etching that may occur during the removal process of the sacrificial film, which may cause unexpected and undesirable damage to the main structure of the device. Deposition processes such as ALD processes provide gap filling techniques, which form internal gaps, such as voids or pores, in the sacrificial film. The contact area of ​​the etching chemical can be increased by the internal voids or pores while retaining the gap filling characteristics of the sacrificial film, thereby increasing the etching process margin and etching rate for removing the sacrificial film. The self-formation of the void can be triggered by applying a thermal treatment, and / or the self-formation of the internal pores can be triggered by precursor purge control. The embodiments disclosed above can be incorporated into a semiconductor process flow with little or no impact on the integrated process.

[0163] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a multilayer stack in a channel region, the multilayer stack comprising alternating layers of a first multilayer and a second multilayer, the first multilayer comprising a first semiconductor material, and the second multilayer comprising a second semiconductor material; removing the second multilayer from the multilayer stack, the remaining first multilayer comprising a first semiconductor layer of the first semiconductor material and a second semiconductor layer of the first semiconductor material; forming a sacrificial film on the first semiconductor layer and the second semiconductor layer, the sacrificial film filling an area between the first semiconductor layer and the second semiconductor layer; forming a gap in the sacrificial film between the first semiconductor layer and the second semiconductor layer; removing the sacrificial film; and forming a gate stack on the channel region.

[0164] In some embodiments, the step of forming the spacers includes forming the voids by heat treatment.

[0165] In some embodiments, the heat treatment is performed at a temperature of 400°C to 800°C.

[0166] In some embodiments, the step of forming the spacers includes forming the plurality of pores by purging a precursor of the sacrificial film with H 2 O.

[0167] In some embodiments, the sacrificial film includes Al2O3.

[0168] In some embodiments, the sacrificial film is formed by performing an atomic layer deposition (ALD) process at a temperature less than about 350° C.

[0169] In some embodiments, after removing the sacrificial film, a work function adjustment layer is formed on the first semiconductor layer and the second semiconductor layer.

[0170] In some embodiments, the channel region is part of a gate-all-around transistor.

[0171] According to some other embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a first multilayer stack in a first region on a substrate, and forming a second multilayer stack in a second region on the substrate, the first multilayer stack including various layers of the second semiconductor layer, and the second multilayer stack including various layers of the first semiconductor layer; forming and removing a sacrificial film, wherein the steps of forming and removing the sacrificial film include: depositing a sacrificial film on the first multilayer stack and the second multilayer stack, wherein the sacrificial film fills a first gap between the various second semiconductor layers of the first multilayer stack, and fills a second gap between the various second semiconductor layers of the first multilayer stack; forming a first plurality of intervals in the sacrificial film between the various second semiconductor layers of the first multilayer stack, and forming a second plurality of intervals between the various first semiconductor layers of the second multilayer stack; forming a mask layer on the sacrificial film; patterning and removing the mask layer in the first region; removing the sacrificial film on the first multilayer stack; removing the mask layer in the second region; and removing the sacrificial film on the second multilayer stack; and forming separate gate electrodes on the first multilayer stack and the second multilayer stack.

[0172] In other embodiments, each of the first plurality of intervals and the second plurality of intervals includes a respective air gap.

[0173] In other embodiments, each of the first plurality of compartments and the second plurality of compartments includes a respective plurality of apertures.

[0174] In other embodiments, the step of forming individual gate electrodes also includes: forming a first layer on each second semiconductor layer of the first multilayer stack and each first semiconductor layer of the second multilayer stack; removing a portion of the first layer on each second semiconductor layer of the first multilayer stack; and forming a second layer on each second semiconductor layer of the first multilayer stack and each first semiconductor layer of the second multilayer stack.

[0175] In other embodiments, forming the first layer is performed before depositing the sacrificial film, removing a portion of the first layer on the first multilayer stack is performed after removing the sacrificial film on the first multilayer stack, and forming the second layer is performed after removing the sacrificial film on the second multilayer stack.

[0176] In other embodiments, the first layer includes a first work function adjusting layer, and the second layer includes a second work function adjusting layer.

[0177] In some other embodiments, the method further includes performing a plurality of cycles of forming and removing the sacrificial film.

[0178] In other embodiments, it also includes forming a first work function adjustment layer having a first thickness on each second semiconductor layer of the first multilayer stack, and forming a second work function adjustment layer having a second thickness on each first semiconductor layer of the second multilayer stack, wherein the second thickness is greater than the first thickness.

[0179] In some other embodiments, the step of depositing the sacrificial film comprises an atomic layer deposition process.

[0180] In other embodiments, the sacrificial film consists essentially of Al2O3.

[0181] According to some other embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a semiconductor layer stack in a channel region; forming a gate dielectric around each semiconductor layer of the semiconductor layer stack; depositing a sacrificial layer on the semiconductor layer stack, the sacrificial layer comprising Al2O3; forming a gap in the sacrificial layer between each semiconductor layer of the semiconductor layer stack; removing the sacrificial layer; and forming a work function adjustment layer around the gate dielectric, the work function adjustment layer comprising La or TiN, the work function adjustment layer having Al2O3 remaining in the sacrificial layer.

[0182] In some other embodiments, the density of Al2O3 in the work function adjustment layer is 2 g / cm 3 Up to 4g / cm 3 range.

[0183] The above summarizes the components of several embodiments so that those skilled in the art can better understand the concepts of the embodiments of the present invention. Those skilled in the art should understand that they can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined as defined by the attached claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a multilayer stack in a channel region, the multilayer stack comprising alternating layers of a first multilayer and a second multilayer, the first multilayer comprising a first semiconductor material and the second multilayer comprising a second semiconductor material; removing the second multilayer from the multilayer stack, the remaining first multilayer comprising a first semiconductor layer of the first semiconductor material and a second semiconductor layer of the first semiconductor material; forming a sacrificial film on the first semiconductor layer and the second semiconductor layer, wherein the sacrificial film fills a region between the first semiconductor layer and the second semiconductor layer; forming a space in the sacrificial film between the first semiconductor layer and the second semiconductor layer, wherein the step of forming the space comprises forming a plurality of pores by performing H2O purging on a precursor of the sacrificial film; removing the sacrificial film; and A gate stack is formed on the channel region.

2. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the step of forming the spacer comprises forming a gap by a heat treatment.

3. The method for manufacturing a semiconductor device according to claim 2, wherein the heat treatment is performed at a temperature of 400°C to 800°C.

4. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the sacrificial film comprises Al2O3. 5 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein the sacrificial film is formed by performing an atomic layer deposition process at a temperature less than 350° C. 6 . The method for manufacturing a semiconductor device as claimed in claim 1 , further comprising forming a work function adjustment layer on the first semiconductor layer and the second semiconductor layer after removing the sacrificial film.

7. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the channel region is a portion of a fully wrapped gate transistor.

8. A method for manufacturing a semiconductor device, comprising: forming a first multilayer stack in a first region on a substrate and forming a second multilayer stack in a second region on the substrate, the first multilayer stack comprising respective layers of the plurality of second semiconductor layers and the second multilayer stack comprising respective layers of the plurality of first semiconductor layers; A sacrificial film is formed and removed, wherein the steps of forming and removing the sacrificial film include: Depositing the sacrificial film on the first multilayer stack and the second multilayer stack, wherein the sacrificial film fills a plurality of first gaps between the second semiconductor layers of the first multilayer stack and fills a plurality of second gaps between the second semiconductor layers of the first multilayer stack; forming a first plurality of spacers in the sacrificial film between respective second semiconductor layers of the first multilayer stack, and forming a second plurality of spacers between respective first semiconductor layers of the second multilayer stack; forming a mask layer on the sacrificial film; patterning and removing the mask layer in the first region; removing the sacrificial film on the first multilayer stack; removing the mask layer in the second region; and removing the sacrificial film on the second multilayer stack; and A plurality of respective gate electrodes are formed on the first multi-layer stack and the second multi-layer stack. 9 . The method of fabricating a semiconductor device as claimed in claim 8 , wherein each of the first plurality of spaces and the second plurality of spaces comprises a respective air gap.

10. The method of fabricating a semiconductor device as claimed in claim 8, wherein each of the first plurality of spaces and the second plurality of spaces comprises a respective plurality of voids.

11. The method for manufacturing a semiconductor device according to claim 8, wherein the step of forming a plurality of said individual gate electrodes further comprises: forming a first layer on each second semiconductor layer of the first multilayer stack and each first semiconductor layer of the second multilayer stack; removing portions of the first layer on each second semiconductor layer of the first multilayer stack; as well as A second layer is formed on each second semiconductor layer of the first multi-layer stack and each first semiconductor layer of the second multi-layer stack.

12. A method for manufacturing a semiconductor device as described in claim 11, wherein forming the first layer is performed before depositing the sacrificial film, removing a portion of the first layer on the first multilayer stack is performed after removing the sacrificial film on the first multilayer stack, and forming the second layer is performed after removing the sacrificial film on the second multilayer stack. 13 . The method for manufacturing a semiconductor device according to claim 11 , wherein the first layer comprises a first work function adjusting layer, and the second layer comprises a second work function adjusting layer.

14. The method of manufacturing a semiconductor device according to claim 8, further comprising performing a plurality of cycles of forming and removing the sacrificial film.

15. The method for manufacturing a semiconductor device as described in claim 14 further includes forming a first work function adjustment layer having a first thickness on each second semiconductor layer of the first multilayer stack, and forming a second work function adjustment layer having a second thickness on each first semiconductor layer of the second multilayer stack, wherein the second thickness is greater than the first thickness.

16. The method for manufacturing a semiconductor device as claimed in claim 8, wherein the step of depositing the sacrificial film comprises an atomic layer deposition process.

17. The method for manufacturing a semiconductor device as claimed in claim 8, wherein the sacrificial film is mainly composed of Al2O3.

18. A method for manufacturing a semiconductor device, comprising: forming a semiconductor layer stack in a channel region; forming a gate dielectric around each semiconductor layer of the semiconductor layer stack; Depositing a sacrificial layer on the semiconductor layer stack, the sacrificial layer comprising Al2O3; forming a plurality of gaps in the sacrificial layer between respective semiconductor layers of the semiconductor layer stack; removing the sacrificial layer; as well as A work function adjustment layer is formed around the gate dielectric, the work function adjustment layer comprising La or TiN, and the work function adjustment layer has Al2O3 remaining in the sacrificial layer.

19. The method for manufacturing a semiconductor device according to claim 18, wherein the density of Al2O3 in the work function adjustment layer is 2 g / cm 3 Up to 4g / cm 3 range.

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