Microelectronic devices including wafer-level packaging

Abstract

The present invention relates to a microelectronic device including wafer-level packaging, which includes an interposer having a first surface and a second surface opposite to the first surface, wherein the interposer includes a redistribution layer, and the redistribution layer includes a first passivation layer located on the first surface and a second passivation layer located on the second surface; at least one chip is mounted on the first passivation layer on the first surface through a plurality of first bumps penetrating the first passivation layer; a molding compound is arranged on the first surface and covers the upper surface of the chip and the first passivation layer; and a plurality of welding bumps are arranged on the second passivation layer on the second surface.

Description

[0001] Divisional Application Information

[0002] This application is a divisional application of the invention patent application with the application date of November 5, 2015, application number 201510744361.1, and invention name “Microelectronic device including wafer-level packaging”. Technical Field

[0003] The present invention relates to the field of semiconductor packaging, and in particular to a wafer level package (WLP) with a substrate-less or through silicon via (TSV)-free interposer and a manufacturing method thereof. Background Art

[0004] As semiconductor manufacturing technology advances, the size of microelectronic devices becomes smaller and the circuits in the devices become more dense. In order to obtain smaller microelectronic devices, their packaging and the structure mounted on the circuit board must become more compact.

[0005] Fan-out wafer-level packaging (FOWLP), which is well known in the field of semiconductor packaging, redistributes the pads of the original semiconductor die to a larger area through a redistribution layer (RDL) located on a substrate, such as a substrate with through-silicon vias (TSV).

[0006] The redistribution layer is a stack of dielectric layers and metal conductors formed on the surface of the wafer, which re-wires the original input / output (I / O) pads of the chip to a layout range with looser spacing. The above-mentioned redistribution is usually made of thin film polymers, such as benzocyclobutene (BCB), polyimide (PI), or other organic polymers as dielectric layer materials, and then metallization processes such as aluminum or copper are used to form metal conductors to re-wire the pads around the chip into an array of connection pads.

[0007] Due to the complicated process, the cost of the interposer substrate with through-silicon vias is relatively high. Therefore, fan-out wafer-level packaging using an interposer with through-silicon vias will also be relatively expensive and not conducive to specific applications. Summary of the invention

[0008] According to one embodiment of the present invention, there is provided a microelectronic device, comprising: a redistribution layer, comprising a first passivation material on a first side and a second passivation material on an opposite second side; a bump pad and an additional bump pad, wherein the bump pad is embedded on the first side within the redistribution layer, and the additional bump pad is embedded on the opposite second side within the redistribution layer; at least one die is mounted on the bump pad via a first bump penetrating through the first passivation material, the first bump comprising a single element in direct contact with the at least one die and the bump pad; a dielectric cover material directly between the additional bump pad and the second passivation material, the additional bump pad being embedded on the second side of the redistribution layer; An additional bump pad is isolated from the second passivation material by the dielectric cover material; an organic dielectric material, which is located on the second passivation material, and the thickness of the organic dielectric material is greater than the thickness of each of the dielectric cover material and the second passivation material; and a second bump, which is mounted on the additional bump pad, the second bump penetrates each of the dielectric cover material, the second passivation material and the organic dielectric material, and the second bump is separated from each other by the dielectric cover material, the second passivation material and each of the organic dielectric material, and the lateral side surfaces of each of the dielectric cover material, the second passivation material and the organic dielectric material are coplanar with each other.

[0009] According to an embodiment of the present invention, there is provided a microelectronic device, comprising: a redistribution layer, comprising a metal segment, wherein the metal segment is embedded in a dielectric material, wherein outer surfaces of the metal segment and the dielectric material are coplanar with each other on each of two opposite sides of the redistribution layer; a barrier material, wherein the barrier material is in direct contact with the metal segment and the dielectric material on the two opposite sides of the redistribution layer; a passivation material, wherein the passivation material is in direct contact with the barrier material, wherein the barrier material isolates the metal segment from the passivation material on the two opposite sides of the redistribution layer; and an organic material, wherein the organic material is in direct contact with the passivation material on one of the two opposite sides of the redistribution layer. direct contact, the thickness of the organic material being greater than the combined thickness of the barrier material and the passivation material; a solder bump, the solder bump being mounted on a first portion of the metal segment and penetrating each of the organic material, the passivation material and the barrier material; at least one grain, the at least one grain being located on a side of the redistribution layer opposite to the organic matter; and a microbump, which includes a single conductive reflow metal material, the single conductive reflow metal material being directly located between the at least one grain and the second portion of the metal segment, the microbump penetrating each of the passivation material and the barrier material and in direct contact with each of the passivation material and the barrier material.

[0010] Undoubtedly, those skilled in the art will understand the purpose of the present invention after reading the following detailed description of the preferred embodiments of the present invention and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1 to 9 FIG. 1 is a schematic cross-sectional view of a method for fabricating a wafer level package (WLP) using an interposer without a substrate or a through silicon via according to an embodiment of the present invention.

[0012] Fig.10 It is a schematic cross-sectional view of a wafer-level package according to a second embodiment of the present invention.

[0013] Figure 11 to Figure 13 It is a schematic cross-sectional view of the wafer-level package according to the third embodiment of the present invention. DETAILED DESCRIPTION

[0014] The following detailed description shall refer to the contents shown in the relevant drawings to illustrate embodiments that can be implemented according to the present invention. These embodiments provide sufficient details to enable those skilled in the art to fully understand and implement the present invention. Structural, logical and electrical modifications can be made to other embodiments without departing from the scope of the present invention.

[0015] Therefore, the following detailed description is not intended to limit the present invention. The scope of the present invention is defined by the claims. Anything equivalent to the claims of the present invention should also fall within the scope of the present invention.

[0016] The following description must refer to the relevant drawings for a thorough understanding of the present invention, wherein the same or similar features are generally described with the same reference numerals, and the structures described are not necessarily drawn to scale. In this specification, "die", "semiconductor chip" and "semiconductor die" have the same meaning and can be used interchangeably.

[0017] In this specification, "wafer" and "substrate" refer to any structure including an exposed surface on which materials can be deposited according to the embodiments of the present invention to form integrated circuit structures, such as redistribution layers (RDL). It should be understood that "substrate" includes semiconductor wafers, but is not limited to them. "Substrate" in the process also means a semiconductor structure including material layers formed thereon.

[0018] Please refer to Figures 1 to 9 , is a schematic cross-sectional view of a method for fabricating a wafer-level package (WLP) using a substrate-free or through-silicon-via-free interposer according to an embodiment of the present invention.

[0019] like Figure 1As shown, a carrier 300 is prepared. The carrier 300 may be, for example, a wafer-shaped glass substrate, including an adhesive layer or a release layer 302 stacked on the upper surface of the glass substrate. The release layer 302 includes at least one passivation layer 310. The passivation layer 310 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride. Next, a dielectric cap layer or a dielectric barrier layer 312 is deposited on the passivation layer 310 in an all-round manner. The dielectric barrier layer 312 may include a material having a function of preventing copper diffusion, such as silicon nitride, but is not limited thereto.

[0020] like Figure 2 As shown, an interlayer dielectric layer (ILD) 314 is then disposed over the dielectric barrier layer 312. The interlayer dielectric layer 314 may include silicon oxide, borosilicate glass, borophosphosilicate glass, or a dielectric material with a low dielectric constant known in the art. Next, a copper damascene process is performed to form a damascene copper layer 402 in the interlayer dielectric layer 314. Then, a dielectric barrier layer 316 is deposited over the interlayer dielectric layer 314 and the damascene copper layer 402.

[0021] The copper inlay process is a prior art in the art. For example, forming an inlay copper layer 402 in the interlayer dielectric layer 314 includes the following steps. First, a photolithography process and an etching process are performed to form a groove in the interlayer dielectric layer 314. Next, a metal barrier layer and a copper layer are deposited in the groove. Then, a chemical mechanical polishing process is used to remove the excess portion of the deposited metal. The inlay copper layer 402 becomes the first metal layer (M1) of the interposer with a redistribution layer.

[0022] Please refer to Figure 3 Then, proceed as follows Figure 2 The copper damascene process described herein forms a redistribution layer (RDL) 410 on the passivation layer 310. For example, the redistribution layer 410 may include a four-layer metal (M1-M4 / V1-V3) structure formed by the copper damascene process. It should be understood that the formation of the four-layer metal structure is only for illustrative purposes. In some embodiments, a structure including only one or two layers of metal may also be used according to different design requirements.

[0023] The redistribution layer 410 may include a dielectric layer stack, including a passivation layer 310, a dielectric barrier layer 312, an interlayer dielectric layer 314, a dielectric barrier layer 316, an interlayer dielectric layer 322, a dielectric barrier layer 324, an interlayer dielectric layer 326, a dielectric barrier layer 328, an interlayer dielectric layer 330, and a dielectric barrier layer 332. In the dielectric layer stack, damascene copper layers 402, 404, 406, 408 and dielectric plugs 401, 403, 405 are disposed. The dielectric plugs 401, 403, 405 penetrate through the respective dielectric barrier layers 316, 324, 328 and are electrically connected to the damascene copper layer below the dielectric barrier layer.

[0024] According to the first embodiment, the inlaid copper layer 408 may include a plurality of bump pads 408a exposed from the upper surface of the interlayer dielectric layer 330. The bump pads 408a are disposed in the chip mounting region. At this time, the inlaid copper layer 408 and the interlayer dielectric layer 330 are covered by a top dielectric barrier layer 332.

[0025] like Figure 4 As shown, a passivation layer 510 is then disposed over the top dielectric barrier layer 332. The passivation layer 510 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride. It should be understood that the passivation layer 510 may also include organic materials, such as polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), or other similar materials. Then, a plurality of bumps 418, such as microbumps, may be formed on the bump pads 408a for subsequent connection. For example, openings are formed in the passivation layer 510 and the top dielectric barrier layer 332 using a photolithography process and an etching process to expose individual bump pads 408a. Then, an under-bump metal (UBM) may be formed in the opening, and then solder bumps or solder balls may be formed on the individual bump pads 408a.

[0026] like Figure 5 As shown, after the bumps 418 are formed, individual flip-chip chips or dies 420 are mounted on the redistribution layer 410 through the bumps 418 with the active surface facing downward to the redistribution layer 410, forming a "chip-to-wafer bonding" (C2W) stacked structure. These individual flip-chip chips or dies 420 are active integrated circuit chips with specific functions, such as a graphics processing unit (GPU), a central processing unit (CPU), a memory chip, etc. After the above steps are completed, a primer 421 can be selectively filled under each chip or die 420. Then, a heat treatment is performed to reflow the bumps 418.

[0027] like Figure 6 As shown, after the die bonding is completed, a molding compound 500 is then covered on the top. The molding compound 500 covers the upper surface of the mounted chip 420 and the redistribution layer 410. The molding compound 500 is then cured by a curing process. The molding compound 500 is, for example, a mixture of epoxy resin and silicon dioxide filler, but is not limited thereto. The upper portion of the molding compound 500 can be selectively polished and removed to expose the upper surface of the chip 420.

[0028] like Figure 7As shown, after the molding material 500 is formed, the carrier 300 is peeled off to expose the passivation layer 310, and the interposer 301 without TSV including the redistribution layer 410 is formed. The release layer 302 is also removed to expose the lower surface of the passivation layer 310. The carrier 300 can be peeled off by laser peeling technology or ultraviolet irradiation technology, but is not limited thereto. When peeling off the carrier 300, another temporary carrier (not shown) can be provided and fixed on the molding material 500.

[0029] Afterwards, if Figure 8 As shown, after the carrier 300 is stripped, openings are then formed in the passivation layer 310 and the dielectric barrier layer 312 to expose the individual pads 402a, and then solder bumps or solder balls 520 are formed on the individual pads 402a. In some embodiments, an under-bump metallization layer (UBM) 518 may be formed in the opening before the solder balls 520 are formed.

[0030] Afterwards, if Fig. 9 As shown, a dicing process is performed to separate individual wafer-level packages 10. For example, before dicing, the wafer-level package 10 may be fixed on the dicing tape 600 with the solder balls 520 facing the dicing tape 600, wherein the solder balls 520 may contact the dicing tape 600. It should be understood that although Fig. 9 Each wafer-level package 10 includes two chips. In some embodiments, each wafer-level package 10 may include only one chip.

[0031] Fig.10 FIG. 1 is a schematic cross-sectional view of a wafer-level package according to a second embodiment of the present invention. Fig. 9 The difference between the wafer level package 10 is that Fig.10 The wafer-level package 10 a shown includes a plurality of openings 310 a , 310 b and 310 c above the pad 402 a , which can release the stress caused by the solder balls 520 .

[0032] Figure 11 to Figure 13 Schematic cross-sectional view of wafer-level packaging according to the third embodiment of the present invention. Fig.11 After forming the molding material 500, the steps similar to the above-mentioned embodiment are performed to peel off the carrier 300, so that the passivation layer 310 is exposed, and the interposer 301 without TSV including the redistribution layer 410 is formed. The release layer 302 is also removed to expose the lower surface of the passivation layer 310. The carrier 300 can be peeled off by laser peeling technology or ultraviolet irradiation technology, but is not limited thereto. When peeling off the carrier 300, another temporary carrier (not shown) can be provided and fixed on the molding material 500.

[0033] According to the third embodiment, when a solder ball with a relatively large size is to be formed, such as a ball grid array solder ball with a size greater than 200 micrometers (μm), an organic dielectric layer 610 is first formed on the exposed lower surface of the passivation layer 310. According to the embodiment, the organic dielectric layer 610 may include polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), or other similar materials.

[0034] like Fig.12 As shown, after the deposition of the organic dielectric layer 610 is completed, openings 610a are then formed in the organic dielectric layer 610, the passivation layer 310 and the dielectric barrier layer 312 to expose the individual pads 402a.

[0035] like Fig.13 As shown, solder bumps or solder balls 520 are then formed on the respective pads 402a. In some embodiments, an under bump metallurgy (UBM) 518 may be formed in the opening 610a before the solder balls 520 are formed.

[0036] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A microelectronic device comprising: a redistribution layer comprising a first passivation material on a first side and a second passivation material on an opposing second side; a bump pad and an additional bump pad, the bump pad being embedded within the redistribution layer on the first side and the additional bump pad being embedded within the redistribution layer on the opposing second side; at least one die mounted on the bump pad via a first bump extending through the first passivation material, the first bump comprising a single element in direct contact with the at least one die and the bump pad; a dielectric cover material directly between the additional bump pad and the second passivation material, the additional bump pad being isolated from the second passivation material by the dielectric cover material; an organic dielectric material disposed on the second passivation material, the organic dielectric material having a thickness greater than a thickness of each of the dielectric cap material and the second passivation material; and A second bump is mounted on the additional bump pad, the second bump is separated from each other by each of the dielectric cover material, the second passivation material and the organic dielectric material, and the second bump penetrates each of the dielectric cover material, the second passivation material and the organic dielectric material, and the lateral side surfaces of each of the dielectric cover material, the second passivation material and the organic dielectric material are coplanar with each other. 2 . The microelectronic device of claim 1 , further comprising a molding compound in contact with sidewalls of the at least one die and an outer surface of the first passivation material on the first side of the redistribution layer. 3 . The microelectronic device of claim 1 , wherein the bump pad and the additional bump pad comprise metal segments embedded in a dielectric material of the redistribution layer, the metal segments and an outer surface of the dielectric material being coplanar with each other.

4. The microelectronic device according to claim 3, wherein: A thickness of each of the metal segments and a thickness of the dielectric material of the redistribution layer closest to the organic dielectric material are substantially equal to one another. 5 . The microelectronic device of claim 1 , further comprising an additional dielectric cover material separating the bump pad from the first passivation material, wherein the first bump is in direct contact with each of the additional dielectric cover material and the first passivation material. 6 . The microelectronic device of claim 1 , wherein the second bumps are relatively larger than respective first bumps, the second bumps having a diameter equal to or greater than approximately 200 microns. 7 . The microelectronic device of claim 1 , wherein the second bump is operatively connected to the at least one die only through the redistribution layer.

8. The microelectronic device of claim 1, wherein an active side of the at least one die faces the redistribution layer.

9. The microelectronic device of claim 1, wherein at least some of the bump pads are vertically aligned with the additional bump pads. 10 . The microelectronic device according to claim 1 , further comprising an under bump metallurgy (UBM) adjacent to the second bump, each of the dielectric capping material, the second passivation material, and the organic dielectric material being in direct contact with a surface of the UBM.

11. A microelectronic device comprising: a redistribution layer comprising a metal segment embedded in a dielectric material, the metal segment and an outer surface of the dielectric material being coplanar with each other on each of two opposing sides of the redistribution layer; a barrier material in direct contact with the metal segments and the dielectric material on the two opposing sides of the redistribution layer; a passivation material in direct contact with the barrier material, the barrier material isolating the metal segments from the passivation material on the two opposing sides of the redistribution layer; an organic material in direct contact with the passivation material on one of the two opposing sides of the redistribution layer, the organic material having a thickness greater than a combined thickness of the barrier material and the passivation material; a solder bump mounted on the first portion of the metal segment and extending through each of the organic material, the passivation material, and the barrier material; at least one grain, the at least one grain being located on a side of the redistribution layer opposite the organic material; as well as A microbump includes a single conductive reflow metal material directly between the at least one die and the second portion of the metal segment, the microbump penetrating through and in direct contact with each of the passivation material and the barrier material. 12 . The microelectronic device of claim 11 , wherein the metal segments of the first portion are configured as bump pads of the solder bumps, and the metal segments of the second portion are configured as bump pads of the at least one die.

13. The microelectronic device of claim 11, wherein the metal segment of the first portion is directly between two portions of the barrier material and laterally flanked by the dielectric material of the redistribution layer. 14 . The microelectronic device according to claim 11 , further comprising a filling underfill material directly located between the at least one die and the passivation material, wherein the micro bump penetrates through the filling underfill material and is in direct contact with the filling underfill material.

15. The microelectronic device according to claim 11, wherein: Where not laterally isolated by barrier material, individual metal segments are laterally isolated from one another by the dielectric material.

16. The microelectronic device of claim 11, wherein the outer surface of the metal segment has a larger cross-sectional area relative to its lateral side surfaces.

17. The microelectronic device of claim 11, wherein the additional portions of the barrier material isolate individual portions of the dielectric material within the redistribution layer from one another, and wherein conductive vias extend through the additional portions of the barrier material.

18. The microelectronic device according to claim 17, wherein: The conductive via is laterally adjacent to the additional portion of the barrier material and the dielectric material of the redistribution layer without being laterally adjacent to the passivation material.

19. The microelectronic device of claim 11, wherein lateral boundaries of the barrier material, the passivation material, and the organic material are vertically aligned with one another along lateral side surfaces of the solder bump.

20. The microelectronic device of claim 11, wherein the passivation material comprises a single material layer comprising silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof, the material composition of the passivation material being different from the material composition of each of the barrier material of the redistribution layer and the dielectric material.

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