Luminous display panel

Abstract

The light-emitting display panel includes a transparent area corresponding to an area where a camera is provided. The transparent area includes: a first pixel circuit layer including a first pixel circuit; a second pixel circuit layer provided on the first pixel circuit layer, the second pixel circuit layer including a second pixel circuit; and a light-emitting device layer provided on the second pixel circuit layer, the light-emitting device layer including at least one light-emitting device. A driving transistor for controlling the amount of current flowing to the light-emitting device is included in at least one of the first pixel circuit layer and the second pixel circuit layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0173677, filed on December 24, 2019, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0003] The present disclosure relates to light-emitting display panels. Background Art

[0004] Since the light-emitting display apparatus displays an image by using a self-luminous device, the light-emitting display apparatus has a fast response time, low power consumption, and a good viewing angle, and thus, is attracting widespread attention as a next-generation display apparatus.

[0005] Each of the plurality of pixels of the light-emitting display panel configuring the light-emitting display device includes a pixel driving circuit. The pixel driving circuit controls the current level flowing from the driving power supply to the light-emitting device according to the switching of the driving transistor based on the data voltage, so that the light-emitting device can emit light. Therefore, the light-emitting display device displays a specific image.

[0006] In a light-emitting display panel, the current flowing in the light-emitting device of each pixel may vary based on the deviation of the threshold voltage of the driving transistor caused by the process deviation. Therefore, even when the same data voltage is supplied to the pixel driving circuit of the light-emitting display panel, the current output from the driving transistor may vary for each pixel, and due to this, uniform image quality may not be achieved. Therefore, an internal compensation circuit for compensating the threshold voltage of the driving transistor is included in each of the pixel driving circuits.

[0007] Recently, the resolution of the light-emitting display panel applied to the mobile electronic device, the virtual image display device or the head mounted display device has gradually increased. As the resolution of the light-emitting display panel gradually increases, the size of each pixel gradually decreases.

[0008] Therefore, it is difficult to form (or place) a pixel driving circuit including an internal compensation circuit in a pixel, and due to this, it is difficult to manufacture a high-resolution light-emitting display panel. Summary of the invention

[0009] Accordingly, the present disclosure is directed to providing a light emitting display panel that substantially obviates one or more problems due to limitations and disadvantages of the related art.

[0010] An aspect of the present disclosure is directed to providing a light emitting display panel in which a plurality of transistors configuring each of a plurality of pixel driving circuits are separately disposed at different layers.

[0011] Other advantages and features of the present disclosure will be described in part in the following description, and will become apparent to those of ordinary skill in the art after reading the following, or may be learned from the practice of the present disclosure. The purposes and other advantages of the present disclosure may be achieved and obtained by the structures specifically indicated in the written description and claims and the accompanying drawings.

[0012] To achieve these and other advantages, and in accordance with the purposes of the present disclosure, as embodied and broadly described herein, there is provided a light-emitting display panel including a transparent area corresponding to an area where a camera is disposed. The transparent area includes: a first pixel circuit layer including a first pixel circuit; a second pixel circuit layer disposed on the first pixel circuit layer, the second pixel circuit layer including a second pixel circuit; and a light-emitting device layer disposed on the second pixel circuit layer, the light-emitting device layer including at least one light-emitting device. A driving transistor for controlling the amount of current flowing to the light-emitting device is included in at least one of the first pixel circuit layer and the second pixel circuit layer.

[0013] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0015] Figure 1 is an exemplary diagram showing an external configuration of an electronic device to which a light-emitting display panel according to an embodiment of the present disclosure is applied;

[0016] Figure 2 is an exemplary diagram schematically showing a light-emitting display device to which a light-emitting display panel according to an embodiment of the present disclosure is applied;

[0017] Figure 3 is a circuit diagram of an embodiment of a pixel applied to a light-emitting display panel according to the present disclosure;

[0018] Figure 4 It shows that Figure 3 A circuit diagram showing an example in which a pixel driving circuit is divided into layer units;

[0019] Figure 5 It is shown Figure 4 A cross-sectional view of the layer structure of a pixel shown in FIG.

[0020] Figure 6 It is shown Figure 4 A diagram showing the circuit configuration of each layer;

[0021] Figure 7 It is shown Figure 4 An exemplary diagram of a first pixel circuit shown in FIG.

[0022] Figure 8 It is shown that Figure 7 An exemplary diagram of a layout of a first pixel circuit layer of a first pixel circuit shown in FIG.

[0023] Fig. 9 It is shown Figure 4 An exemplary diagram of a second pixel circuit shown in FIG.

[0024] Fig.10 It is shown that Fig. 9 An exemplary diagram of a layout of a second pixel circuit layer of a second pixel circuit shown in FIG.

[0025] Fig.11 is shown along Fig.10 An exemplary diagram of a cross-sectional surface taken along line D-D' shown in FIG.

[0026] Fig.12 is an exemplary diagram showing a plane of each pixel of a light-emitting display panel according to the present disclosure;

[0027] Fig.13 is an exemplary diagram showing a cross-sectional surface of a region including a plurality of pixel driving circuits in a light-emitting display panel according to the present disclosure;

[0028] Fig.14 is an exemplary diagram showing non-transmission areas and light-transmission areas repeatedly formed in a transparent area of ​​a light-emitting display panel according to the present disclosure;

[0029] Fig.15 It is shown Fig.14 An enlarged exemplary view of region Y is shown in FIG. DETAILED DESCRIPTION

[0030] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0031] The advantages and features of the present disclosure and its implementation methods will be explained by the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be interpreted as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and comprehensive, and will fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0032] The shapes, sizes, ratios, angles and quantities disclosed in the accompanying drawings for describing the embodiments of the present disclosure are examples only, and therefore, the present disclosure is not limited to the details shown. Throughout the text, the same reference numerals refer to the same elements. In the following description, when it is determined that the detailed description of the relevant known functions or configurations unnecessarily obscures the focus of the present disclosure, the detailed description will be omitted. In the case of using 'including', 'having' and 'comprising' described in this specification, other parts may be added unless 'only to' is used. Unless otherwise indicated, terms in the singular may include plural forms.

[0033] In interpreting an element, although there is no explicit description, the element is interpreted as including an error range.

[0034] In describing a positional relationship, for example, when the positional relationship between two parts is described as 'on', 'over', 'under', and 'immediately adjacent to', one or more other parts may be disposed between the two parts unless 'just' or 'directly' is used.

[0035] When describing a time relationship, for example, when a time order is described as 'after', 'after', 'next to', and 'before', discontinuous cases may be included unless 'just' or 'directly' is used.

[0036] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the present disclosure.

[0037] When describing the elements of the present disclosure, terms such as first, second, A, B, (a), (b) etc. may be used. Such terms are only used to distinguish the corresponding elements from other elements, and the corresponding elements are not limited by the terms in their essence, order or priority. It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it may be directly on or directly connected to another element or layer, or an intermediate element or layer may exist. In addition, it should be understood that when an element is arranged on or under another element, this may represent the situation where the element is arranged to directly contact each other, but may represent that the element is arranged not to directly contact each other.

[0038] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed elements. For example, the meaning of "at least one of a first element, a second element, and a third element" means the combination of all elements proposed from two or more of the first element, the second element, and the third element, as well as the first element, the second element, or the third element.

[0039] As can be fully understood by those skilled in the art, the features of the various embodiments of the present disclosure can be coupled or combined with each other in part or in whole, and can interoperate and be driven technically differently from each other. The embodiments of the present disclosure can be performed independently of each other, or can be performed together in a mutually dependent relationship.

[0040] Figure 1 is an exemplary diagram showing an external configuration of an electronic device to which a light-emitting display panel according to an embodiment of the present disclosure is applied, and Figure 2 is an exemplary diagram schematically illustrating a light-emitting display device to which a light-emitting display panel according to an embodiment of the present disclosure is applied.

[0041] The light-emitting display panel according to the embodiment of the present disclosure may configure an electronic device. The electronic device may include, for example, a smart phone, a tablet personal computer (PC), a television (TV), a monitor, etc. Figure 1 , a smartphone is shown as an example of an electronic device. In the following description, an example in which the electronic device is a smartphone will be described.

[0042] like Figure 1 and Figure 2 As shown in , the electronic device may include a light-emitting display device 10 having a light-emitting display panel 100 according to the present disclosure and a housing 20 covering the light-emitting display device 10 .

[0043] like Figure 1 and Figure 2As shown in , the light-emitting display device 10 to which the light-emitting display panel 100 according to the embodiment of the present disclosure is applied may include a display area AA displaying an image and a non-display area IA disposed outside the display area AA. The display area AA may include: a light-emitting display panel 100 including a transparent area AA1 and an opaque area AA2 disposed outside the transparent area AA1; a camera 600 disposed in the transparent area AA1 in the rear surface of the light-emitting display panel 100 and photographing an area in the forward direction of the light-emitting display panel 100; a gate driver 200 providing a scan control signal to a plurality of scan control lines included in the light-emitting display panel 100; a data driver 300 providing a data voltage to a plurality of data lines included in the light-emitting display panel 100; and a controller 400 controlling the driving of the camera 600, the gate driver 200, and the data driver 300.

[0044] The camera 600 may be provided between the housing 20 and the light-emitting display panel 100, and may be driven based on the control of the controller 400 or the control of an external system that controls the driving of the electronic device. The camera 600 may be provided in the rear surface of the organic light-emitting display panel 100, and may perform a function of photographing an area in a forward direction with respect to the light-emitting display panel 100. Here, the forward direction with respect to the light-emitting display panel 100 may refer to a direction in which the light-emitting display panel 100 displays an image.

[0045] The controller 400 may include: a data aligner, which realigns segments of input video data Idata transmitted from an external system by using a timing synchronization signal TSS transmitted from an external system to generate segments of pixel data Pdata, and provides the segments of pixel data Pdata to the data driver 300; and a control signal generator, which generates a gate control signal GCS and a data control signal DCS by using the timing synchronization signal TSS.

[0046] The data driver 300 may be equipped in a chip-on-film attached to the light-emitting display panel 100. The chip-on-film may be connected to a main board including the controller 400. In this case, the chip-on-film may include a plurality of wires electrically connecting the controller 400, the data driver 300, and the light-emitting display panel 100, and to this end, the wires may be electrically connected to a plurality of pads included in the light-emitting display panel 100 and the main board.

[0047] The data driver 300 may be connected to a plurality of data lines DL provided in the light-emitting display panel 100. The data driver 300 may convert pixel data Pdata provided from the controller 400 into analog data voltages by using a data control signal DCS and a plurality of reference gamma voltages, and may provide the converted data voltages to corresponding data lines DL.

[0048] The gate driver 200 may be configured as an integrated circuit (IC) and then may be mounted in the non-display area IA or may be directly embedded in the non-display area IA.

[0049] The gate driver 200 can generate an initialization control signal, a scanning control signal, and an emission control signal corresponding to the initialization period, the sampling period, and the emission period of each of the multiple pixels P based on the gate control signal GCS provided from the controller 400, and can provide the initialization control signal, the scanning control signal, and the emission control signal to the multiple pixels P.

[0050] The gate driver 200 according to the embodiment may generate emission control signals having the same period and sequentially shifted phases, and may provide the emission control signals to a plurality of emission control lines ECL.

[0051] The gate driver 200 according to an embodiment may be disposed in the left non-display area and / or the right non-display area of ​​the substrate through a process of manufacturing a thin film transistor (TFT) of each of the pixels P.

[0052] For example, the gate driver 200 may be disposed in a left non-display area of ​​the substrate, and may provide an emission control signal to one end of each of the emission control lines ECL based on a single feeding method.

[0053] As another example, the gate driver 200 may be disposed in each of left and right non-display areas of the substrate, and may provide the emission control signal to both ends of each of the emission control lines ECL based on a dual feeding method.

[0054] The external system may perform the functions of driving the controller 400 and the electronic device. That is, when the electronic device is a smart phone, the external system may receive various voice information, video information, and letter information through a wireless communication network, and may transmit the video information to the controller 400. In the following description, the video information transmitted from the external system to the controller 400 may be referred to as input video data. In addition, the external system may execute an application for controlling the camera 600. The application may be downloaded to the external system as an application (App) type, and then may be executed by the external system.

[0055] like Figure 1 and Figure 2 As shown in , the light-emitting display panel 100 may include a display area AA displaying an image and a non-display area IA disposed outside (or at an outer portion) of the display area AA.

[0056] The display area AA may include a transparent area AA1 where the camera 600 is disposed and an opaque area AA2 disposed outside the transparent area AA1. That is, the opaque area AA2 may include all areas of the display area AA except the transparent area AA1.

[0057] The transparent area AA1 may be formed to be transparent so that external light is incident on the camera 600. That is, the transparent area AA1 may perform a function of allowing external light incident through the front surface of the light-emitting display panel 100 to travel to the camera 600 disposed in the rear surface thereof.

[0058] The width of the non-display area IA may be formed to be very small, and then, when most of the non-display area IA is covered by the housing 20, as shown in FIG. Figure 1 As shown in , only the display area AA may be exposed in front of the electronic device.

[0059] The shape and size of the transparent area AA1 can be set in various ways for each electronic device. Figure 1 , as an example of the present disclosure, a light-emitting display panel in which the entire upper end portion of the light-emitting display panel 100 is included in the transparent area AA1 is illustrated, but the transparent area AA1 may be formed at a portion of the upper end portion of the light-emitting display panel 100 .

[0060] Hereinafter, the structure of the light emitting display panel 100 will be described in detail.

[0061] The light-emitting display panel 100 may include a substrate, a display area AA defined on the substrate, and a non-display area IA surrounding the display area AA.

[0062] The substrate may be a base substrate (or base layer) and may include a plastic material or a glass material. The substrate according to the embodiment may have a flat quadrilateral shape, a quadrilateral shape in which each corner portion is rounded with a certain radius of curvature, or a non-quadrilateral shape including at least seven sides. Here, the substrate having a non-quadrilateral shape may include at least one protruding portion or at least one notched portion.

[0063] The substrate according to the embodiment may include a colored polyimide material. For example, the substrate including the polyimide material may be formed by curing a polyimide resin, which is coated to have a certain thickness on the front surface of a release layer provided in a relatively thick carrier substrate. In this case, the carrier substrate can be separated from the substrate by releasing the release layer through a laser release process. The substrate according to the embodiment may also include a backplane coupled to the rear surface of the substrate with respect to the thickness direction Z. The backplane may maintain the substrate in a flat state. The backplane according to the embodiment may include a plastic material, and may include, for example, polyethylene terephthalate. The backplane may be laminated on the rear surface of the substrate separated from the carrier substrate.

[0064] According to another embodiment, the substrate may be a flexible glass substrate. For example, the substrate including the glass material may be a thin glass substrate having a thickness of 100 μm or less, or may be a carrier glass substrate etched to have a thickness of 100 μm or less by a substrate etching process performed after the manufacturing process is completed.

[0065] A plurality of initialization voltage lines IVL, a plurality of scan control lines SCL, a plurality of emission control lines ECL, a plurality of data lines DL, a plurality of pixel driving voltage lines PL, a common electrode layer, and a plurality of pixels P may be disposed in the display area AA.

[0066] The plurality of initialization voltage lines IVL may extend long in a second direction Y intersecting the first direction X, and may be separated from each other in the first direction X. Here, the first direction X may be a direction parallel to the width direction of the substrate, and the second direction Y may be a direction parallel to the length direction of the substrate. However, the present disclosure is not limited thereto, and the first direction X may be a direction parallel to the length direction of the substrate, and the second direction Y may be a direction parallel to the width direction of the substrate. Each of the plurality of initialization voltage lines IVL may transmit an initialization voltage provided from the data driver 300 or the power supply circuit to a corresponding pixel among the plurality of pixels.

[0067] The plurality of scan control lines SCL may extend long in the first direction X and may be disposed adjacent to the plurality of emission control lines ECL, respectively. Each of the plurality of scan control lines SCL may transmit a scan control signal provided from the gate driver 200 to a corresponding pixel among the plurality of pixels.

[0068] The plurality of emission control lines ECL may extend long in the first direction X and may be disposed in parallel with the plurality of scan control lines SCL. Each of the plurality of emission control lines ECL may transmit an emission control signal provided from the gate driver 200 to a corresponding pixel among the plurality of pixels.

[0069] The plurality of data lines DL may extend long in the second direction Y, and may be separated from each other in the first direction X. Each of the plurality of data lines DL may transfer a data voltage provided from the data driver 300 to a corresponding pixel among the plurality of pixels.

[0070] A plurality of pixel driving voltage lines PL may be disposed in parallel with the plurality of data lines DL, respectively. Each of the plurality of pixel driving voltage lines PL may transmit a pixel driving voltage provided from the data driver 300 or a power supply circuit to a corresponding pixel among the plurality of pixels.

[0071] Each of the plurality of pixel driving voltage lines PL according to the embodiment may be disposed to correspond to two pixels each disposed adjacent to each other in the first direction X. That is, one pixel driving voltage line PL may be disposed to be shared by two pixels disposed adjacent to each other in the first direction X.

[0072] The common electrode layer may be disposed throughout the display area AA. The common electrode layer may transmit a common voltage Vss provided from the data driver 300 or a power supply circuit to a plurality of pixels. At least one common power line electrically connected to the common electrode layer may be disposed in the display area AA.

[0073] The general name of the lines arranged in parallel in one direction (e.g., the second direction Y) among the lines may be a signal line. The signal line may include an initialization voltage line IVL, a data line DL, and a pixel driving voltage line PL. The scanning control line SCL and the emission control line ECL may be connected to the gate driver 200, and thus may be arranged in parallel with the first direction X. However, the signal line may refer to the scanning control line SCL and the emission control line ECL arranged in parallel in the first direction X.

[0074] Each of the plurality of pixels P may be disposed in a pixel area defined in the display area AA, and may be electrically connected to a corresponding initialization voltage line IVL passing through the pixel area or disposed near the pixel area, a corresponding scan control line SCL, a corresponding emission control line ECL, a corresponding data line DL, a pixel driving voltage line PL, and a common electrode layer.

[0075] In this case, in order to realize the light-emitting display panel 100 with high resolution, each of the scan control line SCL and the emission control line ECL may be disposed to pass through or through the pixel area, and each of the initialization voltage line IVL, the data line DL, and the pixel driving voltage line PL may be disposed at an outer portion of the pixel area. In addition, two pixels disposed adjacent to each other in the first direction X may have a symmetrical structure with respect to the pixel driving voltage line PL.

[0076] The pixels P according to the embodiment may be arranged in a stripe structure in the display area AA. In this case, one unit pixel may include a red pixel, a green pixel, and a blue pixel, and further, may include a white pixel.

[0077] According to another embodiment, the pixel P may be arranged to have a pentile structure in the display area AA. In this case, one unit pixel may include at least one red pixel, at least two green pixels, and at least one blue pixel arranged to have a polygonal shape one-dimensionally. For example, one unit pixel having a pentile structure may be arranged so that one red pixel, two green pixels, and one blue pixel are arranged to have an octagonal shape one-dimensionally, and in this case, the blue pixel may include an opening area (or emission area) having a relatively maximum size, and the green pixel may include an opening area having a relatively minimum size.

[0078] Each of the plurality of pixels P may operate in the order of an initialization period, a sampling period, and an emission period to emit light having brightness corresponding to a data voltage supplied through a corresponding data line DL.

[0079] The non-display area IA may be disposed along an edge of the substrate to surround the display area AA. One non-display area of ​​the non-display area IA may include a pad portion.

[0080] The pad portion may be disposed in one non-display area of ​​the substrate, and may be electrically connected to a line disposed in the display area AA in the second direction Y. In addition, the pad portion may be electrically connected to the data driver 300 .

[0081] Figure 3 is a circuit diagram of an embodiment of a pixel applied to a light-emitting display panel according to the present disclosure.

[0082] like Figure 3 As shown in , each of a plurality of pixels P applied to a light-emitting display panel according to the present disclosure may include a pixel driving circuit PDC and a light-emitting device ED connected to the pixel driving circuit PDC.

[0083] like Figure 3As shown in , the pixel driving circuit PDC may include: a first transistor T1, which includes a first terminal connected to a pixel driving voltage line PL, a second terminal connected to a first terminal of a driving transistor Tdr, and a gate connected to an emission control line ECL; a driving transistor Tdr, which includes a first terminal connected to a second terminal of the first transistor T1, a second terminal connected to a first terminal of a second transistor T2, and a gate connected to a second terminal of a capacitor C; a second transistor T2, which includes a gate connected to an emission control line ECL, a first terminal connected to a second terminal of the driving transistor Tdr, and a second terminal connected to a light emitting device ED; a capacitor C, which includes a first terminal connected to the first terminal of the first transistor T1 and a second terminal connected to the gate of the driving transistor Tdr; a third transistor T3, which includes a fourth transistor T4 including a gate connected to the nth scan control line SCL(n), a first terminal connected to the data line DL, and a second terminal connected to the first terminal of the driving transistor Tdr; a fifth transistor T5 including a gate connected to the nth scan control line SCL(n), a first terminal connected to the initialization voltage line IVL, and a second terminal connected to the second terminal of the second transistor T2; and a sixth transistor T6 including a gate connected to the n-1th scan control line SCL(n-1), a first terminal connected to the initialization voltage line IVL, and a second terminal connected to the first terminal of the fourth transistor T4.

[0084] The pixel driving circuit PDC may be applied to the plurality of pixels P disposed in the transparent area AA1 , and may also be applied to the plurality of pixels P disposed in the opaque area AA2 .

[0085] However, the arrangement structure of the pixel driving circuit PDC included in each of the pixels provided in the transparent area AA1 may be different from the arrangement structure of the pixel driving circuit PDC included in each of the pixels provided in the opaque area AA2. That is, in order to increase the transmittance of the transparent area AA1, the arrangement structure of the pixel driving circuit PDC in the transparent area AA1 may be formed to be different from the arrangement structure of the pixel driving circuit PDC in the opaque area AA2.

[0086] The structure of the pixel driving circuit PDC in the opaque area AA2 may be similar to the structure of the pixel driving circuit PDC in the opaque area AA2 that is currently and generally used, and therefore, a detailed description thereof is omitted.

[0087] Therefore, hereinafter, the structure of the pixel driving circuit PDC included in each pixel provided in the transparent area AA1 will be described in detail.

[0088] In the following description, when a pixel driving circuit needs to be divided by pixel units, the pixel driving circuit may be referred to as a first pixel driving circuit or a second pixel driving circuit.

[0089] Figure 4 It shows Figure 3 A circuit diagram of an example in which a pixel driving circuit is divided by a layer unit, Figure 5 It shows Figure 4 A cross-sectional view of the layer structure of a pixel is shown in FIG. 1 , and Figure 6 It shows Figure 4 The circuit configuration of each layer is shown in the diagram.

[0090] As described above, the light-emitting display panel according to the present disclosure may include a display area AA displaying an image and a non-display area IA disposed outside the display area AA. The display area AA may include a transparent area AA1 where the camera 600 is disposed and an opaque area AA2 disposed outside the transparent area AA1.

[0091] In this case, the transparent area AA1 may include a first pixel circuit layer 110 including a first pixel circuit PC1, a second pixel circuit layer 120 disposed on the first pixel circuit layer 110 and including a second pixel circuit PC2, and a light emitting device layer 170 disposed on the second pixel circuit layer 120 and including at least one light emitting device ED. A driving transistor for controlling the amount of current flowing to the at least one light emitting device ED may be included in at least one of the first pixel circuit layer 110 and the second pixel circuit layer 120.

[0092] That is to say, Figures 4 to 6 As shown in FIG. 1 , a pixel P applied to a light-emitting display panel according to the present disclosure may include a pixel driving circuit layer 130 including a pixel driving circuit PDC and a light-emitting device layer 170 including a light-emitting device ED electrically connected to the pixel driving circuit PDC.

[0093] The pixel driving circuit layer 130 may include a first pixel circuit layer 110 including a first pixel circuit PC1 and a second pixel circuit layer 120 including a second pixel circuit PC2 .

[0094] The first pixel circuit PC1 and the second pixel circuit PC2 may be included in a pixel driving circuit (hereinafter referred to as a first pixel driving circuit) configuring a pixel (hereinafter referred to as a first pixel among a plurality of pixels arranged in the transparent area AA1), and a light-emitting device (hereinafter referred to as a first light-emitting device) connected to the second pixel circuit PC2 may be included in the light-emitting device layer 170.

[0095] That is, in the present disclosure, the first pixel circuit PC1 and the second pixel circuit PC2 may configure a first pixel driving circuit included in the first pixel.

[0096] To provide additional description, in the present disclosure, a first pixel circuit PC1 and a second pixel circuit PC2 each configuring a pixel driving circuit PDC may be disposed at different layers, and a first light emitting device ED connected to the second pixel circuit PC2 may be disposed on the second pixel circuit PC2.

[0097] First, the first pixel circuit layer 110 according to an embodiment may include a substrate 10, a first pixel circuit PC1, a pixel driving voltage line PL for transmitting a pixel driving voltage to the first pixel circuit PC1, and an emission control line ECL for transmitting an emission control signal to the first pixel circuit PC1.

[0098] As described above, the substrate 10 may include a plastic material or a glass material.

[0099] The emission control line ECL may be disposed in the pixel P in parallel to the first direction X.

[0100] The pixel driving voltage line PL may be disposed in the pixel P in parallel with the second direction Y.

[0101] The first pixel circuit PC1 may control the amount of current flowing to the light emitting device ED.

[0102] According to an embodiment, the first pixel circuit PC1 may include a first transistor T1, the first transistor T1 includes a first terminal connected to the pixel driving voltage line PL, a gate connected to the emission control line ECL, and a second terminal connected to the second pixel circuit PC2 through the first connection line CL1; a driving transistor Tdr, the driving transistor Tdr includes a first terminal connected to the second terminal of the first transistor T1, a second terminal connected to the second pixel circuit PC2 through the second connection line CL2, and a gate connected to the second pixel circuit PC2 through the third connection line CL3; a second transistor T2, the second transistor T2 includes a gate connected to the emission control line ECL, a first terminal connected to the second terminal of the driving transistor Tdr, and a second terminal connected to the light emitting device ED through the fourth connection line CL4; and a capacitor C, the capacitor C includes a first terminal connected to the first terminal of the first transistor T1 and a second terminal connected to the gate of the driving transistor Tdr.

[0103] The driving transistor Tdr may transfer a current corresponding to a gate-source voltage to the light emitting device ED based on a data voltage supplied through the data line DL.

[0104] The driving transistor Tdr according to an embodiment may include a first terminal connected to the second terminal of the third transistor T3 through a first connection line CL1 connected to the first node n1, a second terminal connected to the fourth transistor T4 and the second transistor T2 included in the second pixel circuit layer 120, and a gate connected to the sixth transistor T6 and the capacitor C included in the second pixel circuit layer 120.

[0105] The first terminal of the driving transistor Tdr may be a source electrode, and the second terminal thereof may be a drain electrode. The driving transistor Tdr may be turned on based on its gate-source voltage, and thus, a current corresponding to the gate-source voltage may flow in the first transistor T1, the driving transistor Tdr, the second transistor T2, and the light emitting device ED based on the data voltage.

[0106] The first terminal of the driving transistor Tdr may be connected to the first transistor T1 and the third transistor T3 through the first node n1. In particular, the first terminal of the driving transistor Tdr may be connected to the second terminal of the third transistor T3 included in the second pixel circuit layer 120 through the first connection line CL1 at the first node n1.

[0107] The second terminal of the driving transistor Tdr may be connected to the fourth transistor T4 and the second transistor T2 through the second node n2. In particular, the second terminal of the driving transistor Tdr may be connected to the second terminal of the fourth transistor T4 included in the second pixel circuit layer 120 through the second connection line CL2 at the second node n2.

[0108] The first transistor T1 may be turned on or off based on an emission control signal provided through the emission control line ECL. When the first transistor T1 is turned on, current may be provided to the driving transistor Tdr.

[0109] The first transistor T1 according to an embodiment may include a gate connected to the emission control line ECL, a first terminal connected to the pixel driving voltage line PL, and a second terminal connected to the first terminal of the driving transistor Tdr. The second terminal of the first transistor T1 may be connected to the second terminal of the third transistor T3 included in the second pixel circuit layer 120 through a first connection line CL1.

[0110] The second transistor T2 may be turned on or off based on an emission control signal provided through the emission control line ECL. When the second transistor T2 is turned on, current may be provided to the light emitting device ED through the first transistor T1, the driving transistor Tdr, and the second transistor T2.

[0111] The second transistor T2 according to the embodiment may include a gate connected to the emission control line ECL, a first terminal connected to the second terminal of the driving transistor Tdr, and a second terminal connected to the light emitting device ED.

[0112] The second terminal of the second transistor T2 may be connected to the second terminal of the fifth transistor T5. In particular, the second terminal of the second transistor T2 may also be connected to the second terminal of the fifth transistor T5 included in the second pixel circuit layer 120 at a fourth node n4 through a fourth connection line CL4.

[0113] In the following description, when the gates of the first transistor T1 to the sixth transistor T6 should be distinguished from each other, the gates may be referred to as the first gate electrode to the sixth gate electrode. In addition, the gate of the driving transistor Tdr may be referred to as the driving gate electrode. However, when there is no need to distinguish the gates, each of the gates in the first transistor T1 to the sixth transistor T6 may be referred to as a gate.

[0114] Each of the first transistor T1, the second transistor T2, and the driving transistor Tdr may include a semiconductor layer including an amorphous silicon material, a polycrystalline silicon material, or an oxide semiconductor material, and may be a P-type TFT including a semiconductor layer doped with a P-type impurity, but is not limited thereto, and an N-type TFT including a semiconductor layer doped with an N-type impurity may be used. That is, in Figure 4 , a pixel driving circuit PDC including a plurality of P-type TFTs is shown, but the pixel driving circuit PDC may include a plurality of N-type TFTs.

[0115] Polysilicon materials can have good reliability against strong bias stress and can have high electron mobility. Therefore, each of the first transistor T1, the second transistor T2, and the driving transistor Tdr according to the embodiment may include a P-type TFT having a semiconductor layer including a polysilicon material doped with P-type impurities.

[0116] Characteristics of materials included in the first transistor T1 , the second transistor T2 , and the driving transistor Tdr may be applied to all of the third to sixth transistors T3 to T6 .

[0117] The capacitor C may store a data voltage provided through the data line DL. In addition, the capacitor C may store an initialization voltage provided through the initialization voltage line IVL. In addition, the capacitor C may store a threshold voltage of the driving transistor Tdr. That is, the capacitor C may sense a change in the threshold voltage of the driving transistor Tdr and may store the threshold voltage for performing an internal compensation function of compensating for a change in the threshold voltage.

[0118] The first terminal of the capacitor C according to an embodiment may be connected to the first terminal of the first transistor T1 and the pixel driving voltage line PL.

[0119] The second terminal of the capacitor C may be connected to the third node n3. That is, the second terminal of the capacitor C may be connected to the gate of the driving transistor Tdr, the first terminal of the fourth transistor T4, and the second terminal of the sixth transistor T6. In particular, the second terminal of the capacitor C may be connected to the first terminal of the fourth transistor T4 included in the second pixel circuit layer 120 and the second terminal of the sixth transistor T6 included in the second pixel circuit layer 120 at the third node n3 through the third connection line CL3.

[0120] Secondly, the second pixel circuit layer 120 may be disposed at the top surface (or surface) of the first pixel circuit layer 110. The second pixel circuit layer 120 according to an embodiment may include a second pixel circuit PC2, an nth scan control line SCL(n) for transmitting an nth scan control signal to the second pixel circuit PC2, and an n-1th scan control line SCL(n-1) for transmitting an n-1th scan control signal to the second pixel circuit PC2, a data line DL for transmitting a data voltage to the second pixel circuit PC2, and an initialization voltage line IVL for transmitting an initialization voltage to the second pixel circuit PC2.

[0121] The n-th scan control line SCL(n) may be disposed in the pixel P so as to be separated from and parallel to the emission control line ECL.

[0122] The (n-1)th scan control line SCL(n-1) may be disposed in the pixel P so as to be separated from and parallel to the nth scan control line SCL(n).

[0123] The data line DL may be disposed at one edge of the pixel P in parallel with the second direction Y.

[0124] The initialization voltage line IVL may be disposed in parallel with the data line DL in the pixel P. The initialization voltage provided through the initialization voltage line IVL may initialize the capacitor C, the gate of the driving transistor Tdr, and the light emitting device ED.

[0125] The second pixel circuit PC2 may charge the data voltage provided through the data line DL into the capacitor C and may drive the driving transistor Tdr.

[0126] According to an embodiment, the second pixel circuit PC2 may include a third transistor T3, the third transistor T3 includes a gate connected to the nth scan control line SCL(n), a first terminal connected to the data line DL, and a second terminal connected to the first terminal of the driving transistor Tdr through the first connection line CL1; a fourth transistor T4, the fourth transistor T4 includes a gate connected to the nth scan control line SCL(n), a first terminal connected to the gate of the driving transistor Tdr through the third connection line CL3, and a second terminal connected to the second terminal of the driving transistor Tdr through the second connection line CL2; a fifth transistor T5, the fifth transistor T5 includes a gate connected to the nth scan control line SCL(n), a first terminal connected to the initialization voltage line IVL, and a second terminal connected to the second terminal of the second transistor T2 through the fourth connection line CL4; and a sixth transistor T6, the sixth transistor T6 includes a gate connected to the n-1th scan control line SCL(n-1), a first terminal connected to the initialization voltage line IVL, and a second terminal connected to the first terminal of the fourth transistor T4.

[0127] The third transistor T3 may be turned on or off based on the nth scan control signal provided through the nth scan control line SCL(n). When the third transistor T3 is turned on, the data voltage provided through the data line DL may be charged into the capacitor C.

[0128] The third transistor T3 according to the embodiment may include a gate connected to the nth scan control line SCL(n), a second terminal connected to the first terminal of the driving transistor Tdr through the first node n1, and a first terminal connected to the data line DL. In particular, the second terminal of the third transistor T3 may be connected to the second terminal of the first transistor T1 included in the first pixel circuit layer 110 and the first terminal of the driving transistor Tdr included in the pixel circuit layer 110 at the first node n1 through the first connection line CL1.

[0129] The fourth transistor T4 may be turned on or off based on the nth scan control signal provided through the nth scan control line SCL(n). When the fourth transistor T4 is turned on, the data voltage provided through the data line DL, the third transistor T3, and the driving transistor Tdr may be charged into the capacitor C.

[0130] The fourth transistor T4 according to an embodiment may include a gate connected to the nth scan control line SCL(n), a first terminal connected to the gate of the driving transistor Tdr, and a second terminal connected to the second terminal of the driving transistor Tdr.

[0131] The first terminal of the fourth transistor T4 may be connected to the second terminal of the sixth transistor T6 and the second terminal of the capacitor C. In addition, the second terminal of the fourth transistor T4 may be connected to the first terminal of the second transistor T2. In particular, the first terminal of the fourth transistor T4 may be connected to the gate of the driving transistor Tdr included in the first pixel circuit layer 110 at the third node n3, and further, may be connected to the second terminal of the capacitor C included in the first pixel circuit layer 110.

[0132] The fifth transistor T5 may be turned on or off based on the nth scan control signal provided through the nth scan control line SCL(n). When the fifth transistor T5 is turned on, the light emitting device ED may be initialized by the initialization voltage provided through the initialization voltage line IVL and the fifth transistor T5.

[0133] The fifth transistor T5 according to the embodiment may include a gate connected to the nth scan control line SCL(n), a first terminal connected to the initialization voltage line IVL, and a second terminal connected to the light emitting device ED. The first terminal of the fifth transistor T5 may be connected to the first terminal of the sixth transistor T6. The second terminal of the fifth transistor T5 may be connected to the second terminal of the second transistor T2 and the light emitting device ED. In particular, the second terminal of the fifth transistor T5 may be connected to the second terminal of the second transistor T2 included in the first pixel circuit layer 110 at the fourth node n4 through the fourth connection line CL4, and may be connected to the pixel driving electrode AE ​​of the light emitting device ED included in the light emitting device layer 170.

[0134] The sixth transistor T6 may be turned on or off based on the n-1th scan control signal provided through the n-1th scan control line SCL(n-1). When the sixth transistor T6 is turned on, the third node n3 may be initialized by the initialization voltage provided through the initialization voltage line IVL and the sixth transistor T6.

[0135] The sixth transistor T6 according to the embodiment may include a first terminal connected to the initialization voltage line IVL and the first terminal of the fifth transistor T5; a second terminal connected to the second terminal of the capacitor C, the first terminal of the fourth transistor T4, and the gate of the driving transistor Tdr; and a gate connected to the n-1 scan control line SCL (n-1). The first terminal of the sixth transistor T6 may be connected to the initialization voltage line IVL and the first terminal of the fifth transistor T5. The second terminal of the sixth transistor T6 may be connected to the second terminal of the capacitor C, the first terminal of the fourth transistor T4, and the gate of the driving transistor Tdr. In particular, the second terminal of the sixth transistor T6 may be connected to the gate of the driving transistor Tdr included in the first pixel circuit layer 110 at the third node n3 through the third connection line CL3, and may be connected to the second terminal of the capacitor C included in the first pixel circuit layer 110.

[0136] The light emitting device layer 170 may include a light emitting device ED and a bank pattern BNK (bank pattern), the light emitting device ED being electrically connected to the first pixel circuit PC1 and the second pixel circuit PC2 and emitting current based on current supplied from the first pixel circuit PC1 .

[0137] The light emitting device ED according to the embodiment may include a pixel driving electrode AE ​​(referred to as an anode electrode) connected to a pixel driving circuit PDC, a light emitting layer EL formed on the pixel driving electrode AE, and a common electrode layer CE (referred to as a cathode electrode) electrically connected to the light emitting layer EL.

[0138] The pixel driving electrode AE ​​may be disposed in an opening region of the pixel P and may be electrically connected to a second terminal of the driving transistor Tdr included in the first pixel circuit PC1 through the second transistor T2 .

[0139] The pixel driving electrode AE ​​according to the embodiment may include a metal material with high reflectivity. For example, the pixel driving electrode AE ​​may be formed in a multilayer structure, for example, a stacked structure of aluminum (Al) and titanium (Ti) (titanium / aluminum / titanium (Ti / Al / Ti)), a stacked structure of Al and indium tin oxide (ITO) (indium tin oxide / aluminum / indium tin oxide (ITO / Al / ITO)), an APC (silver / palladium / copper (Ag / Pd / Cu)) alloy, or an APC alloy and an ITO stacked structure (ITO / APC / ITO), or may include a single-layer structure including one material or an alloy material of two or more materials selected from Ag, Al, molybdenum (Mo), gold (Au), magnesium (Mg), calcium (Ca), and barium (Ba).

[0140] However, the light emitting device ED may be formed to be transparent. In this case, the pixel driving electrode AE ​​may include a transparent metal, for example, ITO or indium zinc oxide (IZO).

[0141] The edge of the pixel driving electrode AE ​​may be covered by the bank pattern BNK. The bank pattern BNK may be disposed in the pixel region of the pixel P instead of the opening region and may cover the edge of the pixel driving electrode AE. Thus, the opening region of the pixel P may be defined.

[0142] The bank pattern BNK according to an embodiment may define an opening region of the pixel P as a pentile structure or a stripe structure.

[0143] The light emitting layer EL according to the embodiment may be formed in the entire display area AA of the substrate 10 to cover the pixel driving electrode AE ​​and the bank pattern BNK.

[0144] The light emitting layer EL according to the embodiment may include two or more light emitting parts for emitting white light. For example, the light emitting layer EL according to the embodiment may include a first light emitting part and a second light emitting part for emitting white light based on a combination of the first light and the second light. Here, the first light emitting part may emit the first light and may include one of a blue light emitting part, a green light emitting part, a red light emitting part, a yellow light emitting part, and a yellow-green light emitting part. The second light emitting part may include a light emitting part that emits a second light, and the second light has a color relationship complementary to the first light among the blue light emitting part, the green light emitting part, the red light emitting part, the yellow light emitting part, and the yellow-green light emitting part.

[0145] According to another embodiment, the light emitting layer EL may include one of a blue light emitting portion, a green light emitting portion, and a red light emitting portion for emitting colored light corresponding to the color set in the pixel P. For example, the light emitting layer EL according to another embodiment may include one of an organic light emitting layer, an inorganic light emitting layer, and a quantum dot light emitting layer, or may include a stacked or combined structure of an organic light emitting layer (or an inorganic light emitting layer) and a quantum dot light emitting layer.

[0146] Additionally, the light emitting device ED according to the embodiment may further include a functional layer for enhancing the light emitting efficiency and / or lifetime of the light emitting layer EL.

[0147] The common electrode layer CE may be formed to be electrically connected to the light emitting layer EL. The common electrode layer CE may be formed in the entire display area AA of the substrate 10, and may be commonly connected to the light emitting layer EL provided in each pixel area PA.

[0148] The common electrode layer CE according to the embodiment may include a transparent conductive material, a transparent metal, or a semi-transmissive conductive material that can transmit light. When the common electrode layer CE includes a semi-transmissive conductive material, the luminous efficiency of the light emitted from the light emitting device ED can be increased based on the microcavity. The semi-transmissive conductive material according to the embodiment may include Mg, Ag, or an alloy of Mg and Ag. In addition, a cover layer for adjusting the refractive index of the light emitted from the light emitting device ED to enhance the luminous efficiency of the light may also be formed on the common electrode layer CE.

[0149] According to another embodiment, the light emitting layer EL may include a micro light emitting diode device implemented as an integrated circuit (IC) type. The micro light emitting diode device may include a first terminal electrically connected to the pixel driving electrode AE ​​and a second terminal electrically connected to the common electrode layer CE.

[0150] The pixel P according to the embodiment may further include a planarization layer 160 covering the second pixel circuit layer 120 and an encapsulation layer 190 covering the light emitting device layer 170 .

[0151] The planarization layer 160 may be disposed on the substrate 10 to cover the second pixel circuit layer 120 , and may provide a flat surface on the second pixel circuit layer 120 .

[0152] The light emitting device layer 170 may be disposed on the planarization layer 160. In this case, the pixel driving electrode AE ​​of the light emitting device layer 170 may be connected to the second terminal of the second transistor T2 of the first pixel circuit PC1 through an electrode contact hole disposed in the planarization layer 160, and the first terminal of the second transistor T2 may be electrically connected to the second terminal of the driving transistor Tdr.

[0153] The encapsulation layer 190 may be formed on the substrate 10 to surround the light emitting device layer 170. The encapsulation layer 190 may prevent oxygen or water from penetrating into the light emitting device ED.

[0154] The encapsulation layer 190 according to an embodiment may include at least one inorganic layer for preventing or minimizing the penetration of oxygen or water and an organic layer covering particles occurring during the manufacturing process. For example, the encapsulation layer 190 may include a first inorganic layer, an organic layer on the first inorganic layer, and a second inorganic layer on the organic layer.

[0155] Additionally, the pixel P according to an embodiment of the present disclosure may further include a black matrix overlapping the bank pattern BNK and a wavelength conversion layer disposed in the opening region.

[0156] A black matrix may be disposed on the encapsulation layer 190 to overlap the bank pattern BNK.

[0157] The wavelength conversion layer according to an embodiment may include a color filter disposed on the encapsulation layer 190 overlapping the opening region of the pixel P to transmit only the color wavelength of the white light incident from the light emitting device ED disposed in the pixel P. For example, the wavelength conversion layer may transmit only the wavelength of red, green, or blue. When the light emitting layer EL of the light emitting device ED includes a light emitting layer emitting red, green, and blue light, the wavelength conversion layer may be omitted.

[0158] The pixel P according to an embodiment of the present disclosure may further include a blocking film and a light path control layer.

[0159] The barrier film may be attached on the encapsulation layer 190 by using an adhesive layer. The barrier film may mainly prevent the penetration of oxygen or water, and may include a material with a low water vapor transmission rate.

[0160] The light path control layer can control the path of incident light.

[0161] The light path control layer according to the embodiment may include a plurality of refractive layers. The plurality of refractive layers may have different refractive indices. The light path control layer may have a structure in which high refractive layers and low refractive layers are alternately stacked. The light path control layer according to the embodiment may change the path of the incident light to minimize the color shift phenomenon caused by the viewing angle.

[0162] According to another embodiment, the light path control layer may be a polarizing layer, which may change external light reflected by a TFT and / or a wire disposed in the pixel P into circularly polarized light, thereby improving visibility and contrast.

[0163] The operation of a pixel according to an embodiment of the present disclosure will be described below.

[0164] The pixel P according to the embodiment of the present disclosure may operate in an initialization period, a routing period, and an emission period. For example, one frame of a light-emitting display device to which the light-emitting display panel according to the embodiment of the present disclosure is applied may include an initialization period for initializing the gate of the driving transistor Tdr, a routing period for storing a sampling voltage and a data voltage respectively corresponding to a characteristic value (e.g., a threshold voltage) of the driving transistor Tdr, and an emission period for allowing the light-emitting device ED to emit light with a current corresponding to the data voltage.

[0165] In the initialization period, a low voltage may be provided to the n-1th scan control line SCL(n-1), and therefore, the sixth transistor T6 may be turned on. In this case, the voltage of the third node n3 may be the initialization voltage Vinit. The third node n3 may be a portion connected to the second terminal of the capacitor C, the gate of the driving transistor Tdr, the first terminal of the fourth transistor T4, and the second terminal of the sixth transistor T6.

[0166] In the routing period, a low voltage may be provided to the nth scan control line SCL(n), and thus, the third transistor T3 may be turned on. In this case, the voltage of the third node n3 may be a sum voltage of the data voltage Vdata provided by the data line DL and the threshold voltage Vth of the driving transistor Tdr. That is, the voltage of the third node n3 may be changed from the initialization voltage Vinit to a sum voltage (=Vdata+Vth) of the data voltage Vdata and the threshold voltage Vth.

[0167] In the emission period, a low voltage may be provided to the emission control line ECL, and thus, the first transistor T1 and the second transistor T2 may be turned on. In this case, the current provided to the light emitting device ED may be proportional to the square of the voltage difference between the gate-source voltage Vgs of the driving transistor Tdr and the threshold voltage Vth. In the emission period, the gate voltage of the driving transistor Tdr (i.e., the voltage of the third node n3) may be the sum voltage (=Vdata+Vth) of the data voltage Vdata and the threshold voltage Vth, and the source voltage of the driving transistor Tdr may be the pixel driving voltage Vdd provided by the pixel driving voltage line PL. Therefore, the difference voltage between the gate-source voltage Vgs of the driving transistor Tdr and the threshold voltage Vth may be [((Vdata+Vth)-Vdd)-Vth=Vdata-Vdd]. Therefore, the current provided to the light emitting device ED may be proportional to the square of the voltage difference (=Vdata-Vdd) between the data voltage Vdata and the pixel driving voltage Vdd.

[0168] That is, according to the present disclosure, the current supplied to the light emitting device ED may be independent of the threshold voltage Vth of the driving transistor Tdr, and may be determined only by the pixel driving voltage Vdd and the data voltage Vdata.

[0169] Therefore, according to the present disclosure, even when the driving transistor Tdr deteriorates to cause a change in the threshold voltage Vth of the driving transistor Tdr, the current supplied to the light emitting device ED may not be affected by the change in the threshold voltage Vth. Therefore, according to the present disclosure, the current may be controlled only by the data voltage Vdata regardless of the amount of change in the threshold voltage Vth of the driving transistor Tdr.

[0170] Figure 7 It shows Figure 4 An example diagram of a first pixel circuit is shown in FIG. 1 , and Figure 8 It shows that including Figure 7 An example diagram of the layout of the first pixel circuit layer of the first pixel circuit shown in FIG. Figure 7shows a first pixel circuit PC1 included in one pixel, and Fig. 9 The planar structure of the first pixel circuit layer 110 in one pixel is shown.

[0171] As described above, the first pixel circuit layer 110 may include the driving transistor Tdr, the first transistor T1 , the second transistor T2 , and the capacitor C.

[0172] The first node n1 disposed between the first transistor T1 and the driving transistor Tdr may be connected to the second terminal of the third transistor T3 included in the second pixel circuit layer 120 through the first connection line CL1. Figure 8 As shown in FIG. 1 , a first node n1 connected to a first connection line CL1 may be provided between the first transistor T1 and the driving transistor Tdr, and a first contact hole may be formed in the first node n1. First to fourth nodes n1 to n4 described below may be connected to the transistors included in the transistors T1 to Tdr through the first to fourth connection lines CL1 to CL4. Fig.10 The first node n1 to the fourth node n4 in the second pixel circuit layer 120 shown in FIG. However, the connection line connecting two corresponding nodes may directly connect the two corresponding nodes, or may connect the two corresponding nodes by using separate nodes and separate contact holes. Therefore, Figure 8 The positions of the first node n1 to the fourth node n4 shown in FIG. Fig.10 The positions of the first node n1 to the fourth node n4 are shown in FIG. Figure 8 The first to fourth contact holes described can be compared with those in Fig.10 The described first to fourth contact holes are identical, or may be separate contact holes electrically connected to each other.

[0173] The second node n2 disposed between the second transistor T2 and the driving transistor Tdr may be connected to the second terminal of the fourth transistor T4 included in the second pixel circuit layer 120 through the second connection line CL2. Figure 8 As shown in FIG. 1 , a second node n2 connected to the second connection line CL2 may be provided between the second transistor T2 and the driving transistor Tdr, and a second contact hole may be formed in the second node n2.

[0174] The capacitor C may be formed to overlap the driving transistor Tdr. The third node n3 disposed between the capacitor C and the gate of the driving transistor Tdr may be connected to the second terminal of the sixth transistor T6 included in the second pixel circuit layer 120 and the first terminal of the fourth transistor T4 included in the second pixel circuit layer 120 through the third connection line CL3. To this end, Figure 8As shown in , a third node n3 connected to the third connection line CL3 may be disposed between the capacitor C and the driving transistor Tdr, and a third contact hole may be formed in the third node n3.

[0175] The fourth node n4 disposed between the second transistor T2 and the light emitting device ED may be connected to the second terminal of the fifth transistor T5 included in the second pixel circuit layer 120 through the fourth connection line CL4. Figure 8 As shown in , a fourth node n4 connected to a fourth connection line CL4 may be disposed at one end of the second transistor T2, and a fourth contact hole may be formed in the fourth node n4.

[0176] Fig. 9 It shows Figure 4 An example diagram of a second pixel circuit is shown in FIG. Fig.10 It shows that including Fig. 9 An example diagram of a layout of a second pixel circuit layer of a second pixel circuit is shown in FIG.

[0177] As described above, the second pixel circuit layer 120 may include third to sixth transistors T3 to T6 .

[0178] The third transistor T3 may be connected to the first transistor T1 and the driving transistor Tdr included in the first pixel circuit layer 110 through the first connection line CL1 included in the first node n1. Fig. 9 As shown in , a first node n1 connected to the first connection line CL1 may be disposed at the second terminal of the third transistor T3, and a first contact hole may be formed in the first node n1.

[0179] The fourth transistor T4 may be connected to the second transistor T2 and the driving transistor Tdr included in the first pixel circuit layer 110 through the second connection line CL2 included in the second node n2. Fig. 9 As shown in , a second node n2 connected to the second connection line CL2 may be provided at the second terminal of the fourth transistor T4, and a second contact hole may be formed in the second node n2.

[0180] The fourth transistor T4 may be connected to the capacitor C and the driving transistor Tdr included in the first pixel circuit layer 110 through the third connection line CL3 included in the third node n3. Fig. 9 As shown in , a third node n3 connected to the third connection line CL3 may be provided at the first terminal of the fourth transistor T4, and a third contact hole may be formed in the third node n3.

[0181] The fifth transistor T5 may be connected to the second transistor T2 included in the first pixel circuit layer 110 through a fourth connection line CL4 included in the fourth node n4. Fig. 9 As shown in FIG. 1 , a fourth node n4 connected to a fourth connection line CL4 may be provided at a second terminal of the fifth transistor T5, and a fourth contact hole may be formed in the fourth node n4. The fourth connection line CL4 may extend until a pixel driving electrode AE ​​of the light emitting device ED included in the light emitting device layer 170.

[0182] Fig.11 is shown along Fig.10 An example diagram of a cross-sectional surface taken along line DD' is shown in FIG.

[0183] As described above, the first pixel circuit PC1 included in the first pixel circuit layer 110 may be electrically connected to the second pixel circuit PC2 included in the second pixel circuit layer 120 through the first to fourth connection lines CL1 to CL4 .

[0184] like Fig.11 As shown in FIG. 1 , the fourth connection line CL4 of the first to fourth connection lines CL1 to CL4 may extend from the fourth node n4 of the first pixel circuit layer 110 to the second pixel circuit layer 120. Fig.11 In the cross-sectional view of FIG. 4 , a structure in which the second transistor T2 is connected to the fifth transistor T5 is not clearly shown, but the second transistor T2 may be connected to the fifth transistor T5 through the fourth connection line CL4 .

[0185] The first to third connection lines CL1 to CL3 may be used as Fig.11 A similar type to the fourth connection line CL4 shown in FIG. 1 is provided in the light-emitting display panel 100 .

[0186] Fig.12 is an exemplary diagram showing a plane of each pixel of the light-emitting display panel according to the present disclosure, and particularly, is an exemplary diagram showing a portion of the transparent area AA1 .

[0187] As described above, the transparent area AA1 may include the first pixel circuit layer 110 having the first pixel circuit PC1, the second pixel circuit layer 120 disposed on the first pixel circuit layer 110 and having the second pixel circuit PC2, and the light emitting device layer 170 having at least one light emitting device ED disposed on the second pixel circuit layer 120. The first pixel circuit PC1 and the second pixel circuit PC2 may be included in the pixel driving circuit PDC configuring one pixel.

[0188] That is, in the present disclosure, a pixel driving circuit PDC included in one pixel may be separated into a first pixel circuit PC1 and a second pixel circuit PC2, the first pixel circuit PC1 may be included in the first pixel circuit layer 110, and the second pixel circuit PC2 may be included in the second pixel circuit layer 120. Therefore, the width of an area where the pixel driving circuit PDC is provided may be reduced compared to the width of an area where a pixel driving circuit applied to a related art light emitting display panel is provided.

[0189] Therefore, in one pixel P, the area of ​​the pixel driving circuit PDC can be reduced, and thus, as shown in FIG. Fig.12 As shown in , the pixel driving circuit PDC may be disposed in a region that does not overlap with the light emitting device ED, and in particular, may be disposed outside the light-transmitting area AA1a of the pixel P. Therefore, the width of the light-transmitting area AA1a may be increased, and thus the transmittance of the transparent area AA1 may be increased.

[0190] Furthermore, since the pixel driving circuit PDC does not overlap with the light emitting device ED, the light emitting device ED may also be formed to be transparent, and thus the light transmittance of the transparent area A1 may be further improved.

[0191] In particular, in the present disclosure, in order to simplify the form of the light-transmitting area AA1a and maximize the area of ​​the light-transmitting area AA1a, the first pixel circuit PC1 and the second pixel circuit PC2 may be disposed in an area that does not overlap with the light-emitting device ED. Fig.12 As shown in , a plurality of pixel driving circuits PDC each including a first pixel circuit and a second pixel circuit may be disposed in a region that does not overlap with a plurality of light emitting devices ED.

[0192] In addition, the plurality of first light emitting devices and the plurality of second light emitting devices disposed in the transparent area AA1 may be arranged in a row along the first direction, and the second light emitting devices may be arranged to be staggered relative to the first light emitting devices along the second direction. Fig.12 The width direction is the first direction and Fig.12 When the lengthwise direction is the second direction, the first light emitting devices may be arranged in a row along the first direction, and the second light emitting devices may be arranged in a row along the first direction.

[0193] In this case, the plurality of first light emitting devices and the plurality of second light emitting devices may not be arranged in a row along the second direction, and may be arranged to be staggered along the second direction.

[0194] In particular, the plurality of first light emitting devices and the plurality of second light emitting devices may be disposed to face each other.

[0195] In addition, just as the plurality of first light-emitting devices and the plurality of second light-emitting devices are arranged in a staggered manner, the plurality of first pixel circuit layers and the plurality of second pixel circuit layers connected to the first light-emitting devices may be arranged in a staggered manner relative to the plurality of first pixel circuit layers and the plurality of second pixel circuit layers connected to the second light-emitting devices.

[0196] To provide additional description, in the present disclosure, a plurality of transistors configuring the pixel driving circuit PDC may be distributed and arranged in the first pixel circuit layer 110 and the second pixel circuit layer 120, and the pixel driving circuit PDC may be formed to have a size of, for example, less than 25×10 μm. Fig.12 As shown in , the pixel driving circuit PDC may be disposed under the black matrix, and thus the light transmission area AA1a may be increased.

[0197] In particular, according to the present disclosure, the anode of the light emitting device (i.e., the pixel driving electrode AE) may include a transparent metal, the line in the light-transmitting area AA1a may be removed, and the division of the light-transmitting area AA1a may be minimized. That is, the size of the light-transmitting area AA1a may be increased, and the form of the light-transmitting area AA1a may be simplified, thereby improving the light transmittance of the transparent area AA1.

[0198] That is, according to the present disclosure, the transparency of the light-emitting display panel 100 can be maximized, and when the camera is set at the lower part of the light-emitting display panel, the reduction in the amount of light can be reduced, and the form of the light-transmitting area AA1a can be simplified, thereby preventing the image captured by the camera from being distorted due to diffraction of light.

[0199] Fig.13 is an exemplary diagram showing a cross-sectional surface of a region including a plurality of pixel driving circuits in a light-emitting display panel according to the present disclosure, Fig.14 is an exemplary diagram showing non-transmission areas and light-transmission areas repeatedly formed in a transparent area of ​​a light-emitting display panel according to the present disclosure, and Fig.15 It shows Fig.14 In the following description, the above reference numerals are omitted or briefly described. Figures 1 to 12 The description given is the same or similar to the description.

[0200] As described above, the light-emitting display panel according to the present disclosure may include a display area AA displaying an image and a non-display area IA disposed outside the display area AA. The display area AA may include a transparent area AA1 corresponding to an area where the camera 600 is disposed and an opaque area AA2 disposed outside the transparent area AA1.

[0201] In this case, the transparent area AA1 may include a first pixel circuit layer 110 having a first pixel circuit PC1, a second pixel circuit layer 120 disposed on the first pixel circuit layer 110 and having a second pixel circuit PC2, and a light emitting device layer 170 having at least one light emitting device ED disposed on the second pixel circuit layer 120. At least one of the first pixel circuit layer 110 and the second pixel circuit layer 120 may include a driving transistor Tdr for controlling the amount of current flowing to the at least one light emitting device ED.

[0202] That is to say, Figure 5 As shown in , a pixel P applied to a light-emitting display panel according to the present disclosure may include a pixel driving circuit layer 130 having a pixel driving circuit PDC and a light-emitting device layer 170 having a light-emitting device ED electrically connected to the pixel driving circuit PDC.

[0203] The pixel driving circuit layer 130 may include a first pixel circuit layer 110 including a first pixel circuit PC1 and a second pixel circuit layer 120 including a second pixel circuit PC2 .

[0204] In the above reference Figures 1 to 12 In the present disclosure described above, the first pixel circuit and the second pixel circuit may be included in a pixel driving circuit configured in one of the plurality of pixels disposed in the transparent area AA1, and the light emitting device connected to the second pixel circuit may be included in the light emitting device layer 170. That is, in the above reference Figures 1 to 12 In the present disclosure described above, the first pixel circuit and the second pixel circuit may be included in the pixel driving circuit PDC included in one pixel P.

[0205] However, in Fig.13 In the light-emitting display panel according to the present disclosure shown in , the first pixel circuit PC1 may be a first pixel driving circuit PDC1 included in the first pixel P1, the second pixel circuit PC2 may be a second pixel driving circuit PDC2 included in the second pixel P2, and the light-emitting device layer 170 may include a first light-emitting device ED1 connected to the first pixel circuit PC1 and a second light-emitting device ED2 connected to the second pixel circuit PC2.

[0206] That is to say, Figures 13 to 15 In the light-emitting display panel 100 according to the present disclosure shown in FIG. 1 , the first pixel circuit PC1 may be as follows: Figure 3 In the following description, the pixel driving circuit included in the first pixel P1 may be referred to as a first pixel driving circuit PDC1, and the first pixel driving circuit PDC1 may be the same circuit as the first pixel circuit PC1.

[0207] In addition, in the present disclosure, the second pixel circuit PC2 may be as follows: Figure 3 In the following description, the pixel driving circuit included in the second pixel P2 may be referred to as a second pixel driving circuit PDC2, and the second pixel driving circuit PDC2 may be the same circuit as the second pixel circuit PC2.

[0208] To provide additional description, in the present disclosure, the first pixel circuit PC1 and the second pixel circuit PC2 may be different pixel driving circuits included in different first pixels P1 and second pixels P2 .

[0209] In this case, if Fig.13 As shown in the figure, the first pixel circuit PC1 may be included in the first pixel circuit layer 110, the second pixel circuit PC2 may be included in the second pixel circuit layer 120 disposed on the first pixel circuit layer 110, and the first light-emitting device ED1 and the second light-emitting device ED2 may be included in the light-emitting device layer 170 disposed on the second pixel circuit layer 120.

[0210] To provide additional description, such as Fig.13 As shown in the figure, the second terminal of the second transistor T2 of the first pixel circuit PC1 included in the first pixel circuit layer 110 can pass through the second pixel circuit layer 120 and can be connected to the first light-emitting device ED1 included in the light-emitting device layer 170, and in particular, can be connected to the first pixel driving electrode AE1 configuring the first light-emitting device ED1.

[0211] Furthermore, a second terminal of the second transistor T2 of the second pixel circuit PC2 included in the second pixel circuit layer 120 may be connected to the second light emitting device ED2 included in the light emitting device layer 170 , and in particular, may be connected to the second pixel driving electrode AE2 configuring the second light emitting device ED2 .

[0212] As mentioned above Figure 3 As described, the planarization layer 160 may be disposed between the second pixel circuit layer 120 and the light emitting device layer 170. In addition, the encapsulation layer 190 covering the light emitting device layer 170 may also be disposed on the light emitting device layer 170.

[0213] In this disclosure, Fig.13 As shown in FIG. 1 , since the first pixel circuit PC1 and the second pixel circuit PC2 configuring different pixels overlap each other, the width of the light-transmitting area AA1 a for transmitting light may be increased in the transparent area AA1 .

[0214] For example, in the present disclosure, Fig.14 and Fig.15 As shown in the figure, the transparent area AA1 may include a plurality of non-transmission areas AA1b including a plurality of first pixel circuits PC1 and a plurality of second pixel circuits PC2; and a plurality of light-transmitting areas AA1a, the plurality of light-transmitting areas AA1a are arranged between the plurality of non-transmission areas AA1b, and include a plurality of first light-emitting devices ED1 and a plurality of second light-emitting devices ED2 connected to the plurality of first pixel circuits PC1 or the plurality of second pixel circuits PC2 arranged in the non-transmission areas AA1b; and a plurality of signal lines for transmitting drive signals to the plurality of first pixel circuits PC1 and the plurality of second pixel circuits PC2.

[0215] In the light-transmitting area AA1a, the first light-emitting device ED1 arranged in parallel along the light-transmitting area AA1a can be connected to the first pixel circuit PC1 arranged in the non-transmitting area AA1b, and the second light-emitting device ED2 arranged in parallel along the light-transmitting area AA1a can be connected to the second pixel circuit PC2 arranged in the non-transmitting area AA1b.

[0216] To provide additional description, Fig.14 and Fig.15 For example, a first pixel circuit PC1 arranged in parallel along the non-transmission area AA1b in the non-transmission area AA1b can be connected to a first light-emitting device ED1 arranged in parallel along a light-transmitting area AA1a arranged at one side of the non-transmission area AA1b (for example, an upper end portion of the non-transmission area AA1b).

[0217] In addition, Fig.14 and Fig.15 For example, a second pixel circuit PC2 arranged in parallel along the non-transmission area AA1b in the non-transmission area AA1b can be connected to a second light-emitting device ED2 arranged in parallel along the light-transmitting area AA1a arranged at the other side of the non-transmission area AA1b (for example, the lower end portion of the non-transmission area AA1b).

[0218] In this case, the plurality of first light emitting devices ED1 and the plurality of second light emitting devices ED2 disposed in the transparent area AA1 may be arranged in a row along a first direction, and the second light emitting devices arranged in a row along the first direction may be arranged to be staggered relative to the first light emitting devices ED1 in a second direction different from the first direction. Fig.15 The width direction is the first direction and Fig.15 When the lengthwise direction is the second direction, the first light emitting devices ED1 may be arranged in a row along the first direction, and the second light emitting devices ED2 may be arranged in a row along the first direction.

[0219] In this case, the plurality of first light emitting devices ED1 and the plurality of second light emitting devices ED2 may not be arranged in a row along the second direction, and may be arranged to be staggered along the second direction. Fig.14 and 15 As shown in the figure, a plurality of first light-emitting devices ED1 and a plurality of second light-emitting devices ED2 can be arranged in the light-transmitting area AA1a in opposite directions, wherein the non-transmitting area AA1b is between the plurality of first light-emitting devices ED1 and the plurality of second light-emitting devices ED2, and the first pixel circuit PC1 and the second pixel circuit PC2 for driving the first light-emitting devices ED1 and the second light-emitting devices ED2 can be arranged in the non-transmitting area AA1b.

[0220] In addition, in addition to the first pixel circuit PC1 and the second pixel circuit PC2, other pixel circuits and other light-emitting devices connected to the other pixel circuits may be provided in the non-transmission area AA1b. That is, a plurality of pixels may be provided in the non-transmission area AA1b, and therefore, other pixel circuits and other light-emitting devices configuring the pixels may be provided in the non-transmission area AA1b.

[0221] In the present disclosure, as described above, the first pixel circuit PC1, the second pixel circuit PC2, and other pixel circuits may be disposed in the non-transmission area AA1b, and the light emitting device may be formed to be opaque. Therefore, in the non-transmission area AA1b, the transmittance may be very low due to the light emitting device, the first pixel circuit PC1, the second pixel circuit PC2, and other pixel circuits.

[0222] However, only the first light emitting device ED1, the second light emitting device ED2, and the signal line SL may be disposed in the light transmitting area AA1a.

[0223] Therefore, the transmittance of the light-transmitting area AA1a may be higher than that of the non-transmitting area AA1b, and may be higher than that of a related art light-emitting display panel in which a plurality of pixel circuits and a plurality of light-emitting devices are provided as the same type.

[0224] As mentioned above Figure 1 and Figure 2 As described above, the signal lines SL may refer to lines arranged in parallel along the second direction Y, and the signal lines SL may include an initialization voltage line IVL, a data line DL, a pixel driving voltage line PL, and the like.

[0225] That is, in the transparent area AA1 applied to the present disclosure, as Figures 13 to 15As shown in , the non-transmission area AA1b including the first pixel circuit PC1 and the second pixel circuit PC2 and the light-transmission area AA1a including only the light-emitting device and the signal line SL may be alternately arranged. In this case, the transmittance of the light-transmission area AA1a may be higher than the transmittance of the non-transmission area AA1b, and may be higher than the transmittance of the prior art light-emitting display panel in which a plurality of pixel circuits and a plurality of light-emitting devices are arranged as the same type.

[0226] Therefore, according to the present disclosure, the light transmittance of the transparent area AA1 can be improved.

[0227] The features of the present disclosure described above will be briefly described below.

[0228] In the present disclosure, seven transistors and one capacitor configuring a pixel driving circuit PDC may be separately disposed at two layers (i.e., a first pixel circuit layer 110 and a second pixel circuit layer 120), or two different pixel driving circuits PDC1 and PDC2 may be separately disposed at the first pixel circuit layer 110 and the second pixel circuit layer 120.

[0229] In this case, the second pixel circuit layer 120 may be separated by the planarization layer since the planarization layer is disposed on the top surface of the first pixel circuit layer 110. The planarization layer may include an organic material or an inorganic material, or may be formed of a combination of organic and inorganic materials.

[0230] That is, in the present disclosure, since a plurality of transistors included in at least one pixel driving circuit are separately arranged at two layers, the area in which the plurality of pixel driving circuits are arranged can be minimized, and therefore, a transparent area that does not include the circuits can be ensured, and a camera can be arranged in the transparent area.

[0231] In addition, according to the present disclosure, the transparency or transmittance of the light-emitting display panel 100 can be maximized, and when the camera is set at the lower part of the light-emitting display panel, the reduction in the amount of light can be reduced, and the form of the light-transmitting area AA1a can be simplified, thereby preventing the image captured by the camera from being distorted due to diffraction of light.

[0232] Furthermore, according to the present disclosure, in a high-resolution light-emitting display device including a camera, an internal compensation circuit including seven transistors and one capacitor may be implemented.

[0233] In the embodiments of the present disclosure, all transistors implemented as P-type included in the pixel driving circuit PDC are described, but the present disclosure is not limited thereto. Therefore, without departing from the technical features of the present disclosure in which ultra-high resolution pixels are implemented by stacking two circuit layers, all transistors may be modified to N-type, or some transistors may be modified to N-type.

[0234] The light-emitting display device to which the present disclosure is applied can be applied to portable electronic devices requiring high resolution, such as smart phones, mobile communication terminals, mobile phones, tablet personal computers (PCs), smart watches, watch phones, and wearable devices such as televisions, laptops, monitors, and refrigerators, as well as various products such as virtual image display devices and head-mounted display devices.

[0235] In particular, according to the present disclosure, a light-emitting display panel in which a plurality of optical sensors including a camera are provided at a rear surface thereof and a resolution of 200 ppi or more is achieved can be realized.

[0236] Furthermore, in the above description, the display area of ​​the light-emitting display panel may include the transparent area AA1 and the opaque area AA2 , but the display area may include only the transparent area AA1 .

[0237] That is, in the above description, as an example of the present disclosure, a light-emitting display panel has been described, in which the structure of the pixel driving circuit PDC in the opaque area AA2 is the same as or similar to the structure of the pixel driving circuit PDC in the opaque area AA2 currently and commonly used.

[0238] However, in the light-emitting display panel according to the present disclosure, the opaque area AA2 may be formed in the same structure as that of the transparent area AA1.

[0239] That is, in the present disclosure, the display area of ​​the light-emitting display panel may be configured with only the transparent area AA1 described above.

[0240] In the light-emitting display panel according to the present disclosure, a plurality of transistors configuring each of a plurality of pixel driving circuits can be separately arranged at two layers. Therefore, even in the case where the size of each pixel is reduced by achieving high resolution, a pixel driving circuit including a compensation circuit can be sufficiently arranged in each pixel, thereby achieving a high-resolution light-emitting display panel.

[0241] The above-mentioned features, structures, and effects of the present disclosure are included in at least one embodiment of the present disclosure, but are not limited to one embodiment. In addition, the features, structures, and effects described in at least one embodiment of the present disclosure can be realized by those skilled in the art by combining or modifying other embodiments. Therefore, the contents associated with the combination and modification should be interpreted as being within the scope of the present disclosure.

[0242] It will be apparent to those skilled in the art that various modifications and variations may be made to the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, it is intended that the present disclosure covers modifications and variations of the present disclosure as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. A light-emitting display panel, include: The transparent area corresponding to the area where the camera is set, in The transparent area includes: A first pixel circuit layer, comprising a first pixel circuit; A second pixel circuit layer disposed on the first pixel circuit layer, wherein the second pixel circuit layer includes a second pixel circuit; a light emitting device layer disposed on the second pixel circuit layer, the light emitting device layer comprising at least one light emitting device; and a driving transistor for controlling the amount of current flowing to the light emitting device, which is included in at least one of the first pixel circuit layer and the second pixel circuit layer, The first pixel circuit and the second pixel circuit are included in a first pixel driving circuit configuring a first pixel, wherein the light emitting device layer includes a first light emitting device connected to the second pixel circuit, and Wherein, the first pixel circuit comprises: a first transistor including a first terminal connected to a pixel driving voltage line, a gate connected to an emission control line, and a second terminal connected to the second pixel circuit via a first connection line; a driving transistor including a first terminal connected to the second terminal of the first transistor, a second terminal connected to the second pixel circuit via a second connection line, and a gate connected to the second pixel circuit via a third connection line; a second transistor including a gate connected to the emission control line, a first terminal connected to the second terminal of the drive transistor, and a second terminal connected to the first light emitting device through a fourth connection line; and A capacitor includes a first terminal connected to the first terminal of the first transistor and a second terminal connected to the gate of the drive transistor.

2. The light-emitting display panel according to claim 1, in, The second pixel circuit comprises: a third transistor including a gate connected to an nth scanning control line, a first terminal connected to a data line, and a second terminal connected to the first terminal of the driving transistor through the first connecting line; a fourth transistor including a gate connected to the nth scan control line, a first terminal connected to the gate of the drive transistor through the third connection line, and a second terminal connected to the second terminal of the drive transistor through the second connection line; a fifth transistor including a gate connected to the nth scan control line, a first terminal connected to an initialization voltage line, and a second terminal connected to the second terminal of the second transistor through the fourth connection line; and A sixth transistor includes a gate connected to an (n-1)th scan control line, a first terminal connected to the initialization voltage line, and a second terminal connected to the first terminal of the fourth transistor.

3. The light-emitting display panel according to claim 1, in, The first light emitting device includes a transparent metal.

4. The light-emitting display panel according to claim 1, in, The first pixel circuit and the second pixel circuit are disposed in a region not overlapping the light emitting device.

5. The light emitting display panel according to claim 4, wherein The plurality of first light emitting devices and the plurality of second light emitting devices disposed in the transparent region are each arranged in a row in a first direction, and The plurality of second light emitting devices are arranged to be staggered relative to the plurality of first light emitting devices in a second direction.

6. The light-emitting display panel according to claim 5, in, The plurality of first light emitting devices and the plurality of second light emitting devices are disposed to face each other.

7. The light-emitting display panel according to claim 5, in, The plurality of first pixel circuit layers and the plurality of second pixel circuit layers connected to the plurality of first light emitting devices are disposed to be staggered relative to the plurality of first pixel circuit layers and the plurality of second pixel circuit layers connected to the plurality of second light emitting devices.

8. A light-emitting display panel, include: The transparent area corresponding to the area where the camera is set, in The transparent area includes: A first pixel circuit layer, comprising a first pixel circuit; A second pixel circuit layer disposed on the first pixel circuit layer, wherein the second pixel circuit layer includes a second pixel circuit; a light emitting device layer disposed on the second pixel circuit layer, the light emitting device layer comprising at least one light emitting device; and a driving transistor for controlling the amount of current flowing to the light emitting device, which is included in at least one of the first pixel circuit layer and the second pixel circuit layer, The first pixel circuit is a first pixel driving circuit included in the first pixel, The second pixel circuit is a second pixel driving circuit included in the second pixel, wherein the light emitting device layer includes a first light emitting device connected to the first pixel circuit and a second light emitting device connected to the second pixel circuit, and Wherein, the transparent area also includes: a plurality of non-transmission regions, in which a plurality of first pixel circuits and a plurality of second pixel circuits are disposed; and A plurality of light-transmitting regions are provided with a plurality of first light-emitting devices and a plurality of second light-emitting devices, wherein the plurality of first light-emitting devices and the plurality of second light-emitting devices are connected to the plurality of first pixel circuits or the plurality of second pixel circuits provided in the plurality of non-transmitting regions, and the plurality of light-transmitting regions are provided between the plurality of non-transmitting regions.

9. The light emitting display panel according to claim 8, wherein a plurality of first light emitting devices arranged in parallel along corresponding light-transmitting regions among the plurality of light-transmitting regions are connected to a plurality of first pixel circuits arranged in corresponding non-transmitting regions among the plurality of non-transmitting regions, and A plurality of second light emitting devices disposed in parallel along corresponding light-transmitting regions among the plurality of light-transmitting regions are connected to a plurality of second pixel circuits disposed in corresponding non-transmitting regions among the plurality of non-transmitting regions.

10. The light emitting display panel according to claim 8, wherein a plurality of first pixel circuits disposed in parallel along a corresponding non-transmission area among the plurality of non-transmission areas are connected to a plurality of first light emitting devices disposed in parallel along a corresponding light-transmission area disposed at one side of the corresponding non-transmission area, and A plurality of second pixel circuits disposed in parallel along a corresponding non-transmission area among the plurality of non-transmission areas are connected to a plurality of second light emitting devices disposed in parallel along a corresponding light-transmission area disposed at the other side of the corresponding non-transmission area.

11. The light emitting display panel according to claim 8, in, Each of the first pixel circuit and the second pixel circuit includes: a first transistor including a first terminal connected to a pixel driving voltage line and a gate connected to an emission control line; a drive transistor comprising a first terminal connected to the second terminal of the first transistor; a second transistor including a gate connected to the emission control line, a first terminal connected to the second terminal of the drive transistor, and a second terminal connected to the light emitting device layer; a capacitor comprising a first terminal connected to the first terminal of the first transistor and a second terminal connected to the gate of the drive transistor; a third transistor including a gate connected to an nth scan control line, a first terminal connected to a data line, and a second terminal connected to the first terminal of the driving transistor; a fourth transistor including a gate connected to the nth scan control line, a first terminal connected to the gate of the driving transistor, and a second terminal connected to the second terminal of the driving transistor; a fifth transistor including a gate connected to the nth scan control line, a first terminal connected to an initialization voltage line, and a second terminal connected to the second terminal of the second transistor; and A sixth transistor includes a gate connected to an (n-1)th scan control line, a first terminal connected to the initialization voltage line, and a second terminal connected to the first terminal of the fourth transistor.

12. The light emitting display panel according to claim 8, wherein The plurality of first light emitting devices and the plurality of second light emitting devices disposed in the transparent region are each arranged in a row in a first direction, and The plurality of second light emitting devices are arranged to be staggered relative to the plurality of first light emitting devices in a second direction.

13. The light emitting display panel according to claim 8, wherein The plurality of first pixel circuits and the plurality of second pixel circuits are not provided in the plurality of light-transmitting regions, and The plurality of first light emitting devices and the plurality of second light emitting devices are arranged in the plurality of light-transmitting regions in opposite directions, wherein the non-transmitting region is located between the plurality of first light emitting devices and the plurality of second light emitting devices.

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