Level conversion logic circuit and electronic device

Abstract

The present invention provides a level conversion logic circuit and an electronic device, including: a first depletion-mode logic transistor, a second depletion-mode logic transistor, and a first enhancement-mode logic transistor; both the first depletion-mode logic transistor and the second depletion-mode logic transistor are logic transistors with a negative voltage turn-on characteristic; a first end of the first depletion-mode logic transistor is directly or indirectly connected to a control end of the first enhancement-mode logic transistor, a first end of the first enhancement-mode logic transistor is connected to a voltage source, and a second end of the first enhancement-mode logic transistor is connected to a first end of the second depletion-mode logic transistor; a control end of the first depletion-mode logic transistor and a control end of the second depletion-mode logic transistor are both grounded; a second end of the first enhancement-mode logic transistor and the first end of the second depletion-mode logic transistor are further connected to a signal output end, and a second end of the first depletion-mode logic transistor and a second end of the second depletion-mode logic transistor are both connected to a signal input end.

Description

Technical Field

[0001] The present invention relates to the field of radio frequency signal processing, and particularly to a level conversion logic circuit and an electronic device. Background Art

[0002] A level conversion logic circuit can be understood as a circuit that can perform level conversion on an input signal and then output the converted signal, and it can also be characterized as a Level Shifter logic circuit.

[0003] Among them, the function of level conversion can be realized by logic transistors. In the existing related technologies, enhancement-mode logic transistors can be used to form a multi-stage inverter. Then, when the input signal is equal to 0, the two-stage inverter can output a low level, and when the input signal gradually rises above a certain threshold, the two-stage inverter can output a high level.

[0004] Among them, since the turn-on voltage of the enhancement-mode logic transistor is relatively low, usually about 0.25V, when there is a perturbation in the level of the input terminal signal, the level is prone to incorrect inversion. Summary of the Invention

[0005] The present invention provides a level conversion logic circuit and an electronic device to solve the problem that the level is prone to incorrect inversion.

[0006] According to a first aspect of the present invention, there is provided a level conversion logic circuit, including: a first depletion-mode logic transistor, a second depletion-mode logic transistor, and a first enhancement-mode logic transistor; both the first depletion-mode logic transistor and the second depletion-mode logic transistor are logic transistors with a negative voltage turn-on characteristic;

[0007] A first end of the first depletion-mode logic transistor is directly or indirectly connected to a control end of the first enhancement-mode logic transistor, a first end of the first enhancement-mode logic transistor is connected to a voltage source, a second end of the first enhancement-mode logic transistor is connected to a first end of the second depletion-mode logic transistor; a control end of the first depletion-mode logic transistor and a control end of the second depletion-mode logic transistor are both grounded;

[0008] The second end of the first enhancement-mode logic transistor and the first end of the second depletion-mode logic transistor are further connected to a signal output end, and a second end of the first depletion-mode logic transistor and a second end of the second depletion-mode logic transistor are both connected to a signal input end.

[0009] Optionally, the level conversion logic circuit further includes an active biasing module, and the active biasing module is connected to the control end of the first enhancement-mode logic transistor to provide a biasing voltage to the first enhancement-mode logic transistor.

[0010] Optionally, the active biasing module includes a third depletion-mode logic transistor and a plurality of second enhancement-mode logic transistors;

[0011] The first end of the third depletion-type logic transistor is connected to the voltage source, the first end of the first second enhancement-type logic transistor among the plurality of second enhancement-type logic transistors is connected to the second end of the third depletion-type logic transistor, and the first end of each second enhancement-type logic transistor except the first second enhancement-type logic transistor is connected to the second end of the previous second enhancement-type logic transistor. The second end of the last second enhancement-type logic transistor among the plurality of second enhancement-type logic transistors is connected to the control end of the third depletion-type logic transistor, the first end of the first depletion-type logic transistor, and the control end of the first enhancement-type logic transistor; the first end of each second enhancement-type logic transistor is connected to the control end of this second enhancement-type logic transistor.

[0012] Optionally, the sizes of the second enhancement-type logic transistor and the third depletion-type logic transistor, and the number of the second enhancement-type logic transistors are matched to a static current that meets the requirements.

[0013] Optionally, the number of the second enhancement-type logic transistors is three.

[0014] Optionally, the turn-off voltages of the first depletion-type logic transistor and the second depletion-type logic transistor are within the range of -0.75 volts to -1.25 volts.

[0015] Optionally, the turn-off voltages of the first depletion-type logic transistor and the second depletion-type logic transistor are -1 volt.

[0016] Optionally, the level conversion logic circuit is fabricated using the ED-pHEMT process.

[0017] Optionally, the signal input to the signal input terminal is a radio frequency signal, or: the signal input to the signal input terminal is formed based on the radio frequency signal.

[0018] According to a second aspect of the present invention, there is provided an electronic device including the level conversion logic circuit involved in the first aspect and its optional solutions.

[0019] In the level conversion logic circuit and electronic device provided by the present invention, the change of the input signal can change the state of the depletion-type logic tube. At the same time, the state of the first enhancement-type logic tube can be changed. Furthermore, the output signal between the first enhancement-type logic tube and the second depletion-type logic tube can match the change, realizing the conversion between the output signal and the input signal. Among them, since both the first enhancement-type logic tube and the second depletion-type logic tube are logic tubes that are turned on by negative voltage, furthermore, the two depletion-type logic tubes can be turned on when the input signal is 0V (or close to 0V), and when the input signal rises to a certain amplitude (that is, when a turn-off voltage is formed between the input signal and the ground), the two depletion-type logic tubes can be driven to turn off. Since the absolute value of the turn-off voltage of the logic tube turned on by negative voltage is greater than the turn-on voltage of the enhancement-type logic tube, furthermore, false flips caused by disturbances of the input signal can be avoided, playing an anti-interference role.

[0020] For some processes (such as the ED-pHEMT process), the devices that can be formed are limited. Since the present invention mainly uses depletion-type logic tubes and enhancement-type logic tubes, it is convenient to implement in the ED-pHEMT process or other processes that can form depletion-type logic tubes and enhancement-type logic tubes.

[0021] In a further solution, the active bias module formed by the logic tube can also achieve the positive effects of low power consumption, large driving ability, and reduction of the area of the logic circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0023] Figure 1 is a circuit schematic diagram of the level conversion logic circuit in an embodiment of the present invention Figure 1 ;

[0024] Figure 2 is a circuit schematic diagram of the level conversion logic circuit in an embodiment of the present invention Figure 2 ;

[0025] Figure 3 is a circuit schematic diagram of the level conversion logic circuit in an embodiment of the present invention Figure 3 .

[0026] DESCRIPTION OF THE REFERENCE NUMERALS:

[0027] 1 - Active bias module;

[0028] DT1 - First depletion-type logic tube;

[0029] DT2 - The second depletion-mode logic transistor;

[0030] ET1 - The first enhancement-mode logic transistor;

[0031] ET2, ET3, ET4 - The second enhancement-mode logic transistors;

[0032] DT3 - The third depletion-mode logic transistor;

[0033] Vdd - Voltage source. Detailed implementation manners

[0034] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0035] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned accompanying drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0036] Next, the technical solutions of the present invention will be described in detail with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0037] Please refer to Figure 1 , a level conversion logic circuit, including: a first depletion-mode logic transistor DT1, a second depletion-mode logic transistor DT2, and a first enhancement-mode logic transistor ET1. This level conversion logic circuit can be a level conversion logic circuit based on ED-pHEMT, that is, fabricated using the ED-pHEMT process. In addition, the circuit parts fabricated using the ED-pHEMT process are not limited to this level conversion logic circuit. For example, an RF chip including this level conversion logic circuit can be fabricated using the ED-pHEMT process.

[0038] Among them, E can be understood as representing an E-mode logic transistor, that is, an enhancement-mode logic transistor;

[0039] Among them, D can be understood as representing a D-mode logic transistor, that is, a depletion-mode logic transistor;

[0040] Among them, pHEMT can be understood as a pseudomorphic high electron mobility transistor process.

[0041] Furthermore, ED-pHEMT can be understood as a pseudomorphic high electron mobility transistor process that uses (or mainly uses) E-mode logic transistors and D-mode logic transistors to form a circuit.

[0042] The first depletion-mode logic transistor DT1 and the second depletion-mode logic transistor DT2 are both logic transistors with a negative voltage turn-on characteristic; for logic transistors with a negative voltage turn-on characteristic, the embodiment of the present invention breaks through the conventional control means for logic transistors (that is, inputting an input signal to the control terminal of the logic transistor). Through the negative voltage turn-on characteristic, a turn-off voltage with a relatively large absolute value (greater than the turn-on voltage of the enhancement-mode logic transistor) can be introduced.

[0043] In one implementation, the turn-off voltages of the first depletion-mode logic transistor DT1 and the second depletion-mode logic transistor DT2 are in the range of -0.75 volts to -1.25 volts (which can be understood as about -1 volt). In a further example, the turn-off voltage can be -1 volt.

[0044] Among them, the sizes of the first depletion-mode logic transistor DT1 and the second depletion-mode logic transistor DT2 can be the same or different. No matter what kind of depletion-mode logic transistor is used, as long as it can meet the negative voltage turn-on characteristic and the turn-off voltage in the present invention, it does not deviate from the scope of the embodiment of the present invention.

[0045] The first end of the first depletion-mode logic transistor DT1 is directly or indirectly connected to the control terminal of the first enhancement-mode logic transistor ET1. The first end of the first enhancement-mode logic transistor ET1 is connected to the voltage source Vdd, and the second end of the first enhancement-mode logic transistor ET1 is connected to the first end of the second depletion-mode logic transistor DT2; the control terminals of the first depletion-mode logic transistor DT1 and the second depletion-mode logic transistor DT2 are both grounded;

[0046] The second end of the first enhancement-mode logic transistor ET1 and the first end of the second depletion-mode logic transistor DT2 are also connected to the signal output terminal. Furthermore, a corresponding output signal Vo can be output. The second ends of the first depletion-mode logic transistor DT1 and the second depletion-mode logic transistor DT2 are both connected to the signal input terminal. Furthermore, a corresponding input signal Vc can be input.

[0047] In the above scheme, the change of the input signal can change the state of the depletion-mode logic tube, and at the same time, the state of the first enhancement-mode logic tube can be changed. Then, the output signals between the first enhancement-mode logic tube and the second depletion-mode logic tube can match the change, thereby realizing the conversion between the output signal and the input signal.

[0048] Among them, since the first enhancement-type logic tube and the second depletion-type logic tube are both negative-voltage-turned-on logic tubes, the two depletion-type logic tubes can be turned on when the input signal is 0V (or close to 0V). When the input signal rises to a certain amplitude (that is, when a turn-off voltage is formed between the input signal and the ground), the two depletion-type logic tubes can be driven to turn off. Since the absolute value of the turn-off voltage of the negative-voltage-turned-on logic tube is greater than the turn-on voltage of the enhancement-type logic tube, erroneous flipping caused by disturbances in the input signal can be avoided, thereby playing an anti-interference role.

[0049] Based on the above characteristics of depletion mode logic transistors and enhancement mode logic transistors, the working principle formed can be, for example:

[0050] When the input signal Vc is 0 volts, the first depletion-type logic transistor DT1 and the second depletion-type logic transistor DT2 are turned on, and the control end of the first enhancement-type logic transistor ET4 will be pulled to a low level by the first depletion-type logic transistor DT1. At this time, the first enhancement-type logic transistor ET4 is in the off state; at the same time, the second depletion-type logic transistor DT2 will pull the signal output end down to a low level. At this time, the output signal Vo is a low level.

[0051] When the level of the input voltage Vc continues to increase (for example, gradually increases to 1V), the first depletion-mode logic transistor DT1 and the second depletion-mode logic transistor DT2 will gradually turn off. At this time, the control end of the first enhancement-mode logic transistor ET1 will be converted to a high level, the first enhancement-mode logic transistor ET1 will be turned on, and the output signal Vo will be a high level.

[0052] Among them, the control end of the logic tube can also be understood as the gate end of the logic tube.

[0053] For some processes (such as ED-pHEMT process), the devices that can be formed are limited. Since the present invention mainly adopts depletion-type logic tubes and enhancement-type logic tubes for implementation, it can be easily implemented in ED-pHEMT process or other processes that can form depletion-type logic tubes and enhancement-type logic tubes.

[0054] In one implementation, please refer to Figure 2 The level conversion logic circuit further includes an active bias module 1, which is connected to the control end of the first enhancement mode logic transistor ET1 to provide a bias voltage to the first enhancement mode logic transistor ET1.

[0055] In a specific solution, the active bias module can be implemented using a resistor. For example, a resistor or a resistor unit (the resistor unit may include multiple resistors connected in series and / or in parallel) can be connected to the control end of the first enhanced logic transistor ET1, and a voltage source (such as voltage source Vdd or other voltage source) can be connected through the resistor or resistor unit. The resistor or resistor unit is generally required to form a relatively high impedance.

[0056] Solutions that use resistors or resistor units typically occupy a large area. Furthermore, when applied to ED-pHEMT (i.e., the level-conversion logic circuit is an ED-pHEMT-based level-conversion logic circuit), only two types of logic transistors are typically available: depletion-mode logic transistors and enhancement-mode logic transistors. These two logic transistors have leakage at their control terminals, making input signal processing very difficult. To reduce leakage, very large resistors are required (e.g., for inverters in the prior art and the first enhancement-mode transistor in the example above). The larger the number of logic circuits, the larger the resistor area. Furthermore, for chips with leakage requirements at the uA level, the resistors are typically megohms, and this level of resistance requirement is typically unattainable in ED-pHEMT processes. Furthermore, the use of resistors can also affect the circuit's own driving capability.

[0057] For the above defects, please refer to the specific examples. Figure 3 The active bias module 1 includes a third depletion mode logic transistor DT3 and a plurality of second enhancement mode logic transistors (eg, a second enhancement mode logic transistor ET2 , a second enhancement mode logic transistor ET3 and a second enhancement mode logic transistor ET4 ).

[0058] A first terminal of the third depletion-mode logic transistor DT3 is connected to the voltage source Vdd.

[0059] The plurality of second enhanced logic transistors can be understood as being connected in series. Specifically:

[0060] A first end of a first second enhancement mode logic transistor (for example, the second enhancement mode logic transistor ET2 ) among the plurality of second enhancement mode logic transistors is connected to a second end of the third depletion mode logic transistor DT3 ;

[0061] Except for the first second enhanced logic transistor (for example, the second enhanced logic transistor ET2), the first end of each second enhanced logic transistor is connected to the second end of a second enhanced logic transistor. For example, the first end of the second enhanced logic transistor ET3 is connected to the second end of the second enhanced logic transistor ET2, and the first end of the second enhanced logic transistor ET4 is connected to the second end of the second enhanced logic transistor ET3.

[0062] The second terminal of the last second enhancement-type logic transistor (e.g., the second enhancement-type logic transistor ET4) among the multiple second enhancement-type logic transistors is connected to the control terminal of the third depletion-type logic transistor DT3, the first terminal of the first depletion-type logic transistor DT1, and the control terminal of the first enhancement-type logic transistor ET1.

[0063] In addition, the first terminal of each second enhancement-type logic transistor is connected to the control terminal of this second enhancement-type logic transistor. For example, the first terminal of the second enhancement-type logic transistor ET4 is connected to the control terminal, the first terminal of the second enhancement-type logic transistor ET3 is connected to the control terminal, and the first terminal of the second enhancement-type logic transistor ET2 is connected to the control terminal.

[0064] In the above solution, the active bias module formed by the logic transistors can also achieve the positive effects of low power consumption, large driving ability, and reduction of the area of the logic circuit.

[0065] In Figure 3 In the illustrated example, the number of second enhancement-type logic transistors is three (i.e., the second enhancement-type logic transistor ET2, the second enhancement-type logic transistor ET3, and the second enhancement-type logic transistor ET4). In other examples, the number of second enhancement-type logic transistors can also be two or more than three.

[0066] In order to further meet the requirement of the static current, the sizes of the second enhancement-type logic transistor and the third depletion-type logic transistor, and the number of the second enhancement-type logic transistors are matched to the static current that meets the requirement. Furthermore, by adjusting the sizes and the number of the third depletion-type logic transistor DT3 and the second enhancement-type logic transistors, the static current can be adjusted, and this structure can achieve static currents from nanoamperes (nA), microamperes (μA) to milliamperes (mA).

[0067] When the above level conversion logic circuit is applied to process a radio frequency signal, in one example, the signal input to the signal input terminal can be a radio frequency signal. In another example, the signal input to the signal input terminal is formed based on the radio frequency signal. For example, the radio frequency signal can be filtered, amplified, or converted in other ways to form the signal input to the signal input terminal.

[0068] The embodiment of the present invention also provides an electronic device, including the level conversion logic circuit involved in the above optional solutions.

[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A level conversion logic circuit, characterized in that, Comprising: A first depletion-mode logic transistor, a second depletion-mode logic transistor, and a first enhancement-mode logic transistor; Both the first depletion-mode logic transistor and the second depletion-mode logic transistor are logic transistors with a negative voltage turn-on characteristic; A first end of the first depletion-mode logic transistor is connected to a control end of the first enhancement-mode logic transistor, a first end of the first enhancement-mode logic transistor is connected to a voltage source, and a second end of the first enhancement-mode logic transistor is connected to a first end of the second depletion-mode logic transistor; a control end of the first depletion-mode logic transistor and a control end of the second depletion-mode logic transistor are both grounded; A second end of the first enhancement-mode logic transistor and a first end of the second depletion-mode logic transistor are further connected to a signal output end, and a second end of the first depletion-mode logic transistor and a second end of the second depletion-mode logic transistor are both connected to a signal input end; The level conversion logic circuit is fabricated using an ED-pHEMT process.

2. The level conversion logic circuit according to claim 1, wherein It further includes an active bias module, and the active bias module is connected to a control end of the first enhancement-mode logic transistor to provide a bias voltage to the first enhancement-mode logic transistor.

3. The level conversion logic circuit according to claim 2, wherein The active bias module includes a third depletion-mode logic transistor and a plurality of second enhancement-mode logic transistors; A first end of the third depletion-mode logic transistor is connected to the voltage source, a first end of a first second enhancement-mode logic transistor among the plurality of second enhancement-mode logic transistors is connected to a second end of the third depletion-mode logic transistor, and except for the first second enhancement-mode logic transistor, a first end of each second enhancement-mode logic transistor is connected to a second end of the previous second enhancement-mode logic transistor. A second end of the last second enhancement-mode logic transistor among the plurality of second enhancement-mode logic transistors is connected to a control end of the third depletion-mode logic transistor, a first end of the first depletion-mode logic transistor, and a control end of the first enhancement-mode logic transistor; a first end of each second enhancement-mode logic transistor is connected to a control end of this second enhancement-mode logic transistor.

4. The level conversion logic circuit according to claim 3, wherein The sizes of the second enhancement-mode logic transistor and the third depletion-mode logic transistor, and the number of the second enhancement-mode logic transistors are matched to a static current that meets the requirements.

5. The level conversion logic circuit according to claim 3, characterized in that, The number of the second enhancement-mode logic transistors is three.

6. The level conversion logic circuit according to any one of claims 1 to 5, characterized in that The turn-off voltages of the first depletion-mode logic transistor and the second depletion-mode logic transistor are in the range of -0.75 volts to -1.25 volts.

7. The level conversion logic circuit according to claim 6, wherein The turn-off voltages of the first depletion-mode logic transistor and the second depletion-mode logic transistor are -1 volt.

8. The level conversion logic circuit according to any one of claims 1 to 5, characterized in that The signal input to the signal input end is a radio frequency signal, or: the signal input to the signal input end is formed based on the radio frequency signal.

9. An electronic device, characterized in that, Comprising the level conversion logic circuit according to any one of claims 1 to 8.

Images