Level conversion circuit

Abstract

The present invention relates to a level conversion circuit, comprising a first amplifier, a second amplifier, a third amplifier, a fourth amplifier, a first inverter, a second inverter, a forward input signal, a reverse input signal, a forward output signal, and a reverse output signal, wherein the first amplifier and the third amplifier A3 are powered by a first power supply, and the second amplifier, the fourth amplifier, the first inverter, and the second inverter are powered by a second power supply, wherein the voltage of the first power supply is slightly higher than the voltage of the second power supply. A level conversion circuit of the present invention is a level conversion circuit that can be used for high-speed signal transmission.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a level conversion circuit. Background Art

[0002] Multi-power supply voltage domain technology is widely used in System on Chip (SoC), where each module in the system works at an appropriate power supply voltage according to its timing requirements. Generally speaking, modules with critical timing usually work at a higher power supply voltage to meet the speed performance indicators of the chip; modules with low timing requirements usually work at a lower power supply voltage to reduce the power consumption of the chip.

[0003] In chips that use multi-power supply voltage domain technology, the level conversion circuit is an important module. It provides a way for modules working in different voltage domains to interact and ensure the correct transmission of signals between voltage domains. When the signal is converted from a high voltage domain to a low voltage domain, an ordinary buffer can be used to achieve cross-voltage domain transmission of the signal; when the signal is converted from a low voltage domain to a high voltage domain, a more complex level conversion circuit is required.

[0004] Traditional level conversion circuits include cross-coupled level conversion circuits and current mirror-based level conversion circuits. Figure 1 As shown, in the cross-coupled level conversion circuit, when the input signal A changes from low to high, there are three inverter delays (MP1 / MN1, MP2 / MN2, MP22 / MN22) and the conduction delay of MN12 from the change of input signal A to the change of output signal Y; when the input signal A changes from high to low, there are two inverter delays (MP1 / MN1, MP22 / MN22), the conduction delay of MN11 and the conduction delay of MP12 from the change of input signal A to the change of output signal Y. Since the delay of the inverter (MP2 / MN2) is much smaller than the conduction delay of MP12, the rising delay of the output signal is much faster than the falling delay, resulting in an unreasonable output duty cycle of the level conversion circuit, which restricts the overall performance of the on-chip system. Figure 2 As shown in the figure, in the level conversion circuit based on the current mirror, the rising delay and falling delay of the input and output signals of the circuit are seriously mismatched, which has a great impact on high-speed signals. In addition, the rising delay and falling delay of the level converter in the above two level conversion circuits are large, and the conversion time of the level conversion circuit is long, which is not suitable for high-speed and high-performance chip-on-chip systems. Therefore, a level conversion circuit for high-speed signal transmission is urgently needed. Summary of the invention

[0005] The present invention provides a level conversion circuit to solve the problem that the conversion time of the existing level conversion circuit is long and the system performance is restricted.

[0006] To solve the above technical problems, the present invention provides a level conversion circuit, comprising a first amplifier, a second amplifier, a third amplifier, a fourth amplifier, a first inverter, a second inverter, a positive input signal, a reverse input signal, a positive output signal, and a reverse output signal, wherein the first amplifier and the third amplifier are powered by a first power supply, and the second amplifier, the fourth amplifier, the first inverter, and the second inverter are powered by a second power supply, and the voltage of the first power supply is higher than the voltage of the second power supply; the positive input signal is input to the positive input terminal of the first amplifier and the negative input terminal of the third amplifier, and the reverse input signal is input to the negative input terminal of the first amplifier and the positive input terminal of the third amplifier, the output terminal of the first amplifier is connected to the positive input terminal of the second amplifier, the output terminal of the third amplifier is connected to the positive input terminal of the fourth amplifier, the output terminal of the second amplifier is connected to the negative input terminal of the fourth amplifier, the input terminal of the first inverter, and the output terminal of the second inverter, the output terminal of the fourth amplifier is connected to the negative input terminal of the second amplifier, the output terminal of the first inverter, and the input terminal of the second inverter, the output terminal of the first inverter outputs the reverse output signal, and the output terminal of the second inverter outputs the positive output signal.

[0007] Preferably, the first amplifier includes a first bias voltage signal node, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor and a second NMOS transistor, the first PMOS transistor is connected in series between the first bias voltage signal node and the first power supply, the second PMOS transistor and the first NMOS transistor are connected in series between the first bias voltage signal node and the ground terminal, and the third PMOS transistor and the second NMOS transistor are connected in series between the first bias voltage signal node and the ground terminal.

[0008] Preferably, the source of the first PMOS tube is connected to the first power supply, the gate of the second PMOS tube receives the forward input signal, the gate of the third PMOS tube receives the reverse input signal, the gate and drain of the first NMOS tube are short-circuited, the source of the second NMOS tube and the source of the first NMOS tube are connected to the ground terminal, and the gate of the first NMOS tube is connected to the gate of the second NMOS tube.

[0009] Preferably, the second amplifier includes a fourth PMOS tube, a fifth PMOS tube, a fourth NMOS tube, and a fifth NMOS tube, the fourth PMOS tube and the fourth NMOS tube are connected in series between the second power supply and the ground terminal, and the fifth PMOS tube and the fifth NMOS tube are connected in series between the second power supply and the ground terminal.

[0010] Preferably, the source of the fourth PMOS tube and the source of the fifth PMOS tube are connected to the second power supply, the gate and the drain of the fourth PMOS tube are short-circuited, the source of the fourth NMOS tube and the source of the fifth NMOS tube are connected to the ground terminal, the drain of the fifth NMOS tube and the drain of the fifth PMOS tube output the forward output signal, and the gate of the fifth PMOS tube is connected to the gate of the fourth PMOS tube.

[0011] Preferably, the third amplifier includes a second bias voltage signal node, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a seventh NMOS tube, and an eighth NMOS tube. The ninth PMOS tube and the eighth NMOS tube are connected in series between the second bias voltage signal node and the ground terminal, and the eighth PMOS tube and the seventh NMOS tube are connected in series between the second bias voltage signal node and the ground terminal; the seventh PMOS tube is connected in series between the second bias voltage and the first power supply, the gate of the ninth PMOS tube receives the forward input signal, the gate of the eighth PMOS tube receives the reverse input signal, the gate and the drain of the seventh NMOS tube are short-circuited, the source of the seventh NMOS tube and the source of the eighth NMOS tube are connected to the ground terminal, and the gate of the seventh NMOS tube is connected to the gate of the eighth NMOS tube.

[0012] Preferably, the fourth amplifier includes a tenth PMOS tube, an eleventh PMOS tube, a tenth NMOS tube, and an eleventh NMOS tube, the tenth PMOS tube and the tenth NMOS tube are connected in series between the second power supply and the ground terminal, and the eleventh PMOS tube and the eleventh NMOS tube are connected in series between the second power supply and the ground terminal; the source of the eleventh PMOS tube and the source of the tenth PMOS tube are connected to the second power supply, the gate and the drain of the tenth PMOS tube are short-circuited, the source of the tenth NMOS tube and the source of the eleventh NMOS tube are connected to the ground terminal, the drain of the eleventh NMOS tube and the drain of the eleventh PMOS tube output the reverse output signal, the gate of the eleventh PMOS tube is connected to the gate of the tenth PMOS tube, the gate of the eleventh NMOS tube is connected to the gate of the fourth NMOS tube, and the gate of the tenth NMOS tube is connected to the gate of the fifth NMOS tube.

[0013] Preferably, the first inverter includes a sixth PMOS tube and a sixth NMOS tube, and the second inverter includes a twelfth PMOS tube and a twelfth NMOS tube, the sixth PMOS tube and the sixth NMOS tube are connected in series between the second power supply and the ground terminal, and the twelfth PMOS tube and the twelfth NMOS tube are connected in series between the second power supply and the ground terminal; the source of the sixth PMOS tube and the source of the twelfth PMOS tube are connected to the second power supply, the source of the sixth NMOS tube and the source of the twelfth NMOS tube are connected to the ground terminal, the gate of the sixth PMOS tube, the gate of the sixth NMOS tube, the drain of the twelfth PMOS tube, and the drain of the twelfth NMOS tube output a positive output signal, and the drain of the sixth PMOS tube, the drain of the sixth NMOS tube, the gate of the twelfth PMOS tube, and the gate of the twelfth NMOS tube output a reverse output signal.

[0014] Preferably, the level conversion circuit further includes a third NMOS tube and a ninth NMOS tube, the gate of the third NMOS tube is connected to the gate of the fourth NMOS tube, the gate and the drain of the third NMOS tube are short-circuited, and the source of the third NMOS tube is grounded; the gate of the ninth NMOS tube is connected to the gate of the tenth NMOS tube, the gate and the drain of the ninth NMOS tube are short-circuited, and the source of the ninth NMOS tube is grounded.

[0015] Preferably, the gain Av1 of the first amplifier is gmp3 / gmn3, the gain Av2 of the second amplifier is gmn5*(rop5||ron5), the gain Av3 of the third amplifier is gmp9 / gmn9, and the gain Av4 of the fourth amplifier is gmn11*(rop11||ron11), wherein gmp3, gmp9, gmn3, gmn5, gmn9, gmn11 are the transconductances of the third PMOS tube and the ninth PMOS tube, the third NMOS tube, the fifth NMOS tube, the ninth NMOS tube and the eleventh NMOS tube respectively, rop5, rop11, ron5, ron11 are the small signal resistances of the fifth PMOS tube and the eleventh PMOS tube, the fifth NMOS tube and the eleventh NMOS tube respectively, and the voltage gain Av of the two-stage amplifier is Av1*Av2=Av3*Av4=gmp3*gmn5*(rop5||ron5) / gmn3.

[0016] Compared with the prior art, the level conversion circuit of the present invention has the following beneficial effects:

[0017] (1) The level conversion circuit of the present invention shapes the input low-swing logic level to make its transition edge steep and phase-even, and outputs it with a VDD2 full-swing signal;

[0018] (2) The level conversion circuit of the present invention is completely symmetrical, and the output complementary clock has almost no phase error;

[0019] (3) The level conversion circuit of the present invention adopts a two-stage amplifier structure to provide a higher gain and reduce the delay of level conversion;

[0020] (4) The level conversion circuit of the present invention is designed with a diode-connected NMOS tube to limit the output voltage swing of the first amplifier A1 and the third amplifier A3 and protect the input transistors of the second amplifier A2 and the fourth amplifier A4. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a cross-coupled level conversion circuit in the prior art;

[0022] Figure 2 It is a level conversion circuit based on current mirror in the prior art;

[0023] Figure 3 It is an overall structural diagram of a level conversion circuit of the present invention;

[0024] Figure 4 It is a basic circuit diagram of a level conversion circuit of the present invention;

[0025] Figure 5 It is a transient simulation waveform of Example 1 of a level conversion circuit of the present invention. DETAILED DESCRIPTION

[0026] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0027] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be an intermediate element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be an intermediate element at the same time.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0029] See also Figure 3In the overall structure diagram of a level conversion circuit of the present invention, the first amplifier A1, the second amplifier A2, the third amplifier A3, the fourth amplifier A4, the first inverter I1, the second inverter I2, the positive input signal INP, the reverse input signal I NN, the positive output signal OUTP, the reverse output signal OUTN, the first amplifier A1 and the third amplifier A3 are powered by a first power supply VDD1, the second amplifier A2, the fourth amplifier A4, the first inverter I1 and the second inverter I2 are powered by a second power supply VDD2, the voltage of the first power supply VDD1 is slightly higher than the voltage of the second power supply VDD2, and the voltage of the second power supply VDD2 is lower than the gate breakdown voltage of the transistor.

[0030] The positive input signal I NP is input to the positive input terminal of the first amplifier A1 and the negative input terminal of the third amplifier A3, the negative input signal I NN is input to the negative input terminal of the first amplifier A1 and the positive input terminal of the third amplifier A3, the output terminal of the first amplifier A1 is connected to the positive input terminal of the second amplifier A2, the output terminal of the third amplifier A3 is connected to the positive input terminal of the fourth amplifier A4, the output terminal of the second amplifier A2 is connected to the negative input terminal of the fourth amplifier A4, the input terminal of the first inverter I1 and the output terminal of the second inverter I2, the output terminal of the fourth amplifier A4 is connected to the negative input terminal of the second amplifier A2, the output terminal of the first inverter I1 and the input terminal of the second inverter I2. The first inverter I1 and the second inverter I2 are connected end to end to form a latch, the output terminal of the first inverter I1 outputs the reverse output signal OUTN of the level conversion circuit, and the output terminal of the second inverter I2 outputs the positive output signal OUTP of the level conversion circuit.

[0031] See also Figure 4 In a basic circuit diagram of a level conversion circuit of the present invention, the first amplifier A1 includes three PMOS tubes and two NMOS tubes, the three PMOS tubes are respectively a first PMOS tube MP1, a second PMOS tube MP2, and a third PMOS tube MP3, and the two NMOS tubes are respectively a first NMOS tube MN1 and a second NMOS tube MN2. The first amplifier A1 also includes a first bias voltage signal node, the first PMOS tube MP1 is connected in series between the first bias voltage signal node and a first power supply VDD1, the second PMOS tube MP2 and the first NMOS tube MN1 are connected in series between the first bias voltage signal node and a ground terminal, and the third PMOS tube MP3 and the second NMOS tube MN2 are connected in series between the first bias voltage signal node and a ground terminal.

[0032] The source of the first PMOS tube MP1 is connected to the first power supply VDD1, the gate of the second PMOS tube MP2 receives the positive input signal I NP, the gate of the third PMOS tube MP3 receives the reverse input signal I NN, the gate and drain of the first NMOS tube MN1 are short-circuited, the source of the second NMOS tube MN2 and the source of the first NMOS tube MN1 are connected to the ground end, and the gate of the first NMOS tube MN1 is connected to the gate of the second NMOS tube MN2.

[0033] Specifically, the source of the first PMOS tube MP1 is connected to the first power supply VDD1, the gate of the first PMOS tube MP1 inputs the tail current tube gate bias voltage signal of the first amplifier A1, the drain of the first PMOS tube MP1 is connected to the source of the second PMOS tube MP2 and the source of the third PMOS tube MP3, the gate of the second PMOS tube MP2 receives the positive input signal I NP, the gate of the third PMOS tube MP3 receives the reverse input signal I NN, the drain of the second PMOS tube MP2 is connected to the drain of the first NMOS tube MN1, the drain and the gate of the first NMOS tube MN1 are short-circuited, the source of the first NMOS tube MN1 and the source of the second NMOS tube MN2 are connected to the ground end, the gate of the second NMOS tube MN2 is connected to the gate of the first NMOS tube MN1, and the drain of the second NMOS tube MN2 is connected to the drain of the third PMOS tube MP3.

[0034] The second amplifier A2 includes two PMOS tubes and two NMOS tubes, the two PMOS tubes are respectively a fourth PMOS tube MP4 and a fifth PMOS tube MP5, and the two NMOS tubes are respectively a fourth NMOS tube MN4 and a fifth NMOS tube MN5. The fourth PMOS tube MP4 and the fourth NMOS tube MN4 are connected in series between the second power supply VDD2 and the ground terminal, and the fifth PMOS tube MP5 and the fifth NMOS tube MN5 are connected in series between the second power supply VDD2 and the ground terminal.

[0035] The source of the fourth PMOS tube MP4 and the source of the fifth PMOS tube MP5 are connected to the second power supply VDD2, the gate and the drain of the fourth PMOS tube MP4 are short-circuited, the source of the fourth NMOS tube MN4 and the source of the fifth NMOS tube MN5 are connected to the ground terminal, the drain of the fifth NMOS tube MN5 and the drain of the fifth PMOS tube output the positive output signal OUTP, and the gate of the fifth PMOS tube MP5 is connected to the gate of the fourth PMOS tube MP4.

[0036] Specifically, the source of the fourth PMOS tube MP4 and the source of the fifth PMOS tube MP5 are connected to the second power supply VDD2, the gate and the drain of the fourth PMOS tube MP4 are short-circuited, the gate of the fourth PMOS tube MP4 is connected to the gate of the fifth PMOS tube MP5, and the drain of the fifth PMOS tube MP5 outputs the positive output signal OUTP, the drain of the fourth PMOS tube MP4 is connected to the drain of the fourth NMOS tube MN4, the gate of the fourth NMOS tube MN4 is connected to the drain of the third PMOS tube and the drain of the second NMOS tube, the source of the fourth NMOS tube MN4 and the source of the fifth NMOS tube MN5 are connected to the ground terminal, the drain of the fifth NMOS tube MN5 is connected to the drain of the fifth PMOS tube MP5, and the drain of the fifth NMOS tube MN5 and the drain of the fifth PMOS tube MP5 output the positive output signal OUTP.

[0037] The third amplifier A3 includes three PMOS tubes and two NMOS tubes, the three PMOS tubes are respectively a seventh PMOS tube MP7, an eighth PMOS tube MP8, and a ninth PMOS tube MP9, and the two NMOS tubes are respectively a seventh NMOS tube MN7 and an eighth NMOS tube. The third amplifier A3 also includes a second bias voltage signal node, the seventh PMOS tube MP7 is connected in series between the second bias voltage signal node and the first power supply VDD1, the ninth PMOS tube MP9 and the eighth NMOS tube MN8 are connected in series between the second bias voltage signal node and the ground terminal, and the eighth PMOS tube MP8 and the seventh NMOS tube MN7 are connected in series between the second bias voltage signal node and the ground terminal.

[0038] The source of the seventh PMOS tube MP7 is connected to the first power supply VDD1, the gate of the ninth PMOS tube MP9 receives the positive input signal I NP, the gate of the eighth PMOS tube MP8 receives the reverse input signal I NN, the gate and drain of the seventh NMOS tube MN7 are short-circuited, the source of the seventh NMOS tube MN7 and the source of the eighth NMOS tube MN8 are connected to the ground end, and the gate of the seventh NMOS tube MN7 is connected to the gate of the eighth NMOS tube MN8.

[0039] Specifically, the source of the seventh PMOS tube MP7 is connected to the first power supply VDD1, the gate of the seventh PMOS tube MP7 inputs the tail current tube gate bias voltage signal of the third amplifier A3, the drain of the seventh PMOS tube MP7 is connected to the source of the ninth PMOS tube MP9 and the source of the eighth PMOS tube MP8, the gate of the ninth PMOS tube MP9 receives the positive input signal I NP, the gate of the eighth PMOS tube MP8 receives the reverse input signal I NN, the drain of the eighth PMOS tube MP8 is connected to the drain of the seventh NMOS tube MN7, the drain and the gate of the seventh NMOS tube MN7 are short-circuited, the source of the seventh NMOS tube MN7 and the source of the eighth NMOS tube MN8 are connected to the ground terminal, the gate of the seventh NMOS tube MN7 is connected to the gate of the eighth NMOS tube MN8, and the drain of the eighth NMOS tube MN8 is connected to the drain of the ninth PMOS tube MP9.

[0040] The fourth amplifier A4 includes two PMOS tubes and two NMOS tubes, the two PMOS tubes are respectively the tenth PMOS tube MP10 and the eleventh PMOS tube MP11, and the two NMOS tubes are respectively the tenth NMOS tube MN10 and the eleventh NMOS tube MN11. The tenth PMOS tube MP10 and the tenth NMOS tube MN10 are connected in series between the second power supply VDD2 and the ground terminal, and the eleventh PMOS tube MP11 and the eleventh NMOS tube MN11 are connected in series between the second power supply VDD2 and the ground terminal.

[0041] The source of the eleventh PMOS tube MP11 and the source of the tenth PMOS tube MP10 are connected to the second power supply VDD2, the gate and the drain of the tenth PMOS tube MP10 are short-circuited, the source of the tenth NMOS tube MN10 and the source of the eleventh NMOS tube MN11 are connected to the ground end, the drain of the eleventh NMOS tube MN11 and the drain of the eleventh PMOS tube MP11 output the reverse output signal OUTN, the gate of the eleventh PMOS tube MP11 is connected to the gate of the tenth PMOS tube MP10, the gate of the eleventh NMOS tube MN11 is connected to the gate of the fourth NMOS tube MN4, and the gate of the tenth NMOS tube MN10 is connected to the gate of the fifth NMOS tube MN5.

[0042] Specifically, the source of the tenth PMOS tube MP10 and the source of the eleventh PMOS tube MP11 are connected to the second power supply VDD2, the gate and the drain of the tenth PMOS tube MP10 are short-circuited, the gate of the tenth PMOS tube MP10 is connected to the gate of the eleventh PMOS tube MP11, the drain of the eleventh PMOS tube MP11 outputs the positive output signal OUTP, the drain of the tenth PMOS tube MP10 is connected to the drain of the tenth NMOS tube MN10, the source of the tenth NMOS tube MN10 and the source of the eleventh NMOS tube MN11 are connected to the ground terminal, and the tenth NMOS tube MN10 is connected to the ground terminal. The gate of the OS transistor MN10 is connected to the drain of the ninth PMOS transistor MP9 and the drain of the eighth NMOS transistor MN8 in the third amplifier A3, the drain of the eleventh NMOS transistor MN11 is connected to the drain of the eleventh PMOS transistor MP11, the drain of the eleventh NMOS transistor MN11 and the drain of the eleventh PMOS transistor MP11 output the positive output signal OUTP, the gate of the eleventh NMOS transistor MN11 is connected to the gate of the fourth NMOS transistor MN4 in the second amplifier A2, and the gate of the tenth NMOS transistor MN10 is connected to the gate of the fifth NMOS transistor MN5 in the second amplifier A2.

[0043] The first inverter I1 includes a sixth PMOS transistor MP6 and a sixth NMOS transistor MN6, and the second inverter I2 includes a twelfth PMOS transistor MP12 and a twelfth NMOS transistor MN12. The sixth PMOS transistor MP6 and the sixth NMOS transistor MN6 are connected in series between the second power supply VDD2 and the ground terminal, and the twelfth PMOS transistor MP12 and the twelfth NMOS transistor MN12 are connected in series between the second power supply VDD2 and the ground terminal; the source of the sixth PMOS transistor MP6 and the source of the twelfth PMOS transistor MP12 are connected to the second power supply VDD2, the source of the sixth NMOS transistor MN6 and the source of the twelfth NMOS transistor MN12 are connected to the ground terminal, the gate of the sixth PMOS transistor MP6, the gate of the sixth NMOS transistor MN6, the drain of the twelfth PMOS transistor MP12, and the drain of the twelfth NMOS transistor MN12 output the forward output signal OUTP, and the drain of the sixth PMOS transistor MP6, the drain of the sixth NMOS transistor MN6, the gate of the twelfth PMOS transistor MP12, and the gate of the twelfth NMOS transistor MN12 output the reverse output signal OUTN.

[0044] Specifically, the source of the sixth PMOS tube MP6 and the source of the twelfth PMOS tube MP12 are connected to the second power supply VDD2, the drain of the sixth PMOS tube MP6 is connected to the drain of the sixth NMOS tube MN6, the gate of the sixth PMOS tube MP6 is connected to the gate of the sixth NMOS tube MN6, the source of the sixth NMOS tube MN6 and the source of the twelfth NMOS tube MN12 are connected to the ground terminal, the drain of the twelfth NMOS tube MN12 is connected to the drain of the twelfth PMOS tube MP12, and the The source of the twelfth NMOS tube MN12 is connected to the source of the twelfth PMOS tube MP12, the gate of the sixth PMOS tube MP6, the gate of the sixth NMOS tube MN6, the drain of the twelfth PMOS tube MP12, and the drain of the twelfth NMOS tube MN12 output the forward output signal OUTP, and the drain of the sixth PMOS tube MP6, the drain of the sixth NMOS tube MN6, the gate of the twelfth PMOS tube MP12, and the gate of the twelfth NMOS tube MN12 output the reverse output signal OUTN.

[0045] The level conversion circuit further includes a third NMOS transistor MN3 and a ninth NMOS transistor MN9, wherein the gate of the third NMOS transistor MN3 is connected to the gate of the fourth NMOS transistor MN4, the gate and drain of the third NMOS transistor MN3 are short-circuited, the drain of the third NMOS transistor MN3 is connected to the drain of the third PMOS transistor MP3 and the drain of the second NMOS transistor MN2, and the source of the third NMOS transistor MN3 is grounded; the gate of the ninth NMOS transistor MN9 is connected to the gate of the tenth NMOS transistor MN10, the gate and drain of the ninth NMOS transistor MN9 are short-circuited, the gate of the ninth NMOS transistor MN9 is connected to the drain of the ninth PMOS transistor MP9 and the drain of the eighth NMOS transistor MN8, and the source of the ninth NMOS transistor MN9 is grounded. The third NMOS transistor MN3 and the ninth NMOS transistor MN are respectively used as diode-connected devices to limit the output voltage swing of the first amplifier A1 and the third amplifier A3.

[0046] In the present invention, the forward input signal I NP is connected to the gates of the second PMOS tube MP2 and the ninth PMOS tube MP9, the reverse input signal I NN is connected to the gates of the third PMOS tube MP3 and the eighth PMOS tube MP8, VB is the gate bias voltage signal of the tail current tube of the first amplifier A1 and the third amplifier A3, VB is connected to the gates of the first PMOS tube MP1 and the seventh PMOS tube MP7, the drain of the fifth NMOS tube MN5 outputs the forward output signal OUTP, and the drain of the eleventh NMOS tube MN11 outputs the reverse output signal OUTN. The voltage of the first power supply VDD1 is slightly higher than the voltage of the second power supply VDD2, and the voltage of the second power supply VDD2 is lower than the gate breakdown voltage of the first PMOS tube MP1-twelfth PMOS tube MP12 and the first NMOS tube MN1-twelfth NMOS tube MN12.

[0047] If the body effect of the transistor is ignored, the gain of the first amplifier A1 is approximately Av1=gmp3 / gmn3, the gain of the second amplifier A2 is approximately Av2=gmn5*(rop5||ron5), the gain of the third amplifier A3 is approximately Av3=gmp9 / gmn9, and the gain of the fourth amplifier A4 is approximately Av4=gmn11*(rop11||ron11), wherein gmp3, gmp9, gmn3, gmn5, gmn9, gmn11 are respectively the transconductances of the third PMOS tube MP3 and the ninth PMOS tube MP9, the third NMOS tube MN3, the fifth NMOS tube MN5, the ninth NMOS tube MN9 and the eleventh NMOS tube MN11, and rop5, rop11, ron5, ron11 are respectively the small signal resistances of the fifth PMOS tube MP5 and the eleventh PMOS tube MP11, the fifth NMOS tube MN5 and the eleventh NMOS tube MN11. Since the structure of the level conversion circuit is completely symmetrical and the sizes of the corresponding transistors are the same, the voltage gain of the two-stage amplifier can be expressed as Av=Av1*Av2=Av3*Av4=gmp3*gmn5*(rop5||ron5) / gmn3.

[0048] Example 1: VDD1 = 1.2V, VDD2 = 1V, the positive input signal I NP and the reverse input signal I NN are low-swing logic levels, the high level is 0.5V, and the low level is 0V. When the positive input signal I NP changes from low to high and the negative input signal INN changes from high to low, the output voltage of the first amplifier A1 increases and the output voltage of the third amplifier A3 decreases. Since VB is a constant bias voltage, the tail currents of the first amplifier A1 and the third amplifier A3 remain unchanged. The maximum output voltages of the first amplifier A1 and the third amplifier A3 can be adjusted by changing the sizes of the third NMOS transistor MN3 and the ninth NMOS transistor MN9 to prevent the output voltages from being too high and breaking through the gate oxide layers of the fourth NMOS transistor MN4 and the tenth NMOS transistor MN10. In this example, the maximum output voltages of the first amplifier A1 and the third amplifier A3 are 0.7V. Subsequently, the output voltage of the second amplifier A2 increases and the output voltage of the fourth amplifier A4 decreases. The positive feedback structure formed by the cross-coupled first inverter I1 and the second inverter I2 quickly amplifies the output voltage difference between the second amplifier A2 and the fourth amplifier A4, so that the positive output signal OUTP of the level conversion circuit is 1V and the negative output signal OUTN is 0V. When the positive input signal I NP changes from high to low and the negative input signal I NN changes from low to high, the changes in the voltage signals of each node in the circuit are opposite to the above situation. The positive output signal OUTP of the level conversion circuit is 0V and the negative output signal OUTN is 1V.

[0049] See also Figure 5 In the transient simulation waveform of Example 1, the frequencies of the forward input signal I NP and the reverse input signal I NN are 200 MHz, and the delay of the level conversion is about 300 ps. The simulation results are basically consistent with the experimental principles.

[0050] Compared with the prior art, the level conversion circuit of the present invention has the following beneficial effects:

[0051] (1) The level conversion circuit of the present invention shapes the input low-swing logic level to make its transition edge steep and phase-even, and outputs it with a VDD2 full-swing signal;

[0052] (2) The level conversion circuit of the present invention is completely symmetrical, and the output complementary clock has almost no phase error;

[0053] (3) The level conversion circuit of the present invention adopts a two-stage amplifier structure to provide a higher gain and reduce the delay of level conversion;

[0054] (4) The level conversion circuit of the present invention is designed with a diode-connected NMOS tube to limit the output voltage swing of the first amplifier A1 and the third amplifier A3 and protect the input transistors of the second amplifier A2 and the fourth amplifier A4.

[0055] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0056] The above embodiments only express the preferred implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A level conversion circuit, characterized in that: The invention comprises a first amplifier, a second amplifier, a third amplifier, a fourth amplifier, a first inverter, a second inverter, a positive input signal, a reverse input signal, a positive output signal and a reverse output signal. The first amplifier and the third amplifier are powered by a first power supply, the second amplifier, the fourth amplifier, the first inverter and the second inverter are powered by a second power supply, and the voltage of the first power supply is higher than that of the second power supply. The positive input signal is input to the positive input terminal of the first amplifier and the negative input terminal of the third amplifier, the reverse input signal is input to the negative input terminal of the first amplifier and the positive input terminal of the third amplifier, the output terminal of the first amplifier is connected to the positive input terminal of the second amplifier, the output terminal of the third amplifier is connected to the positive input terminal of the fourth amplifier, the output terminal of the second amplifier is connected to the negative input terminal of the fourth amplifier, the input terminal of the first inverter and the output terminal of the second inverter, the output terminal of the fourth amplifier is connected to the negative input terminal of the second amplifier, the output terminal of the first inverter and the input terminal of the second inverter, the output terminal of the first inverter outputs the reverse output signal, and the output terminal of the second inverter outputs the positive output signal.

2. A level conversion circuit as claimed in claim 1, characterized in that: The first amplifier includes a first bias voltage signal node, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor and a second NMOS transistor, the first PMOS transistor is connected in series between the first bias voltage signal node and a first power supply, the second PMOS transistor and the first NMOS transistor are connected in series between the first bias voltage signal node and a ground terminal, and the third PMOS transistor and the second NMOS transistor are connected in series between the first bias voltage signal node and the ground terminal.

3. A level conversion circuit as claimed in claim 2, characterized in that: The source of the first PMOS tube is connected to the first power supply, the gate of the second PMOS tube receives the forward input signal, the gate of the third PMOS tube receives the reverse input signal, the gate and drain of the first NMOS tube are short-circuited, the source of the second NMOS tube and the source of the first NMOS tube are connected to the ground end, and the gate of the first NMOS tube is connected to the gate of the second NMOS tube.

4. A level conversion circuit as claimed in claim 3, characterized in that: The second amplifier includes a fourth PMOS tube, a fifth PMOS tube, a fourth NMOS tube, and a fifth NMOS tube. The fourth PMOS tube and the fourth NMOS tube are connected in series between the second power supply and the ground terminal, and the fifth PMOS tube and the fifth NMOS tube are connected in series between the second power supply and the ground terminal.

5. A level conversion circuit as claimed in claim 4, characterized in that: The source of the fourth PMOS tube and the source of the fifth PMOS tube are connected to the second power supply, the gate and the drain of the fourth PMOS tube are short-circuited, the source of the fourth NMOS tube and the source of the fifth NMOS tube are connected to the ground terminal, the drain of the fifth NMOS tube and the drain of the fifth PMOS tube output the forward output signal, and the gate of the fifth PMOS tube is connected to the gate of the fourth PMOS tube.

6. A level conversion circuit as claimed in claim 5, characterized in that: The third amplifier includes a second bias voltage signal node, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a seventh NMOS tube, and an eighth NMOS tube. The ninth PMOS tube and the eighth NMOS tube are connected in series between the second bias voltage signal node and the ground terminal, and the eighth PMOS tube and the seventh NMOS tube are connected in series between the second bias voltage signal node and the ground terminal; the seventh PMOS tube is connected in series between the second bias voltage signal node and the first power supply, the gate of the ninth PMOS tube receives the forward input signal, the gate of the eighth PMOS tube receives the reverse input signal, the gate and the drain of the seventh NMOS tube are short-circuited, the source of the seventh NMOS tube and the source of the eighth NMOS tube are connected to the ground terminal, and the gate of the seventh NMOS tube is connected to the gate of the eighth NMOS tube.

7. A level conversion circuit as claimed in claim 6, characterized in that: The fourth amplifier includes a tenth PMOS tube, an eleventh PMOS tube, a tenth NMOS tube, and an eleventh NMOS tube. The tenth PMOS tube and the tenth NMOS tube are connected in series between the second power supply and the ground terminal, and the eleventh PMOS tube and the eleventh NMOS tube are connected in series between the second power supply and the ground terminal; the source of the eleventh PMOS tube and the source of the tenth PMOS tube are connected to the second power supply, the gate and the drain of the tenth PMOS tube are short-circuited, the source of the tenth NMOS tube and the source of the eleventh NMOS tube are connected to the ground terminal, the drain of the eleventh NMOS tube and the drain of the eleventh PMOS tube output the reverse output signal, the gate of the eleventh PMOS tube is connected to the gate of the tenth PMOS tube, the gate of the eleventh NMOS tube is connected to the gate of the fourth NMOS tube, and the gate of the tenth NMOS tube is connected to the gate of the fifth NMOS tube.

8. A level conversion circuit as claimed in claim 7, characterized in that: The first inverter includes a sixth PMOS tube and a sixth NMOS tube, and the second inverter includes a twelfth PMOS tube and a twelfth NMOS tube, the sixth PMOS tube and the sixth NMOS tube are connected in series between the second power supply and the ground terminal, and the twelfth PMOS tube and the twelfth NMOS tube are connected in series between the second power supply and the ground terminal; the source of the sixth PMOS tube and the source of the twelfth PMOS tube are connected to the second power supply, the source of the sixth NMOS tube and the source of the twelfth NMOS tube are connected to the ground terminal, the gate of the sixth PMOS tube, the gate of the sixth NMOS tube, the drain of the twelfth PMOS tube, and the drain of the twelfth NMOS tube output a positive output signal, and the drain of the sixth PMOS tube, the drain of the sixth NMOS tube, the gate of the twelfth PMOS tube, and the gate of the twelfth NMOS tube output a reverse output signal.

9. A level conversion circuit as claimed in claim 8, characterized in that: The level conversion circuit further includes a third NMOS tube and a ninth NMOS tube, the gate of the third NMOS tube is connected to the gate of the fourth NMOS tube, the gate and the drain of the third NMOS tube are short-circuited, and the source of the third NMOS tube is grounded; the gate of the ninth NMOS tube is connected to the gate of the tenth NMOS tube, the gate and the drain of the ninth NMOS tube are short-circuited, and the source of the ninth NMOS tube is grounded.

10. A level conversion circuit as claimed in claim 9, characterized in that: The gain of the first amplifier is Av1=gmp3 / gmn3, the gain of the second amplifier is Av2=gmn5*(rop5||ron5), the gain of the third amplifier is Av3=gmp9 / gmn9, and the gain of the fourth amplifier is Av4=gmn11*(rop11||ron11), wherein gmp3, gmp9, gmn3, gmn5, gmn9, and gmn11 are the transconductances of the third PMOS tube and the ninth PMOS tube, the third NMOS tube, the fifth NMOS tube, the ninth NMOS tube, and the eleventh NMOS tube respectively, and rop5, rop11, ron5, and ron11 are the small signal resistances of the fifth PMOS tube and the eleventh PMOS tube, the fifth NMOS tube, and the eleventh NMOS tube respectively. The voltage gain of the two-stage amplifier is Av=Av1*Av2=Av3*Av4=gmp3* gmn5*(rop5||ron5) / gmn3.

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