Level conversion circuit

Abstract

The present invention relates to a level conversion circuit, comprising a first amplifier, a second amplifier, a third amplifier, a positive input signal INP, a reverse input signal INN, a positive output signal OUTP, and a reverse output signal OUTN, wherein the first amplifier is an amplifier with differential input and differential output, the second amplifier and the third amplifier are amplifiers with differential input and single-ended output, the first amplifier, the second amplifier and the third amplifier are powered by a power supply VDD, the positive input signal INP is connected to the positive input terminal of the first amplifier, and the reverse input signal INN is connected to the negative input terminal of the first amplifier. A level conversion circuit of the present invention is a level conversion circuit that can be used for high-speed signal transmission.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a level conversion circuit. Background Art

[0002] Multi-power supply voltage domain technology is widely used in System on Chip (SoC), where each module in the system works at an appropriate power supply voltage according to its timing requirements. Generally speaking, modules with critical timing usually work at a higher power supply voltage to meet the speed performance indicators of the chip; modules with low timing requirements usually work at a lower power supply voltage to reduce the power consumption of the chip.

[0003] In chips that use multi-power supply voltage domain technology, the level conversion circuit is an important module. It provides a way for modules working in different voltage domains to interact and ensure the correct transmission of signals between voltage domains. When the signal is converted from a high voltage domain to a low voltage domain, an ordinary buffer can be used to achieve cross-voltage domain transmission of the signal; when the signal is converted from a low voltage domain to a high voltage domain, a more complex level conversion circuit is required.

[0004] Traditional level conversion circuits include cross-coupled level conversion circuits and current mirror-based level conversion circuits. Figure 1 As shown, in the cross-coupled level conversion circuit, when the input signal A changes from low to high, there are three inverter delays (MP1 / MN1, MP2 / MN2, MP22 / MN22) and the conduction delay of MN12 from the change of input signal A to the change of output signal Y; when the input signal A changes from high to low, there are two inverter delays (MP1 / MN1, MP22 / MN22), the conduction delay of MN11 and the conduction delay of MP12 from the change of input signal A to the change of output signal Y. Since the delay of the inverter (MP2 / MN2) is much smaller than the conduction delay of MP12, the rising delay of the output signal is much faster than the falling delay, resulting in an unreasonable output duty cycle of the level conversion circuit, which restricts the overall performance of the on-chip system. Figure 2 As shown in the figure, in the level conversion circuit based on the current mirror, the rising delay and falling delay of the input and output signals of the circuit are seriously mismatched, which has a great impact on high-speed signals. In addition, the rising delay and falling delay of the level converter in the above two level conversion circuits are large, and the conversion time of the level conversion circuit is long, which is not suitable for high-speed and high-performance chip-on-chip systems. Therefore, a level conversion circuit for high-speed signal transmission is urgently needed. Summary of the invention

[0005] The present invention provides a level conversion circuit to solve the problem that the conversion time of the existing level conversion circuit is long and the system performance is restricted.

[0006] To solve the above technical problems, the present invention provides a level conversion circuit, including a first amplifier, a second amplifier, a third amplifier, a positive input signal, a reverse input signal, a positive output signal, and a reverse output signal. The first amplifier is an amplifier with differential input and differential output, the second amplifier and the third amplifier are amplifiers with differential input and single-ended output, the first amplifier, the second amplifier and the third amplifier are powered by a power supply, the positive input signal is input to the positive input terminal of the first amplifier, the reverse input signal is input to the negative input terminal of the first amplifier, the positive output terminal of the first amplifier is connected to the positive input terminal of the second amplifier and the negative input terminal of the third amplifier, the negative output terminal of the first amplifier is connected to the negative input terminal of the second amplifier and the positive input terminal of the third amplifier, the output terminal of the second amplifier outputs the positive output signal, and the output terminal of the third amplifier outputs the reverse output signal.

[0007] Preferably, the first amplifier includes a second NMOS tube, a third NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube and a sixth PMOS tube, the first PMOS tube and the second NMOS tube are connected in series between the power supply and the ground terminal, the second PMOS tube and the third NMOS tube are connected in series between the power supply and the ground terminal, the first PMOS tube and the third PMOS tube are connected in parallel between the power supply and the negative output terminal of the first amplifier, the second PMOS tube and the sixth PMOS tube are connected in parallel between the power supply and the positive output terminal of the first amplifier, wherein the first PMOS tube and the second PMOS tube are cross-coupled to form a positive feedback structure.

[0008] Preferably, the first amplifier also includes an enable node and a first NMOS transistor connected in series between the enable node and the ground terminal, the first PMOS transistor and the second NMOS transistor are connected in series between the power supply and the enable node, and the second PMOS transistor and the third NMOS transistor are connected in series between the power supply and the enable node.

[0009] Preferably, the source of the first PMOS tube, the source of the second PMOS tube, the source of the third PMOS tube and the source of the sixth PMOS tube are connected to the power supply, the drain of the first PMOS tube, the gate of the second PMOS tube, the drain of the third PMOS tube, the gate of the third PMOS tube and the drain of the second NMOS tube are connected to the negative output end of the first amplifier, the drain of the second PMOS tube, the gate of the first PMOS tube, the drain of the sixth PMOS tube, the gate of the sixth PMOS tube and the drain of the third NMOS tube are connected to the positive output end of the first amplifier, the source of the second NMOS tube, the source of the third NMOS tube and the drain of the first NMOS tube are connected to the enable node, and the source of the first NMOS tube is connected to the ground end; the gate of the second NMOS tube receives the forward input signal, the gate of the third NMOS tube receives the reverse input signal, and the gate of the first NMOS tube receives the enable signal.

[0010] Preferably, the second amplifier includes a seventh PMOS tube, an eighth PMOS tube, a sixth NMOS tube, and a seventh NMOS tube, the seventh PMOS tube and the sixth NMOS tube are connected in series between the power supply and the ground terminal, the eighth PMOS tube and the seventh NMOS tube are connected in series between the power supply and the ground terminal, the source of the seventh PMOS tube is connected to the power supply, and the gate is connected to the positive output terminal of the first amplifier, the source of the eighth PMOS tube is connected to the power supply, and the gate is connected to the negative output terminal of the first amplifier, and the drain of the eighth PMOS tube and the drain of the seventh NMOS tube are connected to the output terminal of the second amplifier.

[0011] Preferably, the gate and drain of the sixth NMOS tube are short-circuited, the source of the sixth NMOS tube and the source of the seventh NMOS tube are connected to the ground terminal, and the gate of the sixth NMOS tube is connected to the gate of the seventh NMOS tube.

[0012] Preferably, the third amplifier includes a fifth PMOS tube, a fourth PMOS tube, a fifth NMOS tube, and a fourth NMOS tube, the fifth PMOS tube and the fifth NMOS tube are connected in series between the power supply and the ground terminal, the fourth PMOS tube and the fourth NMOS tube are connected in series between the power supply and the ground terminal, the source of the fourth PMOS tube is connected to the power supply, and the gate is connected to the negative output terminal of the first amplifier, the source of the fifth PMOS tube is connected to the power supply, and the gate is connected to the positive output terminal of the first amplifier, and the drain of the fifth PMOS tube and the drain of the fifth NMOS tube are connected to the output terminal of the third amplifier.

[0013] Preferably, the drain and gate of the fourth NMOS tube are short-circuited, the source of the fourth NMOS tube and the source of the fifth NMOS tube are connected to the ground terminal, and the gate of the fourth NMOS tube is connected to the gate of the fifth NMOS tube.

[0014] Preferably, the gain of the first amplifier is approximately Av1=gmn2 / gmp3, the gain of the second amplifier is approximately Av2=gmp8*(rop8||ron7), and the gain of the third amplifier is approximately Av3=gmp5*(rop5||ron5), wherein gmn2, gmp3, gmp8, gmp5 are the transconductances of the second NMOS tube, the third PMOS tube, the eighth PMOS tube, and the fifth PMOS tube, respectively, and ron7, ron5, rop8, rop5 are the small signal resistances of the seventh NMOS tube, the fifth NMOS tube, the eighth PMOS tube, and the fifth PMOS tube, respectively.

[0015] Preferably, the voltage gain of the two-stage amplifier of the level conversion circuit can be expressed as Av=Av1*Av2=Av1*Av3=gmn2*gmp8*(rop8||ron7) / gmp3.

[0016] Compared with the prior art, the level conversion circuit of the present invention has the following beneficial effects:

[0017] (1) The level conversion circuit of the present invention shapes the input low-swing logic level to make its transition edge steep and phase-even, and outputs it with a VDD full-swing signal;

[0018] (2) The level conversion circuit of the present invention is completely symmetrical, and the output differential signal has almost no phase error;

[0019] (3) The level conversion circuit of the present invention adopts a two-stage amplifier structure to provide a higher gain and improve the speed of level conversion. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a cross-coupled level conversion circuit in the prior art;

[0021] Figure 2 It is a level conversion circuit based on current mirror in the prior art;

[0022] Figure 3 It is an overall structural diagram of a level conversion circuit of the present invention;

[0023] Figure 4 It is a basic circuit diagram of a level conversion circuit of the present invention;

[0024] Figure 5 It is a transient simulation waveform of Example 1 of a level conversion circuit of the present invention. DETAILED DESCRIPTION

[0025] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0026] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be an intermediate element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be an intermediate element at the same time.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0028] See also Figure 3 In the overall structure diagram of a level conversion circuit of the present invention, the first amplifier A1, the second amplifier A2, the third amplifier A3, the positive input signal INP, the reverse input signal INN, the positive output signal OUTP, the reverse output signal OUTN are included. The first amplifier A1 is an amplifier with differential input and differential output, the second amplifier A2 and the third amplifier A3 are amplifiers with differential input and single-ended output, and the first amplifier A1, the second amplifier A2 and the third amplifier A3 are powered by a power supply VDD. The positive input signal INP is input to the positive input end of the first amplifier A1, the reverse input signal INN is input to the negative input end of the first amplifier A1, the positive output end of the first amplifier A1 is connected to the positive input end of the second amplifier A2 and the negative input end of the third amplifier A3, the negative output end of the first amplifier A1 is connected to the negative input end of the second amplifier A2 and the positive input end of the third amplifier A3, the output end of the second amplifier A2 outputs the positive output signal OUTP, and the output end of the third amplifier A3 outputs the reverse output signal OUTN.

[0029] See also Figure 4In a basic circuit diagram of a level conversion circuit of the present invention, a first amplifier A1 includes three NMOS tubes and four PMOS tubes, the three NMOS tubes are respectively a first NMOS tube MN1, a second NMOS tube MN2, and a third NMOS tube MN3, and the four PMOS tubes are respectively a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, and a sixth PMOS tube MP6. The first PMOS tube MP1 and the second NMOS tube MN2 are connected in series between the power supply VDD and the ground terminal GND, the second PMOS tube MP2 and the third NMOS tube MN3 are connected in series between the power supply VDD and the ground terminal GND, the first PMOS tube MP1 and the third PMOS tube MP3 are connected in parallel between the power supply VDD and the negative output terminal of the first amplifier, the second PMOS tube MP2 and the sixth PMOS tube MP6 are connected in parallel between the power supply VDD and the positive output terminal of the first amplifier, wherein the first PMOS tube MP1 and the second PMOS tube MP2 are cross-coupled to form a positive feedback structure.

[0030] The first amplifier A1 also includes an enable node E1 and a first NMOS transistor MN1 connected in series between the enable node E1 and a ground terminal GND, the first PMOS transistor MP1 and the second NMOS transistor MN2 are connected in series between the power supply VDD and the enable node E1, and the second PMOS transistor MP2 and the third NMOS transistor MN3 are connected in series between the power supply VDD and the enable node E1.

[0031] The first PMOS tube MP1 and the second PMOS tube MP2 are cross-coupled to form a positive feedback structure, which can quickly amplify the drain voltage difference between the second NMOS tube MN2 and the third NMOS tube MN3. The positive input signal INP is connected to the gate of the second NMOS tube MN2, the reverse input signal INN is connected to the gate of the third NMOS tube MN3, EN is the enable signal of the first amplifier A1, EN is connected to the gate of the first NMOS tube MN1, when the enable signal EN is high level, the first NMOS tube MN1 is turned on, and the level conversion circuit is in working state.

[0032] The source of the first PMOS tube, the source of the second PMOS tube, the source of the third PMOS tube and the source of the sixth PMOS tube are connected to the power supply VDD, the drain of the first PMOS tube, the gate of the second PMOS tube, the drain of the third PMOS tube, the gate of the third PMOS tube and the drain of the second NMOS tube are connected to the negative output end of the first amplifier, the drain of the second PMOS tube, the gate of the first PMOS tube, the drain of the sixth PMOS tube, the gate of the sixth PMOS tube and the drain of the third NMOS tube are connected to the positive output end of the first amplifier, the source of the second NMOS tube, the source of the third NMOS tube and the drain of the first NMOS tube are connected to the enable node E1, and the source of the first NMOS tube is connected to the ground terminal GND; the gate of the second NMOS tube receives the forward input signal, the gate of the third NMOS tube receives the reverse input signal, and the gate of the first NMOS tube receives the enable signal.

[0033] Specifically, the gate and drain of the third PMOS tube MP3 are short-circuited and connected to the drain of the first PMOS tube MP1 at the same time, the source of the third PMOS tube MP3 is connected to the source of the first PMOS tube MP1, the gate and drain of the sixth PMOS tube MP6 are short-circuited and connected to the drain of the second PMOS tube MP2 at the same time, the source of the sixth PMOS tube MP6 is connected to the source of the second PMOS tube MP2, the gate of the first PMOS tube MP1 is connected to the drain of the second PMOS tube MP2, the gate of the second PMOS tube MP2 is connected to the drain of the first PMOS tube MP1; the drain of the second NMOS tube MN2 is connected The drain of the first PMOS tube MP1 and the drain of the third NMOS tube MN3 are connected to the drain of the second PMOS tube MP2, the source of the second NMOS tube MN2 is connected to the source of the third NMOS tube MN3, the forward input signal INP is connected to the gate of the second NMOS tube MN2, and the reverse input signal INN is connected to the gate of the third NMOS tube MN3; the drain of the first NMOS tube MN1 is connected to the sources of the second NMOS tube MN2 and the third NMOS tube MN3, the source of the first NMOS tube MN1 is grounded (connected to the ground terminal GND), and the gate of the first NMOS tube MN1 is connected to the enable signal EN.

[0034] The second amplifier A2 includes two NMOS tubes and two PMOS tubes, the two NMOS tubes are respectively a sixth NMOS tube MN6 and a seventh NMOS tube MN7, and the two PMOS tubes are respectively a seventh PMOS tube MP7 and an eighth PMOS tube MP8. The seventh PMOS tube MP7 and the sixth NMOS tube MN6 are connected in series between the power supply VDD and the ground terminal GND, the eighth PMOS tube MP8 and the seventh NMOS tube MN7 are connected in series between the power supply VDD and the ground terminal GND, the source of the seventh PMOS tube MP7 is connected to the power supply VDD, and the gate is connected to the positive output terminal of the first amplifier A1, the source of the eighth PMOS tube MP8 is connected to the power supply VDD, and the gate is connected to the negative output terminal of the first amplifier A1, and the drain of the eighth PMOS tube MP8 and the drain of the seventh NMOS tube MN7 are connected to the output terminal of the second amplifier A2.

[0035] The gate and drain of the sixth NMOS transistor MN6 are short-circuited, the source of the sixth NMOS transistor MN6 and the source of the seventh NMOS transistor MN7 are connected to the ground terminal GND, and the gate of the sixth NMOS transistor MN6 is connected to the gate of the seventh NMOS transistor MN7.

[0036] Specifically, the gate of the seventh PMOS tube MP7 is connected to the gate of the sixth PMOS tube MP6 in the first amplifier A1, the source of the seventh PMOS tube MP7 is connected to the source of the eighth PMOS tube MP8, the gate of the eighth PMOS tube MP8 is connected to the drain of the first PMOS tube MP1 in the first amplifier A1, the gate and drain of the sixth NMOS tube MN6 are short-circuited and simultaneously connected to the drain of the seventh PMOS tube MP7, the source of the sixth NMOS tube MN6 is connected to the source of the seventh NMOS tube MN7 and is grounded at the same time, the gate of the sixth NMOS tube MN6 is connected to the gate of the seventh NMOS tube MN7, and the drain of the seventh NMOS tube MN7 is connected to the positive output signal OUTP.

[0037] The third amplifier A3 includes two NMOS tubes and two PMOS tubes, the two NMOS tubes are respectively a fourth NMOS tube MN4 and a fifth NMOS tube MN5, and the two PMOS tubes are respectively a fourth PMOS tube MP4 and a fifth PMOS tube MP5. The fifth PMOS tube MP5 and the fifth NMOS tube MN5 are connected in series between the power supply VDD and the ground terminal GND, the fourth PMOS tube MP4 and the fourth NMOS tube MN4 are connected in series between the power supply VDD and the ground terminal GND, the source of the fourth PMOS tube MP4 is connected to the power supply VDD, and the gate is connected to the negative output terminal of the first amplifier A1, the source of the fifth PMOS tube MP5 is connected to the power supply VDD, and the gate is connected to the positive output terminal of the first amplifier A1, and the drain of the fifth PMOS tube MP5 and the drain of the fifth NMOS tube MN5 are connected to the output terminal of the third amplifier A3.

[0038] The drain and gate of the fourth NMOS transistor MN4 are short-circuited, the source of the fourth NMOS transistor MN4 and the source of the fifth NMOS transistor MN5 are connected to the ground terminal GND, and the gate of the fourth NMOS transistor MN4 is connected to the gate of the fifth NMOS transistor MN5.

[0039] Specifically, the source of the fifth PMOS tube MP5 is connected to the source of the fourth PMOS tube MP4, the gate of the fifth PMOS tube MP5 is connected to the drain of the second PMOS tube MP2 in the first amplifier A1, the drain of the fifth PMOS tube MP5 is connected to the drain of the fifth NMOS tube MN5 and is also connected to the reverse output signal OUTN, the gate of the fourth PMOS tube MP4 is connected to the gate of the third PMOS tube MP3 in the first amplifier A1, the drain of the fourth PMOS tube MP4 is connected to the drain of the fourth NMOS tube MN4, the drain and gate of the fourth NMOS tube MN4 are short-circuited and are also connected to the gate of the fifth NMOS tube MN5, the source of the fourth NMOS tube MN4 is connected to the source of the fifth NMOS tube MN5 and is also connected to the ground terminal.

[0040] The drain of the third NMOS tube MN3 is connected to the positive output terminal AP of the first amplifier A1, the drain of the second NMOS tube MN2 is connected to the reverse output signal AN of the negative output terminal of the first amplifier A1, the drain of the seventh NMOS tube MN7 in the second amplifier A2 outputs the positive output signal OUTP of the level conversion circuit, and the drain of the fifth NMOS tube MN5 in the third amplifier A3 outputs the reverse output signal OUTN of the level conversion circuit.

[0041] If the body effect of the transistor is ignored, the gain of the first amplifier A1 is approximately Av1=gmn2 / gmp3, the gain of the second amplifier A2 is approximately Av2=gmp8*(rop8||ron7), and the gain of the third amplifier A3 is approximately Av3=gmp5*(rop5||ron5), wherein gmn2, gmp3, gmp8, and gmp5 are the transconductances of the second NMOS tube MN2, the third PMOS tube MP3, the eighth PMOS tube MP8, and the fifth PMOS tube MP5 respectively, and ron7, ron5, rop8, and rop5 are the small signal resistances of the seventh NMOS tube MN7, the fifth NMOS tube MN5, the eighth PMOS tube MP8, and the fifth PMOS tube MP5 respectively. The first amplifier A1 is a first-stage amplifier, the second amplifier A2 and the third amplifier A3 are second-stage amplifiers, the circuit structure and device size of the second amplifier A2 and the third amplifier A3 are exactly the same, except that the input and output signals are different. Since the structure of the level conversion circuit is completely symmetrical and the sizes of the corresponding transistors are the same, the voltage gain of the two-stage amplifiers of the level conversion circuit can be expressed as Av=Av1*Av2=Av1*Av3=gmn2*gmp8*(rop8||ron7) / gmp3.

[0042] Example 1: Power supply voltage VDD=1V, enable signal EN=1, positive input signal INP and reverse input signal INN are low swing differential logic levels, high level is 0.5V, low level is 0V. When the positive input signal INP changes from low to high and the reverse input signal INN changes from high to low, the second NMOS transistor MN2 is turned on, the third NMOS transistor MN3 is turned off, and the diode-connected sixth PMOS transistor MP6 provides a charging path for the positive output terminal AP of the first amplifier A1, so that the voltage of the positive output signal of the positive output terminal AP increases until the first PMOS transistor MP1 is turned off, and the voltage of the reverse output signal of the negative output terminal AN of the first amplifier A1 decreases, so that the second PMOS transistor MP2 is turned on, and the positive feedback structure composed of the first PMOS transistor MP1 and the first PMOS transistor MP2 quickly amplifies the output voltage difference of the first amplifier A1, the positive output voltage increases, and the reverse output voltage decreases. Then the forward output signal OUTP outputted from the output end of the second amplifier A2 increases, and the reverse output signal OUTN outputted from the output end of the third amplifier A3 decreases, and finally the forward output signal OUTP of the level conversion circuit is 1V, and the reverse output signal OUTN is 0V. When the forward input signal INP changes from high to low, and the reverse input signal INN changes from low to high, the changes in the voltage signals of each node in the circuit are opposite to the above situation, and the forward output signal OUTP of the level conversion circuit is 0V, and the reverse output signal OUTN is 1V.

[0043] See also Figure 5In the transient simulation waveform of Example 1, the frequencies of the forward input signal INP and the reverse input signal INN are 200 MHz, and the delay of the level conversion is about 200 ps. The simulation results are basically consistent with the experimental principles.

[0044] Compared with the prior art, the level conversion circuit of the present invention has the following beneficial effects:

[0045] (1) The level conversion circuit of the present invention shapes the input low-swing logic level to make its transition edge steep and phase-even, and outputs it with a VDD full-swing signal;

[0046] (2) The level conversion circuit of the present invention is completely symmetrical, and the output differential signal has almost no phase error;

[0047] (3) The level conversion circuit of the present invention adopts a two-stage amplifier structure to provide a higher gain and improve the speed of level conversion.

[0048] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0049] The above embodiments only express the preferred implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A level conversion circuit, characterized in that: The invention comprises a first amplifier, a second amplifier, a third amplifier, a positive input signal, a reverse input signal, a positive output signal, and a reverse output signal, wherein the first amplifier is an amplifier with differential input and differential output, the second amplifier and the third amplifier are amplifiers with differential input and single-ended output, the first amplifier, the second amplifier and the third amplifier are powered by a power supply, the positive input signal is input into the positive input terminal of the first amplifier, the reverse input signal is input into the negative input terminal of the first amplifier, the positive output terminal of the first amplifier is connected to the positive input terminal of the second amplifier and the negative input terminal of the third amplifier, the negative output terminal of the first amplifier is connected to the negative input terminal of the second amplifier and the positive input terminal of the third amplifier, the output terminal of the second amplifier outputs the positive output signal, and the output terminal of the third amplifier outputs the reverse output signal; The first amplifier includes a second NMOS tube, a third NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube and a sixth PMOS tube, the first PMOS tube and the second NMOS tube are connected in series between the power supply and the ground terminal, the second PMOS tube and the third NMOS tube are connected in series between the power supply and the ground terminal, the first PMOS tube and the third PMOS tube are connected in parallel between the power supply and the negative output terminal of the first amplifier, the second PMOS tube and the sixth PMOS tube are connected in parallel between the power supply and the positive output terminal of the first amplifier, wherein the first PMOS tube and the second PMOS tube are cross-coupled to form a positive feedback structure; The first amplifier further includes an enable node and a first NMOS transistor connected in series between the enable node and a ground terminal, the first PMOS transistor and the second NMOS transistor are connected in series between the power supply and the enable node, and the second PMOS transistor and the third NMOS transistor are connected in series between the power supply and the enable node; The second amplifier comprises a seventh PMOS tube, an eighth PMOS tube, a sixth NMOS tube, and a seventh NMOS tube, the seventh PMOS tube and the sixth NMOS tube are connected in series between the power supply and the ground terminal, the eighth PMOS tube and the seventh NMOS tube are connected in series between the power supply and the ground terminal, the source of the seventh PMOS tube is connected to the power supply, and the gate is connected to the positive output terminal of the first amplifier, the source of the eighth PMOS tube is connected to the power supply, and the gate is connected to the negative output terminal of the first amplifier, and the drain of the eighth PMOS tube and the drain of the seventh NMOS tube are connected to the output terminal of the second amplifier; The gate of the seventh PMOS tube is connected to the gate of the sixth PMOS tube, the source of the seventh PMOS tube is connected to the source of the eighth PMOS tube, and the gate of the eighth PMOS tube is connected to the drain of the first PMOS tube.

2. A level conversion circuit as claimed in claim 1, characterized in that: The source of the first PMOS tube, the source of the second PMOS tube, the source of the third PMOS tube and the source of the sixth PMOS tube are connected to the power supply, the drain of the first PMOS tube, the gate of the second PMOS tube, the drain of the third PMOS tube, the gate of the third PMOS tube and the drain of the second NMOS tube are connected to the negative output end of the first amplifier, the drain of the second PMOS tube, the gate of the first PMOS tube, the drain of the sixth PMOS tube, the gate of the sixth PMOS tube and the drain of the third NMOS tube are connected to the positive output end of the first amplifier, the source of the second NMOS tube, the source of the third NMOS tube and the drain of the first NMOS tube are connected to the enable node, and the source of the first NMOS tube is connected to the ground end; the gate of the second NMOS tube receives the forward input signal, the gate of the third NMOS tube receives the reverse input signal, and the gate of the first NMOS tube receives the enable signal.

3. A level conversion circuit as claimed in claim 2, characterized in that: The gate and drain of the sixth NMOS tube are short-circuited, the source of the sixth NMOS tube and the source of the seventh NMOS tube are connected to the ground end, and the gate of the sixth NMOS tube is connected to the gate of the seventh NMOS tube.

4. A level conversion circuit as claimed in claim 3, characterized in that: The third amplifier includes a fifth PMOS tube, a fourth PMOS tube, a fifth NMOS tube, and a fourth NMOS tube. The fifth PMOS tube and the fifth NMOS tube are connected in series between the power supply and the ground terminal. The fourth PMOS tube and the fourth NMOS tube are connected in series between the power supply and the ground terminal. The source of the fourth PMOS tube is connected to the power supply, and the gate is connected to the negative output terminal of the first amplifier. The source of the fifth PMOS tube is connected to the power supply, and the gate is connected to the positive output terminal of the first amplifier. The drain of the fifth PMOS tube and the drain of the fifth NMOS tube are connected to the output terminal of the third amplifier.

5. A level conversion circuit as claimed in claim 4, characterized in that: The drain and gate of the fourth NMOS tube are short-circuited, the source of the fourth NMOS tube and the source of the fifth NMOS tube are connected to the ground terminal, and the gate of the fourth NMOS tube is connected to the gate of the fifth NMOS tube.

6. A level conversion circuit as claimed in claim 5, characterized in that: The gain of the first amplifier is Av1=gmn2 / gmp3, the gain of the second amplifier is Av2=gmp8*(rop8||ron7), and the gain of the third amplifier is Av3=gmp5*(rop5||ron5), wherein gmn2, gmp3, gmp8, and gmp5 are the transconductances of the second NMOS tube, the third PMOS tube, the eighth PMOS tube, and the fifth PMOS tube respectively, and ron7, ron5, rop8, and rop5 are the small signal resistances of the seventh NMOS tube, the fifth NMOS tube, the eighth PMOS tube, and the fifth PMOS tube respectively.

7. A level conversion circuit as claimed in claim 6, characterized in that: The voltage gain of the two-stage amplifier of the level conversion circuit is expressed as Av=Av1*Av2=Av1*Av3=gmn2*gmp8*(rop8||ron7) / gmp3.

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