Integrated circuit structure and method for forming the same

Abstract

An integrated circuit structure and a method for forming the same, the method comprising forming metal lines on an interconnect structure, wherein an under-bump metal interconnect structure is formed above a transistor; depositing a pad layer on a plurality of metal lines using a first high-density plasma chemical vapor deposition process without radio frequency bias power; depositing a first passivation layer on the under-bump metal pad layer using a second high-density plasma chemical vapor deposition process with radio frequency bias power; and depositing a second passivation layer in contact with an upper surface of the first under-bump metal passivation layer using a third high-density plasma chemical vapor deposition process with radio frequency bias power.

Description

Technical Field

[0001] The present disclosure relates to a passivation layer for an integrated circuit structure, and more particularly to a method for forming the passivation layer for an integrated circuit structure. Background Art

[0002] Ultra-thick metal (Ultra-Thick Metal) lines are formed in integrated circuits to reduce the resistance of metal lines. With reduced resistance, the performance of integrated circuit components such as sensors can be improved to meet the performance requirements of certain circuits such as mixed signal circuits, analog circuits, and radio frequency (RF) circuits. Ultra-thick metal lines can be covered with a passivation layer. Summary of the invention

[0003] In some embodiments, a method for forming a passivation layer for an integrated circuit structure includes forming a metal line on an interconnect structure, an under bump metal interconnect structure formed above a transistor; depositing a liner layer on the metal line using a first high density plasma chemical vapor deposition (HDPVCD) process without radio frequency bias power; depositing a first passivation layer on the liner layer using a second HDPVCD process with radio frequency bias power; and depositing a second passivation layer in contact with an upper surface of the first passivation layer using a third HDPVCD process with radio frequency bias power.

[0004] In some embodiments, a method for forming a passivation layer for an integrated circuit structure includes forming a metal line on an interconnect structure, wherein an under-bump metal interconnect structure is formed above a transistor; depositing a liner oxide layer in contact with the metal line; forming a passivation oxide structure in contact with an upper surface of the liner layer, wherein the liner layer is more porous than any location in the passivation oxide structure; and forming a protective nitride layer in contact with the upper surface of the passivation oxide structure.

[0005] In some embodiments, the integrated circuit structure includes an interconnect structure, a metal line, a liner layer, a passivation structure, and a nitride layer. The interconnect structure is on the transistor. The metal line extends along the upper surface of the interconnect structure. The liner layer is on the metal line. The passivation structure is on the liner. The nitride layer is on the passivation structure, wherein the passivation structure extends continuously from the liner layer to the nitride layer without an interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure will be better understood from the following detailed description when read together with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A and Figure 1B is a flow chart of a method for manufacturing an integrated circuit (IC) structure having a passivation layer according to some embodiments of the present disclosure;

[0008] Figures 2 to 13 is a cross-sectional view of a method of fabricating an integrated circuit structure having a passivation layer at various stages according to some embodiments of the present disclosure;

[0009] Fig.14 and Fig.15 is a cross-sectional view of a method of fabricating an integrated circuit structure having a passivation layer at various stages according to some embodiments of the present disclosure;

[0010] Figures 16 to 18 is a cross-sectional view of a method of fabricating an integrated circuit structure having a passivation layer at various stages according to some embodiments of the present disclosure;

[0011] Fig.19 is a simplified diagram of a high density plasma chemical vapor deposition (HDPCVD) system according to some embodiments of the present disclosure;

[0012] Fig. 20 is a simplified diagram of a cluster tool having a plurality of single wafer processing chambers mounted thereon according to some embodiments of the present disclosure;

[0013] Fig.21 A simplified diagram of a perspective view of a production site for describing an automatic transfer method of a front opening unified pod (FOUP) system in a substrate handling unit.

[0014]

Explanation of symbols

[0015] E1, E2: Interface

[0016] M1~Mtop: metal layer

[0017] P1, P2, P3, P4: High-density plasma chemical vapor deposition process

[0018] P5: Plasma Enhanced Chemical Vapor Deposition Process

[0019] P6: Planarization process

[0020] K1, K2, K3, K4, T1, T2, T3, T4, T5, T6, T7, T8: thickness

[0021] R1: concave part

[0022] S1: Horizontal upper surface

[0023] S101~S115: Blocks

[0024] 1~5: Processing system

[0025] 2: Wafer

[0026] 6: High-density plasma chemical vapor deposition system / processing system

[0027] 10: Base material

[0028] 12: Interconnection structure

[0029] 14: Semiconductor components

[0030] 16: Contact plug

[0031] 18: Interlayer dielectric layer

[0032] 22: Intermetallic dielectric layer

[0033] 26:Metal Wire

[0034] 28: Conductive column

[0035] 36: Extra thick metal wire

[0036] 38: Process chamber

[0037] 40: Vacuum system

[0038] 42: cushion layer

[0039] 44: Biased plasma system

[0040] 46: Gas distribution system

[0041] 48: Remote microwave plasma cleaning system

[0042] 50: Passivation structure

[0043] 52: First passivation layer

[0044] 54: Second passivation layer

[0045] 56: The third passivation layer

[0046] 58: Heater plate

[0047] 60: Cold plate

[0048] 62: Protective layer

[0049] 64: base part

[0050] 66: substrate receiving part

[0051] 68: Wafer chuck / electrostatic chuck

[0052] 70: Throttling body

[0053] 72: Dual Blade Throttle / Hard Mask Layer

[0054] 74: Gate valve / photoresist layer

[0055] 76: Turbomolecular pump

[0056] 78: Top coil

[0057] 80: Side coil

[0058] 82: Under Bump Metal Layer

[0059] 86:RF bias generator

[0060] 88: Bias matching network

[0061] 89, 90: Matching network

[0062] 92: Conductive column bump

[0063] 94: Gas Ring

[0064] 95: Insertion / removal opening

[0065] 96: Top nozzle

[0066] 98: Top exhaust port

[0067] 100: Method

[0068] 100a, 100b, 100c, 100d, 100e: gas source

[0069] 102: Wafer

[0070] 106, 108: Gas nozzle

[0071] 112, 112a, 112b: valve

[0072] 114: Foreline vacuum line

[0073] 120a, 120b, 120c, 102a, 102b, 102c, 102d, 102e: flow controller

[0074] 124: Remote Microwave Generator

[0075] 126: Reactor cavity

[0076] 128: Clean gas feed port

[0077] 130: Applicator tube

[0078] 132: System Controller

[0079] 134: Processor

[0080] 136: Memory

[0081] 142: Source plasma system

[0082] 150: Passivation structure

[0083] 152: first passivation layer

[0084] 154: Second passivation layer

[0085] 156: third passivation layer

[0086] 162: Main component / protective layer

[0087] 182: Top RF source generator

[0088] 182: Under Bump Metal Layer

[0089] 184: Side RF source generator

[0090] 192: Gas distribution line / conductive column

[0091] 200: Integrated Circuit Structure

[0092] 202: Wafer

[0093] 236: Extra thick metal wire

[0094] 242: cushion layer

[0095] 250: Passivation structure

[0096] 252: first passivation layer

[0097] 254: Second passivation layer

[0098] 256: Third passivation layer

[0099] 262: Protective layer

[0100] 282: Under Bump Metal Layer

[0101] 292: Conductive column

[0102] 300:Multi-chamber processing system

[0103] 332, 334: Load lock chamber

[0104] 336: Wafer transfer chamber

[0105] 350: Dome

[0106] 352: Plasma treatment area

[0107] 413: Load port

[0108] 414: Load port gate

[0109] 419: Overhead lifting and transfer section

[0110] 420: Lifting mechanism

[0111] 421:Disposal Unit

[0112] 430: Front-opening wafer cabin system

[0113] 522: Upper oblique face

[0114] 524: Downward sloping face

[0115] 542: Upper oblique face

[0116] 544: Downward sloping face

[0117] 554: Base material

[0118] 556: substrate support member DETAILED DESCRIPTION

[0119] The following disclosure provides many different embodiments, or examples, for implementing the different features of the provided subject matter. The following describes specific examples of components and arrangements to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat element symbols and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not substantially specify the relationship between the various embodiments and / or configurations discussed.

[0120] Additionally, spatially relative terms, such as "below," "below," "below," "above," "upper," and the like, may be used herein for convenience in description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative terms used herein may be interpreted accordingly.

[0121] Figure 1A and Figure 1B 1 is a flow chart of a method for manufacturing an integrated circuit structure with a passivation layer according to some embodiments of the present disclosure. Method 100 includes relevant portions of the overall manufacturing process. Additional operations may be provided before, during, and after method 100, and some of the operations described may be replaced, eliminated, modified, moved around, or relocated for additional embodiments of the method. One of ordinary skill in the art will recognize that other examples of semiconductor manufacturing processes may benefit from aspects of the present disclosure. Method 100 is an example and is not intended to limit the present disclosure except as expressly recited in the claims.

[0122] The following combination Figures 2 to 13 A method 100 is described, wherein an integrated circuit structure 200 is fabricated using the method 100 . Figures 2 to 13 1 is a cross-sectional view of a method for manufacturing a wafer 2 (the aforementioned wafer may also be referred to as a substrate) with a passivation layer at various stages according to some embodiments of the present disclosure. The method 100 begins at block S101, wherein a semiconductor substrate of a wafer having a metallization layer thereon is provided, wherein the metallization layer includes a topmost metallization layer. Figure 2 , wafer 2 includes substrate 10. In some embodiments, substrate 10 is a semiconductor substrate, such as a silicon substrate, but the under bump metal substrate may include other semiconductor materials, such as silicon germanium, silicon carbide, gallium arsenide, etc. A semiconductor element 14, symbolized by a transistor, may be formed at the surface of substrate 10. In an alternative embodiment, substrate 10 is a dielectric substrate, and no active elements are formed on the dielectric substrate, but passive elements such as capacitors, inductors, resistors, etc. may be formed. Contact plugs 16 are formed in an inter-layer dielectric (ILD) layer 18 and may be electrically coupled to element 14 (e.g., coupled to source / drain regions and gate electrodes of a transistor).

[0123] The interconnect structure 12 is formed on the interlayer dielectric layer 18, and the under-bump metal interconnect structure includes metal lines 26 and conductive pillars 28 (also referred to as vias or through-holes) therein and is electrically coupled to the semiconductor element 14. The metal lines 26 and the conductive pillars 28 can be formed of substantially pure copper (for example, wherein the weight percentage of copper is greater than about 90%, or greater than about 95%) or a copper alloy, and can be formed using a single and / or dual damascene process. In some embodiments, the metal lines 26 and the conductive pillars 28 can be substantially free of aluminum. The interconnect structure 12 includes multiple metal layers, namely M1, M2, M3...Mtop, wherein the metal layer M1 is a metal layer immediately above the interlayer dielectric layer 18, and the metal layer Mtop is a top metal layer immediately below the ultra-thick metal line 36 formed subsequently, such as Figure 3As shown in . Throughout the description, the term "metal layer" refers to a collection of metal lines in the same layer. Metal layers M1 to Mtop are formed in an inter-metal dielectric IMD layer 22, and the inter-metal dielectric IMD layer under the bump may be formed of an oxide such as un-doped silicate glass (USG), fluorinated silicate glass (FSG), a low-k dielectric material, and the like. The low-k dielectric material may have a k value lower than 3.8, but the dielectric material of the inter-metal dielectric layer 22 may also be close to 3.8. In some embodiments, the k value of the low-k dielectric material is lower than about 3.0, and may be lower than about 2.5.

[0124] In the embodiments discussed below, the top metal layer Mtop may be the metal layer M6, and the under-bump metal layer is the sixth metal layer above the interlayer dielectric layer 18, but in other embodiments, a metal layer above or below M6 may be the metal layer Mtop. In addition, in an exemplary embodiment, the metal layer M1 may have a thickness between about 2.0 kilo-angstroms. About and the metal layers M2 to Mtop may have a thickness between about About However, it should be appreciated that the dimensions of the metal layers recited throughout the description are merely examples and may vary in alternative embodiments.

[0125] Back to Figure 1A The method 100 then proceeds to block S102, where ultra-thick metal (ultra-thick metal) wiring is formed on the top metallization layer, wherein the ultra-thick metal lines are separated by gaps. Figure 3 , the ultra-thick metal line 36 may be formed of aluminum, aluminum copper, etc., but other materials such as copper, tungsten, nickel, palladium, etc. may also be used or added. The thickness T1 of the ultra-thick metal line 36 may be significantly greater than the thickness T2 of the metal layer Mtop. In some embodiments, by way of example and not limitation, the ratio T1 / T2 is greater than about 5. By way of example and not limitation, the ratio T1 / T2 may also be between about 6 and about 14. By way of example and not limitation, the thickness T1 of the ultra-thick metal line 36 is greater than about (hence the name ultra-thick metal line). The ultra-thick metal line 36 may have a Figure 3 The longitudinal axis of the cross-sectional view shown in FIG. 3 extends into and out of the page. The formation process of ultra-thick metal line 36 may include blanket depositing a thick metal layer, and then patterning the thick metal layer using suitable photolithography and etching techniques, and the remaining portion of the thick metal layer forms ultra-thick metal line 36.

[0126] Back to Figure 1A , method 100 then proceeds to block S103 , where a liner is deposited to conformally cover the ultra-thick metal line. Figure 4 The liner layer 42 is conformally formed on the ultra-thick metal line 36 and covers the upper surface and sidewalls of the ultra-thick metal line 36. In some embodiments, the liner layer 42 contacts the upper surface and sidewalls of the ultra-thick metal line 36. In addition, the liner layer 42 extends into the space between adjacent ultra-thick metal lines 36 and contacts the upper surface of the inter-metal dielectric layer 22. The formation method of the liner layer 42 includes a suitable deposition method such as a high-density plasma (HDP) chemical vapor deposition (CVD) process P1, but other suitable deposition methods may also be used.

[0127] Fig.19 An exemplary HDP tool capable of performing a high density plasma chemical vapor deposition (HDPVCD) process P1 according to some embodiments of the present disclosure is illustrated. In some embodiments, radio frequency (RF) power is applied to Fig.19 The top coil 78 shown in FIG. 1 is used to form a high density plasma. This plasma preheats the wafer 2 before deposition. During this step, heat can be applied to the back side of the wafer 2, optionally with a heater in the wafer support or with a pedestal, and the UBM pedestal absorbs heat from the plasma or an external heat source such as a heat lamp, and transfers the UBM heat to the wafer 2.

[0128] refer to Figure 4 and Fig.19 The method of the present disclosure can be used to deposit a dielectric layer on a substrate positioned at Fig.19 3. The high density plasma chemical vapor deposition system 6 shown in FIG. 3 is a process chamber 38 for depositing a wafer 2 on a substrate 10 of a wafer 2 in a high density plasma chemical vapor deposition system 6 shown in FIG. The wafer 2 is positioned in a process chamber 38 adjacent to a plasma processing region 352. An inert gas such as argon is flowed into the process chamber 38. After the inert gas is introduced into the process chamber 38, the plasma is triggered. Then, a deposition gas is introduced into the process chamber 38. The deposition gas is composed of, for example, a silicon source gas such as silane gas SiH4 and an oxygen source gas such as molecular oxygen gas O2.

[0129] During deposition, the flow rate of argon gas for the HDPCVD process P1 is, for example, in the range of 40-120 sccm. The flow rate of silane gas for the HDPCVD process P1 is, for example, in the range of 40-120 sccm, and oxygen gas for the HDPCVD process P1 flows into the process chamber 38 at a flow rate, for example, in the range of 80-250 sccm. By way of example and not limitation, the plasma is generated by heating the plasma at a frequency between about 1.8 MHz and about 2.2 MHz and at a power of about 12 W / cm 2 About 16W / cm 2 1 to 13 MHz, and by turning on the top RF source generator 182 at a RF power level between about 12 MHz and about 16 MHz, and by turning on the side RF source generator 184 at a frequency between about 7 and about 13 MHz. It is noteworthy that the RF bias generator 86 coupled to the wafer chuck 68 is turned off during the high-density plasma chemical vapor deposition process P1, which in turn will reduce the downward force applied to the plasma, thereby preventing unwanted damage to the ultra-thick metal lines caused by downward plasma flash. In other words, the liner layer 42 is deposited using the high-density plasma chemical vapor deposition process P1 without RF bias power in order to protect the ultra-thick metal lines from excessive plasma flash.

[0130] In some embodiments, the liner layer 42 is formed of a dielectric material(s). In some embodiments, the liner layer 42 comprises silicon oxide, although other types of oxide materials and nitride materials may be used. The liner layer 42 may also be formed of materials other than oxides and / or nitrides, and may be a homogeneous layer or a composite layer, with the UBM composite layer comprising sublayers formed of different materials. In some embodiments, the thickness of the liner layer 42 is about 1000 Å. to about An excessively thin liner layer 42 may result in increased damage to the ultra-thick metal line 36. An excessively thick liner layer 42 may result in excessive overhangs formed in one or more subsequently formed passivation layers.

[0131] like Fig.19 As illustrated in FIG. 1 , the high density plasma chemical vapor deposition system 6 includes, for example, a process chamber 38, a vacuum system 40, a source plasma system 142, a bias plasma system 44, a gas distribution system 46, and a remote microwave generated plasma cleaning system 48. The upper portion of the process chamber 38 includes a dome 350, and the under bump metal dome is made of a dielectric material such as aluminum oxide or aluminum nitride. The dome 350 can be the upper boundary of a plasma processing region 352. The plasma processing region 352 is bounded on the bottom by the upper surface of the substrate 554 and the substrate support member 556.

[0132] The heater plate 58 and cold plate 60 extend over and are thermally coupled to the dome 350. The heater plate 58 and cold plate 60 allow the dome temperature to be controlled within about ±10° C. of a desired temperature range. This allows the dome temperature to be optimized for various processes.

[0133] The lower portion of the process chamber 38 includes a main body member 162, and the under bump metal main body member connects the process chamber to the vacuum system. The base portion 64 of the substrate support member 556 is mounted on the main body member 162 and forms a continuous inner surface with the main body member 162. The substrate is transferred into and out of the process chamber 38 through the insertion / removal opening 95 in the side of the process chamber 38 by a robot blade (not shown). A motor (not shown) raises and lowers a lift pin plate (not shown), the under bump metal lift pin plate raises and lowers lift pins (not shown), and a plurality of lift pins raise and lower the wafer. After being transferred into the process chamber 38, the substrate is loaded into the raised lift pins and then lowered to the substrate receiving portion 66 of the substrate support member 556. The substrate receiving portion 66 includes an electrostatic chuck 68, which secures the substrate to the substrate support member 556 during substrate processing.

[0134] The vacuum system 40 includes a throttle body 70, which houses a double blade throttle valve 72 and is attached to a gate valve 74 and a turbomolecular pump 76. It should be noted that the throttle body 70 provides minimal obstruction to the flow of gases and allows symmetrical pumping. The gate valve 74 can isolate the pump 76 from the throttle body 70 and can also control the process chamber pressure by limiting the amount of exhaust flow when the throttle valve 72 is fully open. The arrangement of the throttle valve 72, the gate valve 74 and the turbomolecular pump 76 allows accurate and stable control of the process chamber pressure from about 1 mTorr to 100 mTorr.

[0135] The source plasma system 142 includes a top coil 78 and a side coil 80, the UBM top coil and the UBM side coil being mounted on the dome 350. A symmetrical ground shield (not shown) reduces electrical coupling between the coils. The top coil 78 is powered by a top RF source generator 182, while the side coil 80 is powered by a side RF source generator 184, allowing independent power levels and operating frequencies for each coil. This dual coil system allows control of radial ion density in the process chamber 38, thereby improving plasma uniformity. The side coil 80 and the top coil 78 inductively couple energy into the chamber 38. In some embodiments, the top RF source generator 182 provides up to about 2500 W of RF power at nominally about 2 MHz, and the side RF source generator 184 provides up to about 5000 W of RF power at nominally about 2 MHz. The operating frequencies of the top RF generator and the side RF generator may be offset relative to the nominal operating frequency (eg, from about 1.7 MHz to about 1.9 MHz and from about 1.9 MHz to about 2.1 MHz, respectively) to improve plasma generation efficiency.

[0136] RF generators 182 and 184 include digitally controlled synthesizers and operate in a frequency range from about 1.7 MHz to about 2.1 MHz. Each generator includes an RF control circuit (not shown) that measures the reflected power from the process chamber and coil back to the generator and adjusts the operating frequency to obtain the lowest reflected power, as understood by a person of ordinary skill in the art. The RF generator can be designed to operate into a load having a characteristic impedance of about 50Ω. RF power can be reflected from a load having a different characteristic impedance than the generator. This can reduce the power delivered to the load. In addition, the power reflected back to the generator from the load can overload and damage the generator. Because the impedance of the plasma can range from less than about 5Ω to more than about 900Ω, depending on the plasma ion density and other factors, and because the reflected power can vary with frequency, adjusting the generator frequency based on the reflected power increases the power delivered from the RF generator to the plasma and protects the generator. Another way to reduce reflected power and improve efficiency uses a matching network.

[0137] Matching networks 89 and 90 match the output impedance of generators 182 and 184 to coils 78 and 80, respectively. As the load changes, the RF control circuit can tune both matching networks by changing the values ​​of the capacitors within the matching networks to match the generator to the load. When the power reflected from the load back to the generator exceeds a certain limit, the RF control circuit can tune the matching network. One way to provide a constant match and effectively disable the RF control circuit from tuning the matching network is to set the reflected power limit to any expected value that exceeds the reflected power. This can help stabilize the plasma under some conditions by keeping the matching network constant at its nearest condition.

[0138] The bias plasma system 44 includes an RF bias generator 86 and a bias matching network 88. The bias plasma system 44 capacitively couples the substrate receiving portion 66 to the body member 162, with the UBM substrate receiving portion and the UBM body member acting as complementary electrodes. The bias plasma system 44 is used to enhance the transport of plasma species created by the source plasma system 142 to the surface of the substrate. In some embodiments, the RF bias generator 86 provides up to 5000 W of RF power at about 10 MHz to about 15 MHz.

[0139] Other measures may also help stabilize the plasma. For example, RF control circuitry may be used to determine the power delivered to the load (plasma) and may increase or decrease the generator output power to keep the delivered power substantially constant during deposition of the layer.

[0140] The gas distribution system 46 includes a plurality of gas sources 100a, 100b, 100c, 100d, and 100e. In some embodiments, the aforementioned gas sources include silane, molecular oxygen, silicon fluoride, and argon, respectively. The gas distribution system 46 provides gases from a number of sources to a process chamber for processing a substrate via gas distribution lines 192 (some of which are shown). The gases are introduced into the process chamber 38 via a gas ring 94, a top nozzle 96, and a top exhaust port 98. Specifically, gas sources 100a and 100d provide gases to the top nozzle 96 via flow controllers 120a and 120c, respectively, and gas distribution lines 192. Gas from gas source 100b is provided to the gas exhaust port 98 via flow controller 120b. The top nozzle 96 and the top exhaust port 98 allow independent control of the top flow and the side flow of the gas, which improves film uniformity and allows fine tuning of the deposition and doping parameters of the film. The top exhaust port 98 is an annular opening surrounding the top nozzle 96 through which gas can flow from the gas distribution system into the process chamber through the UBM top nozzle.

[0141] Gas is provided to the gas ring 94 from each of the aforementioned gas sources via flow controllers 102a, 102b, 102c, 102d, and 102e and gas distribution lines 192. The gas ring 94 has a plurality of gas nozzles 106 and 108 (two of which are shown) that provide uniform gas flow over the substrate. The nozzle length and nozzle angle can be changed by changing the gas ring 94. This allows for tailoring of uniform distribution and gas utilization efficiency for a specific process within a separate process chamber. In a particular embodiment, the gas ring 94 has a total of twenty-four gas nozzles, twelve first gas nozzles 108 and twelve second gas nozzles 106. In some embodiments, the gas nozzle 108 (one of which is shown) is coplanar with the second gas nozzle 106 and is shorter than the plurality of second gas nozzles.

[0142] In some embodiments, flammable, toxic, or corrosive gases may be used. In these cases, it may be desirable to eliminate the gas remaining in the gas distribution line after deposition. For example, this may be accomplished using a three-way valve such as valve 112 to isolate process chamber 38 from distribution line 192 and vent distribution line 192 to evacuate foreline 114. Fig.19 Other similar valves such as valves 112a and 112b may be incorporated into other gas distribution lines as shown in FIG. Such three-way valves may be placed as close to the process chamber 38 as practical to minimize the volume of the unexhausted gas distribution line (between the three-way valve and the process chamber). Additionally, two-way (on-off) valves (not shown) may be placed between a mass flow controller (MFC) and the process chamber or between a gas source and an MFC.

[0143] A remote microwave generated plasma cleaning system 48 is provided to periodically clean deposition residues from process chamber components. The cleaning system includes a remote microwave generator 124 that creates a plasma from a clean gas source 100e such as fluorine, nitrogen trifluoride, or equivalent in a reactor cavity 126. Reactive species generated by this plasma are transported to the process chamber 38 through a clean gas feed port 128 via an applicator tube 130. The materials used to contain the cleaning plasma (e.g., cavity 126 and applicator tube 130) should be resistant to plasma attack. The distance between the reactor cavity 126 and the feed port 128 is kept as short as practical because the concentration of desirable plasma species can decrease with distance from the reactor cavity 126. Generating the cleaning plasma in a remote cavity allows the use of an efficient microwave generator without subjecting the process chamber components to the temperatures, radiation, or bombardment of a glow discharge that may be present in an in-situ plasma. During cleaning or other processes, gate valve 74 may be closed to isolate turbomolecular vacuum pump 76 from the process chamber. In this configuration, foreline 114 provides process vacuum generated by a remote vacuum pump, which may be a mechanical vacuum pump. Isolating the turbomolecular pump from the process chamber with a gate valve protects the turbomolecular pump from corrosive compounds or other potentially harmful effects generated by process chamber cleaning or other processes.

[0144] The system controller 132 regulates the operation of the HDPCVD system 6 and includes a processor 134 in electrical communication with the UBM system controller to regulate the operation of the UBM system controller. In some embodiments, the processor 134 is part of a single-board computer (SBC) that includes analog and digital input / output boards, interface boards, and stepper motor controller boards. Various components of the HDPCVD system 6 conform to the Versa Modular European (VME) standard, which can be boards, card racks, and connector types and sizes. The VME standard can also be a bus structure such as having a 16-bit data bus and a 24-bit address bus. The processor 134 executes system control software, which is a computer program stored in a memory 136, which is electronically coupled to the processor 134. Any type of memory element can be used, such as a hard disk drive, a floppy disk drive, a card cage, or a combination thereof.

[0145] Back to Figure 1A The method 100 then proceeds to block S104, where a first passivation layer is deposited by performing a high-density plasma chemical vapor deposition process to cover the liner and partially fill the gaps between the ultra-thick metal lines. Figure 5 , the first passivation layer 52 can be Figure 5 The high density plasma chemical vapor deposition process P2 shown in FIG. is deposited on the liner layer 42. It is worth noting that the high density plasma chemical vapor deposition process P2 can use a non-zero bias power to increase the downward plasma strike on the deposited passivation material, because the liner layer 42 can protect the ultra-thick metal line 36 from damage caused by the plasma strike.

[0146] refer to Figure 5 and Fig.19 In both cases, an inert gas such as argon is flowed into the process chamber 38. After the inert gas is introduced into the process chamber 38, the plasma is triggered. Then, a deposition gas is introduced into the process chamber 38. The deposition gas is composed of, for example, a silicon source gas such as silane gas SiH4 and an oxygen source gas such as molecular oxygen gas O2. During deposition, the flow rate of argon is in the range of 40-120 sccm. The flow rate of silane gas is, for example, in the range of 40-120 sccm, and oxygen is flowed into the process chamber at a flow rate in the range of, for example, 80-250 sccm.

[0147] During the HDPCVD process P2, by way of example and not limitation, the PDMS layer is heated to 100 W / cm2 at a frequency between about 1.8 MHz and about 2.2 MHz and at a temperature between about 12 W / cm2. 2 About 16W / cm2 The RF power level between the open Fig.19 The top RF source generator 182 shown in FIG. 1 is configured to generate a radio frequency between about 1.8 MHz and 2.2 MHz and between about 12 W / cm 2 With 16W / cm 2 The side RF source generator 184 is turned on at a power level between about 12 MHz and about 16 MHz and at a power level between about 5 W / cm 2 About 13W / cm 2 The RF bias generator 86 is turned on at a RF bias power level between 0 and 100 Hz to form plasma.

[0148] The non-zero bias power allows the HDPCVD process P2 to perform deposition and sputter etching simultaneously. The sputter etching in the HDPCVD process P2 can suppress the overhang formed on the resulting passivation layer 52 compared to a situation where no sputter etching occurs in the HDPCVD process, which in turn improves the gap filling window of one or more subsequent HDPCVD processes (e.g., HDPCVD processes P3 and P4). The sputter etching in the HDPCVD process P2 can result in a lower oblique facet 524 and an upper oblique facet 522 formed on the first passivation layer 52, wherein the lower oblique facet 524 has a steeper slope than the upper oblique facet 522. The angled facets 522 and 524 are formed such that the first passivation layer 52 becomes narrower as it extends away from the underlying interconnect structure 12, thereby improving the gapfill window for one or more subsequent high density plasma chemical vapor deposition processes.

[0149] In some embodiments, the first passivation layer 52 is made of substantially the same material as the pad layer 42. For example, both the first passivation layer 52 and the pad layer 42 are made of silicon oxide (SiO2). It is noteworthy that a high density plasma chemical vapor deposition (HDPVCD) process with a non-zero bias may result in a lower porosity in the silicon oxide compared to a case where a zero bias is used in the HDPVCD process. Therefore, the first passivation layer 52 formed using a non-zero bias is less porous than the pad layer 42, even though both the UBM first passivation layer and the UBM pad layer are formed of silicon oxide. Due to at least the porosity difference, the first passivation layer 52 and the pad layer 42 may form a distinguishable interface E1 therein (e.g., distinguishable in a TEM image). In some embodiments, the first passivation layer 52 is non-porous. In some embodiments, the thickness of the first passivation layer 52 is about 1000 Å. to about In some embodiments, the thickness K2 of the first passivation layer 52 is greater than the thickness K1 of the liner layer 42 .

[0150] The non-zero RF bias power of the HDPCVD process P2 causes the ions in the plasma to move up and down relative to the surface of the wafer. It is believed that the wafer support structure acts as one plate of the capacitive coupling structure, while the conductive plasma above the substrate provides a complementary electrode. In a simultaneous deposition / sputtering process, increasing the RF bias power generally increases the sputtering etch rate on horizontal surfaces and thus reduces the net deposition rate.

[0151] Plasma density refers to the number of plasma species per unit volume of plasma, which is considered to be a function of the RF power. Within limits, higher plasma density provides more plasma species for sputter etching. The RF bias power creates an electric field orthogonal to the surface of the substrate, and the under-bump metal electric field can accelerate plasma ions into and away from the surface of the substrate. The ions sputter-etch the surface of the substrate by physically bombarding the surface. It was found that the etching rate of the surface is more sensitive to changes in the RF bias power than to changes in the RF power. For example, when increasing or decreasing the RF bias power, an approximately 10% change in the RF bias power level changes the sputter etching rate by approximately 10%. An approximately 10% change in the RF power level changes the sputter etching rate by less than approximately 5%. The sputter etching rate is measured on a horizontal wafer surface.

[0152] When using a deposition / sputtering technique to deposit the passivation layer 52, a consideration is to maintain a suitable deposition to sputtering (D / S) ratio to prevent overhang or over-etching of the passivation layer 52. The D / S ratio may be as follows:

[0153] D / S = Ds / [Ds-D(S+B)];

[0154] Where D / S is the deposition to sputtering ratio, Ds is the deposition rate with top and side RF sources applied, and D(S+B) is the deposition rate with both top and side RF sources and RF bias applied. The range advocated for the D / S ratio may depend on the maximum width-to-depth ratio of the wire-to-wire spacing between adjacent ultra-thick metal lines 36.

[0155] The D / S ratio can be varied in many ways. For example, the D / S ratio can be increased by increasing the deposition rate at a substantially constant sputter etch rate, or by decreasing the sputter etch rate at a substantially constant deposition rate, both of which result in an increased D / S ratio. Conversely, the D / S ratio can be decreased by decreasing the deposition rate at a substantially constant sputter etch rate, or by increasing the sputter etch rate at a substantially constant deposition rate. Varying the RF bias energy also affects the D / S ratio. Specifically, it is believed that by decreasing the RF bias energy, the sputter etch rate decreases and the deposition rate increases, thereby increasing the D / S ratio. By increasing the RF bias energy, the D / S ratio can be decreased in a similar manner.

[0156] In some embodiments, the liner layer 42 and the first passivation layer 52 of the wafer 2 are formed in-situ in the same process tool (ie, in the process chamber 38 of the HDP CVD system 6 ).

[0157] As used herein, the term "in situ" is used to describe a process that is performed while a component or substrate is maintained within a processing system (e.g., including a load lock chamber, transfer chamber, process chamber, or any other fluidly coupled chamber), and wherein, for example, the processing system allows the substrate to be maintained under vacuum conditions. Thus, the term "in situ" may also be generally used to refer to processes in which the component or substrate being processed is not exposed to the external environment (e.g., outside the processing system).

[0158] Back to Figure 1A , the method 100 then proceeds to block S105, wherein the high density plasma chemical vapor deposition process is optionally paused to reduce the temperature of the ultra-thick metal line. Figure 5 , Fig. 20 ,and Fig.21 , through Figure 5 After the first passivation layer 52 is deposited by the high-density plasma chemical vapor deposition process P2 shown in FIG. 1 , the wafer 2 can be transferred from the high-density plasma chemical vapor deposition system 6 to the Fig. 20 The wafer transfer system chamber 336 (also referred to as a non-processing chamber) shown in FIG. 1 is used to cool the ultra-thick metal line 36 to reduce the temperature of the ultra-thick metal line 36. It is worth noting that the liner layer 42 and the first passivation layer 52 may experience different thermal stresses caused by the increased temperature, which may cause cracks at the interface E1 between the liner layer 42 and the first passivation layer 52. Therefore, the transfer can be used to cool the ultra-thick metal line 36 so as to reduce the cracks at the interface E1 between the liner layer 42 and the first passivation layer 52.

[0159] In some embodiments, the wafer 2 may be transferred to a load lock chamber 332 , 334 (also referred to as a non-processing chamber) or transferred to the outside of the multi-chamber processing system 300 to reduce the temperature of the ultra-thick metal line 36 so as to reduce cracks at the interface E1 between the liner layer 42 and the first passivation layer 52 .

[0160] In some embodiments, the wafer 2 may be transferred to a handling unit 421 (also referred to as a non-processing chamber) connected to the multi-chamber processing system 300, or to a front opening unified pod (FOUP) system 430 to reduce the temperature of the ultra-thick metal wire 36. Therefore, cracks at the interface E1 between the liner layer 42 and the first passivation layer 52 may be reduced. In some embodiments, the upper surface of the first passivation layer 52 may be exposed to the atmosphere.

[0161] Fig. 20 Schematic top view of an exemplary multi-chamber processing system 300 is shown. In some embodiments, Fig. 20 , the system 300 may be equivalently referred to as a "cluster tool". The system 300 may generally include load lock chambers 332 and 334, a wafer transfer chamber 336, and a plurality of processing systems 1-6. In various embodiments, the load lock chambers 332 and 334 provide for transfer of wafers 2 into and out of the system 300. In various embodiments, the system 300 is under vacuum, and the load lock chambers 332 and 334 may pump down substrates introduced into the system 300 (e.g., by mechanical pumps and / or turbomolecular pumps). In some embodiments, the load lock chambers 332 and 334 may be adapted to receive a single wafer or multiple wafers (e.g., loaded into a cassette). By way of example, the load lock chambers 332 and 334 may be separated from the wafer transfer chamber 336 by a gate valve, thereby allowing the wafer transfer chamber 336 to remain under vacuum when one or both of the load lock chambers 332 and 334 are vented.

[0162] In various embodiments, the wafer transfer chamber 336 is equipped with an automated robotic arm that can smoothly move along any of the horizontal, vertical, and / or rotational axes to transfer substrates between the load lock chambers 332 and 334 and any of the substrate processing chambers 1-6. Each processing chamber 1-6 can be used to perform a number of substrate processing operations such as atomic layer deposition (ALD), high density plasma chemical vapor deposition, PVD, etching, pre-treatment / pre-soaking, degassing, annealing, and a number of metrology operations such as XPS analysis, AFM analysis, and / or other suitable processing or metrology operations. In various embodiments, the system 300 can have more or fewer processing chambers, for example, for the specific process to be performed by the system 300.

[0163] exist Fig.21, reference numeral 413 designates a load port; 419 designates an overhead hoist transfer (OHT) section; and 420 designates a lifting mechanism. The load port 413 has a FIMS (Front Opening Interface Mechanical Standard) structure. Fig.21 The OHT section 419 in the semiconductor factory is an automatic transfer machine for use with a front-opening wafer cabin system 430 installed in a bay of a semiconductor factory. Each of a plurality of handling units 421 arranged in a line has a load port 413. The front-opening wafer cabin system 430 with the wafer 2 is transferred by using a lifting mechanism 420.

[0164] In some embodiments, the wafer 2 is transported from one handling system 421 to another while being stored in the front opening wafer cabin system 430. An automated transfer machine such as the OHT section 419 is used to transport the front opening wafer cabin system 430 with the wafer 2. In some embodiments, the front opening wafer cabin system 430 with the wafer 2 is lifted away from the load port 413 of the handling unit 421 by using the lifting mechanism 420.

[0165] In some embodiments, the front-opening wafer cabin system 430 with the wafer 2 is transported to a machine room (also referred to as a non-processing chamber) by using the OHT section 419 and temporarily stored in the machine room. In the next treatment process (e.g., an ashing process, etc.), the front-opening wafer cabin system 430 is transported.

[0166] refer to Fig.21 , a front-opening wafer cabin system 430 having a wafer 2 to be processed stored therein is transported from a machine room provided in the process of the manufacturing process to a handling unit 421 through an OHT section 419. The front-opening wafer cabin system 430 having the wafer 2 is lowered to a predetermined position (assembly position) on a load port 413 of the handling unit 421 by a lifting mechanism 420 and is placed in a predetermined position of the under bump metal. The lifting mechanism 420 is disengaged from the front-opening wafer cabin system 430 having the wafer 2, and the front-opening wafer cabin system 430 having the wafer 2 remains on the load port 413. Subsequently, the front-opening wafer cabin system 430 having the wafer 2 is moved forward until the under bump metal front-opening wafer cabin system docks with the load port door 414. The wafer 2 is transported to a multi-chamber processing system 300 provided in the handling unit 421 by a wafer transport robot (not shown) provided in the handling unit 421, wherein the wafer undergoes a predetermined manufacturing process, such as Figures 4 to 7 One or more high density plasma chemical vapor deposition processes P1-P4 shown in FIG.

[0167] Back to Figure 1AThe method 100 then proceeds to block S106, where a second passivation layer is deposited by performing another high-density plasma chemical vapor deposition process to cover the first passivation layer and partially fill the gap. Figure 6 , can be achieved by parallel deposition / sputtering processes such as Figure 6 The high density plasma chemical vapor deposition process P3 shown in FIG. 1 deposits the second passivation layer 54. It is worth noting that the high density plasma chemical vapor deposition process P3 can use a non-zero bias power to increase the downward plasma strike on the deposited passivation material, because the liner layer 42 and the first passivation layer 52 can protect the ultra-thick metal line 36 from damage caused by the plasma strike.

[0168] During the HDPCVD process P3, by way of example and not limitation, the PDMS layer is heated to 100 W / cm2 at a frequency between about 1.8 MHz and about 2.2 MHz and at a temperature between about 12 W / cm2. 2 About 16W / cm 2 The RF power level between the open Fig.19 The top RF source generator 182 shown in FIG. 1 is configured to generate a radio frequency between about 1.8 MHz and about 2.2 MHz and at about 12 W / cm 2 About 16W / cm 2 The side RF source generator 184 is turned on at a power level between about 12 MHz and about 16 MHz and at a power level between about 6 W / cm 2 About 14W / cm 2, and the RF bias power level between 0.1 and 0.2 to form plasma. In some embodiments where the aspect ratio (i.e., the ratio of depth to width) of the wire-to-wire spacing between the ultra-thick metal lines 36 is increased by the first passivation layer 52 (e.g., the reduction in the width of the wire-to-wire spacing caused by the first passivation layer 52 is greater than the reduction in the depth of the wire-to-wire spacing caused by the first passivation layer 52), the non-zero RF bias power of the high-density plasma chemical vapor deposition process P3 may be greater than the non-zero RF bias power of the high-density plasma chemical vapor deposition process P2 to result in a greater sputtering etch rate in the high-density plasma chemical vapor deposition process P3 than in the high-density plasma chemical vapor deposition process P2. In this way, even if the second passivation layer is deposited in the wire-to-wire spacing with an increased aspect ratio, the overhang of the second passivation layer 54 may be suppressed. In such embodiments, the deposition to sputtering ratio of the high-density plasma chemical vapor deposition process P3 is less than the deposition to sputtering ratio of the high-density plasma chemical vapor deposition process P2. On the other hand, if the width-to-depth ratio of the wire-to-wire spacing between the ultra-thick metal lines 36 is reduced by the first passivation layer 52 (e.g., the reduction in the width of the wire-to-wire spacing is less than the reduction in the depth of the wire-to-wire spacing), the non-zero RF bias power of the HDPCVD process P3 may be less than the non-zero RF bias power of the HDPCVD process P2 to result in a greater deposition rate in the HDPCVD process P3 than in the HDPCVD process P2 because the HDPCVD process P3 has a relaxed overhang problem compared to the HDPCVD process P2. In such embodiments, the deposition-to-sputtering ratio of the HDPCVD process P3 is greater than the deposition-to-sputtering ratio of the HDPCVD process P2.

[0169] The non-zero bias power allows the HDPCVD process P3 to perform deposition and sputter etching simultaneously. The sputter etching in the HDPCVD process P3 can suppress the overhang formed on the resulting passivation layer 54 compared to a situation where no sputter etching occurs in the HDPCVD process, which in turn improves the gap filling window of one or more subsequent HDPCVD processes (e.g., HDPCVD process P4). The sputter etching in the HDPCVD process P3 can result in a lower oblique facet 544 and an upper oblique facet 542 formed on the second passivation layer 54, wherein the lower oblique facet 544 has a steeper slope than the upper oblique facet 542. The angled facets 542 and 544 are formed such that the first passivation layer 52 narrows as it extends away from the underlying interconnect structure 12, thereby improving the gapfill window for one or more subsequent high density plasma chemical vapor deposition processes.

[0170] In some embodiments, the second passivation layer 54 is made of substantially the same material as the first passivation layer 52 and has no interface therebetween, because the UBM second passivation layer and the UBM first passivation layer have comparable porosity (e.g., are less porous or non-porous compared to the pad layer), so that the second passivation layer 54 and the first passivation layer 52 can experience comparable stress during the manufacturing process, and thus cracks between the second passivation layer 54 and the first passivation layer 52 can be prevented. For example, both the second passivation layer 54 and the first passivation layer 52 are made of silicon oxide (SiO2).

[0171] In some embodiments, the second passivation layer 54 is made of substantially the same material as the pad layer 42. For example, both the second passivation layer 54 and the pad layer 42 are made of silicon oxide (SiO2). It is noteworthy that a high-density plasma chemical vapor deposition process with a non-zero bias may result in a lower porosity in the silicon oxide compared to a case where a zero bias is used in a high-density plasma chemical vapor deposition process. Therefore, the second passivation layer 54 formed using a non-zero bias is less porous than the pad layer 42, even though both the under bump metal second passivation layer and the under bump metal pad layer are formed of silicon oxide. In some embodiments, the second passivation layer 54 is non-porous. In some embodiments, the thickness of the second passivation layer 54 is about 1000 Å. to about The facets 542 and 544 of the second passivation layer 54 are less vertical than the facets 522 and 524 of the first passivation layer 52 .

[0172] In some embodiments, the second passivation layer 54 and the first passivation layer 52 are formed in-situ in the same process tool (ie, in the same high-density plasma chemical vapor deposition system), as previously described with respect to Figures 19 to 21 In some embodiments, the second passivation layer 54 and the first passivation layer 52 are performed ex-situ in different high-density plasma chemical vapor deposition systems of the same multi-chamber processing system 300, as previously described with respect to Figures 19 to 21 In some embodiments, the second passivation layer 54 and the first passivation layer 52 are performed ex-situ in different high-density plasma chemical vapor deposition systems in different multi-chamber processing systems, as previously described with respect to Figures 19 to 21 Discussed.

[0173] Back to Figure 1B The method 100 then proceeds to block S108, where a third passivation layer is deposited to cover the second passivation layer by performing a high density plasma chemical vapor deposition process. Figure 7 , the third passivation layer 56 may be formed by a parallel deposition / sputtering process such as Figure 7It is worth noting that the high-density plasma chemical vapor deposition process P4 can use a non-zero bias power to increase the downward plasma strike on the deposited passivation material, because the liner layer 42, the first passivation layer 52, and the second passivation layer 54 can protect the ultra-thick metal line 36 from damage caused by the plasma strike.

[0174] During the HDPCVD process P4, by way of example and not limitation, the PDMS layer is heated to 100 W / cm2 at a frequency between about 1.8 MHz and about 2.2 MHz and at a temperature between about 12 W / cm2. 2 About 16W / cm 2 The RF power level between the open Fig.19 The RF source generator 182 shown in FIG. 1 is configured to generate a radio frequency between about 1.8 MHz and about 2.2 MHz and a frequency between about 12 W / cm 2 About 16W / cm 2 The side RF source generator 184 is turned on at a power level between about 12 MHz and about 16 MHz and at a power level between about 7 W / cm 2 About 15W / cm 2, and the RF bias power level between 0.1 and 0.2 to form plasma. In some embodiments where the aspect ratio (i.e., the ratio of depth to width) of the wire-to-wire spacing between the ultra-thick metal lines 36 is increased by the second passivation layer 54 (e.g., the reduction in the width of the wire-to-wire spacing caused by the second passivation layer 54 is greater than the reduction in the depth of the wire-to-wire spacing caused by the second passivation layer 54), the non-zero RF bias power of the high-density plasma chemical vapor deposition process P4 may be greater than the non-zero RF bias power of the high-density plasma chemical vapor deposition process P3 to result in a greater sputtering etch rate in the high-density plasma chemical vapor deposition process P4 than in the high-density plasma chemical vapor deposition process P3. In this way, even if the third passivation layer is deposited in the wire-to-wire spacing with an increased aspect ratio, the overhang of the third passivation layer 56 may be suppressed. In such embodiments, the deposition to sputtering ratio of the high-density plasma chemical vapor deposition process P4 is less than the deposition to sputtering ratio of the high-density plasma chemical vapor deposition process P3. On the other hand, if the width-to-depth ratio of the wire-to-wire spacing between the ultra-thick metal lines 36 is reduced by the second passivation layer 54 (e.g., the width reduction of the wire-to-wire spacing is less than the depth reduction of the wire-to-wire spacing), the non-zero RF bias power of the HDPCVD process P4 can be less than the non-zero RF bias power of the HDPCVD process P3 to result in a greater deposition rate in the HDPCVD process P4 than in the HDPCVD process P3 because the HDPCVD process P4 has a relaxed overhang problem compared to the HDPCVD process P3. In such embodiments, the deposition-to-sputtering ratio of the HDPCVD process P4 is greater than the deposition-to-sputtering ratio of the HDPCVD process P3.

[0175] In some embodiments, the third passivation layer 56 partially fills the gaps between the ultra-thick metal lines 36. In some embodiments, the third passivation layer 56 is made of substantially the same material as the second passivation layer 54 and has no interface therebetween, because the UBM third passivation layer and the UBM second passivation layer have comparable porosity (e.g., are less porous or non-porous compared to the pad layer), so that the third passivation layer 56 and the second passivation layer 54 can experience comparable stress during the manufacturing process, and thus cracks between the third passivation layer 56 and the second passivation layer 54 can be reduced. For example, both the third passivation layer 56 and the second passivation layer 54 are made of silicon oxide (SiO2).

[0176] In some embodiments, the third passivation layer 56 is made of substantially the same material as the pad layer 42. For example, both the third passivation layer 56 and the pad layer 42 are made of silicon oxide (SiO2). It is noteworthy that a high-density plasma chemical vapor deposition process with a non-zero bias can result in a lower porosity in the silicon oxide compared to when a zero bias is used in the high-density plasma chemical vapor deposition process. Therefore, the third passivation layer 56 formed using a non-zero bias is less porous than the pad layer 42, even though both the under bump metal third passivation layer and the under bump metal pad layer are formed of silicon oxide. In some embodiments, the second passivation layer 54 is non-porous. In some embodiments, the thickness of the third passivation layer 56 is about 1000 Å. to about In some embodiments, the entirety of the first passivation layer 52, the second passivation layer 54, and the third passivation layer 56 may be referred to as a passivation structure 50. The passivation structure 50 is a continuous oxide material having a homogeneous pore distribution and thus has no discernible interface inside.

[0177] In some embodiments, the third passivation layer 56 and the second passivation layer 54 are performed in-situ in the same process tool (i.e., performed in the same HDPCVD system). In some embodiments, the third passivation layer 56 and the second passivation layer 54 are performed ex-situ in different HDPCVD systems in the same multi-chamber processing system 300. In some embodiments, the third passivation layer 56 and the second passivation layer 54 are performed ex-situ in different HDPCVD systems in different multi-chamber processing systems.

[0178] Back to Figure 1B The method 100 then proceeds to block S109, where a protective layer is formed on the third passivation layer by a plasma enhanced chemical vapor deposition (PECVD) process. Figure 8 , a protective layer 62 such as a nitride layer is conformally deposited on the passivation structure 50 by a plasma enhanced chemical vapor deposition process P5. The protective layer 62 is deposited by plasma enhanced chemical vapor deposition. The protective layer 62 may include silicon nitride (SiN) or silicon oxynitride (SiON). The protective layer 62 prevents or reduces moisture, mechanical and radiation damage to the integrated circuit. In some embodiments, the thickness T3 of the passivation structure 50 is substantially greater than the thickness T4 of the protective layer 62. The passivation structure 50 and the protective layer 62 form a composite passivation layer. The protective layer 62 is above the upper surface of the ultra-thick metal line 36 and thus does not fill in the gaps between the ultra-thick metal lines 36 (i.e., the wiring to wiring spacing). In some embodiments, the passivation structure 50 extends continuously from the liner layer 42 to the protective layer 62 without an interface.

[0179] Back to Figure 1B The method 100 then proceeds to block S110, where a hard mask and a patterned photoresist are formed on the protective layer. Fig. 9 , a hard mask layer 72 and a photoresist layer 74 are sequentially formed on the protective layer 62. In some embodiments, the hard mask layer 72 includes a material (multiple) such as amorphous silicon (a-Si), silicon oxide, silicon nitride (SiN), titanium nitride, or another suitable material or composition. In some embodiments, the hard mask layer 72 includes an anti-reflection coating (ARC) layer such as a nitrogen-free anti-reflection coating (NFARC) layer, and the under bump metal nitrogen-free anti-reflection coating layer includes a material (multiple) such as silicon oxide, silicon oxycarbide, or plasma enhanced chemical vapor deposition silicon oxide.

[0180] In some embodiments, the photoresist layer 74 is a multilayer resist formed on the hard mask layer 72. In some embodiments, the photoresist layer 74 is coated on the hard mask layer 72 using a spin coating method or any other suitable method. In some embodiments, the photoresist layer 74 may be a deep UV photoresist that may include a polymer having a hydroxystyrene group. In some embodiments, the photoresist layer 74 may be formed of a positive tone photoresist. In some embodiments, the photoresist layer 74 may be formed of a negative tone photoresist. In some embodiments, the photoresist layer 74 includes an i-line photoresist, which typically includes a novolac resin prepared by reacting cresol, xylenol or other substituted phenols with formaldehyde. In some embodiments, the photoresist layer 180 is a polar component such as a polymer having hydroxyl or phenol groups, and multiple hydroxyl or phenol groups can attract or bond to amines or nitrogen-containing compounds that can diffuse out of the underlying dielectric material.

[0181] The photoresist layer 74 is exposed by applying a radiation beam (such as an electron beam). Next, the photoresist layer 74 is developed to form a patterned photoresist layer 74. Specifically, the photoresist layer 74 is patterned based on the received design layout. In some embodiments, an electron beam (e-beam) writer is used to pattern the first photoresist layer 74. Other patterning techniques that can be used in conjunction with or as an alternative to e-beam writing include ion beam writing and masked and unmasked photolithography. In addition, any other suitable patterning technique can be used. The patterned photoresist layer can include soft baking, mask alignment, exposure, post-exposure baking, developing photoresist, cleaning, drying (e.g., hard baking), other suitable processes, and / or combinations thereof.

[0182] Back to Figure 1BThe method 100 then proceeds to block S111, where the hard mask layer is patterned using the patterned photoresist layer as an etching mask. Fig.10 , using a patterned photoresist layer 72 (see Fig. 9 ) as an etching mask to pattern the hard mask layer 72, thereby transferring the pattern of the photoresist layer 74 to the hard mask layer 72. For example, the hard mask layer 72 can be etched using a dry (plasma) etching process, a wet etching process, and / or other etching methods. In some embodiments, the photoresist layer 74 can be partially or completely consumed during the etching of the hard mask layer 72. In some embodiments, any remaining portion of the patterned photoresist layer 74 can be stripped, thereby leaving the hard mask layer 72 on the protective layer 62.

[0183] Back to Figure 1B The method 100 then proceeds to block S112, where the liner and the first passivation layer, the second passivation layer, and the third passivation layer are etched through the patterned mask to form a recess R1 and expose the upper surface of the ultra-thick metal line. Fig.11 , the pad layer 42 and the first passivation layer 52, the second passivation layer 54, and the third passivation layer 56 are patterned. Specifically, the pad layer 42 and the first passivation layer 52, the second passivation layer 54, and the third passivation layer 56 are patterned using the patterned hard mask layer 72 as a mask to form a plurality of recesses R1 therein. This process may be referred to as pattern transfer because the pattern of the hard mask layer 72 is transferred to the pad layer 42 and the first passivation layer 52, the second passivation layer 54, and the third passivation layer 56. In some embodiments, patterning the pad layer 42 and the first passivation layer 52, the second passivation layer 54, and the third passivation layer 56 includes one or more etching processes to selectively remove a portion of the pad layer 42 until the ultra-thick metal line 36 is exposed. The etching process may include dry etching, wet etching, and / or other etching methods.

[0184] Back to Figure 1B The method 100 then proceeds to blocks S113 and S114, where the patterned mask is removed, and then an under bump metallurgy (UBM) layer is formed on the etch protection layer, scribes the sidewalls of the recess R1, and contacts the exposed portion of the ultra-thick metal line. Fig.12 In some embodiments of blocks S113 and S114, the hard mask layer 72 is peeled off from the protective layer 62 (see Fig.11). Then, an under bump metallurgy (UBM) layer 82 is formed on the protection layer 62 and scribes the sidewalls of the recess R1 and contacts the exposed portion of the ultra-thick metal line 36. In some embodiments, the under bump metallurgy layer 82 includes multiple layers of conductive materials, such as titanium layers, copper layers, and / or nickel layers. In some embodiments, the under bump metallurgy layer 82 can be formed by using an electroplating process such as electrochemical plating, but other formation processes such as sputtering, evaporation, or electroless plating processes can be used instead depending on the material to be used.

[0185] Back to Figure 1B The method 100 then proceeds to block S115 where a conductive pillar is formed on the under bump metallurgy layer. Fig.13 A photoresist layer (not shown) is formed on the UBM layer 82 and developed to form holes, and a plurality of holes expose the UBM layer 82 in the recess R1 and on the exposed portion of the ultra-thick metal line 36. The photoresist layer serves as a mold for the metal deposition process for the formation of the conductive pillar. Then, in some embodiments, a conductive material is deposited in the holes by evaporation, electroplating, or screen printing to form a conductive pillar bump 92 on the UBM layer 82, such as Fig.13 The conductive material includes any of various metals or metal alloys such as copper.

[0186] After removing the photoresist layer, the UBM layer 82 not covered by the conductive pillar bump 92 is removed by an etching process, and the UBM etching process etches the exposed portion of the UBM layer 82 down to the underlying protection layer 62. The remaining UBM layer 82 below the conductive pillar bump 92 is disposed on the sidewall of the recess R1, on a portion of the protection layer 62, and contacts the exposed portion of the ultra-thick metal line 36. In some embodiments, the conductive pillar bump 92 is a copper pillar.

[0187] refer to Fig.14 and Fig.15 . Fig.14 and Fig.15 is a cross-sectional view of a method of manufacturing an integrated circuit structure with a passivation layer at various stages according to some embodiments of the present disclosure. Fig.14 The operations for forming the wafer 102 having the integrated circuit structure prior to the structure shown in FIG. 1 are generally similar to those for forming the wafer 102 having the integrated circuit structure. Figures 2 to 8 The operation of the wafer 2 shown in FIG. 1 is the same, and reference may be made to the previous paragraphs for the relevant detailed description and such description is not provided again herein. Figures 2 to 8 The difference between the embodiments in the present invention is that the first passivation layer 152, the second passivation layer 154, the third passivation layer 156 and the protective layer 162 of the present embodiment have Figures 2 to 81 and 1 , and the first passivation layer 52, the second passivation layer 54, and the third passivation layer 56 and the protective layer 62 are shown in FIG. In some embodiments, the first passivation layer 152, the second passivation layer 154, and the third passivation layer 156 as a whole can be referred to as a passivation structure 150. In some embodiments, the passivation structure 150 extends from the liner layer 42 to the protective layer 162 without an interface.

[0188] like Fig.14 As shown in , the first passivation layer 152, the second passivation layer 154, and the third passivation layer 156 and the protective layer 162 have a curved profile in the cross-sectional view. In some embodiments, the thickness T5 of the passivation structure 150 is substantially greater than the thickness T6 of the protective layer 162. In some embodiments, the first passivation layer 152, the second passivation layer 154, and the third passivation layer 156 are more porous than the liner layer 42. In some embodiments, the first passivation layer 152 and the liner layer 42 form a discernible interface E2 therebetween.

[0189] In some embodiments, the liner layer 42 is formed of a dielectric material(s). In some embodiments, the thickness of the liner layer 42 is about to about In some embodiments, the thickness K4 of the first passivation layer 152 is greater than the thickness K3 of the liner layer 42. In some embodiments, the thickness of the first passivation layer 152 is within a range of about to about In some embodiments, the thickness of the second passivation layer 154 is about to about In some embodiments, the thickness of the third passivation layer 156 is about to about In some embodiments, the thickness T5 of the passivation structure 150 is substantially greater than the thickness T6 of the protection layer 162. The passivation structure 150 and the protection layer 162 form a composite passivation layer. The protection layer 162 is above the upper surface of the ultra-thick metal line 36 and thus does not fill in the gaps between the ultra-thick metal lines 36.

[0190] In some embodiments, after depositing the first passivation layer 152 or the second passivation layer 154, the high-density plasma chemical vapor deposition process for deposition is paused to reduce the temperature of the ultra-thick metal line 36. The wafer 102 (also referred to as a substrate) can be transferred from the high-density plasma chemical vapor deposition system 6 to a substrate such as Fig. 2036 to reduce the temperature of the ultra-thick metal line 36. In some embodiments, the liner layer 42 and the first and second passivation layers 152 and 154 may experience different stresses under the manufacturing process, and the multiple different stresses may generate cracks between the liner layer 42 and the second passivation layer 54. Therefore, the transfer can be used to cool the ultra-thick metal line 36 so as to prevent the first and second passivation layers 152 and 154 from cracking due to the increased temperature of the ultra-thick metal line 36.

[0191] In some embodiments, the wafer 102 may be transferred to the load lock chamber 332, 334 or to outside the multi-chamber processing system 300 to reduce the temperature of the ultra-thick metal line 36. Therefore, the transfer may be used to cool the ultra-thick metal line 36 so as to prevent the first passivation layer 152 or the second passivation layer 154 from being cracked due to the elevated temperature of the ultra-thick metal line 36.

[0192] In some embodiments, the wafer 102 may be transferred to the handling unit 421 connected to the multi-chamber processing system 300 or to the front-opening wafer cabin system 430 to reduce the temperature of the ultra-thick metal line 36. Therefore, the transfer may be used to cool the ultra-thick metal line 36 so as to prevent the first passivation layer 152 or the second passivation layer 154 from being cracked due to the increased temperature of the ultra-thick metal line 36.

[0193] exist Fig.15 In the embodiment of the present invention, an under bump metallurgy (UBM) layer 182 is formed on the protective layer 162 and contacts the ultra-thick metal line 36 from the recess of the passivation structure 50. A photoresist layer (not shown) is formed on the under bump metal layer 182 and is developed to form a hole, and the under bump metal hole exposes the under bump metal layer 182 and on the ultra-thick metal line 36. The photoresist layer acts as a mold for the metal deposition process for the formation of the conductive pillar. Then, in some embodiments, a conductive material is deposited by evaporation, electroplating, or screen printing to form a conductive pillar 192 on the under bump metal layer 182. After removing the photoresist layer, the under bump metal layer 182 not covered by the conductive pillar 192 is removed by an etching process, and the under bump metal etching process etches the exposed portion of the under bump metal layer 182 down to the underlying protective layer 162.

[0194] refer to Figures 16 to 18 . Figures 16 to 18 is a cross-sectional view of a method of manufacturing an integrated circuit structure with a passivation layer at various stages according to some embodiments of the present disclosure. It should be noted that Fig.16 The operations for forming the wafer 202 (also referred to as the substrate) having the integrated circuit structure prior to the structure shown in FIG. 1 are generally similar to those for forming the wafer 202 (also referred to as the substrate) having the integrated circuit structure. Figures 2 to 8The operation of the wafer 2 shown in FIG. 1 is the same, and reference may be made to the previous paragraphs for the relevant detailed description and such description is not provided again herein. In some embodiments, the operation of the wafer 2 shown in FIG. 1 may be omitted. Figures 8 to 13 The protective layer 62 is shown in FIG.

[0195] like Fig.16 As shown in FIG. 1 , a planarization process P6 is performed on the first passivation layer 52 , the second passivation layer 54 , the third passivation layer 56 and the protective layer 62 to form a horizontal upper surface S1 . Fig.16 In some embodiments, the first passivation layer 52, the second passivation layer 54, the third passivation layer 56 and the protective layer 62 are removed. In some embodiments, the first passivation layer 52, the second passivation layer 54, the third passivation layer 56 and the protective layer 62 are removed by a chemical mechanical polishing (CMP) process. In some embodiments, the second passivation layer 54, the third passivation layer 56 and the protective layer 62 are removed by an etching process. In some embodiments, the second passivation layer 54, the third passivation layer 56 and the protective layer 62 are removed by an etching process, such as a dry etching process using plasma. Plasma etching can use a source gas containing H2 and N2. In some embodiments, plasma etching is that fluorine compounds are not present in the source gas. In some embodiments, the etching process uses a gas flow rate in the range of from 5 ml / min to 1000 ml / min. In some embodiments, the etching process is performed at a pressure in the range of from 1 mTorr to 100 mTorr. In some embodiments, the etching process uses a plasma source at a power setting ranging from 200 W to 5000 W. In some embodiments, the etching process uses a bias power of up to 500 W. In some embodiments, the etching process is performed at a temperature ranging from 10° C. to 60° C.

[0196] like Fig.17 As shown in FIG. 1 , after the planarization process P6 is performed, other ultra-thick metal lines 236, liner layer 242, first passivation layer 252, second passivation layer 254, and third passivation layer 256, and protective layer 262 are formed on the upper surface S1. In some embodiments, the formation of ultra-thick metal lines 236, liner layer 242, first passivation layer 252, second passivation layer 254, and third passivation layer 256, and protective layer 262 is substantially the same as in FIG. Figures 2 to 82. The formation of the ultra-thick metal line 36, the liner layer 42, the first passivation layer 52, the second passivation layer 54, and the third passivation layer 56, and the protective layer 62 shown in FIG. 2 are the same. In some embodiments, the entirety of the first passivation layer 252, the second passivation layer 254, and the third passivation layer 256 may be referred to as a passivation structure 250. In some embodiments, the passivation structure 250 extends from the liner 242 to the protective layer 262 without an interface. In some embodiments, the thickness T7 of the passivation structure 250 is substantially greater than the thickness T8 of the protective layer 262. In some embodiments, the first passivation layer 252, the second passivation layer 254, and the third passivation layer 256 are more porous than the liner 242. In some embodiments, the first passivation layer 252 and the liner 242 form an interface therebetween.

[0197] In some embodiments, the thickness of the liner 242 is about to about In some embodiments, the thickness of the first passivation layer 252 is greater than the thickness of the liner 242. In some embodiments, the thickness of the first passivation layer 252 is within a range of about to about In some embodiments, the thickness of the second passivation layer 254 is about to about In some embodiments, the thickness of the third passivation layer 256 is about to about In some embodiments, the thickness of the passivation structure 250 is substantially greater than the thickness of the protection layer 262. The passivation structure 250 and the protection layer 262 form a composite passivation layer.

[0198] In some embodiments, after depositing the first passivation layer 252 or the second passivation layer 254, the high-density plasma chemical vapor deposition process for deposition is suspended to reduce the temperature of the ultra-thick metal line 236. The wafer 202 may be transferred from the high-density plasma chemical vapor deposition system 6 to a Fig. 20 336 is used to cool the ultra-thick metal line 236 to reduce the temperature of the ultra-thick metal line 236. In some embodiments, the liner 242 and the first and second passivation layers 252 and 254 may experience different stresses under the manufacturing process, and the multiple different stresses may generate cracks between the liner 242 and the first and second passivation layers 252 and 254. Therefore, the transfer can be used to cool the ultra-thick metal line 236 to prevent the first passivation layers 252 and 254 from cracking due to the increased temperature of the ultra-thick metal line 236.

[0199] In some embodiments, the wafer 202 may be transferred to the load lock chamber 332, 334 or to outside the multi-chamber processing system 300 to reduce the temperature of the ultra-thick metal line 236. Therefore, the transfer may be used to cool the ultra-thick metal line 236 so as to prevent the first passivation layer 252 or the second passivation layer 254 from being cracked due to the elevated temperature of the ultra-thick metal line 236.

[0200] In some embodiments, the wafer 202 may be transferred to the handling unit 421 connected to the multi-chamber processing system 300 or to the front-opening wafer cabin system 430 to reduce the temperature of the ultra-thick metal line 236. Therefore, the transfer may be used to cool the ultra-thick metal line 236 so as to prevent the first passivation layer 252 or the second passivation layer 254 from being cracked due to the increased temperature of the ultra-thick metal line 236.

[0201] like Fig.18 As shown in , an under bump metallurgy (UBM) layer 282 is formed on the protective layer 262 and contacts the ultra-thick metal line 236 from the recess of the passivation structure 250. A photoresist layer (not shown) is formed on the UBM layer 282 and is developed to form a hole, and the UBM hole exposes the UBM layer 282 and on the ultra-thick metal line 236. The photoresist layer acts as a mold for the metal deposition process for the formation of the conductive column. Then, in some embodiments, a conductive material is deposited by evaporation, electroplating, or screen printing to form a conductive column 292 on the UBM layer 282. After removing the photoresist layer, the UBM layer 282 not covered by the conductive column 292 is removed by an etching process, and the UBM etching process etches the exposed portion of the UBM layer 282 down to the underlying protective layer 262.

[0202] Based on the aforementioned embodiments, it can be seen that the present disclosure provides advantages in manufacturing integrated circuit structures. However, it should be understood that other embodiments may provide additional advantages, and not all advantages must be disclosed herein. One advantage is that the passivation structure between the liner and the protective layer on the ultra-thick metal does not have an interface therebetween, so that the entirety of the passivation structure can experience comparable stresses during the manufacturing process, thereby reducing the risk of cracks occurring in the passivation structure.

[0203] Another advantage is that after the passivation layer is deposited on the liner by the high density plasma chemical vapor deposition process, the process on the substrate can be paused to reduce the temperature of the ultra-thick metal line. In some embodiments, the liner and the passivation layer can experience different stresses during the manufacturing process, and the multiple different stresses can cause cracks between the liner and the first passivation layer. Therefore, the pause can be used to cool the ultra-thick metal line below the liner to prevent the passivation layer and the liner from cracking due to the elevated temperature of the ultra-thick metal line.

[0204] In some embodiments of the present disclosure, a method for forming a passivation layer for an integrated circuit structure includes forming a metal line on an interconnect structure, an under bump metal interconnect structure formed above a transistor; depositing a liner layer on the metal line using a first high density plasma chemical vapor deposition (HDPVCD) process without radio frequency bias power; depositing a first passivation layer on the liner layer using a second HDPVCD process with radio frequency bias power; and depositing a second passivation layer in contact with an upper surface of the first passivation layer using a third HDPVCD process with radio frequency bias power.

[0205] In some embodiments, the second HDPCVD process and the third HDPCVD process have different deposition to sputtering ratios.

[0206] In some embodiments, the second HDPCVD process has a deposition to sputtering ratio that is higher than a deposition to sputtering ratio of the third HDPCVD process.

[0207] In some embodiments, the method further includes: depositing a third passivation layer in contact with an upper surface of the second passivation layer using a fourth high density plasma chemical vapor deposition process with a radio frequency bias power.

[0208] In some embodiments, depositing the third passivation layer is performed such that a gap between the plurality of metal lines is filled.

[0209] In some embodiments, the third HDPCVD process and the fourth HDPCVD process have different deposition and sputtering ratios.

[0210] In some embodiments, the third HDPCVD process has a deposition to sputtering ratio that is higher than a deposition to sputtering ratio of the fourth HDPCVD process.

[0211] In some embodiments, the method further includes: forming a protection layer on the third passivation layer using a different material than the third passivation layer.

[0212] In some embodiments, the method further includes: forming an under bump metallurgy layer, the under bump metallurgy layer extending through the second passivation layer, the first passivation layer, and the liner layer to one of the plurality of metal lines; and forming a conductive column bump on the under bump metallurgy layer.

[0213] In some embodiments of the present disclosure, a method for forming a passivation layer for an integrated circuit structure includes forming a metal line on an interconnect structure, wherein an under-bump metal interconnect structure is formed above a transistor; depositing a liner oxide layer in contact with the metal line; forming a passivation oxide structure in contact with an upper surface of the liner layer, wherein the liner layer is more porous than any location in the passivation oxide structure; and forming a protective nitride layer in contact with the upper surface of the passivation oxide structure.

[0214] In some embodiments, the step of forming a passivation oxide structure includes: forming a first passivation layer on the liner oxide layer using a first high-density plasma chemical vapor deposition process with a first non-zero RF bias power; and forming a second passivation layer on the first passivation layer using a second high-density plasma chemical vapor deposition process with a second non-zero RF bias power.

[0215] In some embodiments, the first non-zero RF bias power is different from the second non-zero RF bias power.

[0216] In some embodiments, the second non-zero RF bias power is greater than the first non-zero RF bias power.

[0217] In some embodiments, the step of forming the passivation oxide structure includes forming a third passivation layer on the second passivation layer using a third high density plasma chemical vapor deposition process having a third non-zero RF bias power.

[0218] In some embodiments, the third non-zero RF bias power is different from the second non-zero RF bias power.

[0219] In some embodiments, the third non-zero RF bias power is greater than the second non-zero RF bias power.

[0220] In some embodiments, the liner oxide layer is deposited in a high density plasma chemical vapor deposition chamber with an RF bias generator turned off.

[0221] In some embodiments of the present disclosure, the method includes an interconnect structure, a metal line, a liner layer, a passivation structure, and a nitride layer. The interconnect structure is on the transistor. The metal line extends along the upper surface of the interconnect structure. The liner layer is on the metal line. The passivation structure is on the liner. The nitride layer is on the passivation structure, wherein the passivation structure extends continuously from the liner layer to the nitride layer without an interface.

[0222] In some embodiments, the integrated circuit structure further comprises: an under bump metallurgy layer and a conductive pillar. The under bump metallurgy layer extends through the nitride layer, the passivation structure, and the pad layer to one of the plurality of metal lines. The conductive pillar is on the under bump metallurgy layer.

[0223] In some embodiments, a porosity of the passivation structure is less than a porosity of the liner layer.

[0224] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming an integrated circuit structure, characterized in that: The following steps are involved: forming a metal line on an interconnect structure above the transistor; Depositing a liner layer on the metal line using a first high density plasma chemical vapor deposition process without RF bias power; Depositing a first passivation layer on the liner layer using a second high density plasma chemical vapor deposition process with radio frequency bias power; as well as A second passivation layer contacting an upper surface of the first passivation layer is deposited using a third high density plasma chemical vapor deposition process with radio frequency bias power.

2. The method according to claim 1, characterized in that The second HDPCVD process and the third HDPCVD process have different deposition and sputtering ratios.

3. The method according to claim 1, characterized in that The second HDPCVD process has a deposition to sputtering ratio that is higher than a deposition to sputtering ratio of the third HDPCVD process.

4. The method according to claim 1, characterized in that Also includes: A third passivation layer contacting an upper surface of the second passivation layer is deposited using a fourth high density plasma chemical vapor deposition process with radio frequency bias power.

5. The method according to claim 4, characterized in that Depositing the third passivation layer is performed such that a gap between the metal lines is filled.

6. The method according to claim 4, characterized in that The third HDPCVD process and the fourth HDPCVD process have different deposition and sputtering ratios.

7. The method according to claim 4, characterized in that The third HDPCVD process has a deposition to sputtering ratio that is higher than a deposition to sputtering ratio of the fourth HDPCVD process.

8. The method according to claim 4, characterized in that Also includes: A protection layer is formed on the third passivation layer using a different material than the third passivation layer.

9. The method according to claim 1, characterized in that: Also includes: forming an under bump metallurgy layer, the under bump metallurgy layer extending through the second passivation layer, the first passivation layer, and the pad layer to one of the metal lines; and A conductive column bump is formed on the under-bump metallization layer.

10. A method for forming an integrated circuit structure, characterized in that: The following steps are involved: forming a metal line on an interconnect structure above the transistor; depositing a liner oxide layer in contact with the metal line; forming a passivating oxide structure in contact with an upper surface of the liner oxide layer, wherein the liner oxide layer is more porous than any location in the passivating oxide structure; as well as A protective nitride layer is formed in contact with an upper surface of the passivation oxide structure.

11. The method according to claim 10, characterized in that The steps of forming the passivation oxide structure include: forming a first passivation layer on the liner oxide layer using a first high density plasma chemical vapor deposition process having a first non-zero RF bias power; and A second passivation layer is formed on the first passivation layer using a second high density plasma chemical vapor deposition process with a second non-zero RF bias power.

12. The method according to claim 11, characterized in that The first non-zero RF bias power is different from the second non-zero RF bias power.

13. The method according to claim 11, characterized in that The second non-zero RF bias power is greater than the first non-zero RF bias power.

14. The method according to claim 11, characterized in that The steps of forming the passivation oxide structure include: A third passivation layer is formed on the second passivation layer using a third high density plasma chemical vapor deposition process with a third non-zero RF bias power.

15. The method according to claim 14, characterized in that The third non-zero RF bias power is different from the second non-zero RF bias power.

16. The method according to claim 14, characterized in that The third non-zero RF bias power is greater than the second non-zero RF bias power.

17. The method according to claim 10, characterized in that The liner oxide layer is deposited in a high density plasma chemical vapor deposition chamber with a radio frequency bias generator turned off.

18. An integrated circuit structure, characterized in that: Include: an interconnect structure located on a transistor; A plurality of metal lines extending along an upper surface of the interconnect structure; a liner layer located on the plurality of metal lines; a passivation structure located on the liner layer, wherein a porosity of the passivation structure is less than a porosity of the liner layer; as well as A nitride layer is located on the passivation structure, wherein the passivation structure continuously extends from the liner layer to the nitride layer without an interface.

19. The integrated circuit structure according to claim 18, characterized in that: Also includes: an under bump metallurgy layer extending through the nitride layer, the passivation structure and the liner layer to one of the plurality of metal lines; and A conductive column is located on the under-bump metal layer.

20. The integrated circuit structure according to claim 19, characterized in that: The material of the passivation structure is the same as that of the liner layer.

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