Semiconductor device and method for manufacturing the same

Abstract

The present disclosure relates to semiconductor devices and methods for manufacturing the same. One method includes forming a semiconductor fin protruding above a top surface of an isolation region. The isolation region extends into a semiconductor substrate. A portion of the semiconductor fin is etched to form a trench that extends below a bottom surface of the isolation region and into the semiconductor substrate. The method further includes: filling the trench with a first dielectric material to form a first fin isolation region; recessing the first fin isolation region to form a first recess; and filling the first recess with a second dielectric material. The first dielectric material and the second dielectric material combine to form a second fin isolation region.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and methods of manufacturing the same. Background Art

[0002] Technological advances in integrated circuit (IC) materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous ones. Over the course of IC evolution, functional density (e.g., the number of interconnected devices per chip area) has generally increased while geometry size has decreased. This scaling process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] Such reductions have also increased the complexity of integrated circuit processing and manufacturing, and similar advances in integrated circuit processing and manufacturing are needed to achieve these advances. For example, fin field-effect transistors (FinFETs) have been introduced to replace planar transistors. The structure of FinFETs and methods for manufacturing FinFETs are under development.

[0004] The formation of a FinFET generally includes forming a long semiconductor fin and a long gate stack, and then forming an isolation region to cut the long semiconductor fin and the long gate stack into shorter portions so that the shorter portions can serve as the fin and gate stack of the FinFET. Summary of the Invention

[0005] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a semiconductor fin protruding above a top surface of an isolation region, wherein the isolation region extends into a semiconductor substrate; etching a portion of the semiconductor fin to form a trench, wherein the trench extends below a bottom surface of the isolation region and extends into the semiconductor substrate; filling the trench with a first dielectric material to form a first fin isolation region; recessing the first fin isolation region to form a first groove; and filling the first groove with a second dielectric material, wherein the first dielectric material and the second dielectric material combine to form a second fin isolation region.

[0006] According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: a semiconductor substrate; an isolation region extending into the semiconductor substrate; a dielectric region comprising: a lower portion having a first gap therein; and an upper portion having a second gap therein, wherein the first gap is separated from the second gap by a bottom portion of the upper portion of the dielectric region.

[0007] According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: a substrate; an isolation region extending into the substrate; a semiconductor fin extending upward from a top surface of the isolation region; a first epitaxial semiconductor region and a second epitaxial semiconductor region extending into the semiconductor fin; a first dielectric region, the first dielectric region being laterally located between the first epitaxial semiconductor region and the second epitaxial semiconductor region; and a second dielectric region above the first dielectric region, wherein the second dielectric region includes a U-shaped bottom in contact with a top surface of the first dielectric region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1-4 , 5A, 5B, 6, 7A, 7B, 8A, 8B, and 9-15 illustrate perspective, cross-sectional, and top views of intermediate stages in forming isolation regions and fin field effect transistors (FinFETs) according to some embodiments.

[0010] Figure 16A A top view of a device region is shown in accordance with some embodiments.

[0011] Figure 16B A perspective view of a device region is shown in accordance with some embodiments.

[0012] Figure 17 A process flow for forming isolation regions and FinFETs is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, represent a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature relative to another element or feature(s) illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0015] According to some embodiments, isolation regions for cutting fins and gate stacks, fin field effect transistors (FinFETs), and methods for forming the same are provided. According to some embodiments of the present disclosure, gate isolation regions and fin isolation regions are formed, then recessed, and dielectric material is filled into the resulting grooves. Through this process, the gaps generated in the gate isolation regions and fin isolation regions can be sealed. According to some illustrated embodiments, the formation of FinFETs is used as an example to explain the concepts of the present disclosure. Other types of transistors (e.g., planar transistors, gate-all-around (GAA) transistors, etc.) can also use embodiments of the present disclosure to cut corresponding active regions and gate stacks. The embodiments discussed herein are used to provide examples to enable the practice or use of the subject matter of the present disclosure, and those skilled in the art will readily understand modifications that remain within the contemplated scope of the different embodiments. Throughout the various views and illustrative embodiments, similar reference numerals are used to indicate similar elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0016] Figure 1-4 , 5A, 5B, 6, 7A, 7B, 8A, 8B and 9-15 show perspective views, cross-sectional views and top views of intermediate stages of forming isolation regions and fin field effect transistors (FinFETs) according to some embodiments. The corresponding processes are also schematically shown in Figure 17 The process flow shown.

[0017] Figure 1 1 shows a perspective view of an initial structure. The initial structure includes a wafer 10, which also includes a substrate 20. The substrate 20 may be a semiconductor substrate, which may be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. The substrate 20 may be doped with p-type or n-type impurities. An isolation region 22 such as a shallow trench isolation (STI) region may be formed to extend from the top surface of the substrate 20 into the substrate 20. The corresponding process is shown as follows. Figure 17Process 202 in process flow 200 is shown. The portion of substrate 20 between adjacent STI regions 22 is referred to as semiconductor strip 24. According to some embodiments of the present disclosure, semiconductor strip 24 is a portion of the original substrate 20, and thus the material of semiconductor strip 24 is the same as the material of substrate 20. According to alternative embodiments of the present disclosure, semiconductor strip 24 is a replacement strip formed by etching the portion of substrate 20 between STI regions 22 to form a groove, and performing an epitaxial process to re-grow another semiconductor material in the groove. Thus, semiconductor strip 24 is formed of a semiconductor material different from that of substrate 20. According to some embodiments, semiconductor strip 24 is formed of Si, SiP, SiC, SiPC, SiGe, SiGeB, Ge, or a III-V compound semiconductor such as InP, GaAs, AlAs, InAs, InAlAs, InGaAs, or the like.

[0018] STI regions 22 may include a liner oxide (not shown), which may be a thermal oxide formed by thermally oxidizing a surface layer of substrate 20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), chemical vapor deposition (CVD), etc. STI regions 22 may also include a dielectric material overlying the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, etc.

[0019] Figure 2 The formation of dielectric dummy strips 25 is shown, which can be formed by etching one of the semiconductor strips 24 to form a groove and then filling the groove with dielectric material. The corresponding process is shown as Figure 17 The process flow 200 is shown as process 204. The dielectric material can be formed of or include a high-k dielectric material such as silicon nitride. In addition, the material of the dielectric dummy strips 25 is selected so that it has a high etch selectivity relative to the material of the subsequently formed dummy gate stack and the material of the STI regions 22 (e.g., silicon oxide). The bottom surface of the dielectric dummy strips 25 can be higher than, flush with, or lower than the bottom surface of the STI regions 22.

[0020] Reference Figure 3 , the STI region 22 is recessed. The tops of the semiconductor strips 24 and the dielectric dummy strips 25 protrude above the top surface 22A of the rest of the STI region 22 to form protruding fins 24' and dummy fins 25', respectively. The corresponding process is shown as Figure 17Process 206 in process flow 200 is shown. Etching can be performed using a dry etching process, wherein an etching gas such as a mixture of HF3 and NH3 can be used. According to an alternative embodiment of the present disclosure, recessing of STI region 22 is performed using a wet etching process. The etching chemical can include, for example, an HF solution.

[0021] In the above embodiments, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Typically, double patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a smaller pitch than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fins.

[0022] Further references Figure 3 , forming dummy gate stacks 30 and gate spacers on the top surfaces and sidewalls of the (protruding) fins 24' and dummy fins 25'. The corresponding process is shown as Figure 17 Process 208 in the process flow 200 shown. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 on the dummy gate dielectric 32. The dummy gate electrode 34 may be formed, for example, using polysilicon or amorphous silicon, and other materials may also be used. Each dummy gate stack 30 may also include one (or more) hard mask layers 36 on the dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or multiple layers thereof. The dummy gate stack 30 may span one or more of the protruding fin 24' and the dummy fin 25' and / or the STI region 22. The dummy gate stack 30 also has a longitudinal direction that is perpendicular to the longitudinal direction of the protruding fin 24' and the dummy fin 25'.

[0023] Next, gate spacers 38 are formed on the sidewalls of the dummy gate stack 30. According to some embodiments of the present disclosure, gate spacers 38 are formed of a dielectric material such as silicon nitride (SiN), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), etc., and may have a single-layer structure or a multi-layer structure including multiple dielectric layers. The width of gate spacers 38 may be in a range between approximately 1 nm and approximately 3 nm.

[0024] According to some embodiments of the present disclosure, an etching process (hereinafter referred to as source / drain recess) is performed to etch the portion of the protruding fin 24' not covered by the dummy gate stack 30 and the gate spacer 38, so as to produce Figure 4 The corresponding process is shown as Figure 17 Process 210 of process flow 200 is shown. The recess can be anisotropic, so that the portion of the protruding fin 24' directly below the dummy gate stack 30 and gate spacer 38 is protected and not etched. According to some embodiments, the top surface of the recessed semiconductor strip 24 can be lower than the top surface 22A of the STI region 22. The space left by the etched portion of the protruding fin 24' is referred to as a recess 40. During this etching process, the dielectric dummy fin 25' is not etched. For example, a mixture of NF3 and NH3, a mixture of HF and NH3, etc. can be used to etch the protruding fin 24'.

[0025] Next, epitaxial regions (source / drain regions) 42 are formed by selectively growing semiconductor material from the recess 40, thereby obtaining Figure 5A The corresponding process is shown as Figure 17 Process 212 in the process flow 200 shown. According to some embodiments, the epitaxial region 42 includes silicon germanium, silicon, carbon silicon, etc. Depending on whether the FinFET to be produced is a p-type FinFET or an n-type FinFET, p-type or n-type impurities can be in-situ doped during the epitaxy process. For example, when the FinFET to be produced is a p-type FinFET, silicon germanium boron (SiGeB), SiB, GeB, etc. can be grown. Conversely, when the FinFET to be produced is an n-type FinFET, silicon phosphide (SiP), silicon carbon phosphide (SiCP), etc. can be grown. According to an alternative embodiment of the present disclosure, the epitaxial region 42 is formed of a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, a combination thereof, or multiple layers thereof. After the epitaxial region 42 completely fills the recess 40, the epitaxial region 42 begins to expand horizontally and a facet can be formed.

[0026] Figure 5B 1 shows the formation of source / drain regions 42 according to alternative embodiments of the present disclosure. According to these embodiments, Figure 4 The protruding fin 24' is shown not recessed, and the epitaxial region 41 is grown on the protruding fin 24'. The material of the epitaxial region 41 can be similar to Figure 5AThe epitaxial semiconductor material 42 shown is of a material that depends on whether the resulting FinFET is a p-type or n-type FinFET. Thus, the source / drain regions 42 include the protruding fins 24' and the epitaxial regions 41. An implantation process may (or may not) be performed to implant n-type or p-type impurities.

[0027] Figure 6 4 shows a perspective view of the structure after forming a contact etch stop layer (CESL) 46 and an interlayer dielectric (ILD) 48. The corresponding process is shown as Figure 17 Process 214 in the process flow 200 is shown. CESL 46 can be formed of silicon nitride, silicon carbonitride, or the like. For example, CESL 46 can be formed using a conformal deposition method such as ALD or CVD. ILD 48 can include a dielectric material formed using, for example, FCVD, spin coating, CVD, or another deposition method. ILD 48 can also be made of an oxygen-containing dielectric material, which can be a silicon oxide-based material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like. A planarization process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process is performed to make the top surfaces of ILD 48, dummy gate stack 30, and gate spacers 38 flush with each other.

[0028] Figure 7A FIG. 1 shows a plan view (top view) of a portion of wafer 10 after forming gate isolation region 50, which is sometimes referred to as a cut-poly (CPO) region. The corresponding process is shown as follows. Figure 17 The process 216 in the process flow 200 is shown. The corresponding process may also be referred to as a CPO process. The protruding fin 24', the dielectric dummy fin 25', the dummy gate stack 30 and the gate spacer 38 are shown. The protruding fin 24' may be directly below the dummy gate stack 30, and the source / drain region 42 is formed between the dummy gate stack 30. It should be understood that the source / drain regions 42 grown from adjacent protruding fins 24' can be merged, but for clarity of the drawings, they are not shown in FIG. Figure 7A The protruding fins 24 ′ are elongated strips having a longitudinal direction in the X direction. The dummy gate stacks 30 are formed as elongated strips having a longitudinal direction in the Y direction.

[0029] Figure 7B Shown from Figure 7A7B-7B in FIG. 7B-7B. The gate isolation region 50 is formed to divide the long dummy gate stack 30 into shorter portions so that the shorter dummy gate stack 30 can serve as a dummy gate stack for a different FinFET. It should be understood that in the example embodiment shown, the gate isolation region 50 is formed before the replacement gate stack is formed. In other embodiments, the gate isolation region 50 may also be formed after the replacement gate stack is formed, and thus the replacement gate stack is cut by the gate isolation region 50. According to some embodiments, the formation of the gate isolation region 50 includes forming an etch mask, such as a patterned photoresist, in which the gate isolation region 50 ( Figure 7A The regions of the dummy gate stack 30 are exposed through the openings in the etch mask. The openings in the etch mask are located directly above portions of the dummy fins 25'. The portions of the dummy gate stack 30 exposed through the etch mask are then etched. Figure 7B It can be seen that the etching can be stopped after the dummy fin 25 ′ is exposed. Next, the etch mask is removed, and a dielectric material is deposited to fill the opening in the dummy gate stack 30 .

[0030] According to some embodiments, the deposition of the dielectric material is performed using a conformal deposition method such as atomic layer deposition (ALD) (which may be plasma enhanced ALD (PEALD), thermal ALD, etc.). The dielectric material may be formed of SiN, SiO2, SiOC, SiOCN, etc., or a combination thereof, or include SiN, SiO2, SiOC, SiOCN, etc., or a combination thereof. According to some embodiments, the dielectric material includes SiN, and the deposition is performed using a process gas including dichlorosilane (SiH2Cl2) and ammonia (NH3). Hydrogen (H2) may also be added. The deposition process may be performed using PEALD at a temperature between about 450°C and about 650°C. After the deposition process, a planarization process such as a CMP process or a mechanical grinding process is performed. The remaining portion of the dielectric material is the gate isolation region 50. A gap 51 may be formed in the middle of the gate isolation region, such as Figure 7A and 7B The width of the gap 51 may be in the range between about 0.5 nm and about 2 nm.

[0031] Figure 8A FIG. 5 shows a plan view of the formation of the fin isolation region 54, which is sometimes referred to as the cut poly on OD edge (CPODE) region. The corresponding process is shown as Figure 17The process 218 in the process flow 200 is shown. The corresponding process may also be referred to as a CPODE process. The fin isolation region 54 divides the long protruding fin 24' into shorter parts, so that the shorter protruding fin 24' can serve as the active region (e.g., channel) of different FinFETs. The fin isolation region 54 can also separate the source / drain regions of adjacent FinFETs from each other.

[0032] Figure 8B Shown from Figure 8A 8B-8B in FIG. 5 . According to some embodiments, the formation of the fin isolation region 54 includes forming an etch mask and etching the dummy gate stack 30 using the etch mask. In the etching process, the dummy gate stack 30 is first anisotropically etched until the protruding fin 24' below is exposed. The etching can stop on the STI region 22. The protruding fin 24' is then etched, and the etching continues down into the semiconductor strip 24 below and further down into the underlying main portion of the semiconductor substrate 20. The STI region 22 is used as an etching mask to define the pattern of the resulting opening. Next, a dielectric material is deposited into the resulting opening formed by the etching process, followed by a planarization process to remove excess dielectric material. The remaining dielectric material forms the gate isolation region 54.

[0033] According to some embodiments, dielectric mask 52 is formed (before or after forming fin isolation region 54) to protect ILD 48. Formation of dielectric mask 52 may include recessing ILD 48 and filling the resulting recess with a dielectric material. Dielectric mask 52 may be formed of or include SiN, SiO2, SiOC, SiOCN, or the like. The material of dielectric mask 52 may be the same as or different from the material of fin isolation region 54.

[0034] According to some embodiments, the deposition of the dielectric material of the isolation region 54 is performed using a conformal deposition process such as ALD (which may be PEALD, thermal ALD, etc.). The dielectric material may be formed of or include SiN, SiO2, SiOC, SiOCN, etc., or a combination thereof. The fin isolation region 54 may be formed of a homogenous material or may have a composite structure including more than one layer. For example, Figure 8BThe fin isolation region 54 is shown to include a dielectric liner 54', which may be formed of, for example, silicon oxide. According to some embodiments, the dielectric material of the isolation region 54 includes SiN, and the deposition is performed using a process gas including dichlorosilane and ammonia. Hydrogen (H2) may or may not be added. The deposition process may be performed using PEALD at a temperature between about 450°C and about 650°C. Figure 8A and 8B As shown, a gap 55 may be formed in the middle of the fin isolation region 54. The width of the gap 55 may be in the range between about 0.5 nm and about 2 nm. Figure 8B , top surface 22A and bottom surface 22B of the STI region are marked to illustrate the location of STI region 22 .

[0035] Figure 9 and Figure 10 The formation of a replacement gate stack 62 is shown. Figure 8B The dummy gate stack 30 is shown, and a trench 56 is formed, as shown Figure 9 The corresponding process is shown as Figure 17 The process 220 in the process flow 200 is shown. Next, Figure 10 As shown, a (replacement) gate stack 62 is formed, which includes a gate dielectric layer 58 and a gate electrode 60. The corresponding process is shown as Figure 17Process 222 in the process flow 200 shown. The formation of the gate stack 62 includes forming / depositing multiple layers and then performing a planarization process such as a CMP process or a mechanical grinding process. According to some embodiments of the present disclosure, each gate dielectric layer 58 includes an interfacial layer (IL) as its lower portion. The IL is formed on the exposed surface of the protruding fin 24'. The IL may include an oxide layer such as a silicon oxide layer formed by the following process: a thermal oxidation process or a chemical oxidation process for oxidizing the surface layer of each protruding fin 24', or a deposition process. Each gate dielectric layer 58 may also include a high-k dielectric layer formed above the IL. The high-k dielectric layer may include a high-k dielectric material, for example, HfO2, ZrO2, HfZrOx, HfSiOx, HfSiON, ZrSiOx, HfZrSiOx, Al2O3, HfAlOx, HfAlN, ZrAlOx, La2O3, TiO2, Yb2O3, silicon nitride, etc. The dielectric constant (k value) of the high-k dielectric material is higher than 3.9 and can be higher than about 7.0. The high-k dielectric layer can be formed as a conformal layer and extends over the sidewalls of the protruding fin 24' and the sidewalls of the gate spacer 38. The gate dielectric layer 58 also extends over the top surface and sidewalls of some portions of the dielectric dummy fin 25', except that if the IL is formed by thermal oxidation, no IL is formed on the dielectric dummy fin 25'. According to some embodiments of the present disclosure, the high-k dielectric layer in the gate dielectric layer 58 is formed using ALD, CVD, or the like.

[0036] A gate electrode 60 is formed on top of the gate dielectric layer 58 and fills the remainder of the trench left by the removal of the dummy gate stack. The sub-layers in the gate electrode 60 are not shown individually, however, they can be distinguished from each other due to their different compositions. Deposition of at least the lower sub-layers can be performed using a conformal deposition method such as ALD or CVD so that the thickness of the vertical portion and the thickness of the horizontal portion of the gate electrode 60 (and each sub-layer) are substantially equal to each other.

[0037] The sublayers in the gate electrode 60 may include, but are not limited to, a titanium silicon nitride (TiSN) layer, a tantalum nitride (TaN) layer, a titanium nitride (TiN) layer, a titanium aluminum (TiAl) layer, an additional TiN and / or TaN layer, and a fill metal region. Hereinafter, the gate electrode 60 will be referred to as the metal gate 60. Some of these sublayers define the work function of the respective FinFETs. In addition, the metal layer of the p-type FinFET and the metal layer of the n-type FinFET may be different from each other so that the work function of the metal layer is suitable for the corresponding p-type or n-type FinFET. The fill metal may include tungsten, cobalt, etc.

[0038] Figure 11It is shown that the replacement gate stack 62 is recessed, for example by an etching process, thereby forming the top of the trench 56 again. The corresponding process is shown as Figure 17 Process 224 in process flow 200 is shown.

[0039] Next, if Figure 12 As shown, a dielectric hard mask 66 is formed, which is sometimes referred to as a self-aligned contact (SAC) fill layer 66. The corresponding process is shown as Figure 17 Process 226 in the process flow 200 shown. The dielectric hard mask 66 can be formed of or include SiN, SiO2, SiOC, SiOCN, etc. or a combination thereof. According to some embodiments, the dielectric material includes SiN and the deposition is performed using a process gas including dichlorosilane and ammonia. Hydrogen (H2) may or may not be added. The deposition process can be performed using PEALD at a temperature between about 350°C and about 550°C. After the deposition process, a planarization process is performed. The remainder of the dielectric material is the dielectric hard mask 66. A gap 67 can be formed. The width of the gap 67 can be in the range between about 0.5 nm and about 2 nm. When in a process such as Figure 8A When viewed in the top view of the wafer 10 as shown, the dielectric hard mask 66 is located in the same location as the dummy gate stack 30 as shown, and the gap 67 is located midway between the gate spacers 38 on opposite sides of the dummy gate stack 30 .

[0040] Process conditions such as temperature, deposition rate, etc. may be adjusted to make the dielectric hard mask 66, the fin isolation region 54, and the gate isolation region 50 different from each other. For example, according to some embodiments, the density of the fin isolation region 54 may be higher than the density of the dielectric hard mask 66, and the density of the dielectric hard mask 66 may be further higher than the density of the gate isolation region 50.

[0041] Reference Figure 13 , the dielectric hard mask 66 and the fin isolation region 54 are recessed to form recesses 68A and 68B, respectively, which are collectively referred to as recesses 68. The corresponding process is shown as Figure 17 Process 228 in the illustrated process flow 200 can also be recessed in the gate isolation region 50 that is not in the illustrated plane. The hard mask 52 can be removed by the recessing process. According to some embodiments, the recessing of the dielectric hard mask 66 and the fin isolation region 54 is performed in a common etching process. According to alternative embodiments, the recessing of the dielectric hard mask 66 and the recessing of the fin isolation region 54 are performed in separate etching processes. According to some embodiments, the liner 54' is not recessed. According to alternative embodiments, the liner 54' is recessed, for example, liner 54'S illustrates a possible position of the top surface of the liner 54' when the liner 54' is recessed.

[0042] According to some embodiments, the bottom of the fin isolation region 54 is at a controlled level, for example, at a level below the dashed line 57, where the distance D1 between the dashed line 57 and the top surface of the protruding fin 24' is selected to be less than about 50 nm, or less than about 20 nm. The bottom of the recess 68A can also be located at any level: below the level of the top surface of the replacement gate stack 62, between (or flush with) the top surface of the replacement gate stack 62 and the top surface of the protruding fin 24', or below the level of the top surface of the protruding fin 24'. The fin isolation region 54 can be recessed below the dielectric hard mask 66. Recess 68A can also be deeper than recess 68B. After the recess, gaps 55 and 67 may still exist.

[0043] The etching process may include a wet etching process or a dry etching process. For example, when a dry etching process is used, an etching gas containing carbon and fluorine (based on C x F y ), for example, CF4, C2H6, and the like. The temperature may be in a range between about 25°C and about 300°C. The etching duration may be in a range between about 5 seconds and about 300 seconds. When a wet etching process is used, H3PO4 may be used. During etching, the temperature may be in a range between about 150°C and about 200°C. The etching duration may be in a range between about 50 seconds and about 2000 seconds. The desired depth of the recess 68 can be controlled by controlling the etching time. According to some embodiments, the etching rate of the fin isolation region 54 may be greater than the etching rate of the dielectric hard mask 66, and the etching rate of the dielectric hard mask 66 may be further greater than the etching rate of the gate isolation region 50.

[0044] During the etching process, the ILD 48 and the gate spacers 38 are not intended to be etched. For example, the etching selectivity ER 50-54-66 / ER 48 and etch selectivity ER 50-54-66 / ER 38 May be greater than 10, where ER 48 is the etch rate of ILD 48, ER 38 is the etching rate of the gate spacer 38, and ER 50-54-66is the etch rate of the gate isolation region 50, the fin isolation region 54, and the dielectric hard mask 66. Therefore, the ILD 48 and the gate spacers 38 are generally not etched. According to some embodiments, it may also happen that the gate spacers 38 are etched from their sidewalls due to the recessing of the dielectric hard mask 66, and because the gate spacers 38 are thin, the gate spacers 38 are also recessed. In these embodiments, the top surface of the recessed gate spacers 38 may be lower than the top surface of the ILD 48, as shown at 38TS. The top surface 38TS may be sloped. The gate spacers 38 on opposite sides of the replacement gate stack 62 may be symmetrical or asymmetrical.

[0045] Figure 14 The formation of dielectric regions 70A and 70B (collectively referred to as dielectric regions 70) is shown. The corresponding process is shown as Figure 17 In the process 230 of the process flow 200 shown in FIG. , gaps 71A and 71B (collectively referred to as gaps 71) are formed in the dielectric regions 70A and 70B, respectively. Figure 16A and 16B ) is formed on top of the recessed gate isolation region 50, and dielectric region 70C and the underlying gate isolation region 50 may have a profile similar to dielectric region 70B and dielectric hard mask 66. Dielectric regions 70A, 70B, and 70C may be formed in a common deposition process, which may include a conformal deposition process such as ALD or CVD, followed by a common planarization process. Dielectric region 70A and the underlying remaining fin isolation region 54 combine to form isolation region 75.

[0046] The width of gaps 71A and 71B may be in a range between about 0.5 nm and about 2 nm. According to some embodiments, dielectric region 70 is formed of or includes a material selected from SiN, SiO2, SiOC, SiOCN, or the like, or a combination thereof. Furthermore, the material of dielectric region 70 may be the same as or different from the material of the underlying dielectric hard mask 66, gate isolation region 50, and / or fin isolation region 54. The interfaces (e.g., labeled 54S and 66S) between dielectric region 70 and the underlying dielectric hard mask 66, gate isolation region 50, and / or fin isolation region 54 may be distinguishable or indistinguishable (e.g., in a transmission electron microscope (TEM) image), regardless of whether they are formed of the same material or different materials. For example, when the dielectric hard mask 66 , the gate isolation region 50 , and the fin isolation region 54 are formed of SiN, surface layers of the dielectric hard mask 66 , the gate isolation region 50 , and the fin isolation region 54 may be oxidized by natural oxidation to form a thin SiON interface layer. Figure 14 Example interface layers are shown, also labeled 66S and 54S. According to some embodiments, interface layers 66S and 54S have a U-shape in cross-section.

[0047] like Figure 14 As shown, the bottom of dielectric region 70A separates upper slit 71A from lower slit 55. The bottom of dielectric region 70B separates each upper slit 71B from each lower slit 67. The bottom of dielectric region 70A may have a width W1 in the range of about 12 nm to about 16 nm, which is significantly greater than width W2, which may be in the range of about 0.5 nm to about 2 nm. The bottom of dielectric region 70A may have a height H1 in the range of about 5 nm to about 20 nm.

[0048] Figure 15 The formation of additional features of the FinFET is shown. The corresponding process is shown as Figure 17 The process flow 200 is shown as process 232. For example, gate contact plug 74 is formed over and in contact with gate electrode 60. Source / drain silicide regions 76 and source / drain contact plugs 78 are also formed to be electrically connected to source / drain regions 42. FinFETs 80A and 80B are thus formed. It should be understood that, for example, during the planarization process and etching process used to form gate contact plug 74 and source / drain contact plug 78, the top portions of dielectric regions 70A and 70B may be removed. Slit 71B may be completely removed along with the corresponding top portions of dielectric region 70B, and slit 71A may be shortened.

[0049] Figure 16A A top view of a portion of wafer 10 is shown in accordance with some embodiments. Figure 16A In FIG. 16 , some gate contact plugs 74 and source / drain contact plugs 78 are shown, but more gate contact plugs 74 and source / drain contact plugs 78 may be formed. Figure 15 10. In addition, dielectric region 70C is shown that is formed by the same deposition process as dielectric regions 70A and 70B. It should be understood that in the top view, dielectric regions 70A, 70B, and 70C can form a continuous region with no distinguishable interfaces between them. In other words, when viewed from the top of wafer 10, there are no distinguishable interfaces between dielectric regions 70A, 70B, and 70C formed by the same process. Therefore, there is no distinguishable interface in region 73. According to other embodiments, Figure 15 The process shown completely removes the dielectric region 70C, so that Figure 16A and 16BNo dielectric region 70C will be left in. Instead, the gate isolation region 50 will be visible.

[0050] Figure 16B Shown Figure 16A 84 in FIG. In the embodiment shown, the portion of the fin isolation region 54 on top of the STI region 22 and the dielectric region 70A thereover, as well as the gaps 67 and 71A, are shown in perspective view. In other embodiments, the fin isolation region 54 is Figure 16B , which are not visible in FIG. 1 , because dielectric region 70A extends to the top surface of STI region 22. Dielectric regions 70B and 70C are also shown.

[0051] Embodiments of the present disclosure have several advantageous features. By recessing the gate isolation region, fin isolation region, and dielectric hard mask, additional dielectric regions can be formed within the resulting recesses. Gaps in the gate isolation region, fin isolation region, and dielectric hard mask can be sealed. Otherwise tall gaps can be divided into shorter upper and lower portions. This reduces problems caused by gaps.

[0052] According to some embodiments of the present disclosure, a method includes: forming a semiconductor fin protruding above a top surface of an isolation region, wherein the isolation region extends into a semiconductor substrate; etching a portion of the semiconductor fin to form a trench, wherein the trench extends below a bottom surface of the isolation region and into the semiconductor substrate; filling the trench with a first dielectric material to form a first fin isolation region; recessing the first fin isolation region to form a first groove; and filling the first groove with a second dielectric material, wherein the first and second dielectric materials combine to form a second fin isolation region. In one embodiment, the first dielectric material includes a first gap, and the second dielectric material includes a second gap overlapping the first gap. In one embodiment, the method further includes: removing a top portion of the second dielectric material including the second gap, wherein a bottom portion of the second dielectric material without the second gap remains. In one embodiment, the first dielectric material and the second dielectric material are the same. In one embodiment, the method further includes: forming a gate stack on the semiconductor fin; and forming a gate isolation region that divides the gate stack into a first portion and a second portion, wherein when the first fin isolation region is recessed, the gate isolation region is also recessed to form a second groove, and the second dielectric material is filled into the second groove. In one embodiment, the method further includes: forming a replacement gate stack on the semiconductor fin; recessing the replacement gate stack; and forming a dielectric hard mask over the replacement gate stack that contacts the replacement gate stack, wherein when the first fin isolation region is recessed, the dielectric hard mask is also recessed to form an additional recess, and the second dielectric material is filled into the additional recess. In one embodiment, after the first fin isolation region is recessed, a top surface of a remaining portion of the first fin isolation region is lower than the additional top surface of the semiconductor fin.

[0053] According to some embodiments of the present disclosure, a device includes a semiconductor substrate; an isolation region extending into the semiconductor substrate; and a dielectric region extending from a first level above the top surface of the isolation region to a second level below the bottom surface of the isolation region, wherein the dielectric region includes a lower portion having a first gap therein and an upper portion having a second gap therein, wherein the first gap is separated from the second gap by a bottom of the upper portion of the dielectric region. In one embodiment, there is a distinguishable interface between the lower portion and the upper portion. In one embodiment, the lower portion and the upper portion are formed of the same material, and the distinguishable interface includes an interface layer, and the interface layer includes the same material and oxygen. In one embodiment, the second gap overlaps with the first gap. In one embodiment, the device also includes a first protruding semiconductor fin and a second protruding semiconductor fin having a longitudinal direction aligned with the same straight line, wherein the dielectric region separates the first protruding semiconductor fin from the second protruding semiconductor fin. In one embodiment, the device further includes: a first FinFET including a first protruding semiconductor fin and a first source / drain region, wherein the first source / drain region is between the first protruding semiconductor fin and the dielectric region; and a second FinFET including a second protruding semiconductor fin and a second source / drain region, wherein the second source / drain region is between the second protruding semiconductor fin and the dielectric region. In one embodiment, the device further includes a gate stack on the first protruding semiconductor fin; and a dielectric hard mask above the gate stack, the hard mask including an additional lower portion having a third slit therein; and an additional upper portion above and in contact with the additional lower portion. In one embodiment, the additional upper portion is free of the slit.

[0054] According to some embodiments of the present disclosure, a device includes a substrate; an isolation region extending into the substrate; a semiconductor fin extending upward from a top surface of the isolation region; a first epitaxial semiconductor region and a second epitaxial semiconductor region extending into the semiconductor fin; a first dielectric region laterally between the first epitaxial semiconductor region and the second epitaxial semiconductor region; a second dielectric region above the first dielectric region, wherein the second dielectric region includes a U-shaped bottom in contact with the top surface of the first dielectric region. In one embodiment, the first dielectric region and the second dielectric region include the same dielectric material. In one embodiment, the first dielectric region and the second dielectric region include a first gap and a second gap, respectively, and the first gap is separated from the second gap by a portion of the second dielectric region. In one embodiment, the first gap extends to the U-shaped bottom. In one embodiment, the bottom surface of the second dielectric region is lower than the additional top surface of the first epitaxial semiconductor region.

[0055] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0056] Example 1. A method for manufacturing a semiconductor device, comprising: forming a semiconductor fin that protrudes above a top surface of an isolation region, wherein the isolation region extends into a semiconductor substrate; etching a portion of the semiconductor fin to form a trench, wherein the trench extends below a bottom surface of the isolation region and extends into the semiconductor substrate; filling the trench with a first dielectric material to form a first fin isolation region; recessing the first fin isolation region to form a first groove; and filling the first groove with a second dielectric material, wherein the first dielectric material and the second dielectric material combine to form a second fin isolation region.

[0057] Example 2. The method of Example 1, wherein the first dielectric material includes a first gap and the second dielectric material includes a second gap overlapping the first gap.

[0058] Example 3. The method of Example 2, further comprising: removing a top portion of the second dielectric material including the second gap, wherein a bottom portion of the second dielectric material without the second gap remains.

[0059] Example 4. The method of Example 1, wherein the first dielectric material is the same as the second dielectric material.

[0060] Example 5. The method according to Example 1 further includes: forming a gate stack on the semiconductor fin; and forming a gate isolation region that divides the gate stack into a first part and a second part, wherein, when the first fin isolation region is recessed, the gate isolation region is also recessed to form a second groove, and the second dielectric material is filled into the second groove.

[0061] Example 6. The method according to Example 1 further includes: forming a replacement gate stack on the semiconductor fin; recessing the replacement gate stack; and forming a dielectric hard mask contacting the replacement gate stack above the replacement gate stack, wherein, when the first fin isolation region is recessed, the dielectric hard mask is also recessed to form an additional groove, and the second dielectric material is filled into the additional groove.

[0062] Example 7. The method of Example 1, wherein after the first fin isolation region is recessed, a top surface of a remaining portion of the first fin isolation region is lower than an additional top surface of the semiconductor fin.

[0063] Example 8. A semiconductor device comprising: a semiconductor substrate; an isolation region extending into the semiconductor substrate; a dielectric region comprising: a lower portion having a first gap therein; and an upper portion having a second gap therein, wherein the first gap is separated from the second gap by a bottom of the upper portion of the dielectric region.

[0064] Example 9. The semiconductor device of Example 8, wherein the lower portion and the upper portion have a distinguishable interface therebetween.

[0065] Example 10. The semiconductor device of Example 9, wherein the lower portion and the upper portion are formed of a same material, and the distinguishable interface comprises an interface layer, and the interface layer comprises the same material and oxygen.

[0066] Example 11. The semiconductor device of Example 8, wherein the first slit reaches a bottom surface of the upper portion of the dielectric region.

[0067] Example 12. The semiconductor device of Example 8 further includes: a first protruding semiconductor fin and a second protruding semiconductor fin, wherein the first protruding semiconductor fin and the second protruding semiconductor fin have longitudinal directions aligned with the same straight line, wherein the dielectric region separates the first protruding semiconductor fin from the second protruding semiconductor fin.

[0068] Example 13. The semiconductor device according to Example 12 further includes: a first fin field-effect transistor FinFET, the first FinFET including the first protruding semiconductor fin and a first source / drain region, wherein the first source / drain region is between the first protruding semiconductor fin and the dielectric region; and a second FinFET, the second FinFET including the second protruding semiconductor fin and a second source / drain region, wherein the second source / drain region is between the second protruding semiconductor fin and the dielectric region.

[0069] Example 14. The semiconductor device according to Example 12 further includes: a gate stack on the first protruding semiconductor fin; and a dielectric hard mask above the gate stack, the dielectric hard mask including: an additional lower portion having a third gap therein; and an additional upper portion above and in contact with the additional lower portion.

[0070] Example 15. The semiconductor device of Example 14, wherein the additional upper portion is free of gaps.

[0071] Example 16. A semiconductor device comprising: a substrate; an isolation region extending into the substrate; a semiconductor fin extending upward from a top surface of the isolation region; a first epitaxial semiconductor region and a second epitaxial semiconductor region extending into the semiconductor fin; a first dielectric region, the first dielectric region being laterally located between the first epitaxial semiconductor region and the second epitaxial semiconductor region; a second dielectric region above the first dielectric region, wherein the second dielectric region includes a U-shaped bottom in contact with the top surface of the first dielectric region.

[0072] Example 17. The semiconductor device of Example 16, wherein the first dielectric region and the second dielectric region include the same dielectric material.

[0073] Example 18. The semiconductor device of Example 16, wherein the first dielectric region and the second dielectric region include a first gap and a second gap, respectively, and the first gap is separated from the second gap by a portion of the second dielectric region.

[0074] Example 19. The semiconductor device of Example 18, wherein the first slit extends to the U-shaped bottom.

[0075] Example 20. The semiconductor device of Example 16, wherein a width of the second dielectric region is equal to a width of the first dielectric region.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a semiconductor fin protruding above a top surface of an isolation region, wherein the isolation region extends into the semiconductor substrate; etching a portion of the semiconductor fin to form a trench, wherein the trench extends below a bottom surface of the isolation region and extends into the semiconductor substrate; filling the trench with a first dielectric material to form a first fin isolation region, the first fin isolation region extending below a bottom surface of the isolation region; recessing the first fin isolation region to form a first groove; as well as The first recess is filled with a second dielectric material, wherein the first dielectric material and the second dielectric material combine to form a second fin isolation region.

2. The method according to claim 1, wherein The first dielectric material includes a first gap, and the second dielectric material includes a second gap overlapping the first gap.

3. The method according to claim 2, further comprising: A top portion of the second dielectric material including the second slit is removed, wherein a bottom portion of the second dielectric material without the second slit remains.

4. The method according to claim 1, wherein The first dielectric material is the same as the second dielectric material.

5. The method according to claim 1, further comprising: forming a gate stack on the semiconductor fin; as well as A gate isolation region is formed to divide the gate stack into a first portion and a second portion, wherein when the first fin isolation region is recessed, the gate isolation region is also recessed to form a second groove, and the second dielectric material is filled into the second groove.

6. The method according to claim 1, further comprising: forming a replacement gate stack on the semiconductor fin; recessing the replacement gate stack; as well as A dielectric hard mask is formed over the replacement gate stack and contacts the replacement gate stack, wherein when the first fin isolation region is recessed, the dielectric hard mask is also recessed to form an additional groove, and the second dielectric material is filled into the additional groove.

7. The method according to claim 1, wherein After the first fin isolation region is recessed, a top surface of a remaining portion of the first fin isolation region is lower than an additional top surface of the semiconductor fin.

8. A semiconductor device comprising: semiconductor substrates; an isolation region extending into the semiconductor substrate; a dielectric region extending from a first level above a top surface of the isolation region to a second level below a bottom surface of the isolation region, the dielectric region comprising: a lower portion having a first slit therein, the lower portion extending below a bottom surface of the isolation region; and An upper portion having a second slit therein, wherein the first slit is spaced apart from the second slit by a bottom of the upper portion of the dielectric region.

9. The semiconductor device according to claim 8, wherein A distinguishable interface is defined between the lower portion and the upper portion.

10. The semiconductor device according to claim 9, wherein The lower portion and the upper portion are formed of a same material, and the distinguishable interface includes an interface layer, and the interface layer includes the same material and oxygen.

11. The semiconductor device according to claim 8, wherein The first slit reaches a bottom surface of the upper portion of the dielectric region.

12. The semiconductor device according to claim 8, further comprising: A first protruding semiconductor fin and a second protruding semiconductor fin have longitudinal directions aligned with a common line, wherein the dielectric region separates the first protruding semiconductor fin from the second protruding semiconductor fin.

13. The semiconductor device according to claim 12, further comprising: a first fin field effect transistor (FinFET), the first FinFET comprising the first protruding semiconductor fin and a first source / drain region, wherein the first source / drain region is between the first protruding semiconductor fin and the dielectric region; and A second FinFET includes the second protruding semiconductor fin and a second source / drain region, wherein the second source / drain region is between the second protruding semiconductor fin and the dielectric region.

14. The semiconductor device according to claim 12, further comprising: a gate stack on the first protruding semiconductor fin; as well as A dielectric hard mask over the gate stack, the dielectric hard mask comprising: an additional lower portion having a third gap therein; as well as An additional upper portion is above and in contact with the additional lower portion.

15. The semiconductor device according to claim 14, wherein The additional upper portion has no gaps.

16. A semiconductor device comprising: substrate; an isolation region extending into the substrate; a semiconductor fin extending upward from a top surface of the isolation region; a first epitaxial semiconductor region and a second epitaxial semiconductor region extending into the semiconductor fin; a first dielectric region laterally disposed between the first epitaxial semiconductor region and the second epitaxial semiconductor region, the first dielectric region extending below a bottom surface of the isolation region; a second dielectric region above the first dielectric region, wherein the second dielectric region includes a U-shaped bottom in contact with a top surface of the first dielectric region; The first dielectric region and the second dielectric region include a first gap and a second gap, respectively, and the first gap is separated from the second gap by a portion of the second dielectric region.

17. The semiconductor device according to claim 16, wherein The first dielectric region and the second dielectric region include the same dielectric material.

18. The semiconductor device according to claim 16, wherein The first slit extends to the U-shaped bottom.

19. The semiconductor device according to claim 16, wherein The width of the second dielectric region is equal to the width of the first dielectric region.

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