Assembly structure and packaging structure

Abstract

The present disclosure relates to an assembly structure and a packaging structure. The assembly structure includes a core computing part and a sub-computing part. The core computing part has a first surface and a second surface opposite to the first surface. The core computing part includes at least one conductive via electrically connecting the first surface and the second surface. The sub-computing part has a first surface stacked on the first surface of the core computing part and a second surface opposite to the first surface. The sub-computing part includes at least one conductive via electrically connecting the first surface and the second surface. The assembly structure includes a first signal transmission path and a second signal transmission path. The first signal transmission path is between the at least one conductive via of the sub-computing part and the at least one conductive via of the core computing part. The second signal transmission path is between the second surface of the sub-computing part and the at least one conductive via of the sub-computing part.

Description

Technical Field

[0001] The present disclosure relates to an assembly structure and a package structure, and to an assembly structure including a plurality of signal transmission paths and a package structure including the plurality of signal transmission paths. Background Art

[0002] With the rapid development of the electronics industry and the progress of semiconductor processing technology, semiconductor chips are integrated with an increasing number of electronic components to achieve improved electrical performance and additional functions. Therefore, semiconductor chips have more input / output (I / O) connections. In order to manufacture a semiconductor package containing a semiconductor chip with an increased number of I / O connections, the size of the circuit layer of the semiconductor substrate that can be used to carry the semiconductor chip may be increased accordingly. Therefore, the thickness and warpage of the semiconductor substrate may increase accordingly, and the yield of the semiconductor substrate may decrease, which may adversely affect the yield of the semiconductor package. In addition, the spacing between the input / output (I / O) connections is reduced, which increases the difficulty in the manufacturing process. Summary of the Invention

[0003] In some embodiments, an assembly structure includes a core computing portion and a sub-computing portion. The core computing portion has a first surface and a second surface opposite the first surface. The core computing portion includes at least one conductive via electrically connecting the first surface and the second surface. The sub-computing portion has a first surface stacked on the first surface of the core computing portion and a second surface opposite the first surface. The sub-computing portion includes at least one conductive via electrically connecting the first surface and the second surface. The assembly structure includes a first signal transmission path and a second signal transmission path. The first signal transmission path is between at least one conductive via of the sub-computing portion and at least one conductive via of the core computing portion. The second signal transmission path is between the second surface of the sub-computing portion and at least one conductive via of the sub-computing portion.

[0004] In some embodiments, a package structure includes a lower substrate, an upper substrate, and a stacked structure disposed between the lower and upper substrates. The stacked structure includes a first electronic component and a second electronic component stacked on the first electronic component. The second electronic component is disposed between the first electronic component and the upper substrate. The package structure includes a third signal transmission path and a fourth signal transmission path. The third signal transmission path passes through the first electronic component and is located between the lower substrate and the second electronic component. The fourth signal transmission path is located between the upper substrate and the second electronic component.

[0005] In some embodiments, a packaging structure includes an upper substrate, a processor chip, a sealing body, a memory chip, a sealing body, and a lower substrate. The upper substrate has a top surface and a bottom surface opposite to the top surface. The processor chip has a top surface and a bottom surface opposite to the top surface. The top surface of the processor chip is bonded to and electrically connected to the bottom surface of the upper substrate. The sealing body is disposed on the bottom surface of the upper substrate and covers the processor chip. The memory chip has an active surface and a back surface opposite to the active surface. The active surface of the memory chip is bonded to and electrically connected to the top surface of the upper substrate. The sealing body is disposed on the top surface of the upper substrate and covers the memory chip. The lower substrate is disposed on the sealing body and electrically connected to the bottom surface of the processor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of some embodiments of the present disclosure will be readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various structures may not be drawn to scale, and the dimensions of the various structures may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 A cross-sectional view illustrating a package structure according to some embodiments of the present disclosure.

[0008] Figure 2 illustrate Figure 1 Magnified view of area "A".

[0009] Figure 3 Cross-sectional diagram illustrating an enlarged view of a region of a package structure according to some embodiments of the present disclosure.

[0010] Figure 4 Cross-sectional diagram illustrating an enlarged view of a region of a package structure according to some embodiments of the present disclosure.

[0011] Figure 5 Cross-sectional diagram illustrating an enlarged view of a region of a package structure according to some embodiments of the present disclosure.

[0012] Figure 6 Cross-sectional views illustrating examples of package structures according to some embodiments of the present disclosure.

[0013] Figure 7 Cross-sectional views illustrating examples of package structures according to some embodiments of the present disclosure.

[0014] Figure 8 Cross-sectional views illustrating examples of package structures according to some embodiments of the present disclosure.

[0015] Figure 9 Cross-sectional views illustrating examples of package structures according to some embodiments of the present disclosure.

[0016] Figure 10Cross-sectional views illustrating examples of package structures according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0017] Common reference numerals are used throughout the drawings and detailed description to refer to the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0018] The following disclosure provides many different embodiments or examples for implementing the different features of the provided themes. Specific examples of components and arrangements are described below to explain certain aspects of the present disclosure. Of course, these components and arrangements are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed or arranged in direct contact, and may also include an embodiment in which additional features may be formed or arranged between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0019] Figure 1 A cross-sectional view illustrating a package structure 1 according to some embodiments of the present disclosure. Figure 2 illustrate Figure 1 FIG1 is an enlarged view of region “A” in FIG1 . The package structure 1 may include a lower substrate 12, an upper substrate 14, an assembly structure 2, a first electronic device (e.g., a memory device 3), an encapsulant 16, a plurality of conductive elements (e.g., conductive vias 163), a plurality of passive components 13, a plurality of bonding materials 46, a package substrate 40, and a plurality of external connectors 49.

[0020] The lower substrate 12 may be an interposer or a wiring structure. Figure 1As shown in FIG, lower substrate 12 may be an interposer, and the material of lower substrate 12 may be glass or silicon. Lower substrate 12 may have a top surface 121, a bottom surface 122 opposite top surface 121, and an outer side surface 124 extending between top surface 121 and bottom surface 122. Lower substrate 12 may include a plurality of conductive vias 123 extending between top surface 121 and bottom surface 122. In some embodiments, conductive vias 123 may extend through (or penetrate) lower substrate 12, and both ends of each conductive via 123 may be exposed from top surface 121 and bottom surface 122, respectively. In some embodiments, a circuit layer 125 (including, for example, traces and pads) and a dielectric layer may be disposed on top surface 121 and bottom surface 122 of lower substrate 12. Circuit layer 125 may be electrically connected to conductive vias 123.

[0021] The assembly structure 2 is disposed between the lower substrate 12 and the upper substrate 14 and has a top surface 21 and a bottom surface 22 opposite to the top surface 21. The bottom surface 22 of the assembly structure 2 is bonded to and electrically connected to the lower substrate 12, and the top surface 21 of the assembly structure 2 is bonded to and electrically connected to the upper substrate 14. In some embodiments, the assembly structure 2 may be a processor chip, such as an application processor (AP), a central processing unit (CPU), or a graphics processing unit (GPU). Figure 1 As shown in FIG, the assembly structure 2 may include a first electronic component (e.g., a core-computing section 23) and at least one second electronic component (e.g., at least one sub-computing section) stacked on the first electronic component (e.g., core-computing section 23). Therefore, the assembly structure 2 may also be referred to as a "stacked structure." The second electronic component (e.g., sub-computing section) is disposed between the first electronic component (e.g., core-computing section 23) and the upper substrate 14.

[0022] The first electronic component (e.g., core computing portion 23) may be a processor core or a processor unit and may have a first surface 231 and a second surface 232 opposite the first surface 231. In some embodiments, the first surface 231 of the core computing portion 23 may be an active surface. That is, active electronic components (such as transistors and diodes) and wiring layers are disposed adjacent to the first surface 231 of the core computing portion 23. In some embodiments, there may be a circuit layer 239 (including, for example, traces and pads) disposed on the second surface 232 of the core computing portion 23. The second surface 232 of the core computing portion 23 may be the bottom surface 22 of the assembly structure 2. Furthermore, the second surface 232 of the core computing portion 23 (e.g., the bottom surface 22 of the assembly structure 2) may be bonded to and electrically connected to the top surface 121 of the lower substrate 12 via a bonding material 15. An underfill 11 may be disposed in the space between the core computing portion 23 and the lower substrate 12 of the assembly structure 2 to cover and protect the bonding material 15. In some embodiments, the core computing portion 23 may include at least one conductive via 233 extending between the first surface 231 and the second surface 232 and electrically connecting the first surface 231 and the second surface 232. The conductive via 233 may extend through the core computing portion 23, and both ends of each of the conductive vias 233 may be exposed from the first surface 231 and the second surface 232, respectively, for electrical connection.

[0023] At least one second electronic component (e.g., at least one sub-computing portion) may include at least one memory component 24 and at least one signal transmission component 25 disposed juxtaposedly on the core computing portion 23. For example, the memory component 24 may be a static random access memory (SRAM) chip and may have a first surface 241 and a second surface 242 opposite the first surface 241. In some embodiments, the first surface 241 of the memory component 24 may be an active surface. That is, active electronic components (such as transistors and diodes) and wiring layers are disposed adjacent to the first surface 241 of the memory component 24. In some embodiments, a circuit layer 249 (including, for example, traces and pads) may be disposed on the second surface 242 of the second electronic component (e.g., a sub-computing portion, such as the memory component 24). The second surface 242 of the memory component 24 may be part of the top surface 21 of the assembly structure 2. In some embodiments, the memory component 24 may include at least one conductive via 243 extending between and electrically connecting the first and second surfaces 241 and 242. The conductive vias 243 may extend through the memory component 24, and both ends of each of the conductive vias 243 may be exposed from the first surface 241 and the second surface 242, respectively, for electrical connection. Figure 1 , a first surface 241 of at least one second electronic component (e.g., a sub-computing portion, such as the memory component 24) is bonded to and electrically connected to the first surface 231 of the core computing portion 23. In other words, the first surface 241 (i.e., the active surface) of the at least one second electronic component (e.g., the sub-computing portion, such as the memory component 24) faces the first surface 231 (i.e., the active surface) of the core computing portion 23.

[0024] The signal transmission component 25 may be a physical layer (PHY) chip having a serializer / deserializer (SerDes) for transmitting signals (e.g., data signals, power signals (or electrical signals), and ground signals), and may have a first surface 251 and a second surface 252 opposite the first surface 251. In some embodiments, the first surface 251 of the signal transmission component 25 may be an active surface. That is, active electronic components (e.g., transistors and diodes) and wiring layers are disposed adjacent to the first surface 251 of the signal transmission component 25. In some embodiments, circuit layers (including, for example, traces and pads) may be disposed on the second surface 252 of a non-computing portion or sub-computing portion (e.g., the signal transmission component 25). The second surface 252 of the signal transmission component 25 may be part of the top surface 21 of the assembly structure 2. In some embodiments, the signal transmission component 25 may include at least one conductive via 253 extending between the first surface 251 and the second surface 252 and electrically connecting the first surface 251 and the second surface 252. The conductive vias 253 may extend through the signal transmission component 25, and both ends of each of the conductive vias 253 may be exposed from the first surface 251 and the second surface 252, respectively, for electrical connection. Figure 1 As shown in FIG, the first surface 251 of at least one second electronic component (e.g., a sub-computing portion, such as the signal transmission component 25) is bonded to and electrically connected to the first surface 231 of the core computing portion 23. In other words, the first surface 251 (i.e., the active surface) of the at least one second electronic component (e.g., the sub-computing portion, such as the signal transmission component 25) faces the first surface 231 (i.e., the active surface) of the core computing portion 23.

[0025] A first electronic device (e.g., a memory device 3) is disposed between the lower substrate 12 and the upper substrate 14 and has a top surface 31 and a bottom surface 32 opposite to the top surface 31. The bottom surface 32 of the memory device 3 is bonded to and electrically connected to the top surface 121 of the lower substrate 12 through a bonding material 18, and the top surface 31 of the memory device 3 is bonded to and electrically connected to the upper substrate 14. An underfill 19 may be disposed in the space between the memory device 3 and the lower substrate 12 to cover and protect the bonding material 18. In some embodiments, the memory device 3 may be a memory chip, such as a high bandwidth memory (HBM) chip. Figure 1As shown in FIG, memory device 3 may include a substrate 34, a plurality of memory dies 35, an encapsulant 36, and a plurality of conductive vias 33. Memory dies 35 may be stacked on substrate 34. Encapsulant 36 may cover substrate 34 and memory dies 35. Conductive vias 33 may extend through encapsulant 36 and electrically connect substrate 34. The top surface of substrate 34 may be top surface 31 of memory device 3, and the bottom surface of encapsulant 36 may be bottom surface 32 of memory device 3. One end of conductive via 33 may be exposed from bottom surface 32 of memory device 3 (i.e., the bottom surface of encapsulant 36) for electrical connection. In some embodiments, a circuit layer (including, for example, traces and pads) may be disposed on bottom surface 32 of memory device 3 (i.e., the bottom surface of encapsulant 36). Conductive via 33 electrically connects top surface 31 and bottom surface 32. In some embodiments, the first electronic device (eg, memory device 3 ) may be electrically connected to the core computing portion 23 through the upper substrate 14 and the signal transmission component 25 .

[0026] The seal 16 is disposed between the lower substrate 12 and the upper substrate 14 to cover the assembly structure 2, the memory device 3 and the conductive elements (eg, the conductive vias 163). The seal 16 may be a molding compound with or without a filler. Figure 1 , the seal 16 may include a top surface 161, a bottom surface 162 opposite the top surface 161, and an outer side surface 164 extending between the top surface 161 and the bottom surface 162. The bottom surface 162 of the seal 16 may be disposed on or attached to the top surface 121 of the lower substrate 12, and the top surface 161 of the seal 16 may be disposed on or attached to the bottom surface 142 of the upper substrate 14. In some embodiments, a conductive element (e.g., a conductive via 163) is disposed adjacent to the assembly structure 2 to electrically connect the lower substrate 12 and the upper substrate 14. Figure 1 As shown in FIG, the conductive vias 163 may extend through the sealing body 16, and both ends of each of the conductive vias 163 may be exposed from the top surface 161 and the bottom surface 162, respectively, for electrical connection.

[0027] The upper substrate 14 may be formed or disposed on the top surface 161 of the seal 16, the top surface 21 of the assembly structure 2, and the top surface 31 of the memory device 3, and may contact the conductive via 163. Thus, the conductive via 163 electrically connects the upper substrate 14 and the lower substrate 12. In addition, the assembly structure 2 may be electrically connected to the memory device 3 through the upper substrate 14. Figure 1As shown in FIG, the upper substrate 14 may have a top surface 141, a bottom surface 142 opposite to the top surface 141, and an outer surface 144 extending between the top surface 141 and the bottom surface 142. The upper substrate 14 may be a wiring structure and may include a dielectric structure 145, at least one circuit layer 146, and a plurality of inner vias 147. In some embodiments, the upper substrate 14 may be formed using a build-up technique. Figure 1 As shown in FIG, dielectric structure 145 may include at least one dielectric layer. The material of the dielectric layer may include an insulating material, a passivation material, a dielectric material, or a solder resist material, such as a benzocyclobutene (BCB)-based polymer or polyimide (PI). In some embodiments, the dielectric layer may be made of a photoimageable material. In some embodiments, outer surface 144 of upper substrate 14, outer surface 164 of seal 16, and outer surface 124 of lower substrate 12 may be substantially coplanar with each other.

[0028] At least one circuit layer 146 may include a plurality of circuit layers 146 in contact with or embedded in the dielectric structure 145. Each of the circuit layers 146 may be a fan-out circuit layer 146 or a redistribution layer (RDL). The material of the circuit layer 146 may include, for example, copper, other conductive metals, or alloys thereof. The line width / line space (L / S) of the circuit layer 146 may be less than or equal to approximately 5 μm / approximately 5 μm, or less than or equal to approximately 2 μm / approximately 2 μm, or less than or equal to approximately 1.8 μm / approximately 1.8 μm. Some of the internal vias 147 may be disposed between two adjacent circuit layers 146 to electrically connect the circuit layers 146. Some of the internal vias 147 may be disposed between the circuit layer 146 and the top surface 21 of the assembly structure 2 to electrically connect the circuit layer 146 and the assembly structure 2. Some of the internal vias 147 may be disposed between the circuit layer 146 and the top surface 31 of the memory device 3 to electrically connect the circuit layer 146 and the memory device 3 .

[0029] Passive components 13 are bonded to and electrically connected to bottom surface 122 of lower substrate 12. Passive components 13 may include decoupling capacitors (line width / line space). In addition, bonding material 46 (e.g., solder balls) is disposed adjacent to bottom surface 122 of lower substrate 12 for external connection. Bonding material 46 may be disposed on the circuit layer or exposed from bottom surface 122 of lower substrate 12.

[0030] The package substrate 40 may include a glass-reinforced epoxy material (such as FR4), bismaleimide triazine (BT), epoxy resin, silicon, printed circuit board (PCB) material, glass, ceramic, or photoimageable dielectric (PID) material. The package substrate 40 may have a top surface 401 and a bottom surface 402 opposite to the top surface 401. Figure 1 , the package substrate 40 may include a first circuit layer 41, a second circuit layer 42, and a plurality of conductive vias 43. The first circuit layer 41 may be disposed adjacent to a top surface 401 of the package substrate 40, and the second circuit layer 42 may be disposed adjacent to a bottom surface 402 of the package substrate 40. The conductive vias 43 may extend through the package substrate 40 and electrically connect the first circuit layer 41 and the second circuit layer 42. In some embodiments, the lower substrate 12 is bonded to and electrically connected to the first circuit layer 41 of the package substrate 40 by a bonding material 46. In addition, external connectors 49 (e.g., solder balls) are formed on or disposed on the second circuit layer 42 of the package substrate 40 for external connection.

[0031] exist Figure 1In the embodiment described in the accompanying drawings, the package structure 1 and the assembly structure 2 may include the following signal transmission paths: an interconnect signal transmission path 50, a first signal transmission path 51, a second signal transmission path 52, a third signal transmission path 53, a fourth signal transmission path 54, a fifth signal transmission path 55, an internal signal transmission path 56, a seventh signal transmission path 57, an eighth signal transmission path 58, and a ninth signal transmission path 59. The interconnect signal transmission path 50 is located between the first surface 241 (or first surface 251) (i.e., active surface) of the second electronic component (e.g., a sub-computing portion, such as the memory component 24 and the signal transmission component 25) and the first surface 231 (i.e., active surface) of the first electronic component (e.g., the core computing portion 23) without any conductive vias. The first signal transmission path 51 is located between the conductive vias 243 of the sub-computing portion (e.g., the memory component 24 and the signal transmission component 25) and the conductive vias 233 of the core computing portion 23. Because both the interconnected signal transmission path 50 and the first signal transmission path 51 extend through the interface between the first surface 241 (or first surface 251) (i.e., the active surface) of the second electronic component (e.g., the sub-computing portion, such as the memory component 24 and the signal transmission component 25) and the first surface 231 (i.e., the active surface) of the first electronic component (e.g., the core computing portion 23), the signal transmission speed in the interconnected signal transmission path 50 and the first signal transmission path 51 is high. In other words, high-speed signal transmission is achieved in the interconnected signal transmission path 50 and the first signal transmission path 51, and high-speed signals can be transmitted in the interconnected signal transmission path 50 and the first signal transmission path 51. In some embodiments, the signal transmission speed in the interconnected signal transmission path 50 can be greater than the signal transmission speed in the first signal transmission path 51.

[0032] The second signal transmission path 52 is located between the second surface 242 (or second surface 252) of the sub-computing portion (e.g., the memory component 24 and the signal transmission component 25) and the conductive via 243 (or conductive via 253) of the sub-computing portion (e.g., the memory component 24 and the signal transmission component 25). The signal transmission speed in the interconnected signal transmission path 50 and the first signal transmission path 51 can be greater than the signal transmission speed in the second signal transmission path 52. In addition, the first surface 241 and the second surface 242 of the sub-computing portion (e.g., the memory component 24) both have electrical connection functions and signal transmission functions. The first surface 251 and the second surface 252 of the signal transmission component 25 both have electrical connection functions and signal transmission functions.

[0033] The third signal transmission path 53 passes through (or through) the first electronic component (e.g., the core computing portion 23) and is located between the lower substrate 12 and the second electronic component (e.g., the sub-computing portion, such as the memory component 24 and the signal transmission component 25). Therefore, the first surface 231 and the second surface 232 of the first electronic component (e.g., the core computing portion 23) both have electrical connection functions and signal transmission functions. In some embodiments, the third signal transmission path 53 can be disposed in the conductive via 233 of the core computing portion 23.

[0034] The fourth signal transmission path 54 is between the upper substrate 14 and the second electronic component (e.g., the sub-computing portion, such as the memory component 24 and the signal transmission component 25). Therefore, the top surface 21 and the bottom surface 22 of the assembly structure 2 both have electrical connection functions and signal transmission functions.

[0035] The fifth signal transmission path 55 passes through (or penetrates) the second electronic component (eg, the sub-computing portion, such as the memory component 24 and the signal transmission component 25) and is between the upper substrate 14 and the first electronic component (eg, the core computing portion 23).

[0036] Internal signal transmission path 56 is located between a first electronic device (e.g., memory device 3) and a second electronic component (e.g., a sub-computing portion, such as memory component 24 and signal transmission component 25). In some embodiments, internal signal transmission path 56 may be disposed in upper substrate 14, and data signals are transmitted in internal signal transmission path 56. A first electronic component (e.g., core computing portion 23) can communicate with the first electronic device (e.g., memory device 3) through a second electronic component (e.g., a sub-computing portion, such as signal transmission component 25) and internal signal transmission path 56.

[0037] The seventh signal transmission path 57 may include external connector 49, conductive via 123 of lower substrate 12, a conductive element (e.g., conductive via 163), a second surface 242 of a sub-computing portion (e.g., memory component 24), and conductive via 243. In some embodiments, a power signal (or electrical signal) may be transmitted in the seventh signal transmission path 57. Thus, the power signal may be transmitted through the second surface 242 of the sub-computing portion (e.g., memory component 24) to the conductive via 243. The seventh signal transmission path 57 may be a power path.

[0038] The eighth signal transmission path 58 may include the external connector 49, the conductive via 123 of the lower substrate 12, and the passive component 13. In some embodiments, a power signal may be transmitted in the eighth signal transmission path 58. Therefore, the power signal may be transmitted to the passive component 13 through the eighth signal transmission path 58. The eighth signal transmission path 58 may be a power connection path.

[0039] The ninth signal transmission path 59 may include the external connector 49 and the conductive via 123 of the lower substrate 12. In some embodiments, an external data signal may be transmitted in the ninth signal transmission path 59. Therefore, the external data signal may be transmitted to the assembly structure 2 through the ninth signal transmission path 59.

[0040] refer to Figure 2 Memory component 24 may include a body 245, a layout layer 247, a passivation layer 246, a plurality of electrical contacts 248, and a circuit layer 249. Body 245 may be a silicon substrate. Conductive vias 243 may extend through body 245. Layout layer 247 may be disposed on the bottom surface of body 245 and may be disposed adjacent to first surface 241 of memory component 24. A portion of layout layer 247 may cover or electrically connect one end of conductive via 243. Passivation layer 246 may be disposed on the bottom surface of body 245 to cover layout layer 247. Passivation layer 246 may define a plurality of openings for exposing portions of layout layer 247. Electrical contacts 248 may be under-bump metallurgy (UBM) disposed in the openings of passivation layer 246 to contact the exposed portions of layout layer 247. Electrical contacts 248 do not fill the openings of passivation layer 246. The circuit layer 249 may be disposed on the top surface of the body 245 (ie, the second surface 242 of the memory component 24 ). A portion of the circuit layer 249 may cover or electrically connect the other end of the conductive via 243 .

[0041] The core computing portion 23 may include a body 235, a layout layer 237, a passivation layer 236, a plurality of electrical contacts 238, and a circuit layer 239. The body 235 may be a silicon substrate. Conductive vias 233 may extend through the body 235. The layout layer 237 may be disposed on the top surface of the body 235 and may be disposed adjacent to the first surface 231 of the core computing portion 233. A portion of the layout layer 237 may cover or electrically connect one end of the conductive via 233. The passivation layer 236 may be disposed on the top surface of the body 235 to cover the layout layer 237. The passivation layer 236 may define a plurality of openings for exposing portions of the layout layer 237. The electrical contacts 238 may be under bump metallization (UBM) disposed in the openings of the passivation layer 236 to contact the exposed portions of the layout layer 237. The electrical contacts 238 do not fill the openings of the passivation layer 236. The circuit layer 239 may be disposed on the bottom surface of the body 235 (ie, the second surface 232 of the core computing portion 23). A portion of the circuit layer 239 may cover or electrically connect the other end of the conductive via 233. Figure 2As shown in FIG, the electrical contacts 248 of the memory component 24 are bonded to the electrical contacts 238 of the core computing portion 23 through a plurality of bonding materials 26 such that the first surface 241 of the memory component 24 is bonded to the first surface 231 of the core computing portion 23.

[0042] Figure 3 Cross-sectional diagram illustrating an enlarged view of a region of a package structure according to some embodiments of the present disclosure. Figure 3 The structure is similar to Figure 2 The difference lies in the structure of the electrical contacts 248a of the memory component 24a and the electrical contacts 238a of the core computing part 23a. Figure 3 As shown in FIG, each of the electrical contacts 248a can be a pad filling an opening of the passivation layer 246. Additionally, each of the electrical contacts 238a can be a pad filling an opening of the passivation layer 236. The electrical contacts 248a of the memory component 24a can directly connect or contact the electrical contacts 238a of the core computing portion 23a.

[0043] Figure 4 Cross-sectional diagram illustrating an enlarged view of a region of a package structure according to some embodiments of the present disclosure. Figure 4 The structure is similar to Figure 2 The difference lies in the structure of the conductive via 243b of the memory component 24b and the conductive via 233b of the core computing part 23b. Figure 4 As shown in FIG, the conductive via 243b of the memory component 24b can further extend through a portion of the layout layer 247 and the passivation layer 246. The conductive via 233b of the core computing portion 23b can further extend through a portion of the layout layer 237 and the passivation layer 236. The conductive via 233b can be bonded to the conductive via 243b by the bonding material 26.

[0044] Figure 5 A cross-sectional view illustrating an example of a package structure 1 a according to some embodiments of the present disclosure. Figure 5 The package structure 1a is similar to Figure 1 The package structure 1 is different in that the structure of the lower substrate 12a. Figure 5 As shown in FIG, the lower substrate 12a may be a wiring structure. The lower substrate 12a may have a top surface 121, a bottom surface 122 opposite to the top surface 121, and an outer surface 124 extending between the top surface 121 and the bottom surface 122. The lower substrate 12a may include a dielectric structure 125, at least one circuit layer 126, and a plurality of internal vias 127. In some embodiments, the lower substrate 12a may be formed using a buildup technique. Figure 5As shown in FIG, dielectric structure 125 may include at least one dielectric layer. The dielectric layer may include an insulating material, a passivation material, a dielectric material, or a solder resist material, such as a benzocyclobutene (BCB)-based polymer or polyimide (PI). In some embodiments, the dielectric layer may be made of a photoimageable material.

[0045] At least one circuit layer 126 may include a plurality of circuit layers 126 in contact with or embedded in the dielectric structure 125. Each of the circuit layers 126 may be a fan-out circuit layer 126 or a redistribution layer (RDL). The material of the circuit layer 126 may include, for example, copper, other conductive metals, or alloys thereof. The line width / line spacing (L / S) of the circuit layer 126 may be less than or equal to about 5 μm / about 5 μm, or less than or equal to about 2 μm / about 2 μm, or less than or equal to about 1.8 μm / about 1.8 μm. Some of the internal vias 127 may be disposed between two adjacent circuit layers 126 to electrically connect the circuit layers 126.

[0046] Figure 6 A cross-sectional view illustrating an example of a package structure 1 b according to some embodiments of the present disclosure. Figure 6 The package structure 1b is similar to Figure 5 The package structure 1a is the same as that of FIG. 1 , and the differences are described as follows. Figure 5 The package structure 1b further includes a first electronic device 3 and a package substrate 40. The package structure 1b further includes a second electronic device (e.g., a memory device 6), a package body 17, and at least one bottom passive component 60. In some embodiments, the second electronic device 6 can be a memory chip, such as a dynamic random access memory (DRAM) chip, and can have an active surface 61 and a back surface 62 opposite the active surface 61. The active surface 61 of the second electronic device (e.g., the memory device 6) can be bonded to and electrically connected to the top surface 141 of the upper substrate 14 via a bonding material 64. The package body 17 (e.g., a molding compound) can be disposed on the top surface 141 of the upper substrate 14 to cover the second electronic device (e.g., the memory device 6).

[0047] Assembly structure 2b further includes a signal transmission component 25. Top surface 21 of assembly structure 2b can be bonded to and electrically connected to bottom surface 142 of upper substrate 14 via bonding material 26. Bottom surface 22 of assembly structure 2b can be electrically connected to top surface 121 of lower substrate 12a via a plurality of conductive vias 165. In addition, passive component 13 is bonded to and electrically connected to bottom surface 22 of assembly structure 2b. Thus, passive component 13 is disposed between assembly structure 2b and lower substrate 12a.

[0048] Bottom passive component 60 is bonded to and electrically connected to bottom surface 122 of lower substrate 12a. Bottom passive component 60 may include a decoupling capacitor. Bonding material 46 may be disposed on the circuit layer or exposed from bottom surface 122 of lower substrate 12a. In some embodiments, outer side surface 144 of upper substrate 14, outer side surface 164 of encapsulant 16, outer side surface 124 of lower substrate 12a, and outer side surface of package body 17 may be substantially coplanar with one another.

[0049] Package structure 1b may include the following signal transmission paths: internal signal transmission path 56b, seventh signal transmission path 57b, and ninth signal transmission path 59b. Internal signal transmission path 56b is located between a second electronic device (e.g., memory device 6) and a second electronic component (e.g., a sub-computing portion such as memory component 24 and signal transmission component 25). In some embodiments, internal signal transmission path 56b may extend through upper substrate 14, and data signals are transmitted in internal signal transmission path 56b.

[0050] In some embodiments, the power signal may be transmitted in the seventh signal transmission path 57b. Figure 6 , some of the power signal can be transmitted to the bottom passive component 60 through the first branch of the seventh signal transmission path 57b, which includes the lower substrate 12a. Some of the power signal can be transmitted to the passive component 13 through the second branch of the seventh signal transmission path 57b, which includes the lower substrate 12a, the conductive via 165, and the core computing portion 23. Some of the power signal can be transmitted to the second electronic device (e.g., the memory device 6) through the third branch of the seventh signal transmission path 57b, which includes the lower substrate 12a, the conductive via 163, and the upper substrate 14.

[0051] In some embodiments, the external data signal may be transmitted to the assembly structure 2 b through a ninth signal transmission path 59 b including the lower substrate 12 a and the conductive via 165 .

[0052] Figure 7 A cross-sectional view illustrating an example of a package structure 1 c according to some embodiments of the present disclosure. Figure 7 The package structure 1c is similar to Figure 6 The package structure 1b is different in that it further includes a top substrate 18, a top passive component 80, a plurality of vias 173 and a plurality of conductive vias 175. The top substrate 18 can be disposed on the package body 17. Figure 7As shown in FIG. 1 , top substrate 18 may be a wiring structure and may have a top surface 181 and a bottom surface 182 opposite top surface 181. Top substrate 18 may include a dielectric structure 185, at least one circuit layer 186, and a plurality of internal vias 187. In some embodiments, top substrate 18 may be formed using a buildup technique. Dielectric structure 185 may include at least one dielectric layer. At least one circuit layer 186 may include a plurality of circuit layers 186 in contact with or embedded in dielectric structure 185. Each of circuit layers 186 may be a fan-out circuit layer or a redistribution layer (RDL). Some of internal vias 187 may be disposed between two adjacent circuit layers 186 to electrically connect circuit layers 186.

[0053] In some embodiments, top passive component 80 can be bonded to and electrically connected to back surface 62 of a second electronic device (e.g., memory device 6). Top passive component 80 can include a decoupling capacitor. Furthermore, bottom surface 182 of top substrate 18 can be electrically connected to back surface 62 of a second electronic device (e.g., memory device 6) via conductive vias 175 embedded in package body 17. Furthermore, each of conductive vias 173 can extend through package body 17 and can electrically connect top substrate 18 and upper substrate 14.

[0054] The package structure 1c may include the following signal transmission paths: an internal signal transmission path 56c, a seventh signal transmission path 57c, and a ninth signal transmission path 59c. The internal signal transmission path 56c and the ninth signal transmission path 59c are respectively connected to Figure 6 The internal signal transmission path 56b is the same as the ninth signal transmission path 59b. In addition, some of the power signal can be transmitted to the bottom passive component 60 via the first branch of the seventh signal transmission path 57c, the first branch of which includes the lower substrate 12a. Some of the power signal can be transmitted to the passive component 13 via the second branch of the seventh signal transmission path 57c, the second branch of which includes the lower substrate 12a, the conductive via 165, and the core computing portion 23. Some of the power signal can be transmitted to the top passive component 80 via the third branch of the seventh signal transmission path 57c, the third branch of which includes the lower substrate 12a, the conductive via 163, the upper substrate 14, the through-via 173, the top substrate 18, the conductive via 175, and the second electronic device (e.g., the memory device 6).

[0055] Figure 8 A cross-sectional view illustrating an example of a package structure 1d according to some embodiments of the present disclosure. Figure 8 The package structure 1d is similar to Figure 5 The package structure 1a is replaced by the semiconductor chip 2d. Figure 5The assembly structure 2 is shown. In some embodiments, the semiconductor chip 2d may be a graphics processing unit (GPU). The semiconductor chip 2d is disposed between the lower substrate 12a and the upper substrate 14 and has a top surface 21 and a bottom surface 22 opposite the top surface 21. The bottom surface 22 of the semiconductor chip 2d is bonded to and electrically connected to the lower substrate 12a, and the top surface 21 of the semiconductor chip 2d is bonded to and electrically connected to the upper substrate 14. The semiconductor chip 2d may include a plurality of conductive vias 27 extending through the semiconductor chip 2d.

[0056] The lower substrate 12 a may be adhered to the package substrate 70 via an adhesive layer 72 . Figure 8 The package substrate 70 may be similar to Figure 5 The package substrate 40 may include a top surface 701 and a bottom surface 702 opposite to the top surface 701. Figure 8 , the package substrate 70 may include a first circuit layer (not shown), a second circuit layer 71, and a plurality of conductive vias 73. The first circuit layer may be disposed adjacent to a top surface 701 of the package substrate 70, and the second circuit layer 71 may be disposed adjacent to a bottom surface 702 of the package substrate 70. The conductive vias 73 may extend through the package substrate 70 and electrically connect the first circuit layer and the second circuit layer 71. Additionally, external connectors 79 may be formed on or disposed on the second circuit layer 71 of the package substrate 70 for external connection.

[0057] Package structure 1d may further include a plurality of conductive vias 128, 129 extending through lower substrate 12a and adhesive layer 72 and electrically connecting top surface 701 of package substrate 70. Thus, lower substrate 12a is electrically connected to package substrate 70 via conductive vias 128, 129. Furthermore, conductive elements of encapsulation body 16 (e.g., conductive vias 163) may be bonded to and electrically connected to conductive vias 128 of lower substrate 12a. Bonding materials 15, 18 may be bonded to and electrically connected to conductive vias 129 of lower substrate 12a.

[0058] The package structure 1d may include the following signal transmission paths: an internal signal transmission path 56d, a seventh signal transmission path 57d, and a ninth signal transmission path 59d. The internal signal transmission path 56d is located between the first electronic device (e.g., the memory device 3) and the semiconductor chip 2d. In some embodiments, the internal signal transmission path 56d may be disposed in the upper substrate 14, and data signals are transmitted in the internal signal transmission path 56d. Furthermore, the seventh signal transmission path 57d may include an external connector 79, a conductive via 73 of the package substrate 70, conductive vias 128, a conductive element (e.g., conductive via 163), the top surface 21 of the semiconductor chip 2d, and conductive vias 27. In some embodiments, a power signal may be transmitted in the seventh signal transmission path 57d. Furthermore, the ninth signal transmission path 59d may include an external connector 79, conductive vias 73 of the package substrate 70, and conductive vias 129. In some embodiments, an external data signal may be transmitted in the ninth signal transmission path 59d.

[0059] Figure 9 A cross-sectional view illustrating an example of a package structure 1e according to some embodiments of the present disclosure. Figure 9 The package structure 1e is similar to Figure 8 The package structure 1d is similar to the package structure 1d, except that conductive vias 128 and 129 are omitted, and package substrate 70 further includes conductive via 74. Conductive via 74 extends through package substrate 70 and adhesive layer 72 and electrically connects to bottom surface 122 of lower substrate 12a. Therefore, lower substrate 12a is electrically connected to package substrate 70 through conductive via 74.

[0060] The package structure 1 e may include the following signal transmission paths: an internal signal transmission path 56 e , a seventh signal transmission path 57 e , and a ninth signal transmission path 59 e . Figure 9 The internal signal transmission path 56e can be connected to Figure 8 The seventh signal transmission path 57e may be the same as the internal signal transmission path 56d of FIG. Furthermore, the seventh signal transmission path 57e may include the external connector 79, the conductive via 74 of the package substrate 70, the lower substrate 12a, a conductive element (e.g., conductive via 163), the top surface 21 of the semiconductor chip 2d, and the conductive via 27. In some embodiments, a power signal may be transmitted in the seventh signal transmission path 57e. Furthermore, the ninth signal transmission path 59e may include the external connector 79, the conductive via 74 of the package substrate 70, and the lower substrate 12a. In some embodiments, an external data signal may be transmitted in the ninth signal transmission path 59e.

[0061] Figure 10 Cross-sectional views illustrating examples of package structures 1f according to some embodiments of the present disclosure. Figure 10 The package structure 1f is similar to Figure 9The package structure 1e is different in that it is replaced by the assembly structure 2 Figure 9 semiconductor chip 2d. Figure 10 The assembly structure 2 can be Figure 1 The assembly structure 2 is the same.

[0062] The package structure 1f may include the following signal transmission paths: an internal signal transmission path 56f, a seventh signal transmission path 57f, and a ninth signal transmission path 59f. Figure 10 The internal signal transmission path 56f is connected to Figure 1 The seventh signal transmission path 57f may include the same internal signal transmission path 56 as the seventh signal transmission path 57f. The seventh signal transmission path 57f may include the external connector 79, the conductive via 73 of the package substrate 70, the conductive via 128, a conductive element (e.g., conductive via 163), the second surface 242 of the sub-computing portion (e.g., the memory component 24), and the conductive via 243. In some embodiments, a power signal may be transmitted in the seventh signal transmission path 57f. The ninth signal transmission path 59f may include the external connector 79, the conductive via 73 of the package substrate 70, and the conductive via 129. In some embodiments, an external data signal may be transmitted in the ninth signal transmission path 59f.

[0063] Unless otherwise specified, spatial descriptions such as "above," "below," "up," "left," "right," "lower," "top," "bottom," "vertical," "horizontal," "side," "above," "below," "upper," "on," "below," etc., are indicated relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein may be spatially arranged in any orientation or manner, with the proviso that the embodiments of the present disclosure will not deviate from such arrangements.

[0064] As used herein, the terms "about," "substantially," "approximately," and "approximately" are used to describe and explain small variations. When used in conjunction with an event or circumstance, the terms can refer to situations in which the event or circumstance definitely occurs as well as situations in which the event or circumstance is close to occurring. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two values ​​may be considered “substantially” the same or equal if the difference between them is less than or equal to ±10% of the mean of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%).

[0065] Two surfaces may be considered coplanar or substantially coplanar if the displacement between them does not exceed 5 μm, does not exceed 2 μm, does not exceed 1 μm, or does not exceed 0.5 μm.

[0066] As used herein, the singular terms "a," "an," and "the" may include plural referents unless the context clearly dictates otherwise.

[0067] As used herein, the terms "conductive," "electrically conductive," and "conductivity" refer to the ability to transfer an electric current. Conductive materials generally refer to those materials that exhibit little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, a conductive material is one that has a conductivity greater than about 10 4 S / m (e.g. at least 10 5 S / m or at least 10 6 The electrical conductivity of a material can sometimes change with temperature. Unless otherwise specified, the electrical conductivity of a material is measured at room temperature.

[0068] In addition, amounts, ratios, and other numerical values ​​are sometimes presented herein in a range format. It should be understood that such range format is used for convenience and brevity and should be interpreted flexibly to include not only the values ​​explicitly specified as limits of the range, but also all individual values ​​or sub-ranges encompassed within the range, as if each value and sub-range were explicitly specified.

[0069] Although the present disclosure has been described and illustrated with reference to specific embodiments of the present disclosure, these descriptions and illustrations are not restrictive. Those skilled in the art will understand that various changes may be made and equivalents substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the process reproduction in the present disclosure and the actual device. There may be other embodiments of the present disclosure that are not specifically described. The description and drawings should be regarded as illustrative, not restrictive. Modifications may be made to adapt specific circumstances, materials, compositions of matter, methods or processes to the objectives, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of operations are not limitations of the present invention.

Claims

1. An assembly structure comprising: a core computing portion having a first surface and a second surface opposite the first surface and comprising at least one conductive via electrically connecting the first surface and the second surface; as well as a sub-computing portion having a first surface stacked on the first surface of the core computing portion and a second surface opposite to the first surface, and comprising at least one conductive via electrically connecting the first surface and the second surface; wherein the assembly structure includes a first signal transmission path and a second signal transmission path, the first signal transmission path being between the at least one conductive via of the sub-computing portion and the at least one conductive via of the core computing portion, and the second signal transmission path being between the second surface of the sub-computing portion and the at least one conductive via of the sub-computing portion; The assembly structure further includes an interconnection signal transmission path between the core computing part and the sub-computing part, a signal transmission speed in the interconnection signal transmission path being greater than a signal transmission speed in the second signal transmission path. 2 . The assembly structure of claim 1 , wherein the first surface of the core computing portion is an active surface, and the first surface of the sub-computing portion is an active surface. 3 . The assembly structure of claim 1 , wherein a power signal is transmitted to the at least one conductive via through the second surface of the sub-computing portion.

4. The assembly structure according to claim 1, further comprising an electronic device, wherein the electronic device is electrically connected to the core computing part through the sub-computing part.

5. The assembly structure according to claim 4, wherein the assembly structure further includes an internal signal transmission path between the electronic device and the sub-computing part, wherein a signal transmission speed in the internal signal transmission path is greater than the signal transmission speed in the second signal transmission path.

6. The assembly structure according to claim 4, wherein the sub-computing portion includes a memory component and a signal transmission component arranged in parallel with each other, and the electronic device is electrically connected to the core computing portion through the signal transmission component.

7. The assembly structure according to claim 4, wherein the electronic device is a memory chip.

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