Semiconductor device forming method and semiconductor device

Abstract

The present disclosure provides a method for forming a semiconductor device and a semiconductor device. The method for forming a semiconductor device includes bonding a first surface of a first semiconductor substrate to a first surface of a second semiconductor substrate, and forming a cavity in a first region of the first semiconductor substrate, wherein forming the cavity includes: supplying a passivation gas mixture, depositing a passivation layer on a bottom surface and a plurality of sidewalls of the cavity, wherein during the deposition of the passivation layer, the deposition rate of the passivation layer on the bottom surface of the cavity is the same as the deposition rate of the passivation layer on the plurality of sidewalls of the cavity; and etching the first region of the first semiconductor substrate using an etching gas, wherein the etching gas is supplied simultaneously with the passivation gas mixture, and etching the first region of the first semiconductor substrate includes etching at a rate in a vertical direction greater than etching at a rate in a horizontal direction.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device including a cavity. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications such as, for example, personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of materials on a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually shrinking minimum feature size, allowing more components to be integrated into a given area. However, as minimum feature size shrinks, additional problems arise that need to be solved. Summary of the invention

[0004] An object of the embodiments of the present disclosure is to provide a method for forming a semiconductor device and a semiconductor device to solve at least one of the above problems.

[0005] A method for forming a semiconductor device comprises: bonding a first surface of a first semiconductor substrate to a first surface of a second semiconductor substrate; patterning a mask layer on the second surface of the first semiconductor substrate to expose a first area of ​​the first semiconductor substrate, the second surface being opposite to the first surface; and forming a cavity in the first area of ​​the first semiconductor substrate, wherein forming the cavity comprises: supplying a passivation gas mixture, depositing a passivation layer on a bottom surface and a plurality of side walls of the cavity, wherein during the deposition of the passivation layer, a deposition rate of the passivation layer on the bottom surface of the cavity is the same as a deposition rate of the passivation layer on the plurality of side walls of the cavity; and etching the first area of ​​the first semiconductor substrate using an etching gas, wherein the etching gas is supplied simultaneously with the passivation gas mixture, and etching the first area of ​​the first semiconductor substrate comprises etching at a rate in a vertical direction greater than etching at a rate in a horizontal direction.

[0006] A method for forming a semiconductor device includes: bonding a first semiconductor substrate to a second semiconductor substrate; patterning a mask layer on an unbonded surface of the first semiconductor substrate; and using the mask layer as a patterned mask to etch a cavity in the first semiconductor substrate, wherein etching the cavity includes: exciting a passivation gas mixture to generate a deposition plasma, the deposition plasma depositing a passivation layer on a bottom surface and a plurality of sidewalls of the cavity, wherein a deposition rate of the passivation layer on the bottom surface of the cavity is the same as a deposition rate of the passivation layer on the plurality of sidewalls of the cavity; and exciting an etching gas to generate an etching plasma, wherein generating the etching plasma occurs simultaneously with generating the deposition plasma, a first RF power source accelerates a plurality of ions from the etching plasma to the bottom surface of the cavity, wherein a vertical etching rate of the etching plasma is more significant than a horizontal etching rate of the etching plasma.

[0007] A semiconductor device comprises: a first semiconductor substrate; a second semiconductor substrate bonded to the first semiconductor substrate; and a cavity extending through the first semiconductor substrate, the cavity comprising: a top portion having a plurality of sidewalls having a first sidewall profile; and a bottom portion having a plurality of sidewalls having a second sidewall profile, the sidewalls of the top portion of the cavity having a first profile angle with a top surface of the first semiconductor substrate, and the sidewalls of the bottom portion of the cavity having a second profile angle with the top surface of the first semiconductor substrate, wherein the first profile angle is different from the second profile angle.

[0008] The advantages of the disclosed embodiments are that, by using the method for forming a semiconductor device, there is less dependence on a specific crystal orientation of a silicon wafer, such as in the case of a wet etching process. In addition, some embodiments can reduce the need for one or more mask layers when forming a backside cavity, simplifying the process and making it more cost-effective. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The following will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are only used for illustration. In fact, the size of the components can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention.

[0010] Figure 1A to Figure 1B Cross-sectional views of various intermediate steps in fabricating a device are shown according to some embodiments.

[0011] Figure 1C Cross-sectional views illustrating intermediate etching steps in the fabrication of a device are shown in accordance with some embodiments.

[0012] Figure 1D to Figure 1E Cross-sectional views of various intermediate steps in fabricating a device are shown according to some embodiments.

[0013] Figure 2 An etching system is shown according to some embodiments.

[0014] FIG. 3A to FIG. 3D Cross-sectional views of various intermediate steps in fabricating a device are shown according to some embodiments.

[0015] Figure 4 and Figure 5 Various intermediate etching steps in the fabrication of a device are shown according to alternative embodiments.

[0016] The reference numerals are as follows:

[0017] 100,400,500:Semiconductor substrate

[0018] 102:Semiconductor bare die

[0019] 104a / b: Bonding layer

[0020] 106: mask layer (photoresist)

[0021] 110: Surface

[0022] 116:MEMS structure

[0023] 128: Thin film layer

[0024] 130: polymer layer

[0025] 300, 600, 1000: Bonded semiconductor substrate

[0026] 700: Etching system

[0027] 710: Cavity

[0028] 720: Main air intake

[0029] 730:RF power

[0030] 740: Secondary air intake

[0031] 750:RF secondary power supply

[0032] 760: Platform

[0033] 770: Bias power supply

[0034] 780: Exhaust

[0035] 800: Chip

[0036] 900,1800,2700: Cavity

[0037] D1,D2,D3,D4,D5,D6,D7,E2: Vertical Depth

[0038] E1,H1,T1,T2:Thickness

[0039] R1: Radius of curvature

[0040] W1: Width

[0041] α,β,γ,δ: profile angle DETAILED DESCRIPTION

[0042] The following disclosure provides many embodiments or examples for implementing different elements of the subject matter provided. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that a first element is formed on a second element, it may include an embodiment in which the first and second elements are in direct contact, and it may also include an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact. In addition, the embodiments of the present invention may repeat reference values ​​and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, rather than for indicating the relationship between the different embodiments and / or configurations discussed.

[0043] Furthermore, spatially relative terms such as "under," "below," "lower," "above," "upper," and the like may be used to facilitate description of the relationship between one component or feature and another component or feature in the drawings. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations depicted in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the orientation after the rotation.

[0044] Embodiments discussed herein relate to methods for fabricating devices having backside cavities (e.g., light emitting diode (LED) devices, microelectromechanical system (MEMS) devices, etc.). Various embodiments include methods for dry etching processes, which are applied to, but not limited to, the formation of silicon backside cavities having specific etch profile angles. Advantageous features of one or more embodiments disclosed herein may include the ability to control the etch profile angle and the ability to provide better coverage of deposition (e.g., physical vapor deposition (PVD)) steps on the backside cavity walls. Using embodiments such as those disclosed herein, there is less reliance on a specific crystallographic orientation of the silicon wafer during wet etching processes. In addition, some embodiments may reduce the need for one or more mask layers when forming the backside cavity, simplifying the process and making it more cost-effective.

[0045] Figures 1A to 1E are various cross-sectional views of intermediate steps in a process of forming a device by bonding a substrate to a semiconductor die according to some embodiments. Figure 1A A bonding process is shown wherein the semiconductor substrate 100 is bonded to the semiconductor die 102 to form a bonded semiconductor substrate 300 . Figure 1C to Figure 1D A subsequent etching process is shown, wherein a backside cavity is formed in the semiconductor substrate 100 of the bonded semiconductor substrate 300. By utilizing various etching configurations, the etch profile angle of the backside cavity can be controlled.

[0046] First refer to Figure 1A, shows semiconductor die 102 and semiconductor substrate 100 bonded together to form bonded semiconductor substrate 300. Although semiconductor die 102 is referred to herein as a "die", it should be understood that semiconductor die 102 can be formed as part of a larger wafer (e.g., connected to other dies). Next, semiconductor die 102 can be singulated from other components of the wafer. The singulation process for semiconductor die 102 can be performed before bonding to form bonded semiconductor substrate 300, or after bonding to form bonded semiconductor substrate 300. Semiconductor die 102 can be a bare chip semiconductor die (e.g., an unpackaged semiconductor die). For example, the semiconductor die 102 may be a logic die (e.g., a central processing unit, a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a hybrid memory cube (HBC), a static random access memory (SRAM) die, a wide input / output (wideIO) memory die, a magnetoresistive random access memory (mRAM) die, a resistive random access memory (rRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a microcontroller die, a microprocessor die, ... The semiconductor die 102 and the semiconductor substrate 100 may be formed as a part of a larger wafer, and the semiconductor die 102 may also be referred to as a substrate. The semiconductor die 102 and the semiconductor substrate 100 may include individual singulated dies.

[0047] The semiconductor die 102 may be processed to form an integrated circuit within the semiconductor die 102 using an applicable manufacturing process. For example, the semiconductor die 102 may include a semiconductor substrate, which may include doped or undoped silicon. The semiconductor die 102 may also include an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaSsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. Devices, such as transistors, diodes, capacitors, resistors, etc., may be formed in semiconductor die 102 and may be interconnected by an interconnect structure (not shown) including, for example, metallization patterns in one or more dielectric layers in semiconductor die 102. The devices and the interconnect structure form one or more integrated circuits. The interconnect structure may include any number of metallization patterns disposed in any number of dielectric layers.

[0048] In some embodiments, semiconductor die 102 may include one or more MEMS devices, including MEMS structure 116. MEMS structure 116 may include a movable element that can move freely along at least one axis, such as a flexible membrane, a cantilevered beam, etc. MEMS devices may take the form of micromachined substrates that have been integrated with electronic circuits. These devices can be formed on different types of substrates using a variety of microelectronic technologies, such as vapor deposition, photolithography, and etching. MEMS devices may include sensors, actuators, and oscillators that can operate by electromagnetic, electrostrictive, thermoelectric, piezoelectric, or piezoresistive effects.

[0049] In an alternative embodiment, semiconductor die 102 may be an interposer wafer without active devices. According to some embodiments, semiconductor die 102 may or may not include passive devices (not shown), such as resistors, capacitors, inductors, transformers, etc.

[0050] The semiconductor substrate 100 may include, for example, bulk silicon, which may be doped or undoped. The semiconductor substrate 100 may include silicon having one of any number of crystal orientations, which may include <100>, <110>, and <110> family crystal orientations. In some embodiments, the semiconductor substrate 100 has a height H1 between about 50 μm and about 770 μm, for example about 720 μm.

[0051] The semiconductor substrate 100 is bonded to the surface of the semiconductor die 102 using a suitable technique, such as dielectric-to-dielectric bonding, metal-to-metal bonding, hybrid bonding, etc. For example, in various embodiments, the semiconductor die 102 can be bonded to the semiconductor substrate 100 using dielectric-to-dielectric bonding by using a bonding layer 104a and a bonding layer 104b on the semiconductor substrate 100 and the semiconductor die 102, respectively. In some embodiments, the bonding layer 104a and the bonding layer 104b can each include silicon oxide formed on the surface of the semiconductor substrate 100 and the semiconductor die 102, respectively, by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. In other embodiments, the bonding layers 104a and 104b can be formed on the semiconductor substrate 100 and the semiconductor die 102, respectively, by thermal oxidation of silicon surfaces. In alternative embodiments, the bonding layer 104 a and the bonding layer 104 b may include silicon oxynitride, silicon nitride, or the like.

[0052] Before bonding, at least one of the bonding layers 104a or 104b may be surface treated. The surface treatment may include plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., rinsing with deionized water, etc.), which may be applied to the bonding layer 104a and / or the bonding layer 104b. The semiconductor substrate 100 is then aligned with the semiconductor die 102, and the two are pressed against each other to start pre-bonding of the semiconductor substrate 100 to the semiconductor die 102. The pre-bonding may be performed at room temperature (between about 21 degrees and about 25 degrees). For example, the bonding time may be shorter than about 1 minute. After pre-bonding, the semiconductor substrate 100 and the semiconductor die 102 are bonded to each other. The bonding process may be enhanced by a subsequent annealing process. For example, this may be accomplished by heating the semiconductor substrate 100 and the semiconductor die 102 to a temperature of about 170 degrees for about 1 hour. In an alternative embodiment, hybrid bonding may also be used to bond the semiconductor substrate 100 to the surface of the semiconductor die 102, during which a metal pad is processed in parallel with a dielectric-to-dielectric bonding process at room temperature when forming a pre-bond, and then a metal diffusion bonding is achieved by metal diffusion bonding during annealing.

[0053] After the semiconductor die 102 and the semiconductor substrate 100 are bonded, a thinning process may be applied to the semiconductor die 102. The thinning process may include a grinding or CMP process, an etch back process, or other acceptable processes, performed on the surface 110 of the semiconductor die 102. As a result of this thinning process, the semiconductor die 102 may have a thickness T1 of about 50 μm, and the bonded semiconductor substrate 300 may have a thickness T2 from about 100 μm to about 770 μm. The semiconductor substrate 100 may have a thickness H1 of about 720 μm.

[0054] Figure 1B A mask layer 106 formed and patterned on a semiconductor substrate 100 is shown. The mask layer 106 is patterned to expose the area of ​​the semiconductor substrate where the back cavity will be formed. In some embodiments, the mask layer 106 can be a patterned photoresist layer. Generally speaking, the photoresist layer can be deposited by a process such as spin coating. After the photoresist layer is deposited, it can be patterned by exposing the photoresist layer to a patterned energy source (e.g., patterned light) and a developer. The developer removes the exposed or unexposed portion of the photoresist layer, depending on whether a positive or negative photoresist is used. The remaining portion of the photoresist layer forms the mask layer 106.

[0055] Figure 1C An etching process is shown, which is performed to etch a portion of the semiconductor substrate 100 to form a cavity 900 . Figure 1C It is shown that the above etching process is a highly anisotropic etching process, which etches the semiconductor substrate 100 directionally to form a cavity 900, and the cavity 900 has a sidewall having a specific profile angle α with the top surface of the semiconductor substrate 100. In some embodiments, the etching process can be a dry etching plasma process. The etching process is performed by simultaneously supplying an etching gas and a passivation gas mixture. For example, in an embodiment where the semiconductor substrate 100 includes silicon, the etching gas may include sulfur hexafluoride (SF6), and the passivation gas mixture may include octafluorocyclobutane (C4F8) and oxygen (O2). During the etching process, the plasma is generated by using an electric field of a continuously supplied RF power source, resulting in the simultaneous generation of a deposition plasma from a passivation gas mixture (e.g., C4F8 / O2) and an etching plasma from an etching gas (e.g., SF6). The etching process includes simultaneous deposition and etching portions, which occur due to the simultaneous supply of the etching gas and the passivation gas mixture. As discussed in more detail below, the deposition portion includes forming a passivation layer on the bottom surface and sidewalls of the cavity 900. During the deposition portion, the deposition rate of the passivation layer is the same on the bottom surface and sidewalls of the cavity 900. The etching portion includes etching that occurs in both the horizontal and vertical directions. During the etching portion, the vertical etching rate is greater than the horizontal etching rate. The etching process is performed until the cavity 900 is etched to a desired depth, such as through the semiconductor substrate 100 to the bonding layer 104a / b in this example.

[0056] exist Figure 1C , both the deposition and etching portions of the etching process are shown. These portions occur simultaneously, and control of the deposition rate of the passivation layer, the vertical etching rate, and the horizontal etching rate allows the controlled etching of the cavity 900 to a desired size. The deposition portion includes exciting a passivating gas mixture (e.g., a mixture of C4F8 and O2), using an RF power source and forming a deposition plasma containing C and CF2 radicals. The deposition portion passivates the bottom surface and sidewalls of the cavity 900 by forming a polymer layer 130 on the bottom surface and sidewalls of the cavity 900. The polymer layer 130 protects the sidewalls of the cavity 900 from being etched away by the etching portion of the etching process. The growth rate of the polymer layer 130 is the same or substantially the same on the bottom surface and sidewalls of the cavity 900. For example, the ratio of the deposition rate of the polymer layer 130 on the sidewalls of the cavity 900 to the deposition rate of the polymer layer 130 on the bottom surface of the cavity 900 can be in the range of about 200% to about 100%.

[0057] Figure 1C Also shown is an etching portion of the etching process, which occurs simultaneously with the deposition portion. The etching portion includes vertical etching, removing a portion of the polymer layer 130 formed simultaneously on the bottom surface of the cavity 900 due to the deposition portion of the etching process; and horizontal etching, removing a portion of the polymer layer 130 formed simultaneously on the sidewall of the cavity 900 due to the deposition portion of the etching process. The etching gas (e.g., SF6) is excited by an RF power supply (e.g., disposed on the semiconductor substrate 100) to generate an etching plasma. The excited ions from the etching plasma are accelerated to the bottom surface of the cavity 900 by a separate RF bias power supply (e.g., disposed under the semiconductor substrate 100) to bombard a portion of the polymer layer 130 and remove it from the bottom surface of the cavity 900, leaving the bottom of the cavity 900 exposed. Because the etching plasma is generated directionally, the removal of the polymer layer 130 on the sidewall of the cavity 900 is less significant than the removal of the polymer layer 130 on the bottom surface of the cavity 900. This is because the ions bombarding the sidewalls of the cavity 900 have lower directional kinetic energy than the bottom surface of the cavity 900. Removing the polymer layer 130 less significantly from the sidewalls of the cavity 900 can protect the sidewalls of the cavity 900 from being etched away by the etching portion of the etching process. In addition, removing the polymer layer 130 more significantly from the bottom surface of the cavity 900 can leave a more exposed bottom surface of the cavity 900. Therefore, the bottom surface of the cavity 900 is more easily etched away than the sidewalls of the cavity 900. As a result, although the deposition rate of the passivation layer is the same on the bottom surface and the sidewalls of the cavity 900, the etching process has a higher vertical etching rate than the horizontal etching rate in the etching portion.

[0058] The etching portion of the etching process also includes etching of exposed portions of the semiconductor substrate 100. For example, when excited ions from the etching plasma bombard the bottom surface and sidewalls of the cavity 900, the polymer layer 130 can be removed to expose portions of the semiconductor substrate 100. The etching process includes etching these exposed portions of the semiconductor substrate 100 at the bottom surface and sidewalls of the cavity 900 by reacting with fluorine ions from the etching plasma of the excited etching gas (e.g., SF6). The etching occurs in the portion of the semiconductor substrate 100 where the polymer layer 130 has been removed as described above. Figure 1C Once the simultaneous supply of the etching gas and the passivation gas mixture is provided, the deposition and etching portion of the etching process continues.

[0059] By adjusting the ratio of the flow rate of the passivation gas mixture (e.g., a mixture of C4F8 and O2) to the flow rate of the etching gas (e.g., SF6) and the RF bias power supply, the horizontal etching rate and the vertical etching rate can be controlled. In this way, the cavity 900 can have a sidewall with a controllable profile angle α with the top surface of the semiconductor substrate 100. Reducing the ratio of the flow rate of the passivation gas mixture (e.g., a mixture of C4F8 and O2) to the flow rate of the etching gas (e.g., SF6) results in a reduction in the horizontal etching rate and thus a slower removal of the sidewalls of the cavity 900 and the portion of the polymer layer 130 on the sidewalls of the cavity 900. A lower horizontal etching rate results in an increase in the specific profile angle α with the top surface of the semiconductor substrate 100. Conversely, increasing the ratio of the flow rate of the passivation gas mixture (e.g., a mixture of C4F8 and O2) to the flow rate of the etching gas (e.g., SF6) results in an increase in the horizontal etching rate and thus an increase in the removal of the sidewalls of the cavity 900 and the portion of the polymer layer 130 on the sidewalls of the cavity 900. The above-mentioned increase in the horizontal etching rate may result in a decrease in a specific profile angle α with the top surface of the semiconductor substrate 100 .

[0060] In this way, varying the horizontal etch rate can be used to vary a specific profile angle α with the top surface of the semiconductor substrate 100. In one embodiment, when the horizontal etch rate is negligible, the sidewall of the cavity 900 can have a profile angle α=90°. In one embodiment, when the horizontal etch rate increases, the sidewall of the cavity 900 can have a profile angle α less than 90°, where the horizontal etch rate is not negligible. The degree of difference in the horizontal etch rate of the sidewall of the cavity 900 and the portion of the polymer layer 130 on the sidewall of the cavity 900 can help determine the profile angle α of the sidewall of the cavity 900.

[0061] Adjustment of the RF bias power can also be used to control a specific profile angle α with the top surface of the semiconductor substrate 100. A higher RF bias power will better attract ions to the bottom surface of the cavity 900, resulting in an increase in the vertical etch rate, and may also result in less ion bombardment of the sidewalls of the cavity 900, thereby resulting in less removal of the polymer layer 130. In such an embodiment, horizontal etching is reduced because the unremoved portion of the polymer layer 130 is more protected from horizontal etching. A higher RF bias power can result in a larger profile angle α, while a lower RF bias power can result in a smaller profile angle α.

[0062] Figure 1D Cavity 900 is shown after completion of the etching process. The etching process may result in cavity 900 having portions of polymer layer 130 remaining on the bottom surface and sidewalls of cavity 900. In one embodiment, the etching process may be performed until cavity 900 is etched through semiconductor substrate 100 to bonding layer 104a / b.

[0063] Figure 1E The cavity 900 is shown after the remaining portion of the polymer layer 130 is removed from the bottom surface and sidewalls of the cavity 900 using a suitable etching technique. Figure 1C The etching process shown in can result in the cavity 900 having sidewalls with a profile angle α with the top surface of the semiconductor substrate 100. In one embodiment, the specific profile angle α can range from 55° to 90°. The vertical depth D1 of the cavity can be about 720 μm or less, where the vertical depth D1 is measured from the top surface of the semiconductor substrate 100 to the bottom surface of the cavity, and the etching can expose the bonding layer 104a / b below the semiconductor substrate 100. The width W1 of the cavity 900 can be in the range of about 13 mm to about 17 mm, for example about 14 mm, where the width W1 is measured between the tops of the sidewalls of the cavity 900. The etching process can include etching in both the horizontal and vertical directions, resulting in linear surfaces on the sidewalls of the cavity 900. The size of the horizontal etching on the sidewall can decrease in proportion to the increase in the vertical depth from the top surface of the semiconductor substrate 100. For example, at a vertical depth D2 from the top surface of the semiconductor substrate 100, the horizontal width of the sidewall of the cavity 900 from a point at the bottom of the sidewall of the cavity 900 may be W2. At a vertical depth D3 from the top surface of the semiconductor substrate 100, the horizontal width of the sidewall of the cavity 900 from a point at the bottom of the sidewall of the cavity 900 may be W3, where D3 is greater than D2 and W3 is less than W2. In some embodiments, the higher the ratio of W2 to W3, the smaller the specific profile angle α.

[0064] In some examples, the passivation gas mixture is supplied at a higher flow rate than the etching gas. In one embodiment, the passivation gas mixture comprises C4F8 / O2 and is provided at a flow rate from about 500sccm to about 1600sccm, for example, about 953sccm, and the etching gas comprising SF6 is provided at a flow rate from about 150sccm to about 550sccm, for example, about 355sccm. In some examples, the passivation gas mixture flow rate during the etching process can have a ratio in the range of from about 4:1 to about 0.5:1 to the etching gas flow rate, for example, about 2.7:1. In some examples, the dry plasma etching process includes RF source power, RF secondary power, and RF bias power. The RF power supply may be in the range of about 1000 watts to about 3000 watts, for example, about 2800 watts, the RF secondary power supply may be in the range of about 500 watts to about 2000 watts, for example, about 800 watts, and the RF bias power supply may be in the range of about 50 watts to about 500 watts, for example, about 240 watts, at a frequency in the range of about 10 MHz to about 15 MHz, for example, about 13.56 MHz. The RF power supply, the RF secondary power supply, and the RF bias power supply may be supplied continuously, and the RF power supply and the RF secondary power supply are used to generate etching plasma. The RF bias power supply is used to accelerate ions to bombard the bottom surface of the etched cavity 900. The process pressure is controlled in the range of about 16 mTorr to about 300 mTorr, for example, about 150 mTorr. The substrate temperature is controlled at about 0 degrees Celsius to about 50 degrees Celsius, for example, about 5 degrees Celsius.

[0065] In some embodiments, the profile angle α can be in a range from 55° to 90°. In some examples, when the ratio of the passivation gas mixture (C4F8 / O2) flow rate to the etching gas (O2) flow rate during the etching process is about 2.7:1, the specific profile angle α is 80°. In other examples, when the ratio of the passivation gas mixture (C4F8 / O2) flow rate to the etching gas (O2) flow rate during the etching process is about 1:1, the specific profile angle α is 55°. In some embodiments, when the ratio of the passivation gas mixture (C4F8 / O2) flow rate to the etching gas (O2) flow rate during the etching process is about 2.7:1 and the RF bias power is 190 watts, the specific profile angle α is 80°. In other embodiments, when the ratio of the passivation gas mixture (C4F8 / O2) flow rate to the etching gas (O2) flow rate during the etching process is about 2.7:1 and the RF bias power is 50 watts, the specific profile angle α is 55°. As previously described, the specific profile angle α can be adjusted by changing the ratio of the passivation gas flow rate to the etching gas flow rate and / or the RF bias power.

[0066] Figure 2An etching system 700 is shown according to one embodiment of the present disclosure. Figure 2 As shown, the etching system includes a chamber 710 and a platen 760, and a wafer 800 can be processed on the platen 760. The temperature of the platen 760 can be controlled by controlling the flow of helium gas to the platen 760 to maintain a desired temperature. The wafer 800 can be held in place by, for example, an electrostatic chuck (not shown) on the top surface of the platen 760. The wafer 800 can include multiple devices, such as a bonded semiconductor substrate 300, at some stage of the manufacturing process. For example, the wafer 800, when initially loaded onto the platen 760, can be Figure 1B The stage shown includes a plurality of bonded semiconductor substrates 300, so that the mask layer 106 exposes the semiconductor substrate 100 ready to be formed by an etching process. Figure 1E The area of ​​the cavity 900 shown in FIG. Figure 1A to Figure 1E As described above, the chamber 710 is used as an etching chamber to perform an etching process to recess the semiconductor substrate 100 .

[0067] Reference Figure 2 , the etching system 700 includes a primary gas inlet 720, which is located above the top surface of the wafer 800 and the platform 760. There are also two secondary gas inlets 740, located at the edge and on the opposite sides of the wafer 800 and the platform 760. The secondary gas inlets 740 are used to evenly distribute the gas and to help maintain process uniformity across the wafer 800. Although Figure 2 Two secondary gas inlets 740 are shown in FIG. 7 , and more or less than two secondary gas inlets 740 may be used to control the distribution of the gas entering the chamber 710. The primary gas inlet 720 and the secondary gas inlet 740 are used to supply the reaction gas into the chamber.

[0068] like Figure 2 As shown, etching system 700 also includes two gas outlets 780. Figure 2 Two gas outlets are shown in FIG. 7 , and any number of gas outlets 780 may be used in the etching system 700. Air and gas may be pumped out at the same time. The chamber 710 forms a closed space during the process, and removing air or gas from the chamber 710 allows the desired pressure level to be maintained.

[0069] Also shown in Figure 2, the etching system 700 includes multiple RF power supplies. RF power supply 730 generates plasma above the top surface of the wafer 800 and the platform 760. Two other power supplies, RF sub-power supplies 750, generate plasma at the edge and opposite sides of the wafer 800. The RF sub-power supplies are used to evenly distribute the plasma to help maintain process uniformity across the wafer 800. Although in Figure 2 Two RF sub-power sources 750 are shown, more or less than two sub-power sources may be used. The etching system also includes an RF bias power source 770 to accelerate the generated plasma to the surface of the wafer 800.

[0070] Figure 2 This is just a simplified example, and a person skilled in the art will appreciate many variations. As an example, the shape of the cavity 710 can have different shapes, for example, a cylinder, a cone, or other suitable shapes. A person skilled in the art will also appreciate that Figure 2 Not all components of the etching system are shown. For example, a loading unit for loading and unloading wafers 800 is not shown. Figure 2 As another example, a gas supply (not shown) for mixing different reaction gases may include a mixer (not shown) and a pump (not shown) for pumping the gas into the chamber 710.

[0071] FIG. 3A to FIG. 3D Shown in reference to the previous Figures 1A to 1E The present invention further intermediate steps in the manufacture of the device of the present invention. After forming the cavity 900, the exposed portion of the bonding layer 104a / b in the cavity 900 is removed. The exposed portion of the bonding layer 104a / b in the cavity 900 can be removed by an acceptable dry and / or wet etching process. For example, in an embodiment where the bonding layer 104a / b includes silicon oxide, a dry etching process using a mixture of nitrogen trifluoride (NF3) and ammonia (NH3) can be used. Alternatively, a mixture of hydrogen fluoride (HF) and ammonia can be used. A portion of the top surface of the semiconductor die 102 can be exposed through the bottom of the cavity 900.

[0072] Figure 3BAccording to some embodiments, the mask layer 106 is removed from the top surface of the semiconductor substrate 100. The photoresist 106 can be removed using a suitable photoresist stripping technique, such as chemical solvent cleaning, plasma ashing, dry stripping, and / or the like. In some embodiments, a vertical depth E2 from the top surface of the semiconductor substrate 100 to the bottom of the cavity 900 exceeds a thickness E1 of the semiconductor die 102. In one embodiment, the vertical depth E2 from the top surface of the semiconductor substrate 100 to the bottom of the cavity 900 can be in a range of about 50 μm to about 770 μm, for example, about 720 μm, and the thickness E1 of the semiconductor die 102 can be in a range of about 20 μm to about 500 μm, for example, about 50 μm.

[0073] Figure 3C The deposition of a thin film layer 128 on the upper surface of the semiconductor substrate 100, and the sidewalls and bottom surface of the cavity 900 is shown. In some embodiments, the thin film layer 128 may include titanium (Ti) or gold (Au). The thin film layer 128 may be formed by physical vapor deposition (PVD) and / or other suitable methods. In some embodiments, the cavity 900 may have a sidewall having a profile angle α with the top surface of the semiconductor substrate 100, and may therefore have a better physical vapor deposition (PVD) process step coverage on the sidewall of the cavity 900.

[0074] Figure 3D The bonded semiconductor substrate 300 is shown placed on a frame, which includes a metal ring and a dicing tape thereon. In some embodiments, the bonded semiconductor substrate 300 can then be cut using a die saw to singulate the wafer into individual components.

[0075] Figure 4 1 shows another embodiment, where an etching process is performed on a bonded substrate 600. The bonded semiconductor substrate 600 may include a semiconductor substrate 400 and a semiconductor die 402. The bonded semiconductor substrate 600 and the bonded semiconductor substrate 300 may be described above with respect to Figure 1A The features discussed are similar, wherein similar features are formed using similar processes. Figure 1AIn the features discussed, the semiconductor substrate 400 and the semiconductor die 402 may also be similar to the semiconductor substrate 100 and the semiconductor die 102, respectively. Further description of these features is omitted for brevity. An etching process may be used to form the cavity 1800. The etching process may cause the cavity 1800 to have sidewalls having a profile angle β with the top surface of the semiconductor substrate 400. The etching process performed may include a first etching process, followed by a second etching process after the first etching process, wherein the second etching process etches the semiconductor substrate 400 in both vertical and horizontal directions. The first etching process creates a first etched portion in the cavity 1800 having sidewalls with linear surfaces, and the sidewalls have a vertical depth D4 from the top surface of the semiconductor substrate 400. The first etching process may be similar to the above description regarding Figure 1C The etching process described is similar. For example, during the first etching process, the flow rate of the passivation gas mixture (e.g., C4F8 / O2) and the flow rate of the etching gas (e.g., SF6) can have a ratio of about 2.7:1. The RF power source power can be about 2800 watts, the RF secondary power source can be about 800 watts, and the RF bias power source can be about 190 watts, at a frequency in the range of about 10 MHz to about 15 MHz, for example, about 13.56 MHz. The RF power source power, the RF secondary power source, and the RF bias power source can be continuously supplied during the first etching process.

[0076] The second etching process occurs after the first etching process is completed, and a second etched portion is formed in the cavity 1800, which has a sidewall with a nonlinear surface. During the second etching process, the passivation gas mixture (e.g., C4F8 / O2) and the etching gas (e.g., SF6) can be the same as those used during the first etching process. The sidewall of the cavity 1800 is etched without a specific directionality, resulting in a nonlinear surface with a radius of curvature R1 on the sidewall, and a second etched portion in the cavity 1800, which has a nonlinear surface with a vertical depth D5, wherein the vertical depth D5 is measured from the point where the second etching process on the sidewall is started to the bottom of the cavity 1800. The transition from the first etching process to the second etching process can occur when the RF bias power is gradually increased over time to change the etching profile of the sidewall of the cavity 1800. In one embodiment, during the second etching process, the flow rate of the passivation gas mixture (e.g., C4F8 / O2) and the flow rate of the etching gas (e.g., SF6) can have a ratio of about 2.7:1. The RF power source power may be about 2800 watts, and the RF secondary power source may be about 800 watts, at a frequency in the range of about 10 MHz to about 15 MHz, for example about 13.56 MHz. The RF power source power and the RF secondary power source may be supplied continuously. The RF bias power source may be gradually increased during the second etching process from an RF bias power source of about 190 watts at the beginning of the second etching process to about 240 watts at the end of the second etching process. The second etching process may cause the sidewall of the cavity 1800 to have a nonlinear surface with a radius of curvature R1 of about 380 μm at a vertical depth D5, wherein the vertical depth D5 is measured from a point on the sidewall where the second etching process starts to the bottom of the cavity 1800.

[0077] Figure 5 1 shows another embodiment, in which an etching process is performed on a bonded semiconductor substrate 1000. The bonded semiconductor substrate 1000 may include a semiconductor substrate 500 and a semiconductor die 502. The bonded semiconductor substrate 1000 and the bonded semiconductor substrate 300 may be formed as described above with respect to Figure 1A The features discussed are similar, wherein similar features are formed using similar processes. Figure 1AThe semiconductor substrate 500 and the semiconductor die 502 may also be similar to the semiconductor substrate 100 and the semiconductor die 102, respectively, in the features discussed. Further description of these features is omitted for brevity. An etching process may be used to form the cavity 2700. The etching process performed may include a first etching process, followed by a second etching process after the first etching process, wherein the second etching process etches the semiconductor substrate 500 in both vertical and horizontal directions. The first etching process creates a first etched portion in the cavity 2700 having a sidewall with a linear surface, the sidewall having a vertical depth D6 from the top surface of the semiconductor substrate 500. The first etched portion may have a sidewall having a profile angle γ with the top surface of the semiconductor substrate 500. The first etching process may be similar to the above description regarding Figure 1C The described etching processes are similar and may use similar passivation gas mixture (eg, C4F8 / O2) flow rates with etching gas (eg, SF6).

[0078] The second etching process occurs after the first etching process is completed, and a second etched portion is formed in the cavity 2700, which has a sidewall with a linear surface, and the sidewall has a vertical depth D7 measured from the point on the sidewall where the second etching process starts to the bottom of the cavity 2700. The second etched portion may have a sidewall with a profile angle δ with a line parallel to the top surface of the semiconductor substrate 500, wherein the profile angle γ of the first etched portion is not equal to the profile angle δ of the second etched portion. This difference in profile angles can be achieved by changing the ratio of the flow rate of the passivation gas mixture (e.g., C4F8 / O2) and the flow rate of the etching gas (e.g., SF6) between the first etching portion and the second etching portion and / or the RF bias power supply.

[0079] use Figures 1A to 5 The various formation steps shown in the can form a back cavity in a device (e.g., a light emitting diode (LED) device, a microelectromechanical system (MEMS) device, etc.). The described process and apparatus disclose a method for dry etching, which is applied to, but not limited to, forming a silicon back cavity with a controllable etch profile angle. Advantageous features of one or more of the disclosed embodiments can include the ability to control the etch profile angle and provide better deposition (e.g., physical vapor deposition (PVD)) step coverage on the back cavity wall. Another advantageous feature is the ability to form a back cavity with sidewalls having more than one etch profile angle. By using an embodiment such as one of those disclosed embodiments, the dependence on a specific crystallographic orientation of the silicon wafer is less, where the dependence on a specific crystallographic orientation of the silicon wafer is, for example, the case in a wet etching process. In addition, some embodiments can reduce the need for one or more mask layers when forming the back cavity, simplifying the process and making it more cost-effective.

[0080] According to one embodiment, a method includes: bonding a first surface of a first semiconductor substrate to a first surface of a second semiconductor substrate; patterning a mask layer on the second surface of the first semiconductor substrate to expose a first region of the first semiconductor substrate, the second surface being opposite to the first surface; and forming a cavity in the first region of the first semiconductor substrate, wherein forming the cavity includes: supplying a passivation gas mixture, depositing a passivation layer on a bottom surface and a plurality of sidewalls of the cavity, wherein during the deposition of the passivation layer, a deposition rate of the passivation layer on the bottom surface of the cavity is the same as a deposition rate of the passivation layer on the plurality of sidewalls of the cavity; and etching the first region of the first semiconductor substrate using an etching gas, wherein the etching gas is supplied simultaneously with the passivation gas mixture, and etching the first region of the first semiconductor substrate includes etching at a rate in a vertical direction greater than etching at a rate in a horizontal direction. In one embodiment, the passivation gas mixture includes octafluorocyclobutane (C4F8) and oxygen (O2), and the etching gas includes sulfur hexafluoride (SF6). In one embodiment, a ratio of a flow rate of C4F8 / O2 to a flow rate of SF6 is in a range of 4:1 to 0.5:1. In one embodiment, forming the cavity causes a plurality of sidewalls of the cavity to have a profile angle with the top surface of the first semiconductor substrate, wherein the profile angle is in a range of 55° to 90°. In one embodiment, forming the cavity causes the cavity to have a vertical depth of 720 μm or less, the vertical depth being measured from the top surface of the first semiconductor substrate to the bottom surface of the cavity. In one embodiment, forming the cavity causes the cavity to have a width, measured from the top end of the first sidewall of the cavity to the top end of the second sidewall of the cavity, the width being approximately 17 mm or less. In one embodiment, the method further includes thinning the second surface of the second semiconductor substrate using a grinding process, causing the second semiconductor substrate to have a thickness of approximately 50 μm. In one embodiment, the vertical depth of the cavity is greater than the thickness of the second semiconductor substrate, wherein the vertical depth is measured from the top surface of the first semiconductor substrate to the bottom surface of the cavity.

[0081] According to yet another embodiment, a method includes: bonding a first semiconductor substrate to a second semiconductor substrate; patterning a mask layer on an unbonded surface of the first semiconductor substrate; and using the mask layer as a patterned mask to etch a cavity in the first semiconductor substrate, wherein etching the cavity includes: generating a deposition plasma by exciting a passivation gas mixture, the deposition plasma depositing a passivation layer on a bottom surface and a plurality of sidewalls of the cavity, wherein a deposition rate of the passivation layer on the bottom surface of the cavity is the same as a deposition rate of the passivation layer on the plurality of sidewalls of the cavity; and generating an etching plasma by exciting an etching gas, wherein generating the etching plasma occurs simultaneously with generating the deposition plasma, a first RF power source accelerates a plurality of ions from the etching plasma to the bottom surface of the cavity, wherein a vertical etching rate of the etching plasma is more significant than a horizontal etching rate of the etching plasma. In one embodiment, depositing the passivation layer includes the deposition plasma depositing a polymer layer on the bottom surface and a plurality of sidewalls of the cavity. In one embodiment, a second RF power source excites the passivation gas mixture and the etching gas. In one embodiment, the first RF power source is disposed below the second semiconductor substrate, and the second RF power source is disposed above the unbonded surface of the first semiconductor substrate. In one embodiment, patterning the mask layer includes patterning a photoresist layer on an unbonded surface of the first semiconductor substrate. In one embodiment, the method further includes forming a first portion of the cavity, the first portion of the cavity having a plurality of linear sidewalls, the sidewalls of the first portion of the cavity having a profile angle with the top surface of the first semiconductor substrate, wherein the profile angle is in the range of 55° to 90°; and forming a second portion of the cavity, the second portion of the cavity having a plurality of non-linear sidewalls, the sidewalls of the second portion of the cavity having a radius of curvature R1, wherein R1 is in the range of 200um to 800um. In one embodiment, forming the second portion of the cavity includes gradually increasing the magnitude of the first RF power source over time. In one embodiment, when the first portion of the cavity is formed, the ratio of the flow rate of C4F8 / O2 to the flow rate of SF6 is lower than 2.7:1, and the profile angle of the sidewalls of the first portion of the cavity is greater than 80°. In one embodiment, when the first portion of the cavity is formed, the ratio of the flow rate of C4F8 / O2 to the flow rate of SF6 is higher than 2.7:1, and the profile angle of the sidewalls of the first portion of the cavity is less than 80°.

[0082] According to one embodiment, a semiconductor device includes: a first semiconductor substrate; a second semiconductor substrate bonded to the first semiconductor substrate; and a cavity extending through the first semiconductor substrate, the cavity including: a top portion having a plurality of sidewalls having a first sidewall profile; and a bottom portion having a plurality of sidewalls having a second sidewall profile, the sidewalls of the top portion of the cavity having a first profile angle with a top surface of the first semiconductor substrate, and the sidewalls of the bottom portion of the cavity having a second profile angle with a top surface of the first semiconductor substrate, wherein the first profile angle is different from the second profile angle. In one embodiment, the first semiconductor substrate includes a <100> , <110> ,or <110> In one embodiment, the first profile angle and the second profile angle are respectively in the range of 55° to 90°.

[0083] The above summarizes the components of several embodiments so that those skilled in the art can more easily understand the concepts of the embodiments of the present invention. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and replacements without violating the spirit and scope of the appended claims.

Claims

1. A method for forming a semiconductor device, comprising: Bonding a first surface of a first semiconductor substrate to a first surface of a second semiconductor substrate; patterning a mask layer on a second surface of the first semiconductor substrate to expose a first region of the first semiconductor substrate, the second surface being opposite to the first surface; as well as A cavity is formed in the first region of the first semiconductor substrate, wherein a dielectric layer on the second semiconductor substrate is exposed after forming the cavity, and wherein forming the cavity comprises: supplying a passivation gas mixture to deposit a passivation layer on a bottom surface and a plurality of sidewalls of the cavity, wherein during the deposition of the passivation layer, a deposition rate of the passivation layer on the bottom surface of the cavity is the same as a deposition rate of the passivation layer on the plurality of sidewalls of the cavity; and The first region of the first semiconductor substrate is etched using an etching gas, wherein the etching gas is supplied simultaneously with the passivating gas mixture, and etching the first region of the first semiconductor substrate includes etching at a rate in a vertical direction greater than etching at a rate in a horizontal direction. 2 . The method for forming a semiconductor device as claimed in claim 1 , wherein the passivation gas mixture comprises octafluorocyclobutane and oxygen, and the etching gas comprises sulfur hexafluoride.

3. The method for forming a semiconductor device as claimed in claim 2, wherein the ratio of the flow rate of octafluorocyclobutane and oxygen to the flow rate of sulfur hexafluoride is in the range of 4:1 to 0.5:

1. 4 . The method for forming a semiconductor device as claimed in claim 1 , wherein forming the cavity results in a plurality of sidewalls of the cavity having a profile angle with a top surface of the first semiconductor substrate, wherein the profile angle is in a range of 55° to 90°. 5 . The method for forming a semiconductor device as claimed in claim 1 , wherein forming the cavity results in the cavity having a vertical depth of 720 μm or less, the vertical depth being measured from a top surface of the first semiconductor substrate to the bottom surface of the cavity.

6. The method for forming a semiconductor device as claimed in claim 1, wherein forming the cavity causes the cavity to have a width, measured from a top end of a first sidewall of the cavity to a top end of a second sidewall of the cavity, of 17 mm or less. 7 . The method for forming a semiconductor device as claimed in claim 1 , further comprising thinning a second surface of the second semiconductor substrate by a grinding process, so that the second semiconductor substrate has a thickness of about 50 μm. 8 . The method for forming a semiconductor device as claimed in claim 1 , wherein a vertical depth of the cavity is greater than a thickness of the second semiconductor substrate, wherein the vertical depth is measured from a top surface of the first semiconductor substrate to the bottom surface of the cavity.

9. A method for forming a semiconductor device, comprising: bonding a first semiconductor substrate to a second semiconductor substrate; patterning a mask layer on an unbonded surface of the first semiconductor substrate; as well as Using the mask layer as a patterned mask to etch a cavity in the first semiconductor substrate, wherein a dielectric layer on the second semiconductor substrate is exposed after etching the cavity, and wherein etching the cavity comprises: Exciting a passivation gas mixture to generate a deposition plasma, the deposition plasma depositing a passivation layer on a bottom surface and a plurality of sidewalls of the cavity, wherein a deposition rate of the passivation layer on the bottom surface of the cavity is the same as a deposition rate of the passivation layer on the plurality of sidewalls of the cavity; as well as An etching plasma is generated by exciting an etching gas, wherein the etching plasma is generated simultaneously with the deposition plasma, and a first radio frequency power source accelerates a plurality of ions from the etching plasma to the bottom surface of the cavity, wherein a vertical etching rate of the etching plasma is more significant than a horizontal etching rate of the etching plasma. 10 . The method for forming a semiconductor device as claimed in claim 9 , wherein depositing the passivation layer comprises depositing a polymer layer on the bottom surface and a plurality of sidewalls of the cavity by the deposition plasma. 11 . The method for forming a semiconductor device as claimed in claim 9 , wherein a second radio frequency power source excites the passivation gas mixture and the etching gas. 12 . The method for forming a semiconductor device as claimed in claim 11 , wherein the first RF power source is disposed below the second semiconductor substrate, and the second RF power source is disposed above the unbonded surface of the first semiconductor substrate. 13 . The method for forming a semiconductor device as claimed in claim 9 , wherein patterning the mask layer comprises patterning a photoresist layer on the unbonded surface of the first semiconductor substrate.

14. The method for forming a semiconductor device according to claim 9, wherein forming the cavity further comprises: forming a first portion of the cavity, the first portion of the cavity having a plurality of linear sidewalls, the plurality of sidewalls of the first portion of the cavity having a profile angle with a top surface of the first semiconductor substrate, wherein the profile angle is in a range of 55° to 90°; as well as A second portion of the cavity is formed, the second portion of the cavity having a plurality of non-linear side walls, the plurality of side walls of the second portion of the cavity having a curvature radius R1, wherein R1 is in a range of 200um to 800um. 15 . The method for forming a semiconductor device as claimed in claim 14 , wherein forming the second portion of the cavity comprises gradually increasing the magnitude of the first RF power source over time.

16. The method for forming a semiconductor device as claimed in claim 14, wherein when forming the first portion of the cavity, the ratio of the flow rate of octafluorocyclobutane and oxygen to the flow rate of sulfur hexafluoride is lower than 2.7:1, and the profile angle of the plurality of sidewalls of the first portion of the cavity is greater than 80°.

17. The method for forming a semiconductor device as claimed in claim 14, wherein when forming the first portion of the cavity, the ratio of the flow rate of octafluorocyclobutane and oxygen to the flow rate of sulfur hexafluoride is higher than 2.7:1, and the profile angle of the plurality of sidewalls of the first portion of the cavity is less than 80°.

18. A semiconductor device comprising: a first semiconductor substrate; a second semiconductor substrate bonded to the first semiconductor substrate; as well as a cavity extending through the first semiconductor substrate and exposing a dielectric layer on the second semiconductor substrate, wherein the cavity comprises: a top portion having a plurality of sidewalls having a first sidewall profile; as well as A bottom portion has a plurality of sidewalls having a second sidewall profile, the plurality of sidewalls at the top of the cavity have a first profile angle with a top surface of the first semiconductor substrate, the plurality of sidewalls at the bottom of the cavity have a second profile angle with a top surface of the first semiconductor substrate, wherein the first profile angle is different from the second profile angle.

19. The semiconductor device according to claim 18, wherein the first semiconductor substrate comprises <100> , <110> or <110> Family of crystallographic orientations of silicon. 20 . The semiconductor device of claim 18 , wherein the first profile angle and the second profile angle are respectively in a range of 55° to 90°.

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