Electronic device comprising a level shifter

Abstract

An electronic device including a level shifter is disclosed. The level shifter includes a level shifting circuit, a first adjustment circuit, and a second adjustment circuit. The level shifting circuit determines whether to output a first current from a power voltage line to an output node based on a voltage level of a first node, and determines whether to output a second current from the power voltage line to a third node based on a voltage level of a second node. The first adjustment circuit prevents output of a third current from the third node to the first node when a clock signal having a first voltage level is received. The second adjustment circuit outputs a fourth current from the first node to a ground voltage line when a clock signal having the first voltage level is received.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0007139, filed on January 20, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] Some example embodiments of the inventive concepts described herein relate to electronic devices including a level shifter, and more particularly, to electronic devices including a level shifter that generates an output voltage different from an input voltage based on the input voltage. BACKGROUND

[0003] Electronic devices can include various elements. The various elements can operate in the same voltage domain, or can operate in different voltage domains. Elements belonging to the same voltage domain can operate by using the same supply voltage and the same ground voltage. Elements belonging to different voltage domains can operate by using different supply voltages and different ground voltages.

[0004] For example, a memory can generate a clock signal having a lower voltage than a voltage applied from the outside. The memory can ignore noise occurring at the external voltage by generating the clock signal having the lower voltage. However, in order to input the clock signal to a device in the memory, it can be necessary to increase the voltage level of the clock signal again. The memory can increase the voltage level of the clock signal again by using a level shifter.

[0005] As such, the level shifter can convert a signal belonging to one voltage domain (e.g., a signal that swings between one supply voltage and one ground voltage) into a signal belonging to another voltage domain (e.g., a signal that swings between another supply voltage and another ground voltage). SUMMARY

[0006] Some example embodiments of the inventive concepts provide electronic devices including a level shifter capable of reducing distortion of a duty cycle of an output voltage.

[0007] According to an example embodiment, an electronic device can include a clock generator and a level shifter. The clock generator can output a clock signal that swings between a first voltage level and a second voltage level. When the clock signal having the second voltage level is received, the level shifter can be configured to block output of a first current from a supply voltage line to a first node regardless of a voltage level of an output node, output a second current from the first node to a ground voltage line, and output a third current from the supply voltage line to the output node based on a voltage level of the first node. The second voltage level can be higher than the first voltage level, and can be lower than a voltage level of the supply voltage line.

[0008] According to an example embodiment, an electronic device can include a level shifter circuit, a first adjustment circuit, and a second adjustment circuit. The level shifter circuit can determine whether to output a first current from a power voltage line to an output node based on a voltage level of a first node, and can determine whether to output a second current from the power voltage line to a third node based on a voltage level of a second node. The first adjustment circuit can prevent output of a third current from the third node to the first node when a clock signal having a first voltage level is received. The second adjustment circuit can output a fourth current from the first node to a ground voltage line when the clock signal having the first voltage level is received. The clock signal can be a signal that swings between the first voltage level and a second voltage level lower than the first voltage level. The first voltage level can be lower than a voltage level of the power voltage line.

[0009] According to an example embodiment, an electronic device can include a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a third PMOS transistor, and a second NMOS transistor. The first PMOS transistor can determine whether to connect a power voltage line with a second node based on a voltage level of a first node. The second PMOS transistor can determine whether to connect the second node with a third node based on a clock signal that swings between a first voltage level and a second voltage level. The first NMOS transistor can determine whether to connect the third node with a ground voltage line based on the clock signal. The third PMOS transistor can determine whether to connect the power voltage line with an output node based on a voltage level of the third node. The second NMOS transistor can determine whether to connect the first node with the ground voltage line based on an inverted clock signal, a phase of which corresponds to an inverted version of a phase of the clock signal. The first voltage level can be higher than the second voltage level, and can be lower than a voltage level of the power voltage line. BRIEF DESCRIPTION OF DRAWINGS

[0010] The above and other objects and features of the inventive concept will become apparent from a detailed description of some example embodiments of the inventive concept with reference to the accompanying drawings.

[0011] Figure 1 is a block diagram of a semiconductor device according to an example embodiment of the inventive concept.

[0012] Figure 2 is a block diagram illustrating a conventional level shifter.

[0013] Figure 3 is a graph for describing waveform distortion of an output voltage occurring in a level shifter of Figure 2

[0014] Figure 4 is a block diagram illustrating a level shifter according to an example embodiment of the inventive concept.

[0015] ​Figure 5 is a circuit diagram illustrating a level shifter of Figure 4 .

[0016] Figure 6 is a graph for describing how an output voltage of Figure 5 has a rising transition.

[0017] Figure 7 is a graph for describing how an output voltage of Figure 5 has a falling transition.

[0018] Figure 8 is a graph illustrating a waveform of an output voltage of Figure 5 .

[0019] Figure 9 is a circuit diagram illustrating an embodiment of a level shifter of Figure 4 .

[0020] Figure 10 a memory module according to an example embodiment of the inventive concept is shown. DETAILED DESCRIPTION

[0021] Hereinafter, some example embodiments of the inventive concept can be described in detail to such an extent that a person of ordinary skill in the art can easily implement the inventive concept.

[0022] Figure 1 is a block diagram of a semiconductor device according to an example embodiment of the inventive concept. Referring to Figure 1 , the semiconductor device 10 can include a memory controller 100 and a memory device 200.

[0023] The memory device 200 can receive a clock signal CK, a reset signal RESET, a command CMD, and an address ADD from the memory controller 100. The memory device 200 can operate in synchronization with the clock signal CK. In one example embodiment, the memory device 200 can be a dynamic random access memory (DRAM). However, the inventive concept can not be limited thereto. For example, the memory device 200 can include a volatile memory such as a static RAM (SRAM) or a synchronous DRAM (SDRAM) or a non-volatile memory such as a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), or a ferroelectric RAM (FRAM).

[0024] In order to describe the operation and effects of the inventive concept, a detailed description of related art will be omitted. Figure 1A level shifter 220 included in the memory device 200 is shown in FIG. 2, but the inventive concept is not limited thereto. The level shifter according to example embodiments of the inventive concept can represent an electronic circuit of an electronic device that converts a signal belonging to one voltage domain into a signal belonging to another voltage domain.

[0025] After the power of the semiconductor device 10 is turned on, the memory controller 100 can transmit a reset signal RESET to the memory device 200. The memory device 200 can receive the reset signal RESET to perform a reset operation. The memory device 200 can perform an initialization operation according to the reset operation. In some example embodiments, the memory device 200 can receive a separate initialization command together with the reset signal RESET to perform the initialization operation.

[0026] The memory device 200 can perform an operation corresponding to a command CMD. In one example embodiment, the command CMD can include an activate command ACT, a read command RD, and a write command WR. The memory device 200 can perform a read operation and a write operation based on an address ADD.

[0027] The memory device 200 can exchange a data strobe signal DQS and a data signal DQ with the memory controller 100. The memory controller 100 can output the data strobe signal DQS and the data signal DQ to request a write operation to the memory device 200. In addition, the memory controller 100 can output a clock signal CK and a command CMD to request a read operation to the memory device 200. The memory device 200 can output the data strobe signal DQS and the data signal DQ based on the clock signal CK and the command CMD. For example, in the case of receiving a read command, the memory device 200 can delay the clock signal CK to generate the data strobe signal DQS. The memory device 200 can transmit the data signal DQ including read data to the memory controller 100 together with the data strobe signal DQS.

[0028] The memory device 200 can include a delay-locked loop (DLL) 210, a level shifter 220, and a data output circuit 230. The delay-locked loop 210 can delay a clock signal CK to output an internal clock signal. The level shifter 220 can adjust a voltage level of the internal clock signal output from the delay-locked loop 210. The level shifter 220 can generate a data strobe signal DQS based on the internal clock signal whose voltage level is adjusted. The data output circuit 230 can output a data signal DQ together with the data strobe signal DQS. The data output circuit 230 can include a driver (not shown) for driving an output of each signal.

[0029] Further, the data output circuit 230 can output the internal clock signal to components in the memory device 200. The components in the memory device 200 can operate in synchronization with the internal clock signal.

[0030] The delay-locked loop 210 can output the internal clock signal by delaying the clock signal CK by a determined delay amount. The phase of the internal clock signal can be locked according to the determined delay amount. The delay-locked loop 210 can generate the internal clock signal by delaying the clock signal CK by using an external voltage applied from the outside. The voltage level of the internal clock signal can be different from the voltage level of the external voltage. For example, the voltage level of the internal clock signal can be lower than the voltage level of the external voltage. In the case where the voltage level of the external voltage is 1.5V, the voltage level of the internal clock signal can be 1.1V. Since the delay-locked loop 210 reduces the voltage level of the external voltage to generate the internal clock signal, the delay-locked loop 210 can not have an influence of noise occurring in the external voltage.

[0031] In order for the components in the memory device 200 to operate based on the internal clock signal, it is desired to adjust the voltage level of the internal clock signal to the voltage level of the external voltage again. The level shifter 220 can increase the voltage level of the internal clock signal output from the delay-locked loop 210 again. The components in the memory device 200 can operate in synchronization with the internal clock signal whose voltage level is adjusted.

[0032] In the case where the imbalance between the pull-up and the pull-down of the output voltage is increased in the process of adjusting the voltage level of the internal clock signal, the components in the memory device 200 can abnormally operate. In the specification, the imbalance between the pull-up and the pull-down indicates that the difference between the length of time required for the pull-up and the length of time required for the pull-down is great. According to an example embodiment of the inventive concept, the level shifter can pull up and pull down the output voltage more quickly according to the change of the input voltage. Further, the level shifter can reduce the imbalance between the pull-up and the pull-down of the output voltage, so that the waveform distortion and the duty cycle distortion of the output voltage are reduced.

[0033] Figure 2 is a block diagram illustrating a conventional level shifter.

[0034] The clock generator 310 can output a clock signal CLK0 that swings between a first voltage level and a second voltage level. The second voltage level can be higher than the first voltage level. The clock signal CLK0 generated from the clock generator 310 can be input to the level shifter 320.

[0035] The level shifter 320 can receive the clock signal CLK0, the power supply voltage VDD, and the ground voltage VSS. The level shifter 320 can output the voltage V1 based on the clock signal CLK0, the power supply voltage VDD, and the ground voltage VSS. A voltage level difference between the power supply voltage VDD and the ground voltage VSS can be greater than a difference between the first voltage level and the second voltage level. In the following description, it is assumed that a voltage level of the power supply voltage VDD is higher than the second voltage level, and a voltage level of the ground voltage VSS is equal to the first voltage level, but the inventive concept is not limited thereto.

[0036] The voltage V1 can be in the form of a clock signal that swings between certain voltages. The voltage V1 can repeat a rising transition and a falling transition as the clock signal CLK0 transitions. A voltage level of the pulled-up voltage V1 can be higher than the second voltage level. In the following description, it is assumed that the voltage level of the pulled-up voltage V1 is equal to the voltage level of the power supply voltage VDD, but the inventive concept is not limited thereto. The voltage level of the pulled-up voltage V1 can be a voltage level between the second voltage level and the voltage level of the power supply voltage VDD.

[0037] A voltage level difference between the pulled-up voltage V1 and the pulled-down voltage V1 can be greater than a difference between the first voltage level and the second voltage level. In the following description, it is assumed that the voltage level of the pulled-up voltage V1 is higher than the second voltage level, and the voltage level of the pulled-down voltage V1 is equal to the first voltage level, but the inventive concept is not limited thereto.

[0038] The level shifter 320 can include transistors 321 to 324. The transistors 321 and 322 can be cross-coupled and can be PMOS transistors. The transistors 323 and 324 can be connected with the transistors 321 and 322, respectively, and can be NMOS transistors.

[0039] The transistor 321 can be disposed between a power supply voltage (VDD) line and the transistor 323. A source terminal, a drain terminal, and a gate terminal of the transistor 321 can be connected with the power supply voltage (VDD) line, a gate terminal of the transistor 322, and a node ND1, respectively. The transistor 321 can determine whether to output a current from the power supply voltage (VDD) line to the transistor 323 based on a voltage level of the voltage V1. The voltage V1 represents a voltage of the node ND1.

[0040] The transistor 322 can be disposed between the power supply voltage (VDD) line and the transistor 324. A source terminal, a drain terminal, and a gate terminal of the transistor 322 can be connected with the power supply voltage (VDD) line, a gate terminal of the transistor 321, and a node ND0, respectively. The transistor 322 can determine whether to output a current from the power supply voltage (VDD) line to the transistor 324 based on a voltage level of the voltage V0. The voltage V0 represents a voltage of the node ND0.

[0041] The transistor 323 can be connected between the transistor 321 and a ground voltage (VSS) line. The source terminal and the drain terminal of the transistor 323 can be connected with the ground voltage (VSS) line and the transistor 321, respectively. A clock signal CLK0 can be input to the gate terminal of the transistor 323. The transistor 323 can determine whether to output a current from the transistor 321 to the ground voltage (VSS) line based on a voltage level of the clock signal CLK0.

[0042] The transistor 324 can be connected between the transistor 322 and the ground voltage (VSS) line. The source terminal and the drain terminal of the transistor 324 can be connected with the ground voltage (VSS) line and the transistor 322, respectively. An inverted clock signal / CLK0 can be input to the gate terminal of the transistor 324. The inverted clock signal / CLK0 can be an output signal of the inverter 330, which has a phase corresponding to an inverted version of a phase of the clock signal CLK0. The transistor 324 can determine whether to output a current from the transistor 322 to the ground voltage (VSS) line based on a voltage level of the inverted clock signal / CLK0.

[0043] The voltage level of the voltage V0 can be adjusted by the operations of the transistors 321 and 323, and the voltage level of the voltage V1 can be adjusted by the operations of the transistors 322 and 324. Because the operation of the transistor 322 is determined according to the voltage V0, the voltage level of the voltage V1 can be adjusted after the voltage level of the voltage V0 is adjusted. In the case where the clock signal CLK0 having the second voltage level is input to the level shifter 320, because a current flows from the transistor 321 to the node ND0 for a period of time, the voltage level of the voltage V0 can decrease slowly. Because a current starts to flow to the node ND1 after the voltage level of the voltage V0 decreases, it takes a lot of time for the voltage level of the voltage V1 to increase.

[0044] In the case where the clock signal CLK0 having the first voltage level is input to the level shifter 320, unlike when the clock signal CLK0 having the second voltage level is input to the level shifter 320, the voltage level of the voltage V0 can be adjusted after the voltage level of the voltage V1 is adjusted. Accordingly, the time taken for the voltage level of the voltage V1 to decrease to a target level can be shorter than the time taken for the voltage level of the voltage V1 to increase to the target level. In this case, an imbalance between the pull-up and the pull-down of the voltage V1 occurs, and thus, the waveform and the duty cycle of the output voltage are distorted.

[0045] Figure 3 is a graph for describing the waveform distortion of an output voltage occurring in a level shifter of Figure 2 is a graph for describing the waveform distortion of an output voltage occurring in a level shifter of Figure 2 is a voltage V1 of

[0046] As described with reference to Figure 2 Even if the clock signal CLK0 having the second voltage level LV2 is input to the level shifter 320, the voltage level of the voltage V0 can be slowly decreased because the current flows from the transistor 321 to the node ND0 for a certain period of time. In addition, the voltage level of the voltage V1 can take a lot of time to increase because the current starts to flow to the node ND1 after the voltage level of the voltage V0 is decreased. The voltage V1 can be adjusted to have the third voltage level LV3 by the operation of the level shifter 320. The third voltage level LV3 can be the voltage level of the power supply voltage VDD.

[0047] In contrast, in the case where the clock signal CLK0 having the first voltage level LV1 is input to the level shifter 320, the voltage level of the voltage V0 can be adjusted after the voltage level of the voltage V1 is adjusted unlike when the clock signal CLK0 having the second voltage level LV2 is input to the level shifter 320. Accordingly, the time taken for the voltage level of the voltage V1 to decrease to the target level can be shorter than the time taken for the voltage level of the voltage V1 to increase to the target level. The voltage V1 can be adjusted to have the first voltage level LV1 by the operation of the level shifter 320. The first voltage level LV1 can be the voltage level of the ground voltage VSS. The waveform of the voltage V1 can be distorted due to the imbalance between the time taken for the voltage level of the voltage V1 to increase to the target level and the time taken for the voltage level of the voltage V1 to decrease to the target level. It is observed from the graph shown in FIG. 2 that the time taken for the voltage level of the voltage V1 to increase to the target level and the time taken for the voltage level of the voltage V1 to decrease to the target level are imbalanced. Figure 3 It is observed from the graph shown in FIG. 2 that the time taken for the voltage level of the voltage V1 to increase to the target level and the time taken for the voltage level of the voltage V1 to decrease to the target level are imbalanced.

[0048] Figure 4 is a block diagram of a level shifter according to an example embodiment of the inventive concept.

[0049] The level shifter 420 can be included in the level shifter 220 of Figure 1 The clock generator 410 can correspond to the delay-locked loop 210 of Figure 1

[0050] The clock generator 410 can output a clock signal CLK1 that swings between a first voltage level LV1 and a second voltage level LV2. The second voltage level LV2 can be higher than the first voltage level LV1. The clock signal CLK1 generated from the clock generator 410 can be input to the level shifter 420.

[0051] ​The level shifter 420 can receive the clock signal CLK1, the power supply voltage VDD, and the ground voltage VSS. The level shifter 420 can output an output voltage to the output terminal OUT based on the clock signal CLK1, the power supply voltage VDD, and the ground voltage VSS. The output voltage can repeatedly rise and fall transitions as the clock signal CLK1 transitions. The output voltage having a rise transition can be expressed as the output voltage being pulled up. The output voltage having a fall transition can be expressed as the output voltage being pulled down.

[0052] In the following description, it is assumed that the voltage level of the pulled-up output voltage is equal to the voltage level of the power supply voltage VDD, but the inventive concept is not limited thereto. The voltage level of the pulled-up output voltage can be a voltage level between the second voltage level LV2 and the voltage level of the power supply voltage VDD.

[0053] The difference in voltage levels between the pulled-up output voltage and the pulled-down output voltage can be greater than the difference between the first voltage level LV1 and the second voltage level LV2. In the following description, it is assumed that the voltage level of the pulled-up output voltage is higher than the second voltage level LV2 and the voltage level of the pulled-down output voltage is equal to the first voltage level LV1, but the inventive concept is not limited thereto.

[0054] Further, in the following description, it is assumed that the level shifter 420 is a level shifter that receives a low voltage signal and outputs a high voltage signal, but the inventive concept is not limited thereto. The level shifter 420 can be a level shifter that receives a high voltage signal and outputs a low voltage signal.

[0055] The level shifter 420 can include a level shift circuit 421, a first adjustment circuit 422, and a second adjustment circuit 423.

[0056] The level shift circuit 421 can receive the power supply voltage VDD and can pull up the voltage level of the output voltage to the voltage level of the power supply voltage VDD. The level shift circuit 421 can include a plurality of transistors, the configuration of which will be described more fully with reference to Figure 5 The level shift circuit 421 can include a plurality of transistors, the configuration of which will be described more fully with reference to

[0057] The first adjustment circuit 422 can determine whether to output a current to the second adjustment circuit 423 based on the clock signal CLK1. The speed at which the output voltage is adjusted can vary depending on whether the current is output to the second adjustment circuit 423. The first adjustment circuit 422 can include a plurality of transistors, the configuration of which will be described more fully with reference to Figure 5 The first adjustment circuit 422 can include a plurality of transistors, the configuration of which will be described more fully with reference to

[0058] The second adjustment circuit 423 can determine whether to output a current to the ground voltage (VSS) line based on the clock signal CLK1 and the inverted clock signal / CLK1. The speed at which the output voltage is adjusted can vary depending on whether a current is output to the ground voltage (VSS) line. The second adjustment circuit 423 can include a plurality of transistors, the configuration of the second adjustment circuit 423 will be described with reference to Figure 5 is described more fully.

[0059] Figure 5 is a circuit diagram illustrating Figure 4 a level shifter. Figure 5 The level shift circuit 421, the first adjustment circuit 422, and the second adjustment circuit 423 of Figure 4 in the level shifter 420.

[0060] The level shift circuit 421 can include transistors 421_1 and 421_2. In the following description, it is assumed that the transistors 421_1 and 421_2 are PMOS transistors, but the inventive concept is not limited thereto. The transistors 421_1 and 421_2 can be replaced with switches that determine whether to switch based on voltages V10 and V12.

[0061] The source terminals of the transistors 421_1 and 421_2 can be connected to the power supply voltage (VDD) line. The drain terminal of the transistor 421_1 can be connected to the source terminal of the transistor 422_1, and the drain terminal of the transistor 421_2 can be connected to the drain terminal of the transistor 422_2. The gate terminals of the transistors 421_1 and 421_2 can be connected to nodes ND13 and ND11, respectively. The transistors 421_1 and 421_2 can determine whether to output a current to the transistors 422_1 and 422_2 based on a voltage V13 input to the gate terminal of the transistor 421_1 and a voltage V11 input to the gate terminal of 421_2.

[0062] The first adjustment circuit 422 can include transistors 422_1 and 422_2. In the following description, it is assumed that the transistor 422_1 is a PMOS transistor and the transistor 422_2 is an NMOS transistor, but the inventive concept is not limited thereto. The transistors 422_1 and 422_2 can be replaced with switches that determine whether to switch based on the clock signal CLK1 and the power supply voltage VDD, respectively.

[0063] The source terminal and the drain terminal of the transistor 422_1 can be connected with the drain terminal of the transistor 421_1 and the drain terminal of the transistor 423_1, respectively. The clock signal CLK1 can be input to the gate terminal of the transistor 422_1. The transistor 422_1 can determine whether to output a current to the transistor 423_1 based on the voltage level of the clock signal CLK1. The drain terminal and the source terminal of the transistor 422_2 can be connected with the drain terminal of the transistor 421_2 and the drain terminal of the transistor 423_2, respectively. The power supply voltage VDD can be input to the gate terminal of the transistor 422_2. Accordingly, the transistor 422_2 can output a current to the transistor 423_2 regardless of the clock signal CLK1. In other words, the transistor 422_2 can enable a current to flow between the node ND12 (or, optionally, an output node) and the node ND13 regardless of the clock signal CLK1.

[0064] The second adjustment circuit 423 can include transistors 423_1 and 423_2. In the following description, it is assumed that the transistors 423_1 and 423_2 are NMOS transistors, but the inventive concept is not limited thereto. The transistors 423_1 and 423_2 can be replaced with switches that determine whether to switch based on the clock signal CLK1 and the inverted clock signal / CLK1, respectively.

[0065] The inverted clock signal / CLK1 can be an output signal of an inverter 430, which has a phase corresponding to an inverted version of a phase of the clock signal CLK1. The inverter 430 can operate in the same voltage domain as that of the clock generator 410. For example, in the case where the clock generator 410 operates based on the voltage VDD1 and the ground voltage VSS, the inverter 430 can also operate based on the voltage VDD1 and the ground voltage VSS. In this case, the level of the voltage VDD1 can be lower than that of the power supply voltage VDD.

[0066] The drain terminal of the transistor 423_1 can be connected with the drain terminal of the transistor 422_1, and the drain terminal of the transistor 423_2 can be connected with the source terminal of the transistor 422_2. The source terminals of the transistors 423_1 and 423_2 can be connected with a ground voltage (VSS) line. The clock signal CLK1 can be input to the gate terminal of the transistor 423_1, and the inverted clock signal / CLK1 can be input to the gate terminal of the transistor 423_2. The transistors 423_1 and 423_2 can determine whether to output a current to the ground voltage (VSS) line based on the clock signal CLK1 and the inverted clock signal / CLK1, respectively.

[0067] The rising transition of the voltage V12 will be described. Upon receiving the clock signal CLK1 having the second voltage level LV2, the transistor 423_1 can output a current from the node ND11 to the ground voltage (VSS) line. Upon receiving the clock signal CLK1 having the second voltage level LV2, the transistor 422_1 can prevent output of a current to the node ND11. Since no current flows to the node ND11, the voltage level of the voltage V11 can decrease through the transistor 423_1 regardless of whether the transistor 421_1 outputs a current. Accordingly, when the clock signal CLK1 having the second voltage level LV2 is input to the level shifter 420, the voltage level of the voltage V11 can decrease faster. As the voltage level of the voltage V11 decreases faster, the time taken for the transistor 421_2 to output a current to the node ND12 can decrease. In other words, Figure 5 The level shifter 400 is configured to, when receiving the clock signal having the second voltage level, prevent output of a current from the power supply voltage (VDD) line to the node ND11 regardless of the voltage level of the node ND12 (or optionally, the output node), output a current from the node ND11 to the ground voltage (VSS) line, and output a current from the power supply voltage (VDD) line to the node ND12 based on the voltage level of the node ND11. The second voltage level can be lower than the voltage level of the power supply voltage (VDD) line.

[0068] Upon receiving the inverted clock signal / CLK1 having the first voltage level LV1, the transistor 423_2 can prevent output of a current to the ground voltage (VSS) line. Since the output of a current from the node ND12 to the ground voltage (VSS) line is prevented, and a current flows to the node ND12 through the transistor 421_2, the voltage level of the voltage V12 can increase faster.

[0069] The falling transition of the voltage V12 will be described. Upon receiving the clock signal CLK1 having the first voltage level LV1, the transistor 423_1 can prevent output of a current from the node ND11 to the ground voltage (VSS) line. Upon receiving the clock signal CLK1 having the first voltage level LV1, the transistor 422_1 can output a current from the node ND10 to the node ND11. Accordingly, the voltage level of the voltage V11 can increase. As the voltage level of the voltage V11 increases, the transistor 421_2 can prevent output of a current to the node ND12.

[0070] As soon as the inverting clock signal / CLK1 having the second voltage level LV2 is received, the transistor 423_2 can output a current from the node ND13 to the ground voltage (VSS) line. The transistor 422_2 can output a current from the node ND12 to the node ND13 regardless of the voltage level of the inverting clock signal / CLK1. Because the output of a current to the node ND12 is blocked by the transistor 421_2, and a current flows from the node ND12 to the ground voltage (VSS) line, the voltage level of the voltage V12 can decrease. In other words, Figure 5 The level shifter of FIG. 1 is configured to, when receiving the inverting clock signal / CLK1 having the second voltage level, block the output of a current to the node ND12 (or an optional output node) based on the voltage level of the node ND11, and output a current from the node ND12 to the ground voltage (VSS) line regardless of the voltage level of the node ND11.

[0071] Because the voltage V12 is used for the time taken for the rising transition to decrease, the imbalance between the time when the voltage V12 has a rising transition and the time when the voltage V12 has a falling transition can decrease. In addition, the waveform distortion and the duty cycle distortion of the voltage V12 can decrease.

[0072] The level shifter 420 can additionally mitigate or prevent the waveform distortion and the duty cycle distortion of the voltage V12 by using the transistor 422_2. The transistor 422_2 can also decrease the imbalance between the time when the voltage V12 has a rising transition and the time when the voltage V12 has a falling transition by adjusting the speed of the current flow from the node ND12 to the node ND13. For example, the level shifter 420 can include the transistor 422_2 having a capability suitable for reducing the duty cycle distortion.

[0073] Figure 6 is a graph for describing how the output voltage of Figure 5 has a rising transition. The output voltage represents the voltage of the node ND12.

[0074] The operation of the level shifter shown in Figure 6 will be described with reference to Figure 5 when the clock signal CLK1 having the first voltage level LV1 is received in a first step "STEP 1", and then the clock signal CLK1 having the second voltage level LV2 is received in a second step "STEP 2".

[0075] In the first step "STEP 1", because the clock signal CLK1 having the first voltage level LV1 and the inverting clock signal / CLK1 having the second voltage level LV2 are input to the level shifter, the voltage level of the output voltage can be maintained at the first voltage level LV1.

[0076] In the second step "STEP 2", the voltage level of the clock signal CLK1 input to the level shifter can be switched. In the second step "STEP 2", the clock signal CLK1 having the second voltage level LV2 and the inverted clock signal / CLK1 having the first voltage level LV1 can be input to the level shifter. As soon as the clock signal CLK1 having the second voltage level LV2 is input to the level shifter, the transistor 423_1 can output a current from the node ND11 to the ground voltage (VSS) line. In this case, the voltage level of the node ND11 can decrease. As the voltage level of the voltage V11 decreases, a current can flow through the transistor 421_2 to the node ND12. In this case, the voltage level of the output voltage can increase to the third voltage level LV3.

[0077] In the third step "STEP 3", the voltage level of the clock signal CLK1 input to the level shifter can be maintained at the second voltage level LV2. In this case, the voltage level of the output voltage can be maintained at the third voltage level LV3.

[0078] Figure 7 is a graph for describing how the output voltage of Figure 5 has a falling transition. The output voltage represents the voltage of the node ND12.

[0079] The operation of the level shifter shown in Figure 7 will be described with reference to Figure 5 when the clock signal CLK1 having the second voltage level LV2 is received in the fourth step "STEP 4" and then the clock signal CLK1 having the first voltage level LV1 is received in the fifth step "STEP 5".

[0080] In the fourth step "STEP 4", because the clock signal CLK1 having the second voltage level LV2 and the inverted clock signal / CLK1 having the first voltage level LV1 are input to the level shifter, the voltage level of the output voltage can be maintained at the third voltage level LV3.

[0081] In the fifth step "STEP 5", the voltage level of the clock signal CLK1 input to the level shifter can be switched. In the fifth step "STEP 5", the clock signal CLK1 having the first voltage level LV1 and the inverted clock signal / CLK1 having the second voltage level LV2 can be input to the level shifter. As soon as the clock signal CLK1 having the first voltage level LV1 is input to the level shifter, the transistor 422_1 can output a current to the node ND11. In this case, the voltage level of the node ND11 can increase. As the voltage level of the node ND11 increases, outputting a current to the node ND12 can be prevented by the transistor 421_2. As soon as the inverted clock signal / CLK1 having the second voltage level LV2 is input to the level shifter, a current can flow from the node ND12 to the ground voltage (VSS) line through the transistors 422_2 and 423_2. In this case, the voltage level of the output voltage can decrease to the first voltage level LV1.

[0082] In the sixth step "STEP 6", the voltage level of the clock signal CLK1 input to the level shifter can be maintained at the first voltage level LV1. In this case, the voltage level of the output voltage can be maintained at the first voltage level LV1.

[0083] Figure 8 is a graph showing a waveform of the output voltage of Figure 5 . The output voltage represents Figure 5 the voltage V12.

[0084] As described with reference to Figure 5 , as soon as the clock signal CLK1 having the second voltage level LV2 is input to the level shifter 420, the voltage level of the voltage V11 can decrease. In this case, the voltage level of the voltage V11 can decrease independently of the voltage level of the voltage V10. When the voltage level of the voltage V11 reaches the first voltage level LV1, the voltage level of the voltage V12 can increase.

[0085] As soon as the clock signal CLK1 having the first voltage level LV1 is input to the level shifter 420, the voltage level of the voltage V11 can increase. In this case, the voltage level of the voltage V10 can decrease to a fourth voltage level LV4. The fourth voltage level LV4 can be lower than the third voltage level LV3 and can be higher than the second voltage level LV2. The voltage level of the voltage V11 can increase independently of the voltage level of the voltage V10. When the voltage level of the voltage V11 reaches the third voltage level LV3, the voltage level of the voltage V12 can decrease.

[0086] That is, the speed at which the voltage level of the voltage V12 increases can be equal to the speed at which the voltage level of the voltage V12 decreases. From Figure 8It is observed from the graph that the imbalance between the time taken for the voltage level of the voltage V12 to rise to the target level and the time taken for the voltage level of the voltage V12 to fall to the target level is reduced.

[0087] Figure 9 is a circuit diagram illustrating an example embodiment of a level shifter. Figure 4 Figure 9 The level shift circuit 421a, the first adjustment circuit 422a, and the second adjustment circuit 423a of Figure 4 may be included in the level shifter 420 of

[0088] Unlike the first adjustment circuit 422 of Figure 5 , the first adjustment circuit 422a can not include the transistor 422_2. Except that the first adjustment circuit 422a does not include the transistor 422_2, Figure 9 The circuits 421a, 422a, and 423a of Figure 5 provide the same or substantially similar operations as the circuits 421, 422, and 423 of Figure 9 , additional description will be omitted to avoid redundancy. In some example embodiments, Figure 9 The level shifter ofmay further include an NMOS transistor configured to electrically connect the node ND12 and the node ND13 based on the voltage level of the power supply voltage line.

[0089] Figure 10 A memory module 600 according to an example embodiment of the inventive concept is illustrated. The memory module 600 can include a memory 620, a driver (RCD) 630, a power management integrated circuit (PMIC) 640, a buffer (DB) 650, and a connector CN on a printed circuit board. The power management integrated circuit 640 can supply power to the memory 620, the driver 630, and the buffer 650. The driver 630 can receive an address ADDR and a command CMD, and can control the memory 620 and the buffer 650. The memory 620 can exchange data DQ and a data strobe signal DQS with an external device through the buffer 650. Each of the driver 630 and the buffer 650 can include Figure 4The driver 630 and the buffer 650 can adjust the level of the voltage used therein by using the level shifter 420. For example, the driver 630 can operate in a voltage domain lower than the power voltage VDD to generate a control signal in response to the address ADDR and the command CMD. The driver 630 can make the voltage domain of the control signal higher by using the level shifter 420 before outputting the control signal to the memory 620 and the buffer 650.

[0090] According to some example embodiments of the inventive concepts, the level shifter can pull up and pull down the output voltage more quickly according to a change in the input voltage. In addition, the level shifter can reduce or mitigate an imbalance between the pull up and the pull down of the output voltage, such that waveform distortion and duty cycle distortion of the output voltage are reduced.

[0091] The units and / or circuits described herein can be implemented using hardware components, as well as combinations of software and hardware components. For example, hardware components can include a microcontroller, a memory module, a sensor, an amplifier, a band pass filter, an analog-to-digital converter, and a processing device, among others. The processing device can be implemented using one or more hardware devices configured to run and / or execute program code by performing arithmetic operations, logical operations, and input / output operations. The processing device can include a processor, a controller, and an arithmetic logic unit, a digital signal processor, a microcomputer, a field programmable array, a programmable logic unit, a microprocessor, or any other device capable of responding to and executing instructions in a defined manner. The processing device can run an operating system (OS) and one or more software applications running on the OS. The processing device can also access, store, manipulate, process, and create data in response to the execution of software. For simplicity, the processing device is described using a singular noun; however, one of ordinary skill in the art will understand that the processing device can include multiple processing elements and multiple types of processing elements. For example, the processing device can include multiple processors, or a processor and a controller. In addition, different processing configurations, such as parallel processors, multi-core processors, distributed processing, and the like, are possible.

[0092] Although the inventive concepts have been described with reference to certain example embodiments thereof, it will be clear to one of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the inventive concepts as set forth in the claims.

Claims

1. An electronic device comprising: a clock generator configured to output a clock signal that swings between a first voltage level and a second voltage level; and a level shifter configured to, when receiving the clock signal having the second voltage level, prevent output of a first current from a power voltage line to a first node regardless of a voltage level of an output node, output a second current from the first node to a ground voltage line, and output a third current from the power voltage line to the output node based on a voltage level of the first node, wherein the second voltage level is higher than the first voltage level and lower than a voltage level of the power voltage line, and wherein the level shifter comprises an NMOS transistor configured to determine whether to connect the output node with a second node based on the voltage level of the power voltage line. 2.The electronic device of claim 1, wherein the level shifter is configured to, when receiving the clock signal having the second voltage level, adjust the voltage level of the output node to a third voltage level that is greater than the second voltage level. 3.The electronic device of claim 1, wherein the level shifter is configured to output the third current when receiving the clock signal having the second voltage level and the voltage level of the first node is the voltage level of the ground voltage line. 4.The electronic device of claim 1, wherein the level shifter is configured to adjust the voltage level of the output node based on the clock signal and an inverted clock signal whose phase is opposite to that of the clock signal, and the level shifter is configured to, when receiving the inverted clock signal having the second voltage level, prevent output of the third current to the output node based on the voltage level of the first node, and output a fourth current from the output node to the ground voltage line regardless of the voltage level of the first node. 5.The electronic device of claim 4, wherein, the level shifter is configured to, when receiving the inverted clock signal having the second voltage level, decrease the voltage level of the output node from the third voltage level to a fourth voltage level. 6.The electronic device of claim 4, wherein the level shifter is configured to, when receiving the clock signal having the first voltage level, output the first current from the power voltage line to the first node regardless of the voltage level of the output node, and prevent output of the second current from the first node to the ground voltage line.

7. The electronic device according to any one of claims 1 to 6, wherein the level shifter further comprises: a first transistor configured to determine whether to output the first current based on the clock signal; and a second transistor configured to determine whether to output the second current based on the clock signal, wherein the first transistor is located between the power voltage line and the second transistor. 8.The electronic device of claim 7, wherein the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor. 9.An electronic device comprising: a level shifting circuit configured to determine whether to output a first current from a power voltage line to an output node based on a voltage level of a first node, and determine whether to output a second current from the power voltage line to a third node based on a voltage level of a second node; a first adjusting circuit configured to prevent output of a third current from the third node to the first node when receiving a clock signal having a first voltage level; and a second adjusting circuit configured to, when receiving the clock signal having the first voltage level, output the third current from the third node to the first node based on the voltage level of the first node. a second adjustment circuit configured to output a fourth current from the first node to a ground voltage line when receiving a clock signal having a first voltage level, wherein the clock signal is a signal that swings between a first voltage level and a second voltage level lower than the first voltage level, wherein the first voltage level is lower than a voltage level of the power voltage line, and wherein the first adjustment circuit is further configured to output the first current to the second node from the level shifting circuit regardless of a voltage level of the clock signal when receiving the first current from the level shifting circuit. 10.The electronic device of claim 9, wherein The level shifting circuit is configured to output the first current to adjust the voltage level of the output node to a voltage level higher than the first voltage level. 11.The electronic device of claim 9, wherein, the second adjustment circuit is configured to block the output of the first current from the first adjustment circuit to the ground voltage line when receiving an inverted clock signal having a second voltage level, the inverted clock signal being opposite in phase to the clock signal. 12.The electronic device of any one of claims 9-11, wherein, The level shifting circuit includes: a first transistor configured to determine whether to output the first current based on a voltage level of the first node; and a second transistor configured to determine whether to output the second current based on a voltage level of the second node. 13.The electronic device of claim 12, wherein, The first transistor and the second transistor are PMOS transistors. 14.The electronic device of any one of claims 9-11, wherein, The first adjustment circuit includes: a first transistor configured to block the output of a third current to the first node when receiving the clock signal having the first voltage level; and a second transistor configured to output the first current from the level shifting circuit to the second node regardless of the voltage level of the clock signal. 15.The electronic device of claim 14, wherein, the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor. 16.The electronic device of any one of claims 9-11, wherein, The second adjustment circuit includes: a first transistor configured to output the fourth current to the ground voltage line when receiving the clock signal having the first voltage level; and a second transistor configured to block the output of a fifth current from the second node to the ground voltage line when receiving an inverted clock signal having the second voltage level. 17.The electronic device of claim 16, wherein, The first transistor and the second transistor are NMOS transistors. 18.The electronic device of any one of claims 9 to 11, wherein, the level shifting circuit includes a PMOS transistor between the power voltage line and the output node and a PMOS transistor between the power voltage line and a third node, the first adjustment circuit includes an NMOS transistor between the output node and the second node and a PMOS transistor between the third node and the first node, and the second adjustment circuit includes an NMOS transistor between the second node and the ground voltage line and an NMOS transistor between the first node and the ground voltage line. 19.An electronic device comprising: a first PMOS transistor configured to determine whether to connect a power voltage line with a second node based on a voltage level of a first node; a second PMOS transistor configured to determine whether to connect the second node with a third node based on a clock signal that swings between a first voltage level and a second voltage level; and a third PMOS transistor configured to determine whether to connect the third node with a fourth node based on a voltage level of the fourth node. The first NMOS transistor is configured to determine whether to connect the third node with the ground voltage line based on a clock signal; The third PMOS transistor is configured to determine whether to connect the power voltage line with the output node based on a voltage level of the third node; And The second NMOS transistor is configured to determine whether to connect the first node with the ground voltage line based on an inverted clock signal, a phase of the inverted clock signal corresponding to an inverted version of a phase of the clock signal, The third NMOS transistor is configured to determine whether to connect the output node with the first node based on a voltage level of the power voltage line, Wherein the first voltage level is higher than the second voltage level and lower than a voltage level of the power voltage line.

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