Silicon carbide power diode and manufacturing method thereof

Abstract

The invention relates to the field of semiconductor technology, and discloses a silicon carbide power diode and a manufacturing method thereof, comprising: a silicon carbide substrate; an N-type silicon carbide epitaxial layer formed on one side of the silicon carbide substrate, the surface of the N-type silicon carbide epitaxial layer having an active region and a field limiting ring terminal region surrounding the active region; the active region comprising a plurality of N-type regions arranged at intervals and a P+ region located between two adjacent N-type regions; the doping concentration of the N-type region is higher than the doping concentration of the N-type silicon carbide epitaxial layer; the field limiting ring terminal region comprises a plurality of P+ regions arranged at intervals; a first Schottky contact metal formed in at least one N-type region; an anode metal layer formed in the N-type silicon carbide epitaxial layer, the anode metal layer comprising an anode metal and a second Schottky contact metal, the contact potential barrier formed by the first Schottky contact metal and the N-type region is lower than the contact potential barrier formed by the second Schottky contact metal and the N-type region, and is used to reduce the forward conduction voltage drop of the silicon carbide power diode.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a silicon carbide power diode and a manufacturing method thereof. Background Art

[0002] Silicon carbide (SiC) is one of the third-generation wide bandgap semiconductors. It has excellent physical properties such as wide bandgap, high breakdown electric field, high thermal conductivity, high temperature resistance, high voltage resistance, and radiation resistance. Therefore, SiC power devices are very suitable for high temperature, high voltage, and high power power electronics application systems. It has broad application prospects in electric vehicles, photovoltaic inverters, rail transit, wind power generation, motor drives and other application fields.

[0003] Silicon carbide junction barrier Schottky diode (SiC JBS) is a common silicon carbide power diode that combines the advantages of Schottky diode (SBD) and PIN diode, with characteristics such as low turn-on voltage, low reverse leakage, and high switching frequency. One of the main parameters of SiC JBS is the forward conduction voltage drop (Vf), which affects the working loss. Low conduction voltage drop is conducive to reducing working losses, reducing heat, and reducing the heat dissipation requirements of the power system. Therefore, how to reduce the forward conduction voltage drop of silicon carbide power diodes is of great significance. Summary of the invention

[0004] The invention discloses a silicon carbide power diode and a manufacturing method thereof, which are used to reduce the forward conduction voltage drop of the silicon carbide power diode.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] The present invention provides a silicon carbide power diode, comprising:

[0007] Silicon carbide substrate;

[0008] An N-type silicon carbide epitaxial layer is formed on one side of the silicon carbide substrate, wherein the surface of the N-type silicon carbide epitaxial layer facing away from the silicon carbide substrate has an active region and a field limiting ring terminal region surrounding the active region; the active region includes a plurality of spaced N-type regions and a P+ region between two adjacent N-type regions; the doping concentration of the N-type region is higher than the doping concentration of the N-type silicon carbide epitaxial layer; the field limiting ring terminal region includes a plurality of spaced P+ regions;

[0009] A first Schottky contact metal formed on a side of at least one of the N-type regions away from the silicon carbide substrate;

[0010] An anode metal layer is formed on a side of the N-type silicon carbide epitaxial layer away from the silicon carbide substrate, the anode metal layer includes an anode metal and a second Schottky contact metal, wherein the second Schottky contact metal covers the active area, and the anode metal is located on a side of the second Schottky contact metal away from the N-type silicon carbide epitaxial layer; and a contact barrier formed by the first Schottky contact metal and the N-type area is lower than a contact barrier formed by the second Schottky contact metal and the N-type area.

[0011] In the above-mentioned silicon carbide power diode, the silicon carbide power diode includes a silicon carbide substrate, an N-type silicon carbide epitaxial layer, an active region, a field limiting ring terminal region, a first Schottky contact metal and an anode metal layer; the forward voltage drop of the silicon carbide Schottky diode is related to the doping concentration of the epitaxial layer, the higher the doping concentration of the epitaxial layer, the lower the resistivity, the smaller the on-resistance, and therefore the lower the forward conduction voltage drop; in the silicon carbide power diode provided by the present invention, the doping concentration of the N-type silicon carbide epitaxial layer on the side away from the silicon carbide substrate is optimized, and the surface doping concentration is relatively high, or the doping concentration of the N-type silicon carbide epitaxial layer is optimized by nitrogen ion implantation to form an N-type region of the active region, so that the doping concentration of the active region on the surface is higher. In addition, the forward voltage drop and reverse leakage of the silicon carbide Schottky diode are related to the Schottky metal contact barrier. The lower the contact barrier, the lower the forward voltage drop, but the reverse leakage is high. The contact barrier formed by the first Schottky contact metal on the side of the N-type region away from the silicon carbide substrate and the N-type region is lower than the contact barrier formed by the second Schottky contact metal and the N-type region. The active region adopts a mixed structure of two Schottky contact metals with different barriers. The Schottky contact metal with a lower barrier is conducive to further reducing the forward conduction voltage drop, and the Schottky contact metal with a high barrier will not increase the reverse leakage.

[0012] Optionally, the doping concentration of the N-type region is 10% to 40% higher than the doping concentration of the N-type silicon carbide epitaxial layer.

[0013] Optionally, the depth of the N-type region does not exceed 1 μm.

[0014] Optionally, the first Schottky contact metal includes one or more of molybdenum, titanium, palladium, and tungsten;

[0015] And / or, the second Schottky contact metal includes one or both of nickel and gold.

[0016] Optionally, the silicon carbide power diode further includes:

[0017] A dielectric layer formed on a side of the N-type silicon carbide epitaxial layer away from the silicon carbide substrate, the dielectric layer surrounding the anode metal layer;

[0018] A passivation layer is formed on the anode metal layer and the dielectric layer on a side away from the N-type silicon carbide epitaxial layer, and a portion of the passivation layer corresponding to the anode metal layer is provided with a hollow structure;

[0019] An ohmic contact metal layer formed on a side of the silicon carbide substrate away from the N-type silicon carbide epitaxial layer;

[0020] A cathode metal layer is formed on a side of the ohmic contact metal layer away from the silicon carbide substrate.

[0021] Optionally, the passivation layer includes an insulating dielectric passivation layer and a polyimide passivation layer, and the polyimide passivation layer is located on and outside the insulating dielectric passivation layer.

[0022] The present invention also provides a method for manufacturing a silicon carbide power diode, which is used to manufacture any of the above-mentioned silicon carbide power diodes, comprising:

[0023] forming an N-type silicon carbide epitaxial layer on a silicon carbide substrate;

[0024] Processing a side of the N-type silicon carbide epitaxial layer away from the silicon carbide substrate to form an N-type region, so that the doping concentration of the N-type region is higher than the doping concentration of the N-type silicon carbide epitaxial layer;

[0025] Performing P-type impurity ion implantation on the N-type silicon carbide epitaxial layer to form an active region and a P+ region in a field limiting ring terminal region;

[0026] Making the first Schottky contact metal and annealing it;

[0027] An anode metal layer is prepared and annealed, wherein the anode metal layer includes an anode metal and a second Schottky contact metal, wherein the second Schottky contact metal covers the active area, and the anode metal is located on a side of the second Schottky contact metal away from the N-type silicon carbide epitaxial layer; and a contact barrier formed between the first Schottky contact metal and the N-type area is lower than a contact barrier formed between the second Schottky contact metal and the N-type area.

[0028] Optionally, processing a side of the N-type silicon carbide epitaxial layer away from the silicon carbide substrate to form an N-type region so that the doping concentration of the N-type region is higher than the doping concentration of the N-type silicon carbide epitaxial layer comprises:

[0029] N-type impurity ions are implanted into the side of the N-type silicon carbide epitaxial layer away from the silicon carbide substrate; or, an N-type silicon carbide epitaxial layer with a higher doping concentration is epitaxially grown on the N-type silicon carbide epitaxial layer.

[0030] Optionally, P-type impurity ions are implanted into the N-type silicon carbide epitaxial layer to form an active region and a P+ region in a field limiting ring terminal region, including:

[0031] Depositing an ion implantation mask layer, dry-etching the ion implantation mask layer to expose an ion implantation region of the ion implantation mask layer, and implanting P-type impurity ions into the ion implantation region of the ion implantation mask layer to simultaneously form a P+ region in an active region and a field limiting ring terminal region;

[0032] removing the ion implantation mask layer and preparing a carbon film as a high temperature activated protective layer;

[0033] The injected P-type impurity ions are activated at high temperature, and the carbon film is removed after activation; and when N-type impurity ions are injected into the N-type silicon carbide epitaxial layer on the side away from the silicon carbide substrate, the injected P-type impurity ions are activated at high temperature while the injected N-type impurity ions are activated at high temperature.

[0034] Optionally, the method for manufacturing a silicon carbide power diode further includes:

[0035] Depositing a dielectric layer on the N-type silicon carbide epitaxial layer, and etching to expose an anode metal contact window;

[0036] Preparing an insulating dielectric passivation layer on the anode metal layer and the dielectric layer;

[0037] Preparing a top polyimide passivation layer on the insulating dielectric passivation layer;

[0038] Depositing an ohmic contact metal on a side of the silicon carbide substrate away from the N-type silicon carbide epitaxial layer, and annealing the ohmic contact metal to form an ohmic contact metal layer;

[0039] A cathode metal is deposited on the ohmic contact metal layer to form a cathode metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A schematic diagram of the structure of a silicon carbide power diode provided in an embodiment of the present invention;

[0041] Figure 2 A schematic diagram of a method for manufacturing a silicon carbide power diode provided by an embodiment of the present invention;

[0042] Figure 3a-3m for Figure 1 Schematic diagram of the membrane preparation of the medium structure.

[0043] In the figure: 1-silicon carbide substrate; 2-N-type silicon carbide epitaxial layer; 3-N-type region; 4-P+ region; 5-first Schottky contact metal; 6-anode metal layer; 7-dielectric layer; 8-insulating dielectric passivation layer; 9-polyimide passivation layer; 10-ohmic contact metal layer; 11-cathode metal layer; 12-ion implantation mask layer. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] like Figure 1 As shown, an embodiment of the present invention provides a silicon carbide power diode, comprising: a silicon carbide substrate 1; an N-type silicon carbide epitaxial layer 2 formed on one side of the silicon carbide substrate 1, the surface of the N-type silicon carbide epitaxial layer 2 facing away from the silicon carbide substrate 1 has an active area A and a field limiting ring terminal area B surrounding the active area A; the active area A includes a plurality of N-type areas 3 arranged at intervals and a P+ area 4 located between two adjacent N-type areas 3; the doping concentration of the N-type area 3 is higher than the doping concentration of the N-type silicon carbide epitaxial layer 2; the field limiting ring terminal area B includes a plurality of P+ areas 4 arranged at intervals ; A first Schottky contact metal 5 is formed on the side of at least one N-type region 3 away from the silicon carbide substrate 1; an anode metal layer 6 is formed on the side of the N-type silicon carbide epitaxial layer 2 away from the silicon carbide substrate 1, the anode metal layer 6 includes an anode metal and a second Schottky contact metal, wherein the second Schottky contact metal covers the active area A, and the anode metal is located on the side of the second Schottky contact metal away from the N-type silicon carbide epitaxial layer 2; the contact barrier formed by the first Schottky contact metal 5 and the N-type region 3 is lower than the contact barrier formed by the second Schottky contact metal and the N-type region 3.

[0046] In the above-mentioned silicon carbide power diode, the silicon carbide power diode includes a silicon carbide substrate 1, an N-type silicon carbide epitaxial layer 2, an active area A, a field limiting ring terminal area B, a first Schottky contact metal 5 and an anode metal layer 6; the forward voltage drop of the silicon carbide Schottky diode is related to the doping concentration of the epitaxial layer. The higher the doping concentration of the epitaxial layer, the lower the resistivity and the smaller the on-resistance, so the forward conduction voltage drop is lower; in the silicon carbide power diode provided by the present invention, the doping concentration of the N-type silicon carbide epitaxial layer 2 on the side away from the silicon carbide substrate 1 is optimized, and the surface doping concentration is relatively high, or the doping concentration of the N-type silicon carbide epitaxial layer 2 is optimized by nitrogen ion implantation to form an N-type region 3 of the active area A, so that the doping concentration of the active area A on the surface is higher. In addition, the forward voltage drop and reverse leakage of the silicon carbide Schottky diode are related to the Schottky metal contact barrier. The lower the contact barrier, the lower the forward voltage drop, but the reverse leakage is high. The contact barrier formed by the first Schottky contact metal 5 and the N-type region 3 on the side of the N-type region 3 away from the silicon carbide substrate 1 is lower than the contact barrier formed by the second Schottky contact metal and the N-type region 3. The active region A adopts a mixed structure of two Schottky contact metals with different barriers, among which the Schottky contact metal with a lower barrier is conducive to further reducing the forward conduction voltage drop, and the Schottky contact metal with a high barrier will not increase the reverse leakage.

[0047] In a specific embodiment, the silicon carbide substrate 1 is N-type silicon carbide with a doping concentration of 1e18-2e19 cm -3 The thickness of the N-type silicon carbide epitaxial layer 2 is 5 to 100 μm, and the N-type doping concentration is 1e15 to 5e16 cm -3 .

[0048] In an optional implementation manner, the doping concentration of the N-type region 3 is 10% to 40% higher than the doping concentration of the N-type silicon carbide epitaxial layer 2 .

[0049] It should be noted that the forward voltage drop of the silicon carbide Schottky diode is related to the doping concentration of the epitaxial layer. The higher the doping concentration of the epitaxial layer, the lower the resistivity and the smaller the on-resistance, so the forward conduction voltage drop is lower. However, the higher the doping concentration, the better. The concentration range for devices of different voltage levels is different. Generally, the doping concentration of the N-type region 3 is preferably 10% to 40% higher than the doping concentration of the N-type silicon carbide epitaxial layer 2, for example: 10%, 20%, 30% or 40%.

[0050] In an optional implementation manner, the depth of the N-type region 3 does not exceed 1 μm.

[0051] It should be noted that in the above-mentioned silicon carbide power diode, the formation method of the N-type region 3 includes two-step epitaxy or a method of N-type impurity ion implantation, wherein the two-step epitaxy is specifically to further epitaxially grow an epitaxial layer with a higher doping concentration on the N-type silicon carbide epitaxial layer 2, but the thickness is thinner, generally not exceeding 1.0μm; and the method of N-type impurity ion implantation is adopted to inject N-type impurity ions into the N-type silicon carbide epitaxial layer 2 to increase the doping concentration of the surface area of ​​the N-type silicon carbide epitaxial layer 2, and the ion implantation junction depth of the N-type region 3 does not exceed 1μm.

[0052] In an optional embodiment, the first Schottky contact metal 5 includes one or more of molybdenum, titanium, palladium, and tungsten;

[0053] And / or, the second Schottky contact metal includes one or both of nickel and gold.

[0054] It should be noted that the first Schottky contact metal 5 is a metal or alloy that can form a low contact barrier with the N-type region 3, including but not limited to Mo, Ti, Pd, W or any combination thereof. The anode metal layer 6 is a laminated metal, including a second Schottky contact metal and a thickened anode metal. The second Schottky contact metal is a metal or alloy that can form a higher contact barrier with the N-type region 3, including but not limited to Ni, Au or a combination thereof; the thickened anode metal includes but is not limited to Al, Ti / Al, Ni / Al or Ti / Ni / Al, etc., with a total thickness of 2 to 5 μm.

[0055] In an optional implementation, each N-type region 3 corresponds to a first Schottky contact metal 5 on the side facing away from the silicon carbide substrate 1, the second Schottky contact metal is located between two adjacent first Schottky contact metals 5 and above the first Schottky contact metals 5, the second Schottky contact metal is in direct contact with the N-type region 3 and the P+ region 4, and the anode metal is located above the second Schottky contact metal.

[0056] Based on the above technical solutions, please continue to refer to Figure 1 , silicon carbide power diodes also include:

[0057] A dielectric layer 7 is formed on a side of the N-type silicon carbide epitaxial layer 2 away from the silicon carbide substrate 1, and the dielectric layer 7 surrounds the anode metal layer 6;

[0058] A passivation layer is formed on the anode metal layer 6 and the dielectric layer 7 on the side away from the N-type silicon carbide epitaxial layer 2, and a portion of the passivation layer corresponding to the anode metal layer 6 is provided with a hollow structure;

[0059] An ohmic contact metal layer 10 is formed on a side of the silicon carbide substrate 1 away from the N-type silicon carbide epitaxial layer 2;

[0060] A cathode metal layer 11 is formed on a side of the ohmic contact metal layer 10 facing away from the silicon carbide substrate 1 .

[0061] It should be noted that the dielectric layer 7 includes but is not limited to SiO, SiO2, SiN, SiON or any combination thereof, with a thickness of 50 to 2000 nm; the ohmic contact metal layer 10 is Ni, Ti / Ni, Ti / Al, Ti / Ni / Al, etc., with a total thickness of 10 to 500 nm; the cathode electrode metal is Ti / Ni / Ag or Ti / Al / Ni / Ag, etc., with a total thickness of 0.5 to 4.0 μm.

[0062] Based on the above technical solutions, please continue to refer to Figure 1 The passivation layer includes an insulating dielectric passivation layer 8 and a polyimide passivation layer 9 , and the polyimide passivation layer 9 is located on the upper part and outside of the insulating dielectric passivation layer 8 .

[0063] It should be noted that the insulating dielectric passivation layer 8 includes but is not limited to SiN, SiO2 or any combination thereof, with a total thickness of 0.5-2 μm. The top polyimide (PI) passivation layer has a thickness of 1-5 μm after curing.

[0064] Please refer to Figure 2 The present invention also provides a method for manufacturing a silicon carbide power diode, which is used to manufacture any of the above-mentioned silicon carbide power diodes, comprising:

[0065] forming an N-type silicon carbide epitaxial layer 2 on a silicon carbide substrate 1;

[0066] Processing the side of the N-type silicon carbide epitaxial layer 2 away from the silicon carbide substrate 1 to form an N-type region 3, so that the doping concentration of the N-type region 3 is higher than the doping concentration of the N-type silicon carbide epitaxial layer 2;

[0067] Performing P-type impurity ion implantation into the N-type silicon carbide epitaxial layer 2 to form a P+ region 4 in the active region A and the field limiting ring terminal region B;

[0068] Making the first Schottky contact metal 5 and annealing it;

[0069] An anode metal layer 6 is prepared and annealed, wherein the anode metal layer 6 includes an anode metal and a second Schottky contact metal, wherein the second Schottky contact metal covers the active area A, and the anode metal is located on a side of the second Schottky contact metal away from the N-type silicon carbide epitaxial layer 2; and a contact barrier formed between the first Schottky contact metal 5 and the N-type area 3 is lower than a contact barrier formed between the second Schottky contact metal and the N-type area 3.

[0070] In the silicon carbide power diode manufactured by the manufacturing method provided by the present invention, the doping concentration of the N-type silicon carbide epitaxial layer 2 on the side away from the silicon carbide substrate 1 is optimized, and the surface doping concentration is relatively high, or the doping concentration of the N-type silicon carbide epitaxial layer 2 is optimized by nitrogen ion implantation to form an N-type region 3 of the active region A, so that the doping concentration of the active region A on the surface is higher. In addition, the forward voltage drop and reverse leakage of the silicon carbide Schottky diode are related to the Schottky metal contact barrier. The lower the contact barrier, the lower the forward voltage drop, but the reverse leakage is high; the active region A adopts a mixed structure of two Schottky contact metals with different barriers, wherein the Schottky contact metal with a lower barrier is conducive to further reducing the forward conduction voltage drop, and the Schottky contact metal with a high barrier does not increase the reverse leakage.

[0071] For an alternative implementation, please refer to Figure 3a , an N-type silicon carbide epitaxial layer 2 is formed on the silicon carbide substrate 1.

[0072] It should be noted that the silicon carbide substrate 1 is N-type silicon carbide (SiC) with a doping concentration of 1e18 to 2e19 cm -3 The thickness of the N-type silicon carbide epitaxial layer 2 is 5 to 100 μm, and the N-type doping concentration is 1e15 to 5e16 cm -3 .

[0073] On the basis of the above technical solution, the side of the N-type silicon carbide epitaxial layer 2 away from the silicon carbide substrate 1 is processed to form an N-type region 3, so that the doping concentration of the N-type region 3 is higher than the doping concentration of the N-type silicon carbide epitaxial layer 2, including:

[0074] Please refer to Figure 3b , an N-type silicon carbide epitaxial layer 2 with a higher doping concentration is epitaxially grown on the N-type silicon carbide epitaxial layer 2; the N-type silicon carbide epitaxial layer 2 on the silicon carbide substrate 1 is an N-silicon carbide epitaxial layer. In this method, the formation of the N-type region 3 adopts two-step epitaxy, and an N-type silicon carbide epitaxial layer 2 with a higher doping concentration is epitaxially grown on the N-silicon carbide epitaxial layer, but the thickness is thinner, generally not exceeding 1.0μm.

[0075] Please refer to Figure 3c and Figure 3d , N-type impurity ions are injected into the side of the N-type silicon carbide epitaxial layer 2 away from the silicon carbide substrate 1; the N-type silicon carbide epitaxial layer 2 on the silicon carbide substrate 1 is an N-silicon carbide epitaxial layer. In this method, the N-type region 3 is formed by an N-type impurity ion implantation method, and N-type impurity ions are implanted into the N-silicon carbide epitaxial layer to increase the doping concentration of the surface area of ​​the epitaxial layer.

[0076] Please refer to Figure 3e , performing P-type impurity ion implantation on the N-type silicon carbide epitaxial layer 2 to form an active region A and a P+ region 4 in the field limiting ring terminal region B, including:

[0077] Depositing an ion implantation mask layer 12, dry etching the ion implantation mask layer 12, exposing an ion implantation region of the ion implantation mask layer 12, and implanting P-type impurity ions into the ion implantation region of the ion implantation mask layer 12, thereby forming a P+ region 4 in the active region A and the field limiting ring terminal region B;

[0078] It should be noted that the ion implantation mask layer 12 is SiO2 or polysilicon, or a combination of the two, with a thickness of 0.2-4 μm; the ion implantation is a single-step or multi-step ion implantation process, and the ions are Al or B, or a combination of the two.

[0079] Please refer to Figure 3f , removing the ion implantation mask layer 12, and preparing a carbon film as a high temperature activation protection layer;

[0080] The injected P-type impurity ions are activated at high temperature, and the carbon film is removed after activation; and when N-type impurity ions are injected into the side of the N-type silicon carbide epitaxial layer 2 away from the silicon carbide substrate 1, the injected P-type impurity ions are activated at high temperature while the injected N-type impurity ions are activated at high temperature.

[0081] It should be noted that the carbon film is prepared by photoresist carbonization or radio frequency sputtering, with a thickness of 0.05 to 2 μm and an activation temperature of 1500 to 1900°C.

[0082] Please refer to Figure 3g , depositing an ohmic contact metal on a side of the silicon carbide substrate 1 away from the N-type silicon carbide epitaxial layer 2, and annealing the ohmic contact metal to form an ohmic contact metal layer 10;

[0083] It should be noted that the ohmic contact metal layer 10 is Ni, Ti / Ni, Ti / Al, Ti / Ni / Al, etc., and has a total thickness of 10 to 500 nm.

[0084] Please refer to Figure 3h , a cathode metal is deposited on the ohmic contact metal layer 10 to form a cathode metal layer 11.

[0085] It should be noted that the cathode electrode metal is Ti / Ni / Ag or Ti / Al / Ni / Ag, and the total thickness is 0.5 to 4.0 μm.

[0086] Please refer to Figure 3i , depositing a dielectric layer 7 on the N-type silicon carbide epitaxial layer 2, and etching to expose an anode metal contact window;

[0087] It should be noted that the dielectric layer 7 includes but is not limited to SiO, SiO2, SiN, SiON or any combination thereof, and the deposition method includes but is not limited to plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), and the thickness is 50 to 2000 nm.

[0088] Please refer to Figure 3j , making the first Schottky contact metal 5 and annealing;

[0089] It should be noted that the first Schottky contact metal 5 is a metal or alloy that can form a low contact barrier with N-type silicon carbide, including but not limited to Mo, Ti, Pd, W or any combination thereof. The annealing temperature is 300-600 degrees.

[0090] Please refer to Figure 3k , preparing an anode metal layer 6 and annealing it;

[0091] It should be noted that the anode metal layer 6 is a laminated metal, including a second Schottky contact metal and an anode metal. The second Schottky contact metal is a metal or alloy that can form a higher contact barrier with N-type SiC, including but not limited to Ni, Au or a combination thereof; the anode metal includes but is not limited to Al, Ti / Al, Ni / Al or Ti / Ni / Al, etc., with a total thickness of 2 to 5 μm. The annealing temperature is not higher than the annealing temperature of the first Schottky metal 5. In an optional embodiment, a plurality of first Schottky contact metals 5 are arranged at intervals, and a second Schottky contact metal is deposited on the N-type silicon carbide epitaxial layer 2 and the first Schottky contact metal 5, and then an anode metal is deposited on the second Schottky contact metal.

[0092] Please refer to Figure 3l , preparing an insulating dielectric passivation layer 8 on the anode metal layer 6 and the dielectric layer 7;

[0093] It should be noted that the insulating dielectric passivation layer 8 includes but is not limited to SiN, SiO2, or any combination thereof; the total thickness is 0.5-2 μm.

[0094] Please refer to Figure 3m , preparing a top polyimide passivation layer 9 on the insulating dielectric passivation layer 8;

[0095] It should be noted that the thickness of the polyimide (PI) passivation layer after curing is 1 to 5 μm.

[0096] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A silicon carbide power diode, characterized in that: include: Silicon carbide substrate; An N-type silicon carbide epitaxial layer is formed on one side of the silicon carbide substrate, wherein the surface of the N-type silicon carbide epitaxial layer facing away from the silicon carbide substrate has an active region and a field limiting ring terminal region surrounding the active region; the active region includes a plurality of spaced N-type regions and a P+ region between two adjacent N-type regions; the doping concentration of the N-type region is higher than the doping concentration of the N-type silicon carbide epitaxial layer; the field limiting ring terminal region includes a plurality of spaced P+ regions; A first Schottky contact metal formed on a side of at least one of the N-type regions away from the silicon carbide substrate; An anode metal layer is formed on a side of the N-type silicon carbide epitaxial layer away from the silicon carbide substrate, the anode metal layer includes an anode metal and a second Schottky contact metal, wherein the second Schottky contact metal covers the active area, and the anode metal is located on a side of the second Schottky contact metal away from the N-type silicon carbide epitaxial layer; and a contact barrier formed by the first Schottky contact metal and the N-type area is lower than a contact barrier formed by the second Schottky contact metal and the N-type area.

2. The silicon carbide power diode according to claim 1, characterized in that: The doping concentration of the N-type region is 10% to 40% higher than the doping concentration of the N-type silicon carbide epitaxial layer.

3. The silicon carbide power diode according to claim 1, characterized in that: The depth of the N-type region does not exceed 1 μm.

4. The silicon carbide power diode according to claim 1, characterized in that: The first Schottky contact metal includes one or more of molybdenum, titanium, palladium, and tungsten; And / or, the second Schottky contact metal includes one or both of nickel and gold.

5. The silicon carbide power diode according to claim 1, characterized in that: The silicon carbide power diode further comprises: A dielectric layer formed on a side of the N-type silicon carbide epitaxial layer away from the silicon carbide substrate, the dielectric layer surrounding the anode metal layer; A passivation layer is formed on the anode metal layer and the dielectric layer on a side away from the N-type silicon carbide epitaxial layer, and a portion of the passivation layer corresponding to the anode metal layer is provided with a hollow structure; An ohmic contact metal layer formed on a side of the silicon carbide substrate away from the N-type silicon carbide epitaxial layer; A cathode metal layer is formed on a side of the ohmic contact metal layer away from the silicon carbide substrate.

6. The silicon carbide power diode according to claim 5, characterized in that: The passivation layer includes an insulating medium passivation layer and a polyimide passivation layer, and the polyimide passivation layer is located on and outside the insulating medium passivation layer.

7. A method for manufacturing a silicon carbide power diode, used for manufacturing the silicon carbide power diode according to any one of claims 1 to 6, characterized in that: include: forming an N-type silicon carbide epitaxial layer on a silicon carbide substrate; Processing a side of the N-type silicon carbide epitaxial layer away from the silicon carbide substrate to form an N-type region, so that the doping concentration of the N-type region is higher than the doping concentration of the N-type silicon carbide epitaxial layer; Performing P-type impurity ion implantation on the N-type silicon carbide epitaxial layer to form an active region and a P+ region in a field limiting ring terminal region; Making the first Schottky contact metal and annealing it; An anode metal layer is prepared and annealed, wherein the anode metal layer includes an anode metal and a second Schottky contact metal, wherein the second Schottky contact metal covers the active area, and the anode metal is located on a side of the second Schottky contact metal away from the N-type silicon carbide epitaxial layer; and a contact barrier formed between the first Schottky contact metal and the N-type area is lower than a contact barrier formed between the second Schottky contact metal and the N-type area.

8. The method according to claim 7, characterized in that: Processing a side of the N-type silicon carbide epitaxial layer away from the silicon carbide substrate to form an N-type region so that the doping concentration of the N-type region is higher than the doping concentration of the N-type silicon carbide epitaxial layer, comprising: implanting N-type impurity ions into the side of the N-type silicon carbide epitaxial layer away from the silicon carbide substrate; or, Another N-type silicon carbide epitaxial layer with a higher doping concentration is epitaxially grown on the N-type silicon carbide epitaxial layer.

9. The production method according to claim 7 or 8, characterized in that: Performing P-type impurity ion implantation on the N-type silicon carbide epitaxial layer to form an active region and a P+ region in a field limiting ring terminal region, comprising: Depositing an ion implantation mask layer, dry-etching the ion implantation mask layer to expose an ion implantation region of the ion implantation mask layer, and implanting P-type impurity ions into the ion implantation region of the ion implantation mask layer to simultaneously form a P+ region in an active region and a field limiting ring terminal region; removing the ion implantation mask layer and preparing a carbon film as a high temperature activated protective layer; The injected P-type impurity ions are activated at high temperature, and the carbon film is removed after activation; and when N-type impurity ions are injected into the N-type silicon carbide epitaxial layer on the side away from the silicon carbide substrate, the injected P-type impurity ions are activated at high temperature while the injected N-type impurity ions are activated at high temperature.

10. The manufacturing method according to claim 8, characterized in that: Also includes: Depositing a dielectric layer on the N-type silicon carbide epitaxial layer, and etching to expose an anode metal contact window; Preparing an insulating dielectric passivation layer on the anode metal layer and the dielectric layer; Preparing a top polyimide passivation layer on the insulating dielectric passivation layer; Depositing an ohmic contact metal on a side of the silicon carbide substrate away from the N-type silicon carbide epitaxial layer, and annealing the ohmic contact metal to form an ohmic contact metal layer; A cathode metal is deposited on the ohmic contact metal layer to form a cathode metal layer.

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