Switching Regulators

Abstract

The present invention discloses a switching regulator, comprising: a first power switch and an inductor, wherein the first power switch is coupled between the input terminal of the switching regulator and the first terminal of the inductor, and the second terminal of the inductor is coupled to the output terminal of the switching regulator; a diode, which is forward biased when the first power switch is turned off to provide a current path coupled to the first terminal of the inductor; a first driver, which is used to drive the first power switch; and a driver power clamp, which is used to clamp the voltage at the ground terminal of the first driver. The implementation of the present invention can protect the power switch in the switching regulator and the MOS in the power switch driver from damage.

Description

Technical Field

[0001] The present invention relates generally to voltage regulators, and more particularly to switching voltage regulators. Background Art

[0002] A switching regulator is a voltage regulator that uses a switching component to convert an input power source into a stable output voltage. Power is provided from the input to the output by turning a power switch (such as a MOSFET) on and off. The main advantage of a switching regulator over a standard linear regulator is higher efficiency. By inherently switching the power switch between the on and off states, lower power dissipation is achieved. Repeatedly switching the power switch provides voltage efficiently and generates less heat.

[0003] However, the switching of the power switch may cause a voltage spike in the circuit. In response to the switching of the power switch, the parasitic capacitance and inductance introduced by the printed circuit board (PCB) or other packaging components may cause signal bounce. Signal bounce includes, for example, ground bounce, supply bounce, and output bounce. The potential difference generated by the signal bounce may cause stress or even damage to certain devices in the circuit.

[0004] Figure 1A A buck regulator 102 is depicted. When the power switch Mp switches from the on state to the off state, there is a positive voltage spike at the internal power supply PVDD of the buck regulator 102 (due to the current continuity of the parasitic inductance) and a negative voltage spike at the connection terminal between the power switches Mp and Mn (due to the discharge of the parasitic capacitance). During such a transition interval, a strong voltage stress is applied to the power switch Mp. The power switch Mp may be damaged.

[0005] Figure 1B A boost regulator 104 is shown. When the power switch Mn switches from the on state to the off state, there is a negative voltage spike at the internal ground Pgnd of the boost regulator 104 (due to the current continuity of the parasitic inductance) and a positive voltage spike at the connection terminal between the power switches Mp and Mn (due to charging the parasitic capacitance). During such a transition interval, a strong voltage stress is applied to the power switch Mn. The power switch Mn may be damaged.

[0006] How to protect the power switches Mp and Mn and the MOS (eg, MOSFET) in the power switch driver from being damaged is an important issue in the field of switching regulators. Summary of the invention

[0007] The invention provides a switching regulator, which can protect a power switch in the switching regulator and a MOS in a power switch driver from being damaged.

[0008] In some embodiments, the switching regulator provided by the present invention may include: a first power switch and an inductor, wherein the first power switch is coupled between the input terminal of the switching regulator and the first terminal of the inductor, and the second terminal of the inductor is coupled to the output terminal of the switching regulator; a diode, which is forward biased when the first power switch is turned off to provide a current path coupled to the first terminal of the inductor; a first driver, which is used to drive the first power switch; and a driver power clamp, which is used to clamp the voltage at the ground terminal of the first driver. Such a regulator clamps the voltage at the ground terminal of the first driver through the driver power clamp, thereby protecting the power switch in the switching regulator and the MOS in the power switch driver from damage.

[0009] In some embodiments, the switching regulator provided by the present invention may include: an inductor and a first power switch, wherein the first end of the inductor is coupled to the input end of the switching regulator, and the first power switch is coupled between the second end of the inductor and the negative power end of the power supply; a diode, which is forward biased when the first power switch is turned off to establish a current path between the second end of the inductor and the output end of the switching regulator; a first driver, which is used to drive the first power switch; and a driver power clamp, which is used to clamp the voltage at the power end of the first driver. Such a regulator clamps the voltage at the power end of the first driver through the driver power clamp, thereby protecting the power switch in the switching regulator and the MOS in the power switch driver from damage. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A A step-down (buck) regulator 102 is depicted.

[0011] Figure 1B A boost regulator 104 is shown.

[0012] Figure 2A A buck regulator 202 is depicted in accordance with an exemplary embodiment of the present invention.

[0013] Figure 2B A boost regulator 222 is depicted in accordance with an exemplary embodiment of the present invention.

[0014] Figure 3A clamped internal power supply PVDD_clamp (or a clamped boost voltage Vboost_clamp) and a clamped internal ground Pgnd_clamp generated by the driver power clamp 208 / 228 are depicted.

[0015] Figure 4A The timing of the driver power clamp of the buck regulator 202 is depicted in accordance with an exemplary embodiment of the present invention.

[0016] Figure 4B The timing of the driver power clamp of the boost regulator 222 is depicted in accordance with an exemplary embodiment of the present invention.

[0017] Figure 5A A first voltage divider 502 and a second voltage divider 504 are depicted for driver supply clamping operation of the buck regulator 202 .

[0018] Figure 5B A first voltage divider 506 and a second voltage divider 508 are shown for driver supply clamping operation of the boost regulator 222 . DETAILED DESCRIPTION

[0019] Certain words are used in the specification and claims to refer to specific components. It should be understood by those skilled in the art that hardware manufacturers may use different terms to refer to the same component. The specification and claims do not use differences in names as a way to distinguish components, but use differences in the functions of components as the criteria for distinction. "Including" and "including" mentioned throughout the specification and claims are open-ended terms, so they should be interpreted as "including but not limited to". "Substantially" means that within an acceptable error range, those skilled in the art can solve the technical problem within a certain error range and basically achieve the technical effect. In addition, the term "coupled" includes any direct and indirect electrical connection means. Therefore, if the text describes a first device coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means. The following is a preferred way to implement the present invention, the purpose of which is to illustrate the spirit of the present invention rather than to limit the scope of protection of the present invention. The scope of protection of the present invention shall be subject to the definition of the attached claims.

[0020] The following description is the best embodiment of the present invention. These descriptions are used to illustrate the general principles of the present invention and should not be used to limit the present invention. The scope of protection of the present invention should be determined based on the claims of the present invention.

[0021] A switching regulator is introduced in the present invention to clamp the power supply or ground of the power switch driver.

[0022] Figure 2A A buck regulator 202 is depicted according to an exemplary embodiment of the present invention. The buck regulator 202 has a first power switch Mp, a second power switch Mn, an inductor L, a first driver (Mp driver) 204 configured to drive the first power switch Mp, a second driver (Mn driver) 206 configured to drive the second power switch Mn, and a driver power clamp 208 for clamping the ground of the first driver 204 and clamping the power of the second driver 206.

[0023] The first power switch Mp is coupled between the input terminal Vin of the buck regulator 202 and the first terminal t1 of the inductor L. The second terminal t2 of the inductor L is coupled to the output terminal Vout of the buck regulator 202. The second power switch Mn is coupled between the first terminal t1 of the inductor L and the internal ground Pgnd of the buck regulator 202.

[0024] When the first power switch Mp is turned on, the body diode 210 of the second power switch Mn is reverse biased. Current flows from the input terminal Vin of the buck regulator 202 to the inductor L, and then to the connected load at the output terminal Vout of the buck regulator 202. When the first power switch Mp is turned off, the body diode 210 of the second power switch Mn is forward biased to establish a current path coupled to the first terminal t1 of the inductor L. Since the current path establishes a loop, the energy stored in the inductor L forces the current to continue to flow through the load L in the same direction. A buck voltage is generated at the output terminal Vout of the buck regulator 202.

[0025] It should be noted that the driver power clamp 208 generates a clamped internal ground Pgnd_clamp to clamp the voltage at the ground terminal 212 of the first driver 204. In this way, the bounce at the ground terminal 212 of the first driver 204 is controlled within a limited region. The first power switch Mp operates in a safe region and is protected from Figure 1A The voltage stress damage is shown. In addition, the MOS in the first driver 204 is also protected from damage.

[0026] In this example, the driver power clamp 208 further generates a clamped internal power PVDD_clamp to clamp the voltage at the power terminal 214 of the second driver 206. Therefore, the bounce at the power terminal 214 of the second driver 206 is controlled within a limited region. The second power switch Mn is also protected by the driver power clamp 208. In addition, the MOS in the second driver 206 is also protected from damage.

[0027] More details of the buck regulator 202 are described in this paragraph. The first driver 204 includes a power supply terminal 216 coupled to the internal power supply PVDD of the buck regulator 202. The first power switch Mp is a PMOS, including a source biased by the power supply terminal 216 of the first driver 204, a gate controlled by the first driver 204, and a drain coupled to the first terminal t1 of the inductor L. The second driver 206 includes a ground terminal 218 coupled to the internal ground Pgnd of the buck regulator 202. The second power switch Mn is an NMOS, including a source biased by the ground terminal 218 of the second driver 206, a gate controlled by the second driver 206, and a drain coupled to the first terminal t1 of the inductor L. There is a first parasitic inductor LP1 between the input terminal Vin of the buck regulator 202 and the internal power supply PVDD, and there is a second parasitic inductor LP2 between the internal ground Pgnd and the negative power supply terminal VSS of the power supply. There may be other variations in the buck regulator architecture.

[0028] In some exemplary embodiments, the second power switch Mn of the buck regulator 202 is replaced by a diode. When the first power switch Mp is turned on, the diode is reverse biased, and when the first power switch Mp is turned off, the diode is forward biased.

[0029] Figure 2B According to an exemplary embodiment of the present invention, a boost regulator 222 is depicted. The boost regulator 222 includes a first power switch Mn, a second power switch Mp, an inductor L, a first driver (Mn driver) 224 configured to drive the first power switch Mn, a second driver (Mp driver) 226 configured to drive the second power switch Mp, and a driver power clamp 228 that clamps the power supply of the first driver 224 and clamps the ground of the second driver 226.

[0030] An input terminal Vin of the boost regulator 222 is coupled to a first terminal t1 of the inductor L, and a first power switch Mn is coupled between a second terminal t2 of the inductor L and a negative power terminal VSS of a power source.

[0031] When the first power switch Mn is turned on, the body diode 230 of the second power switch Mp is reverse biased. Due to the shorter internal path provided by the turned-on first power switch Mn, the current flowing through the inductor L increases. When the first power switch Mn is turned off, the body diode 230 of the second power switch Mp is forward biased to establish a current path between the second terminal t2 of the inductor L and the output terminal Vout of the boost regulator 222. The energy stored in the inductor L is pushed to the connected load at the output terminal Vout of the boost regulator 222. A boosted power supply is generated at the output terminal Vout of the boost regulator 222. The boost regulator 202 also has an internal boost terminal Vboost (the boost voltage is also marked as Vboost).

[0032] It should be noted that the driver power clamp 228 generates a clamped boost voltage Vboost_clamp to clamp the voltage at the power terminal 232 of the first driver 224. In this way, the bounce at the power terminal 232 of the first driver 224 is controlled within a limited region. The first power switch Mn operates in a safe region and is protected from Figure 1B The voltage stress shown is damaged. In addition, the MOS in the first driver 224 is also protected from damage. In this example, the driver power clamp 228 also generates a clamped internal ground Pgnd_clamp to clamp the voltage at the ground terminal 234 of the second driver 226. Therefore, the bounce at the ground terminal 234 of the second driver 226 is controlled within a limited area. The second power switch Mp is also protected by the driver power clamp 228. In addition, the MOS in the second driver 226 is also protected from damage.

[0033] More details of the boost regulator 222 are described in this paragraph. The first driver 224 includes a ground terminal 236 coupled to the internal ground Pgnd of the boost regulator 222. The first power switch Mn is an NMOS, including a source biased by the ground terminal 236 of the first driver 224, a gate controlled by the second driver 224, and a drain coupled to the second terminal t2 of the inductor L. The second driver 226 includes a power terminal 238, which is an internal boost terminal Vboost coupled to the output terminal Vout of the boost regulator 222. The second power switch Mp is a PMOS, including a source biased by the power terminal 238 of the second driver 226, a gate controlled by the second driver 226, and a drain coupled to the second terminal t2 of the inductor L. There is a first parasitic inductor LP1 between the internal ground Pgnd and the negative power terminal VSS of the power supply, and there is a second parasitic inductor LP2 between the output terminal Vout of the boost regulator 222 and the internal boost terminal Vboost.

[0034] In some exemplary embodiments, the second power switch Mp of the boost regulator 222 is replaced by a diode. When the first power switch Mn is turned on, the diode is reverse biased, and when the first power switch Mn is turned off, the diode is forward biased.

[0035] Figure 3 The clamped internal power supply PVDD_clamp (or the clamped boost voltage Vboost_clamp) and the clamped internal ground Pgnd_clamp generated by the driver power clamp 208 / 228 are depicted. The driver power clamp 208 / 228 is powered by the internal power supply PVDD (or the boost voltage Vboost) and grounded to the internal ground Pgnd. As shown, the bounce of the internal power supply PVDD (or the bounce of the boost voltage Vboost) and the bounce of the internal ground Pgnd are effectively clamped. The clamped internal power supply PVDD_clamp (or the clamped boost voltage Vboost_clamp) and the clamped internal ground Pgnd_clamp are applied to the power switch driver to protect the power switches Mp and Mn and the MOS of the power switch driver from damage.

[0036] Figure 4A The timing of the driver power clamp of the buck regulator 202 is depicted according to an exemplary embodiment of the present invention. The driver power clamp 208 is activated during a transition interval when the first driver 204 switches the first power switch Mp from an on state to an off state.

[0037] Figure 4B The timing of the driver power clamp of the boost regulator 222 is depicted according to an exemplary embodiment of the present invention. The driver power clamp 228 is activated during a transition interval when the first driver 224 switches the first power switch Mn from an on state to an off state.

[0038] In some exemplary embodiments, the driver supply clamp 208 / 228 is implemented by a voltage divider.

[0039] Figure 5AA first voltage divider 502 and a second voltage divider 504 for a driver power clamping operation of a buck regulator 202 are depicted. The first voltage divider 502 includes a first resistor component R1 and a second resistor component R2 coupled in series between an internal power supply PVDD of the buck regulator 202 and an internal ground Pgnd of the buck regulator 202. The voltage at a ground terminal 212 of the first driver 204 is clamped by a divided voltage at a connection terminal between the first resistor component R1 and the second resistor component R2. The second voltage divider 504 includes a third resistor component R3 and a fourth resistor component R4 coupled in series between an internal power supply PVDD of the buck regulator 202 and an internal ground Pgnd of the buck regulator 202. The voltage at a power terminal 214 of the second driver 206 is clamped by a divided voltage at a connection terminal between the third resistor component R3 and the fourth resistor component R4. It should be noted that Figure 5A The driver power clamping shown in FIG. 1 is performed during a transition interval in which the first driver 204 switches the first power switch Mp from an on state to an off state.

[0040] Figure 5B A first voltage divider 506 and a second voltage divider 508 for a driver power clamping operation of a boost regulator 222 are shown. The first voltage divider 506 includes a first resistor component R1 and a second resistor component R2 coupled in series between a boost voltage Vboost of the boost regulator 222 and an internal voltage Pgnd. The voltage at a power supply terminal 232 of the first driver 224 is clamped by a divided voltage at a connection terminal between the first resistor component R1 and the second resistor component R2. The second voltage divider 508 includes a third resistor component R3 and a fourth resistor component R4 coupled in series between a boost voltage Vboost of the boost regulator 222 and an internal ground Pgnd. The voltage at a ground terminal 234 of the second driver 226 is clamped by a divided voltage at a connection terminal between the third resistor component R3 and the fourth resistor component R4. It should be noted that Figure 5B The driver power clamping shown in FIG. 1 is performed during a transition interval in which the first driver 224 switches the first power switch Mn from an on state to an off state.

[0041] Various modifications are possible to the switching regulator architecture.Any switching regulator with a driver supply clamp should be considered within the scope of the present invention.

[0042] Those skilled in the art will readily observe that various modifications and variations can be made to the apparatus and methods while maintaining the teachings of the present invention.Therefore, the above disclosure should be interpreted as being limited only by the appended claims.

Claims

1. A switching regulator, characterized in that: include: a first power switch and an inductor, wherein the first power switch is coupled between an input terminal of the switching regulator and a first terminal of the inductor, and a second terminal of the inductor is coupled to an output terminal of the switching regulator; a diode coupled between the first end of the inductor and an internal ground of the switching regulator, and forward biased to provide a current path coupled to the first end of the inductor when the first power switch is turned off; a first driver, coupled to an internal power supply of the switching regulator and the first power switch, for driving the first power switch; and The driver power clamp is coupled to the first driver and is used for clamping the voltage at the ground terminal of the first driver.

2. The switching regulator according to claim 1, characterized in that Also includes: a second power switch coupled between the first end of the inductor and an internal ground of the switching regulator, wherein: When the first power switch is turned off, the forward biased diode is the body diode of the second power switch.

3. The switching regulator according to claim 2, characterized in that Also includes: a second driver coupled to an internal ground of the switching regulator and the second power switch, for driving the second power switch, The driver power clamp is also coupled to the second driver and is used to clamp the voltage at the power terminal of the second driver.

4. The switching regulator according to claim 3, wherein: The driver power clamp includes a first voltage divider; The first voltage divider includes a first resistance component and a second resistance component connected in series between the internal power supply of the switching regulator and the internal ground of the switching regulator; and The voltage at the ground terminal of the first driver is clamped by the divided voltage at the connection terminal between the first resistance component and the second resistance component.

5. The switching regulator according to claim 4, wherein: The connection terminal between the first resistance component and the second resistance component is connected to the ground terminal of the first driver during a transition interval in which the first driver switches the first power switch from an on state to an off state.

6. The switching regulator according to claim 4, wherein: The driver power clamp also includes a second voltage divider; the second voltage divider comprising a third resistance component and a fourth resistance component connected in series between the internal power supply of the switching regulator and the internal ground of the switching regulator; and The voltage at the power supply terminal of the second driver is clamped by a divided voltage at a connection terminal between the third resistance component and the fourth resistance component.

7. The switching regulator according to claim 6, wherein: During a transition interval in which the first driver switches the first power switch from an on state to an off state, the connection end between the first resistance component and the second resistance component is connected to the ground terminal of the first driver and the connection end between the third resistance component and the fourth resistance component is connected to the power terminal of the second driver.

8. The switching regulator according to claim 7, wherein: The first driver includes a power supply terminal coupled to the internal power supply of the switching regulator; The first power switch is a PMOS, the PMOS comprising a source biased by the power terminal of the first driver, a gate controlled by the first driver, and a drain coupled to the first terminal of the inductor; The second driver includes a ground terminal coupled to the internal ground of the switching regulator; and The second power switch is an NMOS including a source biased by the ground terminal of the second driver, a gate controlled by the second driver, and a drain coupled to the first terminal of the inductor.

9. The switching regulator according to claim 8, characterized in that Also includes: a first parasitic inductor between the input terminal of the switching regulator and the internal power supply of the switching regulator; and A second parasitic inductor is provided between the internal ground of the switching regulator and a negative power terminal of the power supply.

10. A switching regulator, characterized in that: include: an inductor and a first power switch, wherein a first end of the inductor is coupled to an input of the switching regulator, and the first power switch is coupled between a second end of the inductor and a negative power terminal of a power supply, wherein the negative power terminal of the power supply provides an internal ground; a diode coupled between the second end of the inductor and an internal boost terminal of the switching regulator, and forward biased when the first power switch is turned off to establish a current path between the second end of the inductor and an output terminal of the switching regulator; a first driver coupled to an internal ground of the switching regulator and the first power switch, for driving the first power switch; and The driver power clamp is coupled to the first driver and is used for clamping the voltage at the power terminal of the first driver.

11. The switching regulator according to claim 10, characterized in that Also includes: a second power switch coupled between the second end of the inductor and the internal boost terminal of the switching regulator, wherein: When the first power switch is turned off, the forward biased diode is the body diode of the second power switch.

12. The switching regulator according to claim 11, wherein: Also includes: A second driver is coupled to the internal boost terminal of the switching regulator and the second power switch, and is used to drive the second power switch. The driver power clamp is also coupled to the second driver and is used to clamp the voltage at the ground terminal of the second driver.

13. The switching regulator according to claim 12, wherein: The driver power clamp comprises a first voltage divider; and The first voltage divider includes a first resistance component and a second resistance component coupled in series between a boost terminal of the switching regulator and an internal ground of the switching regulator; and The voltage at the power supply terminal of the first driver is clamped by the divided voltage at the connection terminal between the first resistance component and the second resistance component.

14. The switching regulator according to claim 13, wherein: The connection terminal between the first resistance component and the second resistance component is connected to the power terminal of the first driver during a transition interval in which the first driver switches the first power switch from an on state to an off state.

15. The switching regulator according to claim 13, wherein: The driver power clamp further includes a second voltage divider; and The second voltage divider includes a third resistor component and a fourth resistor component coupled in series between the boost terminal of the switching regulator and an internal ground of the switching regulator; and The voltage at the ground terminal of the second driver is clamped by a divided voltage at a connection terminal between the third resistance component and the fourth resistance component.

16. The switching regulator according to claim 15, wherein: During a transition interval in which the first driver switches the first power switch from an on state to an off state, the connection end between the first resistance component and the second resistance component is connected to the power supply terminal of the first driver and the connection end between the third resistance component and the fourth resistance component is connected to the ground terminal of the second driver.

17. The switching regulator according to claim 16, wherein: The first driver includes a ground terminal coupled to the internal ground of the switching regulator; The first power switch is an NMOS, the NMOS comprising a source biased by the ground terminal of the first driver, a gate controlled by the first driver, and a drain coupled to the second terminal of the inductor; The second driver includes a power supply terminal coupled to the boost terminal of the switching regulator; and The second power switch is a PMOS, and the PMOS includes a source biased by the power terminal of the second driver, a gate controlled by the second driver, and a drain coupled to the second terminal of the inductor.

18. The switching regulator according to claim 17, wherein: Also includes: a first parasitic inductor between the internal ground of the switching regulator and the negative power terminal of the power supply; and A second parasitic inductor is provided between a positive power terminal of the power supply and the output terminal of the switching regulator.

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