Dynamically predict latency attributes

Abstract

The present invention is entitled "Dynamically Predicted Delay Attributes". The present disclosure as a whole relates to dynamically changing predicted delay related attributes to increase the deterministic window of operation (DTWIN). The host device workload characteristics and the current status of the memory device provide valuable information for the duration of the DTWIN. If the memory device is near the end of its life, the DTWIN duration will be shorter. In addition, if the workload from the host device is large, the DTWIN duration will also be shorter. Dynamically adjusting the DTWIN duration based on workload and status will provide a DTWIN duration that gradually shortens over time relative to the longer DTWIN duration that is currently available, rather than utilizing a fixed DTWIN duration based on a worst-case scenario of the host device workload and memory device status.

Description

Background Art Technical Field

[0002] Embodiments of the present disclosure are generally directed to dynamically changing predicted delay-related properties to increase a deterministic window of operation (DTWIN).

[0003] Description of Related Art

[0004] The predictable latency mode (PLM) is used to achieve predictable latency for both read and write operations in NVMe devices. When the NVMe device is configured to operate in this mode, using the predictable latency mode configuration feature, the namespace in the NVM group provides different separate operation windows for deterministic operations and non-deterministic operations. One such different window is the deterministic window (DTWIN), which is an operation window in which the NVM group is able to provide deterministic latency for read operations and write operations. Another such different window is the non-deterministic window (NDWIN), which is an operation window in which the NVM group cannot provide deterministic latency for read operations and write operations due to the preparation of subsequent deterministic windows.

[0005] Exemplary actions that may be performed in NDWIN include background operations on non-volatile media.The current window in which the NVM group is operating is configured by the host using the PLM window feature or by the controller as a result of autonomous action.

[0006] The predictable latency of each NVM fetch log page can be used to determine the current window for a given NVM group. When PLM is supported, there is one log page for each NVM group. The log page indicates typical values ​​and reliable estimates of the attributes associated with the DTWIN and NDWIN for a given NVM group. For reads, writes, and times in the DTWIN, two values ​​are provided in the predictable latency of each NVM fetch log page: the typical or maximum amount of the attribute that the host can consume during any given DTWIN; and a reliable estimate of the amount of the attribute that remains to be consumed during the current DTWIN.

[0007] To remain in DTWIN, the host device needs to follow operating rules to ensure that certain attributes do not exceed the typical or maximum values ​​indicated in the predictable latency for each NVM fetch log page. If an attribute exceeds either of the typical or maximum values ​​indicated in the predictable latency for each NVM fetch log page or a deterministic excursion occurs, the associated NVM group may autonomously transition to NDWIN. A deterministic excursion is a rare occurrence in the NVM subsystem that requires immediate action by the controller.

[0008] DTWIN is a constraint on the quality of service (QoS) of the data storage device because the data storage device is forced to operate under a worst-case scenario by assuming that the memory device is in an end-of-life (EOL) condition. In addition, the data storage device still has a large workload on the host interface. Therefore, the worst-case scenario for the host workload must also be assumed. In most cases, these constraints reduce DTWIN and increase NDWIN.

[0009] Therefore, there is a need in the art for improved DTWIN for storage devices. Summary of the invention

[0010] The present disclosure as a whole relates to dynamically changing predicted delay related attributes to increase the deterministic window of operation (DTWIN). The host device workload characteristics and the current status of the memory device provide valuable information for the duration of the DTWIN. If the memory device is near the end of its life, the DTWIN duration will be shorter. In addition, if the workload from the host device is large, the DTWIN duration will also be shorter. Dynamically adjusting the DTWIN duration based on the workload and status will provide a DTWIN duration that gradually shortens over time relative to the currently available longer DTWIN duration, rather than utilizing a fixed DTWIN duration based on a worst-case scenario of the host device workload and memory device status.

[0011] In one embodiment, a data storage device includes: at least one memory device; and a controller coupled to the at least one memory device, the controller being configured to: collect statistics about host device usage of the data storage device; collect statistics about parameters of the at least one memory device; determine a deterministic window (DTWIN) duration of the data storage device based on the collected statistics; and deliver the DTWIN duration to at least one host device.

[0012] In another embodiment, a data storage device includes: a plurality of memory devices; and a controller coupled to the plurality of memory devices, the controller being configured to: logically arrange the plurality of memory devices into a first plurality of memory device groups; determine a first deterministic window (DTWIN) duration for each memory device group in the first plurality of memory device groups; logically rearrange the plurality of memory devices into a second plurality of memory device groups; and determine a second DTWIN duration for each memory device group in the second plurality of memory device groups.

[0013] In another embodiment, a data storage device includes: means for dynamically adjusting a deterministic window (DTWIN) duration of at least one memory device; and means for communicating the DTWIN duration to at least one host device. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Thus, a detailed understanding of the manner in which the above-described features of the present disclosure are understood, a more particular description of the present disclosure, the above brief overview, may be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments of the present disclosure and are therefore not to be considered limiting of its scope, as the present disclosure may admit to other equally effective embodiments.

[0015] Figure 1 is a schematic diagram of a system according to one embodiment.

[0016] Figure 2 is a schematic diagram of DTWIN duration and NDWIN duration according to one embodiment.

[0017] Figure 3 is a graph showing DTWIN duration over time.

[0018] Figure 4 is a flow chart illustrating a method of implementing DTWIN duration variation.

[0019] Figure 5 is a schematic diagram of a group of memory devices according to one embodiment.

[0020] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. DETAILED DESCRIPTION

[0021] Hereinafter, reference is made to the embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the embodiments specifically described. On the contrary, any combination of the following features and elements (whether or not related to different embodiments) is considered to realize and practice the present disclosure. In addition, although the embodiments of the present disclosure can achieve advantages that are superior to other possible solutions and / or superior to the prior art, whether a specific advantage is achieved by a given embodiment is not a limitation to the present disclosure. Therefore, the following aspects, features, embodiments and advantages are merely illustrative, and are not considered to be elements or limitations of the appended claims, unless explicitly stated in the claims. Similarly, reference to "the present disclosure" should not be interpreted as a summary of any inventive subject matter disclosed herein, and should not be considered to be elements or limitations of the appended claims, unless explicitly stated in the claims.

[0022] The present disclosure as a whole relates to dynamically changing predicted delay related attributes to increase the deterministic window of operation (DTWIN). The host device workload characteristics and the current status of the memory device provide valuable information for the duration of the DTWIN. If the memory device is near the end of its life, the DTWIN duration will be shorter. In addition, if the workload from the host device is large, the DTWIN duration will also be shorter. Dynamically adjusting the DTWIN duration based on the workload and status will provide a DTWIN duration that gradually shortens over time relative to the currently available longer DTWIN duration, rather than utilizing a fixed DTWIN duration based on a worst-case scenario of the host device workload and memory device status.

[0023] Figure 1 1 is a schematic diagram of a system 100 according to one embodiment. The system 100 includes a host device 102 that communicates with a data storage device 104 via an interface 105. The data storage device includes a controller 108 that communicates with one or more memory devices 110 via a memory device interface 112.

[0024] The disclosure herein describes dynamically changing predicted delay-related attributes to allow adaptive maximization of deterministic window periods. Dynamically changing predicted delay-related attributes is achieved by adaptively tracking realistic current host device 102 workload characteristics and current memory device 110 (e.g., NAND) conditions. The dynamic approach is in contrast to the static approach using rigid values ​​that are fixed throughout the life of the data storage device 104 and are set based on simulated assumptions of the end-of-life conditions of the memory device 110 on the one hand, and on the other hand based on extreme host device 102 workloads (which actually represent worst-case scenarios).

[0025] The innovative concepts presented herein can be implemented by adding designated logic hardware to the data storage device 104. The designated hardware logic will track both the current workload of the host device 102 and the current status of the memory device 110 (as reflected in the internal memory device 110 parameters). The designated logic hardware will generate dynamically updated values ​​of the relevant attributes of the deterministic window / non-deterministic window accordingly. The updated values ​​will be placed in a predictable delay for each NVM to obtain a log page.

[0026] A host statistics collector 116 and a host log generator 114 are also coupled to the controller 108. The host statistics collector 116 collects information or statistics about the host device 102 usage of the data storage device 104. Such information includes the intensity with which the host device 102 uses the memory. More specific information includes the workload from the host device 102 (i.e., write intensive / read intensive), the sequential write and read composition, the random write and read composition, the FTL table or address translation table, and the stream allocation of the host device 102. If the host device 102 works using streams or namespaces, it is easier to maintain this order.

[0027] The current state of the memory device 110 is also collected. Such information collected for the memory device 110 includes the number of program / erase cycles, the temperature range within a predetermined time period, the remaining free space, and the bad block budget. In one embodiment, the predetermined time period may be between about 1 ms and about 10 seconds.

[0028] The information collected from the host statistics collector 116 and from the memory devices 110 is aggregated and used in part to determine the DTWIN duration and the frequency of background operations that will determine the NDWIN duration. The DTWIN duration and the NDWIN duration are dynamic in that the DTWIN duration and the NDWIN duration are constantly updated based on the changing conditions of the memory devices 110 and the host statistics found in the host statistics collector 116. The DTWIN duration and the NDWIN duration are updated and stored in the host log generator 114. As discussed herein, the DTWIN duration and the NDWIN duration are not static, but change dynamically based on the collected information.

[0029] Figure 2 FIG. 4 is a schematic diagram of DTWIN duration and NDWIN duration according to one embodiment. Figure 2As shown, DTWIN 204, 208, 212 alternates with NDWIN 202, 206, 210, 214 in time. In a static environment, DTWIN 204, 208, 212 all have the same duration and never change. Similarly, NDWIN 202, 206, 210, 214 all have the same duration and never change in a static environment. The reason why the duration of DTWIN 204, 208, 212 and NDWIN 202, 206, 210, 214 never changes in a static environment is that the data storage device must assume the worst case scenario of operation and base the DTWIN duration and NDWIN duration on the worst case scenario. From the perspective of the memory device, the worst case scenario is the performance of the EOL and the accompanying EOL of the memory device. For host device use, it is assumed that the workload is large. In this way, the data storage device has a fixed DTWIN duration and NDWIN duration that is stored in the acquisition log table and provided to the host device. In a static environment, the data storage device must assume the worst-case scenario because the data storage device is not allowed to process front-end actions longer than the DTWIN duration. If any front-end activity exceeds the DTWIN duration, the data storage device cannot proceed and returns an error to the host device. Therefore, in a static environment, the data storage device cannot notify the host device that the DTWIN duration is greater than the worst-case scenario, otherwise the data storage device will fail.

[0030] Figure 3 is a graph showing the DTWIN duration over time. Figure 3 As shown, in the static case, the DTWIN duration never changes and is initially set to the worst case scenario for the EOL of the data storage device. However, in the dynamic case, the EOL performance will be the same for the DTWIN duration, but the path to the EOL of the data storage device results in a dynamic DTWIN duration. At the beginning of use, the host device is not interacting with the memory device, and the memory device is not in use. Therefore, the best possible performance of the memory device is at the beginning of life. Therefore, the best possible DTWIN duration will occur at the beginning of the life of the memory device, as reflected by the high DTWIN duration for the dynamic DTWIN duration. Over time, the memory device experiences some usage, and host device statistics are collected. Therefore, over time, the DTWIN duration decreases. Eventually, the data storage device will reach an EOL condition. As shown in FIG. Figure 4As shown, at the EOL of the data storage device, the DTWIN duration in the dynamic case eventually reaches the DTWIN duration advertised to the host device for the static case. Therefore, using a dynamic DTWIN duration significantly increases the DTWIN duration of the data storage device during the life of the data storage device compared to a static DTWIN.

[0031] Figure 4 4 is a flow chart illustrating a method 400 for implementing a DTWIN change. The data storage device collects statistics about host device usage at 402 and also collects statistics about the state of the memory device at 404. The data storage device then analyzes the collected statistics to determine the DTWIN and NDWIN durations at 406. The data storage device then notifies the host device of the modified durations in accordance with the update rules at 408. There are several possible triggering options for updating the acquisition log table: immediately when a DTWIN duration recalibration occurs; when the next power cycle occurs; and at set intervals such as when a predetermined time or a predetermined number of DTWINs have passed.

[0032] In one embodiment, the host device determines the update rules. In another embodiment, the data storage device sets the update rules. The data storage device continuously collects statistics and thus continuously updates the DTWIN and NDWIN durations. Thus, the data storage device is always ready to provide new DTWIN and NDWIN durations to the host device at any time defined by the host device or the data storage device.

[0033] In one embodiment, a system includes a single host device that communicates with a single internal non-removable data storage device. DTWIN and NDWIN durations dynamically change over time and are communicated to the single host device.

[0034] In another embodiment, a single removable data storage device communicates with at least two host devices at different times. Although the data storage device statistics will be the same regardless of the host device, the DTWIN and NDWIN durations may be different for each host device because the workload triggered by each host device may be different. Therefore, different DTWIN and NDWIN durations may be provided to each host device. In addition, the DTWIN and NDWIN durations change dynamically over time.

[0035] In another embodiment, a single data storage device communicates with at least two host devices. The communications may occur simultaneously or serially. Although the data storage device statistics will be the same regardless of the host device, the DTWIN and NDWIN durations may be different for each host device because the workload triggered by each host device may be different. Therefore, different DTWIN and NDWIN durations may be provided to each host device. In addition, the DTWIN and NDWIN durations change dynamically over time.

[0036] In another embodiment, multiple data storage devices communicate with a single host device. Both the data storage device statistics and the host device statistics can be different. For example, the data storage device statistics can be different due to different usage of the host device. The host device statistics can also be different if the host device uses different data storage devices in different ways. Therefore, different DTWIN and NDWIN durations for each data storage device can be provided to the host device. In addition, the DTWIN and NDWIN durations change dynamically over time.

[0037] In another embodiment, multiple host devices share and communicate with multiple data storage devices. Both the data storage device statistics and the host device statistics can be different. For example, the data storage device statistics can be different due to different usage of the host devices. Because each host device uses different data storage devices in different ways, the host device statistics can also be different. Therefore, different DTWIN and NDWIN durations can be provided from each data storage device to each host device. In addition, the DTWIN and NDWIN durations change dynamically over time.

[0038] It is also contemplated that memory devices may be logically arranged in groups, and that the groups may change during the life of the data storage device. Figure 5 is a schematic diagram of a memory device group according to one embodiment. In the enterprise market, dies can be grouped together to take advantage of dynamic DTWIN durations. For example, if some dies reach EOL conditions before other dies, the system can group these dies together under common DTWIN and NDWIN durations, such as Figure 5 shown.

[0039] exist Figure 5, three groups 500, 520, 540 are shown for illustration purposes. The first group 500 includes NDWINs 502, 506, 510, 514 alternating with DTWINs 504, 508, 512. The NDWINs 502, 506, 510, 514 all have the same duration. Similarly, the DTWINs 504, 508, 512 all have the same duration.

[0040] The second group 520 includes NDWINs 522, 526, 530, 534 alternating with DTWINs 524, 528, 532. The NDWINs 522, 526, 530, 534 all have the same duration. Similarly, the DTWINs 524, 528, 532 all have the same duration.

[0041] The third group 540 includes NDWINs 542, 546, 550, 554 alternating with DTWINs 544, 548, 552. The NDWINs 542, 546, 550, 554 all have the same duration. Similarly, the DTWINs 544, 548, 552 all have the same duration.

[0042] Since all data sets 500, 520, 540 are logically arranged, groups 500, 520, 540 can be logically arranged based on the quality of the memory device. In addition, groups 500, 520, 540 can be logically arranged to provide optimal parameters for specific requests of the host device. In addition, each group 500, 520, 540 has a separate acquisition log table and different DTWIN and NDWIN durations. For example, the NDWIN 502, 506, 510, 514 of group 500 has different durations from the NDWIN 522, 526, 530, 534 of group 520 and the NDWIN 542, 546, 550, 554 of group 540. In addition, the NDWIN 522, 526, 530, 534 of group 520 has different durations from the NDWIN 542, 546, 550, 554 of group 540. With respect to DTWIN, the DTWINs 504, 508, 512 of group 500 have different durations than the DTWINs 524, 528, 532 of group 520 and the DTWINs 544, 548, 552 of group 540. Additionally, the DTWINs 524, 528, 532 of group 520 have different durations than the DTWINs 544, 548, 552 of group 540. Based on host statistics and / or memory device statistics, memory devices may be logically rearranged into different groups to obtain the best possible DTWIN and NDWIN durations, or simply tailor the DTWIN and NDWIN durations to the needs of the host device.

[0043] In one embodiment, a data storage device includes: at least one memory device; and a controller coupled to the at least one memory device, the controller being configured to: collect statistics about host device usage of the data storage device; collect statistics about parameters of the at least one memory device; determine a deterministic window (DTWIN) duration of the data storage device based on the collected statistics; and deliver the DTWIN duration to at least one host device. The controller is further configured to change the DTWIN duration. The controller includes a host statistics collector that collects statistics about host device usage. The controller includes a CPU that collects the statistics from the host device and from the at least one memory device. The collected statistics about host device usage include one or more of: workload, sequential read or write composition, random read or write composition; FTL table or address translation table; and stream allocation. The collected statistics about the parameters of the at least one memory device include one or more of program-erase cycles, temperature range within a predetermined time period, remaining free space, and bad block budget. The controller is configured to deliver the DTWIN duration upon receiving a request for the DTWIN duration from at least one host device. The controller is further configured to analyze the collected statistics about host device usage and the parameter of the at least one memory device, and wherein the controller is further configured to determine the DTWIN duration and a non-deterministic window (NDWIN) duration. The controller is further configured to determine different DTWIN durations for each host device of the at least one memory device. The different DTWIN durations are based on different host device usage statistics for each host device. The different DTWIN durations are based on the same statistics from the parameter of the at least one memory device.

[0044] In another embodiment, a data storage device includes: a plurality of memory devices; and a controller coupled to the plurality of memory devices, the controller configured to: logically arrange the plurality of memory devices into a first plurality of memory device groups; determine a first deterministic window (DTWIN) duration for each memory device group in the first plurality of memory device groups; logically rearrange the plurality of memory devices into a second plurality of memory device groups; and determine a second DTWIN duration for each memory device group in the second plurality of memory device groups. At least one DTWIN duration within the first DTWIN duration is different from at least one other DTWIN duration within the first DTWIN duration. At least one DTWIN duration within the first DTWIN duration is different from at least one second DTWIN duration within the second DTWIN duration. At least one DTWIN duration within the second DTWIN duration is different from at least one other DTWIN duration within the second DTWIN duration. The controller is configured to deliver the second DTWIN duration when determining the second DTWIN duration. The controller is further configured to adjust the first DTWIN duration to a third DTWIN duration for at least one memory device group before logically rearranging the plurality of memory devices. The controller is further configured to deliver the third DTWIN duration to a host device.

[0045] In another embodiment, a data storage device includes: means for dynamically adjusting a deterministic window (DTWIN) duration of at least one memory device; and means for delivering the DTWIN duration to at least one host device. The at least one memory device is a plurality of memory devices logically arranged as a plurality of memory groups.

[0046] By continuously collecting statistics of one or more of the host device usage of the data storage device and the memory device performance, a dynamic DTWIN duration that will adapt to the current state of the memory device and the host usage can be utilized. Thus, the QoS of the data storage device can be improved, and the DWTIN can be reduced over time instead of remaining fixed.

[0047] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be envisaged without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the appended claims.

Claims

1. A data storage device, comprising: at least one memory device; and a controller coupled to the at least one memory device, the controller being configured to: collecting statistics regarding host device usage of the data storage device; collecting statistics about parameters of the at least one memory device; reducing a deterministic window duration (DTWIN duration) of the data storage device based on the collected statistical values, wherein the DTWIN duration is an operation window that provides deterministic latency for read operations and write operations; and The DTWIN duration is delivered to at least one host device. 2 . The data storage device of claim 1 , wherein the controller is further configured to vary the DTWIN duration. 3 . The data storage device of claim 1 , wherein the controller comprises a host statistics collector that collects statistics regarding host device usage. 4 . The data storage device of claim 1 , wherein the controller comprises a CPU that collects the statistical values ​​from the host device and from the at least one memory device.

5. A data storage device according to claim 1, wherein the statistical values ​​collected about the use of the host device include one or more of the following: workload, sequential read or write composition, random read or write composition; flash translation layer table (FTL table or address translation table) and stream allocation.

6. The data storage device of claim 1 , wherein the statistics collected about the parameters of the at least one memory device include one or more of program-erase cycles, a temperature range within a predetermined time period, remaining free space, and a bad block budget.

7. The data storage device of claim 1, wherein the controller is configured to deliver the DTWIN duration upon receiving a request for the DTWIN duration from at least one host device.

8. The data storage device of claim 1 , wherein the controller is further configured to analyze the collected statistics regarding usage of the host device and the parameters of the at least one memory device, and wherein the controller is further configured to reduce the DTWIN duration and the non-deterministic window NDWIN duration.

9. The data storage device of claim 1, wherein the controller is further configured to reduce a different DTWIN duration for each host device of the at least one memory device.

10. The data storage device of claim 9, wherein the different DTWIN durations are based on different host device usage statistics for each host device.

11. The data storage device of claim 10, wherein the different DTWIN durations are based on a same statistical value of a parameter from the at least one memory device.

12. A data storage device, comprising: multiple memory devices; and a controller coupled to the plurality of memory devices, the controller being configured to: logically arranging the plurality of memory devices into a first plurality of memory device groups; reducing a first deterministic window duration, i.e., a first DTWIN duration, of each of the first plurality of memory device groups, wherein the DTWIN duration is an operating window during which deterministic latency is provided for read operations and write operations; logically rearranging the plurality of memory devices into a second plurality of memory device groups; as well as A second DTWIN duration of each memory device group in the second plurality of memory device groups is reduced.

13. The data storage device of claim 12, wherein at least one DTWIN duration within the first DTWIN duration is different from at least one other DTWIN duration within the first DTWIN duration.

14. The data storage device of claim 12, wherein at least one DTWIN duration within the first DTWIN duration is different from at least one second DTWIN duration within the second DTWIN duration.

15. The data storage device of claim 12, wherein at least one DTWIN duration within the second DTWIN duration is different from at least one other DTWIN duration within the second DTWIN duration. 16 . The data storage device of claim 12 , wherein the controller is configured to deliver the second DTWIN duration upon determining the second DTWIN duration.

17. The data storage device of claim 12, wherein the controller is further configured to reduce the first DTWIN duration to a third DTWIN duration for at least one memory device group before logically rearranging the plurality of memory devices.

18. The data storage device of claim 17, wherein the controller is further configured to deliver the third DTWIN duration to a host device.

19. A data storage device, the data storage device comprising: means for dynamically reducing a deterministic window duration (DTWIN duration) of at least one memory device, wherein the DTWIN duration is an operating window during which deterministic latency is provided for read operations and write operations; and Means for delivering the DTWIN duration to at least one host device.

20. The data storage device of claim 19, wherein the at least one memory device is a plurality of memory devices logically arranged as a plurality of memory groups.

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