Method for manufacturing a silicon carbide semiconductor device

Abstract

This invention provides a method for manufacturing a silicon carbide semiconductor device, which is a silicon carbide diode with a JBS structure that combines a Schottky junction and a pn junction. The method for manufacturing the silicon carbide semiconductor device can maintain the low forward voltage of the SBD structure and improve the surge current withstand capability. The metal material film (52) and the semiconductor substrate (30) are reacted by two heat treatments at low temperature and high temperature to form a nickel silicide film (33) in self-alignment on the oxide film (51). The metal material film (52) is sequentially stacked with a first nickel film (58), an aluminum film (53), and a second nickel film (54) that are in partial contact with the p-type region (13) exposed at the openings (51a, 51b) of the oxide film (51) and the entire connection area (20a) of the FLR (21).

Description

Technical Field

[0001] This invention relates to a method for manufacturing silicon carbide semiconductor devices. Background Technology

[0002] In recent years, silicon carbide (SiC) semiconductors have attracted much attention as semiconductor materials capable of fabricating semiconductor devices that exceed the limits of semiconductor devices using silicon (Si) semiconductors (hereinafter referred to as silicon carbide semiconductor devices). In particular, compared with silicon semiconductors, silicon carbide semiconductors are expected to be used in high-voltage (e.g., above 1700V) semiconductor devices due to their advantages of high dielectric breakdown electric field strength and high thermal conductivity.

[0003] When the silicon carbide semiconductor device is a diode (hereinafter referred to as a silicon carbide diode), due to the configuration of n - n-type drift region - The design specifications of the epitaxial layer can be set to a thin thickness and a high impurity concentration, so silicon carbide diodes with a withstand voltage of around 3300V generally adopt the Schottky Barrier Diode (SBD) structure.

[0004] The structure of existing SBD (Silicon Carbide Diode) structures is described. Figure 22 It is a top view showing the state of an existing silicon carbide semiconductor device as viewed from the front side of a semiconductor substrate. Figure 22 The existing silicon carbide semiconductor device 140 shown is a vertical silicon carbide diode with an SBD structure, wherein a Schottky junction is formed along the entire front side of the semiconductor substrate 130 containing silicon carbide in the active region 110.

[0005] The existing silicon carbide semiconductor device 140 has a Schottky junction exposed on the front side of the semiconductor substrate 130. - A front electrode (not shown) is formed by a drift region 112 and a metal layer disposed on the front side of the semiconductor substrate 130. Reference numerals 120 and 121 are the edge termination region and the field limiting ring (FLR), respectively.

[0006] Typically, in SBD structures, there is a problem where the electric field strength at the junction between the semiconductor substrate 130 and the front electrode is high, leading to increased reverse leakage current due to electron tunneling through the Schottky barrier when a reverse voltage is applied, or due to inherent surface defects in silicon carbide. Therefore, a silicon carbide diode employing a junction barrier Schottky (JBS) structure, where a Schottky junction and a pn junction are mixed on the front side of the semiconductor substrate 130, has been proposed.

[0007] The structure of existing JBS-structured silicon carbide diodes is described. Figure 23 This is a top view showing another example of a conventional silicon carbide semiconductor device as viewed from the front side of a semiconductor substrate. Figure 23 The diagram omits the voltage-resistant structure of the edge terminal region, the front electrode 114 disposed on the front side of the semiconductor substrate 130, and the field oxide film 115. Figure 24 It means Figure 23 A cross-sectional view of the cross-sectional structure at the cutting line AA-AA'. Symbol 119 represents the back electrode.

[0008] Figure 23 and Figure 24 The existing silicon carbide semiconductor device 140' shown is... Figure 22 The difference between the existing silicon carbide semiconductor device 140 shown is that, in the active region 110, on the front side of the semiconductor substrate 130, there is a mixture of n... - The SBD structure formed by the p-type drift region 112 and the Schottky junction of the titanium film 131 constituting the front electrode 114, and the p-type region 113 and n-type drift region 112 and the Schottky junction constituting the front electrode 114, and the SBD structure formed by the p-type drift region 112 and the titanium film 131 constituting the front electrode 114, and the SBD structure formed by the p-type drift region - JBS structure formed by pn junction in drift region 112.

[0009] p-type regions 113 are selectively disposed in the active region 110 on the surface region of the front side of the semiconductor substrate 130. Between adjacent p-type regions 113, n-type regions are exposed on the front side of the semiconductor substrate 130. - Type-across drift region 112. Consists of p-type region 113 and n-type region 112. - A pn junction is formed on the front side of the semiconductor substrate 130 in the p-type drift region 112. The n-junctions between adjacent p-type regions 113... - The drift region 112 forms a Schottky junction with the bottom titanium film 131 of the front electrode 114 disposed on the front side of the semiconductor substrate 130.

[0010] Thus, by employing a JBS structure in which a Schottky junction and a pn junction are mixed at the junction surface between the semiconductor substrate 130 and the front electrode 114, the electric field strength at the junction surface between the semiconductor substrate 130 and the front electrode 114 can be reduced, thereby suppressing reverse leakage current equivalent to that of a silicon semiconductor FWD (Free Wheeling Diode). Figure 23 In the image, the striped p-type region 113 extending in a direction parallel to the front side of the semiconductor substrate 130 is indicated by shading.

[0011] In addition, Figure 22In the existing silicon carbide semiconductor device 140 shown, when a surge voltage is applied, the amount of surge current generated in the semiconductor substrate 130 and flowing in the forward direction is drawn from the semiconductor substrate 130 to the front electrode 114 (hereinafter referred to as the extraction amount) is small. The reason for this is that the diode of the SBD structure is a unipolar device that conducts electricity without using minority carriers. Therefore, in the high current domain where a high forward current flows in the diode, the contact (electrical contact) between the semiconductor substrate 130 and the front electrode 114 has a high resistance.

[0012] When the contact between the semiconductor substrate 130 and the front electrode 114 has high resistance, a high surge current flows forward through the semiconductor substrate, causing localized surge current concentration due to heat generation at the interface between the semiconductor substrate 130 and the front electrode 114. This surge current concentration leads to an increase in the n-axis at the Schottky junction surface and directly below the Schottky junction surface. - Type epitaxial layer (n) - The type drift region 112) breaks down, so the amount of surge current drawn from the semiconductor substrate 130 to the front electrode 114 is reduced.

[0013] It was confirmed that the surge current extraction rate increases in diodes using the JBS structure with silicon semiconductors. Therefore, in Figure 23 In the existing silicon carbide semiconductor device 140' shown, similar to a diode using a JBS structure with silicon semiconductor, in the p-type region 113 and n... - In the drift region 112, the surge current rises due to the bipolar action of the pn junction formed on the front side of the semiconductor substrate 130. It is estimated that the amount of surge current extracted increases, but the effect is not obvious.

[0014] Figure 23 One of the important factors contributing to the low surge current extraction rate in the existing silicon carbide semiconductor device 140' shown is the inability to obtain a sufficiently low-resistance ohmic contact between the p-type region 113, which constitutes the pn junction of the JBS structure, and the front electrode 114. Therefore, it is estimated that forming a metal electrode (hereinafter referred to as an ohmic electrode) between the p-type region 113 and the front electrode 114, which is ohmically connected to the p-type region 113, will allow surge current to flow locally in the pn junction of the JBS structure, thereby improving the surge current tolerance.

[0015] Figure 25 This is a cross-sectional view showing another example of an existing silicon carbide semiconductor device. Figure 25 It is the following patent document 2 Figure 3 . Figure 25 The existing silicon carbide semiconductor device 150 shown is... Figure 23 and Figure 24The difference between the existing silicon carbide semiconductor device 140' shown is that an ohmic electrode 133' is disposed on the p-type region 113 as the bottom layer of the front electrode 114, and an n-type electrode is mixed on the front side of the semiconductor substrate 130. - The p-type drift region 112 forms a Schottky junction with the Schottky electrode 131' and the p-type region 113 forms an ohmic junction with the ohmic electrode 133'.

[0016] As a method for manufacturing silicon carbide diodes with existing JBS structures, the following method is proposed: only in n - The type-type drift region is formed on the exposed portion of the front side of the semiconductor substrate, and is related to n. - After the metal electrode with Schottky junction in the drift region (hereinafter referred to as Schottky electrode) is formed, an ohmic electrode with p-type ohmic junction constituting the pn junction of the JBS structure is formed on the front side of the semiconductor substrate in such a way as to cover the Schottky electrode (see, for example, Patent Document 1 below).

[0017] Patent Document 1 discloses the use of aluminum (Al) or nickel (Ni) as ohmic electrode materials and molybdenum (Mo) as Schottky electrode materials. Furthermore, Patent Document 1 also discloses the selective formation of p-type regions with higher impurity concentrations than the p-type regions within the p-type region constituting the JBS structure's pn junction. + Silicon carbide diodes with p-type contact areas to improve the ohmic performance of the p-type region and the ohmic electrode.

[0018] As an alternative manufacturing method for existing JBS structure silicon carbide diodes, a method has been proposed that, after forming an ohmic electrode only on the p-type region constituting the pn junction of the JBS structure, a junction with the n-type region is formed on the front side of the semiconductor substrate in a manner that covers the ohmic electrode. - A method for Schottky electrodes with drift region Schottky junctions (see, for example, Patent Document 2 below). Patent Document 2 below discloses the use of aluminum as the material for the ohmic electrode and molybdenum (Mo) as the material for the Schottky electrode.

[0019] In addition, as another method for manufacturing existing JBS structure silicon carbide diodes, the following method is disclosed: A silicon film and a nickel film are sequentially stacked on a silicon carbide semiconductor substrate in a stoichiometric ratio of 2:1 (=Si:Ni) to form a silicon-nickel film that reacts only with each other through a silanization reaction. - The silicide (NiSi2) film of the anode electrode is ohmically bonded to the p-type region of the pn junction constituting the JBS structure and has a Schottky-type drift region. (For example, see Patent Document 3 below.)

[0020] As a method for forming an ohmic electrode on a p-type region, the following method is proposed: After sequentially stacking an aluminum film and a nickel film on a semiconductor substrate containing silicon carbide in such a way as to cover the p-type region, the silicon atoms in the semiconductor substrate and the nickel atoms in the nickel film are subjected to silicide reaction by annealing (heat treatment) at 1000°C to form a nickel silicide (NiSi) film that becomes an ohmic electrode that is ohmically bonded to the p-type region (for example, see Non-Patent Document 1 below).

[0021] As another method for forming an ohmic electrode on a p-type region, a method is proposed as follows: after sequentially stacking a nickel film and an aluminum film on a semiconductor substrate containing silicon carbide in such a way as to cover the p-type region, the metal films and the semiconductor substrate are reacted by heat treatment at a temperature of 850°C or higher and 1050°C or lower to form a p-type ohmic electrode containing an alloy of nickel, aluminum, silicon and carbon (C) (for example, see Patent Document 4 below).

[0022] As another method for forming an ohmic electrode on a p-type region, the following method is proposed: after sequentially stacking an aluminum film and a silicon film with an elemental composition ratio of 89:11 (=Al:Si) on a semiconductor substrate containing silicon carbide in such a way as to cover the p-type region, an alloy film of aluminum film and silicon film is formed by heat treatment at a temperature of 400°C to 500°C, and an ohmic bond is formed between the alloy film and the p-type region (for example, see Patent Document 5 below).

[0023] As another method for forming ohmic electrodes, it is proposed to form a nickel film on a high-concentration impurity region formed by ion implantation of silicon atoms into a semiconductor substrate containing silicon carbide, and to form a heating reaction layer precursor layer only at the interface between the high-concentration impurity region and the nickel film by heat treatment at a temperature of 400°C to 600°C, and then to transform the heating reaction layer precursor layer into a low-resistance heating reaction layer by heat treatment at 950°C (for example, see Patent Document 6 below).

[0024] As another method for forming ohmic electrodes, it has been proposed to form a heating reaction layer precursor layer between a silicon carbide semiconductor substrate and a metal material film by heat treatment within the contact holes of the interlayer insulating film, and to transform the heating reaction layer precursor layer into a heating reaction layer by heat treatment at a higher temperature than the initial heat treatment (for example, see Patent Document 7 below). In Patent Document 7 below, it is disclosed that the material of the metal material film is titanium, aluminum, or nickel, and the initial heat treatment is set at a low temperature that does not cause harmful solid-phase reactions between the metal material film and the interlayer insulating film.

[0025] In addition, Patent Document 7 discloses a method in which a metal material film is formed in contact with the entire surface of a semiconductor substrate within a contact hole of an interlayer insulating film, the contact position between the metal material film and the semiconductor substrate is silicided by heat treatment, and a heating reaction layer is formed in a self-aligned salicide process on the entire surface of the contact position, and the unsilicided portion of the metal material film (the portion other than the heating reaction layer) is removed by etching, thereby leaving only the portion that is the heating reaction layer of the metal material film.

[0026] Figure 26 This is a cross-sectional view showing an example of an ohmic electrode self-aligned and formed using existing silicon carbide semiconductor device manufacturing methods. Figure 26 It is the following patent document 7 Figure 1 . Figure 26 The conventional silicon carbide semiconductor device 160 shown has a heating reaction layer that serves as an ohmic electrode 164 within the contact hole 163a of the interlayer insulating film 163. This heating reaction layer is in contact with and electrically connected to a high-concentration impurity region 162 on the surface region of the semiconductor substrate 161 containing silicon carbide and a wiring layer 165 buried in the contact hole 163a of the interlayer insulating film 163.

[0027] The ohmic electrode 164 is formed, in self-alignment, on the entire surface of the semiconductor substrate 161 within the contact hole 163a of the interlayer insulating film 163 using the self-aligned silicide process described in Patent Document 7, with the interlayer insulating film 163 serving as a mask. The ohmic electrode 164 is disposed on the surface region of the high-concentration impurity region 162 exposed on the surface of the semiconductor substrate 161 within the contact hole 163a of the interlayer insulating film 163, and protrudes from the front side of the semiconductor substrate 161 in a direction away from the front side of the semiconductor substrate 161.

[0028] Existing technical documents

[0029] Patent documents

[0030] Patent Document 1: Japanese Patent No. 5546759

[0031] Patent Document 2: Japanese Patent Application Publication No. 2008-282972

[0032] Patent Document 3: Japanese Patent Application Publication No. 2003-158259

[0033] Patent Document 4: Japanese Patent No. 4291875

[0034] Patent Document 5: Japanese Patent Application Publication No. Heisei 1-020616

[0035] Patent Document 6: Japanese Patent Application Publication No. 2017-175115

[0036] Patent Document 7: Japanese Patent Application Publication No. 2005-276978

[0037] Non-patent literature

[0038] Non-Patent Literature 1: N. Kiritani, 7 others, Single Material Ohmic Contacts Simultaneously Formed on the Source / p-well / Gate of 4H-SiC Vertical MOSFETs, Materials Science Forum, Switzerland, Trans Tech Publications, 2003, Vol. 433-436, pp. 669-672 Summary of the Invention

[0039] Technical issues

[0040] However, in order to improve the existing silicon carbide semiconductor device 140' (a silicon carbide diode with a JBS structure: see reference) Figure 23 and Figure 24 Even if an ohmic electrode that only contacts the p-type region 113 is provided between the semiconductor substrate 130 and the Schottky electrode (titanium film 131), the surge current withstand capability cannot be achieved if the ohmic electrode is a nickel silicide film. This is because the contact resistance between the p-type region 113 and the ohmic electrode cannot be sufficiently reduced, so the predetermined design value of the surge current withstand capability cannot be obtained.

[0041] To increase the contact resistance between the p-type region 113 and the ohmic electrode, if the active region 110 is maintained with the same surface area, increasing the junction area between the p-type region 113 and the ohmic electrode will increase n. - The smaller the junction area between the drift region 112 and the Schottky electrode, the better. Therefore, under forward bias, from n... - The electron current in the drift region 112 facing the Schottky electrode decreases, making it difficult to achieve a low forward voltage (Vf).

[0042] Therefore, in order to make the junction area between the p-type region 113 and the ohmic electrode the junction area required for the predetermined surge current withstand capacity, and to maximize n... -The junction area between the p-type drift region 112 and the Schottky electrode is such that an ohmic electrode is formed only on the p-type region 113, and between adjacent p-type regions 113, in the n-type region... - A Schottky electrode can be formed on the entire surface of the p-type drift region 112. Alternatively, by using an aluminum / nickel laminate as the material for the ohmic electrode, the contact resistance between the p-type region 113 and the ohmic electrode can be reduced.

[0043] However, due to the width w101 of the p-type region 113 (refer to...) Figure 23 The width is less than a few μm, making it difficult to control the patterning of stacked films of two metals (aluminum and nickel) with different etching rates. Considering the process margin of mass production, the ohmic electrode is formed with a width narrower than the width w101 of the p-type region 113. Therefore, the p-type region 113 contacts the Schottky electrode, creating an ineffective region where the contact resistance does not decrease, failing to obtain sufficient characteristics to increase the surge current extraction.

[0044] In the technology described in the aforementioned Patent Document 2, a metal film is patterned by photolithography and etching, leaving behind an ohmic electrode 133' (see reference). Figure 25 This leads to an increase in processes and costs. Furthermore, since the metal film can only be patterned with the smallest etching size, it is not suitable for miniaturization. In cases where miniaturization is not possible, the forward voltage reduction is lowered as described above because the bonding area of ​​the Schottky electrodes within the surface of the semiconductor substrate 130 is reduced.

[0045] In the technology described in Patent Document 7, as mentioned above, an interlayer insulating film 163 is used as a mask, and a finely patterned ohmic electrode 164 is self-aligned within the contact hole 163a of the interlayer insulating film 163. However, it has been confirmed that the contact resistance between the high-concentration impurity region 162 and the ohmic electrode 164 is not sufficiently reduced. Furthermore, it has been confirmed that if the conventional self-aligning technology described in Patent Documents 2 and 7 is applied to a laminated film made of aluminum and nickel films, the following problems arise.

[0046] For example, the case in which an ohmic electrode 133' is formed only on the p-type region 113 will be used as an example. Figure 20 This is an explanatory diagram showing the state during the formation process of an existing ohmic electrode. Figure 21 This is an enlarged illustration showing the state of an existing ohmic electrode. In Figure 20 and Figure 21 The upper section schematically shows the state of the ohmic electrode 133' as observed by a scanning electron microscope (SEM), and the lower section shows a cross-sectional view near the ohmic electrode 133'.

[0047] like Figure 20As shown, an n-type region covering the space between adjacent p-type regions 113 is formed on the front side of the semiconductor substrate 130. - The oxide film mask 171 of the p-type drift region 112 is then formed. Next, a metal material film 172 is formed on the oxide film mask 171 in such a way that it contacts the p-type region 113 within the opening 171a of the oxide film mask 171. Then, the metal material film 172 is reacted with the semiconductor substrate 130 and silicided by heat treatment to form a nickel silicide film that becomes the ohmic electrode 133'.

[0048] When the metal material film 172 is a laminate of aluminum and nickel films, during the heat treatment to silicide the contact area between the metal material film 172 and the semiconductor substrate 130, aluminum atoms in the metal material film 172 penetrate into the oxide mask 171 and react, generating product 134 within the oxide mask 171. It has been confirmed that this product 134 remains between the semiconductor substrate 130 and the Schottky electrode 131' even after device fabrication (see reference). Figure 21 This becomes a source of leakage current.

[0049] In order to eliminate the problems of the prior art, the present invention aims to provide a method for manufacturing a silicon carbide semiconductor device that maintains a low Vf characteristic and has high surge current tolerance by forming a low-resistance ohmic electrode, thereby increasing the amount of positive surge current extraction.

[0050] Technical solution

[0051] To solve the above-mentioned problems and achieve the objective of the present invention, the method for manufacturing a silicon carbide semiconductor device of the present invention has the following features. First, a first step is performed to form a first conductivity type region constituting a first main surface of the semiconductor substrate within a silicon carbide-containing semiconductor substrate. Next, a second step is performed to selectively form a first second conductivity type region on a surface region of the first conductivity type region located on the first main surface side of the semiconductor substrate. Next, a third step is performed to form an oxide film covering the first conductivity type region and the first second conductivity type region on the first main surface of the semiconductor substrate. Next, a fourth step is performed to selectively remove the oxide film, forming a first opening in the oxide film exposing the first second conductivity type region. Next, a fifth step is performed to sequentially stack a first nickel film, an aluminum film, and a metal film with a melting point higher than that of aluminum in contact with the first main surface of the semiconductor substrate at the first opening of the oxide film to form a metal material film. Next, a sixth step is performed to react the metal material film with the semiconductor substrate through a first heat treatment, and a compound layer is self-aligned and formed on the first main surface of the semiconductor substrate located in the first opening of the oxide film, using the oxide film as a mask. Next, after the sixth step described above, a seventh step is performed to remove the remaining portion of the metal material film, excluding the compound layer.

[0052] Next, following the seventh step, a second heat treatment at a temperature higher than the first heat treatment is performed to generate nickel silicide inside the compound layer, thus forming an eighth step of an ohmic bonded nickel silicide film to the semiconductor substrate. Next, following the eighth step, the oxide film sandwiched between the nickel silicide film is removed, forming a ninth step of a contact hole connecting all the first openings. Next, a tenth step is performed whereby a titanium film and an aluminum-containing metal electrode film, which are in contact with and Schottky bonded to the first conductivity type region, are sequentially stacked on the first main surface of the semiconductor substrate inside the contact hole to form a first electrode. Next, an eleventh step is performed to form a second electrode on the second main surface of the semiconductor substrate.

[0053] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the metal film with a melting point higher than that of aluminum is a second nickel film.

[0054] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the ratio of the thickness of the aluminum film to the thickness of the metal material film is 20% or more and 55% or less.

[0055] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the thickness of the first nickel film is 50 nm or more and 120 nm or less, the thickness of the aluminum film is 25 nm or more and 250 nm or less, and the thickness of the second nickel film is 50 nm or more and 120 nm or less.

[0056] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the metal film with a melting point higher than that of aluminum is a titanium film, a molybdenum film, or a tungsten film.

[0057] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the ratio of the thickness of the aluminum film to the thickness of the metal material film is 33% or more and 63% or less.

[0058] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the thickness of the first nickel film is 50 nm or more and 120 nm or less, and the thickness of the aluminum film is 25 nm or more and 210 nm or less.

[0059] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, in the sixth step, the temperature of the first heat treatment is set to 500°C or higher and 700°C or lower.

[0060] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, in the eighth step, the temperature of the second heat treatment is set to 900°C or higher and 1100°C or lower.

[0061] According to the invention described above, a silicide layer is formed using a stacked metal film consisting of a first nickel film, an aluminum film, and a metal film with a melting point higher than that of aluminum, such as a second nickel film. This suppresses the condensation of aluminum on the surface of the semiconductor substrate during heat treatment. Therefore, even if the sintering temperature is the same as conventionally, the silicide layer can be thickened, reducing surface resistance. Furthermore, the contact resistance between the nickel silicide film, which serves as an ohmic electrode, and the semiconductor substrate can be reduced.

[0062] Invention Effects

[0063] According to the method for manufacturing a silicon carbide semiconductor device of the present invention, by forming a low-resistance ohmic electrode, it is possible to maintain a low Vf characteristic and a high surge current tolerance, thereby improving the extraction of positive surge current. Attached Figure Description

[0064] Figure 1This is a top view showing the layout of the silicon carbide semiconductor device of the embodiment as viewed from the front side of the semiconductor substrate.

[0065] Figure 2 This is a top view showing the layout of the silicon carbide semiconductor device of the embodiment as viewed from the front side of the semiconductor substrate.

[0066] Figure 3 It means Figure 2 A cross-sectional view of the structure at the cutting line A-A'.

[0067] Figure 4 This is a flowchart illustrating a general outline of a method for manufacturing a silicon carbide semiconductor device according to an embodiment.

[0068] Figure 5 This is a cross-sectional view showing the state of the silicon carbide semiconductor device during the manufacturing process of the embodiment.

[0069] Figure 6 This is a cross-sectional view showing the state of the silicon carbide semiconductor device during the manufacturing process of the embodiment.

[0070] Figure 7 This is a cross-sectional view showing the state of the silicon carbide semiconductor device during the manufacturing process of the embodiment.

[0071] Figure 8 This is a cross-sectional view showing the state of the silicon carbide semiconductor device during the manufacturing process of the embodiment.

[0072] Figure 9 This is a cross-sectional view showing the state of the silicon carbide semiconductor device during the manufacturing process of the embodiment.

[0073] Figure 10 This is a cross-sectional view showing the state of the silicon carbide semiconductor device during the manufacturing process of the embodiment.

[0074] Figure 11 This is a cross-sectional view showing the state of the silicon carbide semiconductor device during the manufacturing process of the embodiment.

[0075] Figure 12 This is a cross-sectional view showing the state of the silicon carbide semiconductor device during the manufacturing process of the embodiment.

[0076] Figure 13 This is a cross-sectional view showing the state of the silicon carbide semiconductor device during the manufacturing process of the embodiment.

[0077] Figure 14 This is a cross-sectional view showing the state of the silicon carbide semiconductor device during the manufacturing process of the embodiment.

[0078] Figure 15This is a cross-sectional view showing the state of the silicon carbide semiconductor device during the manufacturing process of the embodiment.

[0079] Figure 16 This is a cross-sectional view schematically showing the state of the front electrode of the silicon carbide semiconductor device during the manufacturing process of an embodiment.

[0080] Figure 17 This is a cross-sectional view schematically showing the state of the front electrode of the silicon carbide semiconductor device during the manufacturing process of an embodiment.

[0081] Figure 18 This is a cross-sectional view schematically showing the state of the front electrode of the silicon carbide semiconductor device during the manufacturing process of an embodiment.

[0082] Figure 19 This is a graph showing the contact resistance of the front electrode of a silicon carbide semiconductor device utilizing various metal films.

[0083] Figure 20 This is an explanatory diagram showing the state during the formation process of an existing ohmic electrode.

[0084] Figure 21 This is an illustrated diagram showing the state of an existing ohmic electrode in an enlarged manner.

[0085] Figure 22 It is a top view showing the state of an existing silicon carbide semiconductor device as viewed from the front side of a semiconductor substrate.

[0086] Figure 23 This is a top view showing another example of an existing silicon carbide semiconductor device as viewed from the front side of a semiconductor substrate.

[0087] Figure 24 It means Figure 23 A cross-sectional view of the structure at the cutting line AA-AA'.

[0088] Figure 25 This is a cross-sectional view showing another example of an existing silicon carbide semiconductor device.

[0089] Figure 26 This is a cross-sectional view showing an example of an ohmic electrode self-aligned and formed using existing silicon carbide semiconductor device manufacturing methods.

[0090] Symbol Explanation

[0091] 10: Active region

[0092] 11:n + Type of starting substrate

[0093] 12:n - Type Drift Zone

[0094] 13, 72, 74: p-type regions constituting the JBS structure

[0095] 14: Front electrode

[0096] 15: Field Oxidation Film

[0097] 15': Covering the active region with n in the oxide film (oxide film mask) - Part of the drift zone

[0098] 15a: Contact pores of field oxide film

[0099] 16: Thermal Oxidation Film

[0100] 17: Accumulated oxide film

[0101] 18: Passivation film

[0102] 18a: Opening of the passivation film

[0103] 19: Back electrode

[0104] 20: Edge Terminal Area

[0105] 20a: Connection area of ​​edge terminal region

[0106] 21: Field-Constrained Loop (FLR)

[0107] 22: p that constitutes the JTE structure - Type area

[0108] 23: p that constitutes the JTE structure -- Type area

[0109] 24:n + Type-shaped trench cutoff area

[0110] 30: Semiconductor substrate

[0111] 31: Titanium film

[0112] 32: Aluminum alloy film

[0113] 33 (33a, 33b): Nickel silicide films (first nickel silicide film, second nickel silicide film)

[0114] 40: Silicon carbide semiconductor devices

[0115] 41: Solder pad

[0116] 42: The junction between the solder pad and the conductor

[0117] 50: Carbon protective film

[0118] 51: Oxide film (oxide film mask)

[0119] 51a, 51b: Openings of the oxide film (oxide film mask)

[0120] 52: Metallic material film

[0121] 53: Aluminum film

[0122] 54: Second nickel film

[0123] 55: Aluminum-nickel-silicon (Al-Ni-Si) compounds

[0124] 56: Aluminum-nickel compounds

[0125] 57: Resist film

[0126] 58: First nickel film

[0127] 61-64: Thermal diffusion

[0128] w1: Width of the p-type region constituting the JBS structure

[0129] w2a: Width of the first nickel silicide film

[0130] w2b: Width of the second nickel silicide film

[0131] w3: Width of the connection area in the edge terminal region Detailed Implementation

[0132] Hereinafter, preferred embodiments of the method for manufacturing the silicon carbide semiconductor device of the present invention will be described in detail with reference to the accompanying drawings. In this specification and the drawings, layers and regions prefixed with n or p respectively indicate that electrons or holes are the majority carriers. Furthermore, the + and - symbols marked on n and p respectively indicate higher and lower impurity concentrations than unmarked layers and regions. It should be noted that in the following description of the embodiments and the accompanying drawings, the same symbols are used to denote the same components, and repeated descriptions are omitted. It should be noted that in the expression of Miller indices, "-" is a symbol placed on the index following it, and a negative index is indicated by placing "-" before the index.

[0133] (Implementation Method)

[0134] The structure of the silicon carbide semiconductor device according to the embodiment will be described. Figure 1 and Figure 2 This is a top view showing the layout of a silicon carbide semiconductor device according to an embodiment, viewed from the front side of a semiconductor substrate. Figure 1 An example of the layout of the p-type region (first second conductivity type region) 13 constituting the JBS structure is shown. Figure 2 The diagram illustrates an example of the layout of pads 41 in various portions of the front side of a silicon carbide (SiC) semiconductor substrate (semiconductor chip) 30.

[0135] Figure 1 and Figure 2 The silicon carbide semiconductor device 40 shown in the embodiment is a silicon carbide diode, in which, in the active region 10, a front electrode (first electrode) 14 (see reference 14) is mixed on the front side of the semiconductor substrate 30. Figure 3 ) and n - The SBD structure is composed of a Schottky structure in the p-type drift region (first conductivity type region) 12 and an n-type region 13. - The JBS structure is formed by the pn structure of the drift region 12.

[0136] n - The p-type drift region 12 and the p-type region 13 are arranged in a roughly uniform pattern and are roughly equal in size within the surface of the active region 10. - The p-type drift region 12 and the p-type region 13 are configured as stripes extending in the same direction parallel to the front side of the semiconductor substrate 30, and are alternately and repeatedly arranged in a manner that they contact each other in a short-side direction orthogonal to the long-side direction in which the stripes extend. - The p-type drift region 12 is exposed on the front side of the semiconductor substrate 30 between adjacent p-type regions 13.

[0137] The active region 10 is the area where current flows when the silicon carbide diode is in the on-state. The active region 10 has a planar shape, for example, generally rectangular, and is disposed approximately at the center of the semiconductor substrate 30. The edge termination region 20 is the region between the active region 10 and the end of the semiconductor substrate 30, and surrounds the active region 10. The edge termination region 20 is a buffer zone. - The drift region 12 is a region on the front side of the semiconductor substrate 30 that maintains a withstand voltage while resisting the electric field. Withstand voltage refers to the limiting voltage at which the component will not malfunction or break down.

[0138] The edge terminal area 20 is equipped with a junction termination extension (JTE) structure and other pressure-resistant structures (see reference). Figure 3 The JTE structure is configured with multiple p-type regions of varying impurity concentrations, where the impurity concentration decreases from the inner side (center side of the semiconductor substrate 30) to the outer side (end side of the semiconductor substrate 30). Figure 3 The symbols 22 and 23) surround the active region 10 in a roughly rectangular planar shape, which is configured as a concentric circle pressure-resistant structure with the center of the active region 10 as the reference.

[0139] Additionally, in the connection area 20a of the edge terminal area 20 (refer to...) Figure 3 The active region 10 is equipped with a field-limiting ring (FLR, second conductivity type region) 21. The FLR 21 is a roughly rectangular ring surrounding the active region 10.+ Type region, and extends outward from the connection region 20a of the edge terminal region 20 and connects with p as described later. - Type 22 (refer to) Figure 3 FLR21 can contact the p-type region 13 along its length direction, where it extends in a striped pattern.

[0140] The connection region 20a of the edge termination region 20 is the region between the active region 10 and the field oxide film 15 (described later), surrounding the active region 10 and connecting the active region 10 to the voltage-resistant structure of the edge termination region 20. The voltage-resistant structure of the edge termination region 20 refers to the portion of the edge termination region 20 from the inner end of the field oxide film 15 (described later) to the end of the semiconductor substrate (chip end), and is equipped with a JTE structure and n... + Type 24 trench cutoff zone (refer to) Figure 3 (and other predetermined pressure-resistant structures.)

[0141] Front electrode 14 (reference) Figure 3 The active region 10 is disposed on the front side of the semiconductor substrate 30. The front electrode 14 is connected to n - The contact method between the n-type drift region 12 and the p-type region 13 is the same as that between the n-type drift region 12 and the n-type drift region 13. - The p-type drift region 12 and the p-type region 13 are electrically connected. A passivation film 18 is provided on the front side of the semiconductor substrate 30 (see reference). Figure 3 The passivation film 18 functions as a protective film for the component structure on the front side of the semiconductor substrate 30 and the front electrode 14.

[0142] An opening 18a is provided in the passivation film 18, exposing a portion of the front electrode 14. The portion of the front electrode 14 exposed in the opening 18a of the passivation film 18 functions as a pad 41. The pad 41 is disposed, for example, in the center of a semiconductor substrate 30. When current is supplied to the pad 41, aluminum (Al) wires, which are the most common wiring connections, are bonded (joined) to the pad 41.

[0143] exist Figure 2 In the diagram, the junction 42 between the pad 41 and the aluminum wire (not shown) is represented by a circular planar shape. For the junction 42 between the pad 41 and the aluminum wire, for example, in the case of bonding an aluminum wire with a diameter of 500 μm to the pad 41, a surface area of ​​approximately 1 mm square needs to be assumed. This is because, when a surge voltage is applied in the plane of the semiconductor substrate 30, the flow pattern of the forward-flowing surge current varies depending on the voltage rating of the silicon carbide diode.

[0144] Preferably, the pad 41 is positioned at the center of the semiconductor substrate 30, but as described above, n -The p-type drift region 12 and the p-type region 13 are arranged in a substantially uniform pattern and are approximately equally distributed within the plane of the active region 10. Therefore, even if the pad 41 is not disposed in the center of the semiconductor substrate 30, it will not adversely affect the electrical characteristics. As a result, the wire bonding has a high degree of freedom.

[0145] Next, the cross-sectional structure of the silicon carbide semiconductor device 40 according to the embodiment will be described. Figure 3 It means Figure 2 A cross-sectional view of the cross-sectional structure at the cutting line A-A'. As described above, the silicon carbide semiconductor device 40 of the embodiment has an SBD structure and a JBS structure of silicon carbide diode in the active region 10 of the silicon carbide semiconductor substrate 30, and has a JTE structure as a withstand voltage structure in the edge termination region 20.

[0146] Semiconductor substrate 30 is an n-type substrate containing silicon carbide. + The front side of the type starting substrate 11 is stacked with n - Type drift region 12 of n - An epitaxial substrate formed by an epitaxial layer. + Type-starting substrate 11 is n + Type-n cathode region. Semiconductor substrate 30 will have n - The main surface on the 12th side of the drift region (becoming n) - Type drift region 12 of n - The surface of the epitaxial layer is taken as the front side, and n is used as the front side. + Main surface (n) on side of type starting substrate 11 + The back side of the type starting substrate 11 is used as the back side.

[0147] In the active region 10, one or more p-type regions 13 constituting a JBS structure are selectively provided on the surface region of the front side of the semiconductor substrate 30. The p-type regions 13 are disposed on the front side of the semiconductor substrate 30 and the n-type region 13. - Between the n-type drift regions 12. The p-type region 13 is exposed on the front side of the semiconductor substrate 30 and is adjacent to the n-type drift region 12. - Type drift zone 12 contact.

[0148] In the edge terminal region 20, FLR 21 and one or more p-type regions (here, two) constituting the JTE structure are selectively provided on the surface area of ​​the front side of the semiconductor substrate 30. - Type 22 and p -- Type 23) and n + Type-type channel cutoff area 24. FLR21 is provided in the entire area of ​​the connection area 20a of the edge terminal area 20, and extends outward from the connection area 20a to connect with p. - Type region 22 is in contact. The inner side of FLR21 is the active region 10.

[0149] p- The connection area 20a between the type area 22 and the edge terminal area 20 is separately disposed on the outside of the FLR 21 and adjacent to the FLR 21. -- Type 23 is set in p - The outer side of type region 22, and with p - Type region 22 is adjacent. + Type 24 cutoff zone with p -- The separation method of type region 23 is set in a ratio of p -- The area near the outer edge of section 23. + The channel cutoff region 24 is exposed at the end (chip end) of the semiconductor substrate 30.

[0150] FLR21, p - Type 22, p -- Type 23 and n + The channel cutoff region 24 is disposed on the front side of the semiconductor substrate 30 and the n - Type drift zone 12. FLR21, p - Type 22, p -- Type 23 and n + The channel cutoff region 24 is exposed on the front side of the semiconductor substrate 30 and is adjacent to the n-type channel cutoff region 24. - Type drift region 12 contact. FLR21, p - Type 22, p -- Type 23 and n + The depth of the p-type channel cutoff region 24 can be the same as, for example, the depth of the p-type region 13.

[0151] The front side of the semiconductor substrate 30 is covered by a field oxide film 15. The field oxide film 15 may be, for example, a laminated film in which a thermal oxide film 16 and a stacked oxide film 17 are sequentially stacked. The thermal oxide film 16 can improve the adhesion between the semiconductor substrate 30 and the field oxide film 15. By including the stacked oxide film 17 in the field oxide film 15, the field oxide film 15 can be formed in a shorter time compared to the case where all field oxide films 15 are thermal oxide films 16.

[0152] The field oxide film 15 has contact holes 15a that expose almost the entire front side of the semiconductor substrate 30 in the active region 10. The sidewalls of the contact holes 15a (the inner side of the field oxide film 15) are substantially orthogonal to, for example, the front side of the semiconductor substrate 30. The contact holes 15a of the field oxide film 15 are provided over the entire region from the active region 10 to the connection region 20a of the edge termination region 20.

[0153] The active region 10 is exposed in the contact hole 15a of the field oxide film 15. -The portion inside the FLR21 in the p-type drift region 12, p-type region 13, and edge terminal region 20. Inside the contact hole 15a of the field oxide film 15, a front electrode 14, which functions as an anode electrode, is provided along the front side of the semiconductor substrate 30.

[0154] The front electrode 14 has a stacked structure consisting of a titanium film 31 and an aluminum alloy film (a metal electrode film containing aluminum) 32 sequentially stacked. Furthermore, the front electrode 14 has a bottommost nickel silicide (NiSi) film 33 (33a, 33b) selectively disposed between the front side of the semiconductor substrate 30 and the titanium film 31. The nickel silicide film 33 contains aluminum. The nickel silicide film 33 may also contain carbon (C). The front electrode 14 may extend outwards on the field oxide film 15.

[0155] A titanium film 31 is disposed inside the contact hole 15a on the entire front side of the semiconductor substrate 30, and is connected to n - Type drift region 12 contact. Titanium film 31 and n - The junction position of the drift region 12 is formed with n - Schottky electrode of Schottky junction in drift region 12. Titanium film 31 can extend outward on field oxide film 15, for example, it can be terminated in the depth direction at a position opposite to FLR 21.

[0156] The aluminum alloy film 32 covers the entire surface of the titanium film 31 and is electrically connected to the titanium film 31, and is electrically connected to the nickel silicide film 33 through the titanium film 31. The aluminum alloy film 32 may extend outwards from the titanium film 31 on the field oxide film 15, for example, it may extend in the depth direction in relation to the p-type surface. - The terminal is located opposite to the type area 22. The aluminum alloy film 32 is, for example, an aluminum silicon (AlSi) film. An aluminum film can be used instead of the aluminum alloy film 32.

[0157] The nickel silicide film 33 has a first nickel silicide film 33a disposed between the p-type region 13 and the titanium film 31, and a second nickel silicide film 33b disposed between the FLR 21 and the titanium film 31. The first nickel silicide film 33a is an ohmic electrode that is ohmically bonded to the p-type region 13. The first nickel silicide film 33a has the function of increasing the amount of surge current (extraction amount) extracted from the semiconductor substrate 30 to the front electrode 14 when a surge voltage is applied.

[0158] The first nickel silicide film 33a, as described later, is formed by a metal material film 52 (see reference 13) deposited on the front side of the semiconductor substrate 30 in the p-type region 13. Figure 10The first nickel silicide film 33a is formed by reacting the surface area of ​​the semiconductor substrate 30 with the metal material film 52 through heat treatment at the contact position. Therefore, the first nickel silicide film 33a is disposed on the surface area of ​​the front side of the semiconductor substrate 30, contacts the p-type region 13 in the depth direction, and protrudes from the front side of the semiconductor substrate 30 in a direction away from the front side of the semiconductor substrate 30.

[0159] Preferably, the width w2a of the first nickel silicide film 33a is approximately the same as, for example, the width w1 of the p-type region 13. By making the width w2a of the first nickel silicide film 33a the same as the width w1 of the p-type region 13, the p-type region 13 is not exposed on the front side of the semiconductor substrate 30. As a result, since a high-resistance Schottky junction between the p-type region 13 and the titanium film 31 is not formed, a lower forward voltage (Vf) of the silicon carbide diode can be achieved compared to the case where the p-type region 13 is exposed on the front side of the semiconductor substrate 30.

[0160] The width w2a of the first nickel silicide film 33a can be narrower than the width w1 of the p-type region 13. By making the width w2a of the first nickel silicide film 33a narrower than the width w1 of the p-type region 13, it is possible to obtain a mask used to improve the performance of the first nickel silicide film 33a (the remainder of the field oxide film 15 described later: see reference). Figure 10 The design margin for alignment accuracy is such that the first nickel silicide film 33a can be positioned with good accuracy in the depth direction opposite to the p-type region 13.

[0161] The second nickel silicide film 33b is an ohmic electrode ohmically bonded to the FLR21. The second nickel silicide film 33b is disposed over almost the entire surface of the FLR21 in the connection region 20a of the edge terminal region 20. The second nickel silicide film 33b is in contact with the field oxide film 15 at the sidewall. Like the first nickel silicide film 33a, the second nickel silicide film 33b has the function of increasing the surge current extraction rate and thus improving the surge current withstand capability.

[0162] By providing a second nickel silicide film 33b, an ohmic electrode with the same function as the first nickel silicide film 33a can be configured in the connection region 20a of the edge terminal region 20. Therefore, even when the chip size (the planar dimension parallel to the front side of the semiconductor substrate 30) is reduced, the ohmic bonding area between the front electrode 14 and the semiconductor substrate 30, sufficient for the predetermined surge current withstand capability, can be ensured within the total bonding area of ​​the first nickel silicide film 33a, the second nickel silicide film 33b, and the semiconductor substrate 30.

[0163] Furthermore, by extending the second nickel silicide film 33b outward to the position where it contacts the field oxide film 15, the ohmic bonding area between the FLR 21 and the second nickel silicide film 33b can be maximized. As a result, the width w2b of the second nickel silicide film 33b is approximately the same as the width w3 of the connection region 20a of the edge termination region 20, and as described above, the second nickel silicide film 33b can be disposed over almost the entire surface of the FLR 21 in the connection region 20a of the edge termination region 20.

[0164] Furthermore, by making the width w2b of the second nickel silicide film 33b approximately the same as the width w3 of the connection region 20a of the edge termination region 20, a low forward voltage can be achieved in the silicon carbide diode, similar to the case where the width w2a of the first nickel silicide film 33a is approximately the same as the width w1 of the p-type region 13. The width w2b of the second nickel silicide film 33b can be narrower than, for example, the width w3 of the connection region 20a of the edge termination region 20. The reason is the same as that for the first nickel silicide film 33a to be narrower than the width w1 of the p-type region 13.

[0165] As described later, the second nickel silicide film 33b is formed by reacting the semiconductor substrate 30 with the metal material film 52 at the contact position between the FLR 21 and the metal material film 52 deposited on the front side of the semiconductor substrate 30 through heat treatment. The second nickel silicide film 33b is disposed on the surface region of the front side of the semiconductor substrate 30, contacts the FLR 21 in the depth direction, and protrudes from the front side of the semiconductor substrate 30 in a direction away from the front side of the semiconductor substrate 30.

[0166] On the front side of the semiconductor substrate 30, the portion other than the area in contact with the front electrode 14 is covered by a field oxide film 15. A passivation film 18 comprising polyimide is provided on the outermost surface of the front side of the semiconductor substrate 30. Here, in n + The upper part of the channel cutoff area 24 can be set to interact with n + The channel cutoff electrode is electrically connected to the channel cutoff region 24 by means of contact. The channel cutoff electrode may be, for example, an aluminum alloy film formed simultaneously with the aluminum alloy film 32.

[0167] The passivation film 18 is a protective film that protects the front electrode 14 and the field oxide film 15. An opening 18a is provided in the active region 10 of the passivation film 18, exposing a portion of the aluminum alloy film 32. The portion of the front electrode 14 exposed at the opening 18a of the passivation film 18 functions as a pad 41. On the back side (n) of the semiconductor substrate 30... + A back electrode (second electrode) 19 is provided on the entire back surface of the type starting substrate 11, which is electrically connected to n + Type-initiating substrate 11.

[0168] Next, the manufacturing method of the silicon carbide semiconductor device 40 according to the embodiment will be described. Figure 4 This is a flowchart illustrating a general outline of a method for manufacturing a silicon carbide semiconductor device according to an embodiment. Figures 5-15 This is a cross-sectional view showing the state of the silicon carbide semiconductor device during the manufacturing process of the embodiment. Figures 16-18 This is a cross-sectional view schematically showing the state of the front electrode of the silicon carbide semiconductor device during the manufacturing process of an embodiment. Figure 19 This is a graph showing the contact resistance of the front electrode of a silicon carbide semiconductor device utilizing various metal films.

[0169] First, such as Figure 5 As shown, n + Type-based starting substrate (semiconductor wafer) 11, for example, prepared with 1×10⁻⁶ doped substrate. 16 / cm 3 A four-layer periodic hexagonal (4H-SiC) substrate of nitrogen (N) silicon carbide. + The front surface of the type-starting substrate 11 can have an angle of about 4° relative to, for example, the (0001) surface. Next, in n + On the front side of the type-starting substrate 11, make it n - For example, drift region 12 is doped with 1.8 × 10⁻⁶. 16 / cm 3 The left and right nitrogen n - Epitaxial layer growth (first process).

[0170] Become n + n-type cathode region + The thickness of the type-initiating substrate 11 can be, for example, around 350 μm. This becomes n - Type drift region 12 of n - The thickness of the epitaxial layer can be, for example, around 6 μm. Through the processes up to this point, an epitaxial layer is fabricated on the n-type... + The front side of the type starting substrate 11 is stacked with n - Type drift region 12 of n - A semiconductor substrate (semiconductor wafer) 30 with an epitaxial layer. As described above, the semiconductor substrate 30 has an n-type epitaxial layer. - The main surface on each side of the drift zone 12 is taken as the front surface, and n + The main surface of the type starting substrate 11 is used as the back side.

[0171] Next, as Figure 6 As shown, by photolithography and first ion implantation of p-type impurities such as aluminum, in the active region 10 (reference) Figure 1 and Figure 3In this process, one or more p-type regions 13 and FLR 21 constituting the JBS structure are selectively formed on the surface region of the front side of the semiconductor substrate 30 (step S1(one): second process, third process). Figure 6 In the middle, simplified to use comparison Figure 1 The minimum number (3 in this case) is illustrated in p-type area 13 (in Figures 7-15 The same applies to the middle section. Multiple p-type regions 13 are arranged at equal intervals in a direction parallel to the front side of the semiconductor substrate 30, for example, with a spacing of about 2 μm.

[0172] At this time, while heating the semiconductor substrate 30 to a temperature of, for example, around 500°C, the front side of the semiconductor substrate 30 is turned towards n - Type epitaxial layer (n) - A first ion implantation is performed in the drift region 12. In this first ion implantation, the impurity concentration in a box profile, for example, from the front surface of the semiconductor substrate 30 to a depth of 500 nm, is set to 2 × 10⁻⁶. 19 / cm 3 The method involves multi-stage ion implantation of p-type impurities using different acceleration energies ranging from 30 keV to 350 keV.

[0173] Next, as Figure 7 As shown, the process of photolithography and second ion implantation of impurities, grouped into one step, is repeatedly performed under different conditions in the edge terminal region 20 (refer to...). Figure 3 In the process, p-type regions constituting the JTE structure are selectively formed on the surface region of the front side of the semiconductor substrate 30. - Type 22 and p -- Type 23) and n + Type 24 trench cutoff zone (refer to) Figure 3 (Step S1 (Part Two)). The second ion implantation is performed in multiple stages, for example, in the same manner as the first ion implantation, to make the impurity concentration distribution into a box-shaped distribution.

[0174] Next, as Figure 8 As shown, after the entire front side of the semiconductor substrate 30 is protected by, for example, a carbon (C) protective film 50, the impurities that have undergone the first and second ion implantations are activated by heat treatment (step S2). In the process of step S2, for example, the semiconductor substrate 30 is inserted into the processing furnace of the heat treatment apparatus, and the atmosphere inside the processing furnace is drawn (evacuated) to 1×10⁻⁶. -2 After a pressure below Pa, argon (Ar) gas is introduced into the processing furnace at a pressure of 1×10⁻⁶ Pa. 5 The mixture is subjected to heat treatment at a temperature of approximately 1700°C for about 5 minutes in an atmosphere with a pressure of approximately Pa.

[0175] Next, as Figure 9 As shown, for example, an ashing apparatus is used to remove the carbon protective film 50 by ashing. For example, a reactive ion etching (RIE) apparatus is used as the ashing apparatus. After setting the processing furnace of the RIE apparatus to an oxygen (O2) gas atmosphere with a pressure of about 6 Pa, a high-frequency (RF) power of about 500 W is applied, and the carbon protective film 50 is removed by ashing for about 5 minutes in a plasma-enhanced oxygen atmosphere.

[0176] Next, as Figure 10 As shown, an oxide film 51 is formed on the entire front side of the semiconductor substrate 30 (step S3: third process). Next, the oxide film 51 is selectively removed by photolithography and etching to form openings (first opening, second opening) 51a, 51b (step S4: fourth process). In the process of step S4, multiple openings 51a that expose different p-type regions 13 and one opening 51b that surrounds the active region 10 and exposes the inner side of the FLR 21 in a generally rectangular shape are formed on the oxide film 51.

[0177] Through the treatment in step S4, the oxide film 51 is retained in the active region 10, covering n - The drift region 12 portion 15' and the portion that becomes the field oxide film 15 in the edge terminal region 20. After the processing in step S4, all oxide films 51, including the portion that becomes the field oxide film 15, become the oxide film mask used to form the nickel silicide film 33 in the subsequent process. The oxide film 51 covers n in the active region 10. - Part 15' of the drift zone 12 does not remain in the product.

[0178] That is, in step S4, a field oxide film 15 and an oxide film mask for forming a nickel silicide film 33 are formed simultaneously. Therefore, oxide film 51 has the same stacked structure as field oxide film 15. Specifically, oxide film 51 is formed by, for example, sequentially stacking a thermal oxide film 16 and a deposited oxide film 17 (see reference) via thermal oxidation and chemical vapor deposition (CVD). Figure 3 A stacked oxide film with a thickness of about 500 nm.

[0179] The process in step S4 can be performed using dry etching with high dimensional accuracy. This allows the p-type region 13 and FLR21 to be exposed with high dimensional accuracy. Furthermore, the sidewall outside the opening 51b of the oxide film 51 becomes the sidewall of the contact hole 15a of the field oxide film 15. Therefore, by using dry etching to perform step S4, the contact hole 15a of the field oxide film 15 can be formed with high dimensional accuracy.

[0180] Next, a metal material film 52 is formed on the surface of the semiconductor substrate 30 from the surface of the oxide film 51 to the front surface (surface) of the semiconductor substrate 30 within the openings 51a and 51b of the oxide film 51 using, for example, sputtering (step S5: fifth process). The metal material film 52 is a stacked metal film consisting of a first nickel film 58, an aluminum film (a metal film containing aluminum) 53, and a metal film with a melting point higher than that of aluminum, such as a second nickel film 54. Figure 16 ).exist Figure 10 In the diagram, the first nickel film 58, the aluminum film 53, and the second nickel film 54 are collectively shown as a single-layer metal material film 52.

[0181] In silicon carbide semiconductor devices, aluminum films are formed as ohmic electrodes to reduce contact resistance with the p-type region (p-type region 13 and field confinement ring 21 constituting the JBS structure). However, using only aluminum results in a violent alloying reaction and surface shrinkage after heat treatment. By using nickel silicides in addition to aluminum, it is possible to further reduce the contact resistance with the p-type region, but the reduction in sheet resistance is limited.

[0182] Therefore, when silicon carbide and nickel are silicided using a stacked metal film with aluminum and nickel films sequentially layered, the surface resistivity can be reduced by reacting the remaining carbon with aluminum to form Al3C. Furthermore, by performing a two-stage sintering process similar to that used for nickel silicide, self-aligned formation is possible.

[0183] However, in a stacked metal film consisting of aluminum and nickel films layered sequentially, the condensation of aluminum occurs on the surface of the semiconductor substrate, thus limiting the upper limit of the sintering temperature in the first stage and restricting the thickness of the resulting silicide layer. Furthermore, a portion of the silicide layer disappears in subsequent processes.

[0184] Therefore, in the method for manufacturing a silicon carbide semiconductor device according to the embodiment, a stacked metal film consisting of a first nickel film 58, an aluminum film 53, and a second nickel film 54 is used. The first nickel film 58 is a film used to suppress the condensation of aluminum on the surface of the semiconductor substrate 30 during the heat treatment in step S6 (described later), and has, for example, a thickness t3 of about 80 nm. Without the first nickel film 58, the aluminum film 53 is in contact with the semiconductor substrate 30, making it impossible for the Al-Ni-Si compound (compound layer) 55 (described later) to be uniformly formed on the entire front side of the semiconductor substrate 30.

[0185] In this embodiment, since the stacked metal film consists of three layers—a first nickel film 58, an aluminum film 53, and a second nickel film 54—the thickness of the resulting silicide layer can be increased. Furthermore, by utilizing the first nickel film 58, even if the sintering temperature in the first stage (step S6 described later) is the same as in the conventional case (for a stacked metal film with aluminum and nickel films stacked sequentially), the silicide layer can still be thickened. Therefore, the ohmic area can be increased, and the surface resistivity can be reduced.

[0186] exist Figure 19 In the diagram, the vertical axis represents contact resistance, with units of Ωcm. 2 The horizontal axis represents the composition of the metal film used to form the silicide layer. For example... Figure 19 As shown, Ni has a lower contact resistance than Ti, and AlNi has a lower contact resistance than Ni. Furthermore, the contact resistance of the NiAlNi embodiment is 2.51 × 10⁻⁶. -4 Ωcm 2 The thickness is even lower. Furthermore, when the metal film is NiAlNi, the film thickness is 80 nm.

[0187] The second nickel film 54 is a capping film that prevents the aluminum film 53 from melting during the heat treatment in step S6 (described later), and has a thickness t2 of, for example, about 80 nm. The capping film is used for the following reasons: Without the capping film, the molten aluminum film 53 in the heat treatment of step S6 becomes granular and partially contacts the semiconductor substrate 30. In this case, it is impossible to uniformly form the Al-Ni-Si compound (compound layer) 55 (described later) on the entire front side of the semiconductor substrate 30.

[0188] Here, the second nickel film 54 is a film used to prevent aluminum, which melts on the surface of the semiconductor substrate 30 due to heat treatment, from scattering. Therefore, it can be a film of other metals with a higher melting point than aluminum, such as molybdenum (Mo), tantalum (Ta), titanium (Ti), or tungsten (W). For example, in the case of titanium, a film thickness of about 50 nm is preferred. Since the nickel film can be removed in the wet etching of step S7, which removes the remaining metal (residual portion) described later, the second nickel film 54 is more preferred than other materials.

[0189] Furthermore, when the metal film is configured as a first nickel film 58, an aluminum film 53, and a second nickel film 54, the film thickness t1 of the aluminum film 53 is preferably 20% or more and 55% or less of the film thickness of the metal film. Additionally, the film thickness t3 of the first nickel film 58 is preferably 50 nm or more and 120 nm or less; the film thickness t1 of the aluminum film 53 is preferably 25 nm or more and 250 nm or less; and the film thickness t2 of the second nickel film 54 is preferably 50 nm or more and 120 nm or less.

[0190] Furthermore, when the second nickel film 54 is a metal other than nickel, the film thickness t1 of the aluminum film 53 is preferably 33% or more and 63% or less of the thickness of the metal film. Additionally, the film thickness t3 of the first nickel film 58 is preferably 50 nm or more and 120 nm or less, and the film thickness t1 of the aluminum film 53 is preferably 25 nm or more and 210 nm or less. When the film thickness t1 of the aluminum film 53 is 20 nm or less, since the second nickel film 54 facilitates the reaction between the aluminum film 53 and the second nickel film 54, the film thickness t1 of the aluminum film 53 is preferably thicker than 20 nm, and more preferably 25 nm or more.

[0191] Then, the metal film 52 is subjected to a first sintering (sintering) through heat treatment (step S6: sixth process), thereby generating an aluminum-nickel-silicon (Al-Ni-Si) compound 55 (refer to) within the openings 51a and 51b of the oxide film 51. Figure 11 ).use Figures 16-18 The mechanism by which this heat treatment (first sintering) generates Al-Ni-Si compound 55 is explained in detail.

[0192] exist Figure 16 Only the contact positions between the metal material film 52 within the openings 51a and 51b of the oxide film 51 and the semiconductor substrate 30 are shown; illustrations of other parts are omitted. Figure 17 , Figure 18 The same applies in China). Although in Figure 16 The diagram shows the state within one opening (51a, 51b) of the oxide film 51, but all openings 51a and 51b of the oxide film 51 are identical to... Figure 16 The state shown is the same as the state shown.

[0193] Through the heat treatment in step S6, at the contact points between the metal material film 52 and the semiconductor substrate 30 within the openings 51a and 51b of the oxide film 51, silicon atoms in the semiconductor substrate 30 undergo thermal diffusion 61 into the aluminum film 53. Aluminum atoms in the aluminum film 53 undergo thermal diffusion 62 into the first nickel film 58 and the second nickel film 54. Nickel atoms in the first nickel film 58 undergo thermal diffusion 63 into the semiconductor substrate 30, and nickel atoms in the second nickel film 54 undergo thermal diffusion 64 into the aluminum film 53. Figure 17 ).

[0194] Through thermal diffusion 62 of aluminum atoms into the second nickel film 54 and thermal diffusion 64 of nickel atoms into the aluminum film 53, an aluminum-nickel (AlNi) compound 56 is formed on the front side of the semiconductor substrate 30 within the openings 51a and 51b of the oxide film 51 and on the surface of the oxide film 51. Furthermore, through thermal diffusion 62 of aluminum atoms into the first nickel film 58, thermal diffusion 63 of nickel atoms into the semiconductor substrate 30, and thermal diffusion 61 of silicon atoms into the first nickel film 58, an Al-Ni-Si compound 55 is formed at the contact site between the metal film 52 and the semiconductor substrate 30. Figure 18 ).

[0195] The Al-Ni-Si compound 55 is formed by reacting a portion of the p-type region 13 and FLR21, which are diffusion regions formed by ion implantation, at a shallow depth of approximately 20 nm to 30 nm from the front side of the semiconductor substrate 30 with a metal film 52. Therefore, the compound layer containing the Al-Ni-Si compound 55 is formed by self-aligning the oxide film 51 as a mask, in a manner that penetrates into the interior of the semiconductor substrate 30 in the depth direction within the openings 51a and 51b of the oxide film 51.

[0196] Furthermore, the Al-Ni-Si compound 55 contacts a portion of the p-type region 13 or the FLR 21 that is located at a depth greater than the aforementioned low-impurity-concentration portion on the front side of the semiconductor substrate 30, and where the impurity concentration is higher than that of the low-impurity-concentration portion. The Al-Ni-Si compound 55 forms a low-resistance ohmic bond with the high-impurity-concentration portion within the p-type region 13 or the FLR 21.

[0197] Within the Al-Ni-Si compound 55, the residual carbon (C) in the semiconductor substrate 30 (hereinafter referred to as residual carbon) can be precipitated in a non-layered manner through the silicide reaction between the Al-Ni-Si compound 55 and the semiconductor substrate 30. Residual carbon refers to the carbon atoms remaining in the semiconductor substrate 30 after the silicon atoms in the semiconductor substrate 30 have been consumed by the aforementioned silicide reaction. Specifically, within the Al-Ni-Si compound 55, the residual carbon can be precipitated and distributed in a granular form.

[0198] Considering the uniformity of the chemical reaction, the heat treatment time in step S6 can be, for example, more than 2 minutes, and considering the mass production of the product, it can be, for example, less than 1 hour. Preferably, the heat treatment temperature in step S6 is, for example, between 500°C and 700°C. The reason is as follows: When the heat treatment temperature in step S6 exceeds 700°C, the aluminum-nickel compound 56 penetrates into the oxide film 51, which is a silicon oxide (SiO2) film, and reacts, generating a product within the oxide film 51 as described later. In the subsequent step S7, which removes the remaining metal (residual portion), since the nickel silicide film 33 is not removed, this product remains in the field oxide film 15, and this product becomes a cause of leakage current problems under reverse bias.

[0199] This is because when the heat treatment temperature in step S6 is less than 500°C, the aforementioned reaction between the semiconductor substrate 30 and the metal film 52 does not occur, so the metal film 52 is not used, and in the subsequent step S7, the metal film 52 is completely removed. The heat treatment in step S6 is preferably performed in, for example, a heat treatment furnace where the heat treatment temperature can be easily and uniformly managed. Temperature uniformity means approximately the same temperature within a range that includes the error allowed by process variations. The above is a detailed description of the first sintering.

[0200] Next, as Figure 12 As shown, the remaining metal (residual portion) on the oxide film 51 and within the openings 51a and 51b of the oxide film 51 is removed (step S7: seventh process). The remaining metal refers to the unreacted metal material film 52 and the metal formed from the metal material film 52 other than the nickel silicide film 33; specifically, it is the aluminum-nickel compound 56, which does not contribute to the formation of the nickel silicide film 33. In the process of step S7, for example, the entire front side of the semiconductor substrate 30 is etched using wet etching with phosphonitroacetic acid. Through the process of step S7, Al-Ni-Si compound 55 remains within each opening 51a and 51b of the oxide film 51.

[0201] Next, as Figure 13 As shown, the Al-Ni-Si compound 55 undergoes a second sintering process (step S8: eighth step) through heat treatment. Through the heat treatment in step S8, nickel silicide is generated within the Al-Ni-Si compound 55, making the Al-Ni-Si compound 55 a nickel silicide film 33 that is ohmically bonded to the semiconductor substrate 30. Thus, nickel silicide films 33 that are ohmically bonded to the semiconductor substrate 30 are formed in each opening 51a, 51b of the oxide film 51, using the oxide film 51 as a mask, in a self-aligned manner.

[0202] The heat treatment temperature in step S8 can be, for example, a higher temperature than that in step S6. Preferably, the heat treatment temperature in step S8 is at a level above 900°C where nickel silicide is formed within the Al-Ni-Si compound 55, and at a level below 1100°C where it can be performed at low cost using a vertical heat treatment furnace. The heat treatment in step S8 is preferably performed using, for example, a heat treatment furnace capable of uniformly controlling the heat treatment temperature.

[0203] Next, as Figure 14 As shown, a photoresist film 57 is formed by photolithography to create an opening in the contact hole 15a of the field oxide film 15. Next, the photoresist film 57 is used as a mask for etching to form a contact hole 15a penetrating the field oxide film 15 in the depth direction (step S9: ninth process). In this step S9, only the portion of the oxide film 51 that becomes the field oxide film 15 remains.

[0204] In the process of step S9, by covering the active region 10 with n in the oxide film 51 - The entire portion 15' of the drift region 12 is removed, and all openings 51a and 51b of the oxide film 51 are connected, thereby creating the contact hole 15a formed in step S4. During this step S9, since the entire sidewall outside the opening 51b of the oxide film 51 is completely covered by the resist film 57, the sidewall outside the opening 51b of the oxide film 51 is not etched.

[0205] The contact hole 15a of the field oxide film 15 exposes the entire surface of the active region 10 and the entire surface of the connection region 20a of the edge terminal region 20. Thus, the contact hole 15a of the field oxide film 15 exposes all of the nickel silicide films 33 (33a, 33b) and n - The portion of the drift region 12 sandwiched between adjacent nickel silicide films 33.

[0206] When the width w2a of the first nickel silicide film 33a is less than the width w1 of the p-type region 13, and the width w2b of the second nickel silicide film 33b is less than the width w3 of the connection region 20a of the edge terminal region 20, the contact hole 15a of the field oxide film 15 still exposes the portion of the surface of the p-type region 13 and FLR21 that is not bonded to the nickel silicide film 33.

[0207] The processing in step S9 is preferably performed by wet etching. This is because if step S9 is performed by dry etching, plasma damage caused by dry etching may remain on the front side of the semiconductor substrate 30. Even if step S9 is performed by wet etching, contact holes 15a can be formed in the field oxide film 15 with high dimensional accuracy. This is because, during the processing in step S4, the sidewalls of the openings 51b formed with high dimensional accuracy in the oxide film 51 by dry etching are formed by the sidewalls of the contact holes 15a in the field oxide film 15.

[0208] In step S4, the covering n in the residual oxide film 51 - Part 15' of the drift region 12 and part of the field oxide film 15 (see reference) Figure 10 Therefore, after the processing in step S4, the covering n in the oxide film 51 becomes - The portion 15' of the drift region 12 remains within the contact hole 15a of the field oxide film 15, and the outer sidewall of the opening 51b of the oxide film 51 is formed by the sidewall of the contact hole 15a of the field oxide film 15. During the processing in step S9, the outer sidewall of the opening 51b of the oxide film 51 is completely covered by the resist film 57 and is not etched. Therefore, after the processing in step S4, the position of the outer sidewall of the opening 51b of the oxide film 51 remains unchanged.

[0209] Thus, the dimensional accuracy of the contact hole 15a of the field oxide film 15 is the same as the dimensional accuracy of the opening 51b of the oxide film 51 formed by dry etching, and does not depend on the dimensional accuracy of the wet etching in step S9. Furthermore, since the position of the outer sidewall of the opening 51b of the oxide film 51 does not change after step S4, the second nickel silicide film 33b, which is self-aligned and formed using the oxide film 51 as a mask, also remains in contact with the outer sidewall of the opening 51b of the oxide film 51 after step S9. That is, the second nickel silicide film 33b also remains in contact with the field oxide film 15 in the sidewall of the contact hole 15a after step S9.

[0210] Next, as Figure 15 As shown, a titanium film 31 is formed on the entire surface of the semiconductor substrate 30, from the surface of the field oxide film 15 to the front side within the contact hole 15a, for example, by physical vapor deposition (PVD) such as sputtering. Next, photolithography and etching are used to ensure that the titanium film 31 remains only within the contact hole 15a (step S10: tenth process). The thickness of the titanium film 31 can be, for example, around 100 nm. The titanium film 31 can extend from within the contact hole 15a onto the field oxide film 15.

[0211] Next, the titanium film 31 is sintered at a temperature of approximately 500°C for about 10 minutes. Through this heat treatment, the titanium film 31 and n are formed. - The Schottky junction of the drift region 12 is then formed. Next, an aluminum alloy film with a thickness of approximately 5 μm is formed over the entire surface from the surface of the titanium film 31 to the surface of the field oxide film 15 by physical vapor deposition, such as sputtering. The aluminum alloy film is then selectively removed by photolithography and etching, leaving it as the aluminum alloy film 32 that serves as the front electrode 14 on the surface of the titanium film 31.

[0212] Next, after protecting the front side of the semiconductor substrate 30 (semiconductor wafer) by covering it with a protective film (not shown), the semiconductor substrate 30 is thinned to the product thickness by grinding from the back side. Next, a physical vapor deposition method, such as sputtering, is used to deposit a thin film on the back side (n) of the semiconductor substrate 30. + After nickel and titanium are formed on the entire back surface of the starting substrate 11, the back electrode 19 is formed by laser annealing (step S11: eleventh process). Subsequently, after removing the protective film on the front surface of the semiconductor substrate 30, the semiconductor substrate 30 is monolithically formed into individual chips by cutting (splitting), thereby completing the process. Figures 1-3 The silicon carbide semiconductor device 40 shown.

[0213] As described above, according to the embodiment, a silicide layer is formed using a stacked metal film in which a first nickel film, an aluminum film, and a second nickel film are sequentially stacked. This suppresses the condensation of aluminum on the surface of the semiconductor substrate during heat treatment. Therefore, even if the sintering temperature is the same as conventionally, the silicide layer can be thickened, reducing surface resistance. Furthermore, according to the embodiment, the contact resistance between the nickel silicide film, which serves as an ohmic electrode, and the semiconductor substrate can be reduced.

[0214] The present invention is not limited to the embodiments described above. Various modifications can be made without departing from the spirit of the present invention, and it can be applied to silicon carbide semiconductor devices having ohmic electrodes that are ohmically bonded to p-type regions arranged in a predetermined pattern.

[0215] Specifically, for example, the present invention addresses the use of p-type regions (or p-type regions disposed between the p-type region and the main surface of the semiconductor substrate) to reduce p-type regions. + A silicon carbide semiconductor device is useful for constructing a contact resistance between a p-type contact region and an ohmic electrode, and for constructing a silicon carbide semiconductor device with a structure that allows an ohmic electrode that is ohmically bonded to the p-type region to contact an oxide film.

[0216] Furthermore, for example, in a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with an SBD built into the same semiconductor substrate, the present invention can be applied to the configuration of the front side of the semiconductor substrate.

[0217] Furthermore, in the reverse-conducting IGBT (RC-IGBT), which integrates an IGBT (Insulated Gate Bipolar Transistor) and a FWD (Free Wheeling Diode) connected in reverse parallel with the IGBT on the same semiconductor chip, it can be applied to the portion of the back side of the semiconductor substrate where a p-type collector region is formed. In contrast, the IGBT can be applied to the entire back side of the semiconductor substrate.

[0218] Industrial availability

[0219] As described above, the method for manufacturing a silicon carbide semiconductor device of the present invention is useful for power semiconductor devices used in power conversion devices, power supply devices for various industrial machinery, and the like.

Claims

1. A method for manufacturing a silicon carbide semiconductor device, characterized in that, include: In the first step, a first conductivity type region constituting the first main surface of the semiconductor substrate is formed inside the semiconductor substrate containing silicon carbide. In the second step, a first second conductivity type region is selectively formed on the surface region of the first conductivity type region located on the first main surface side of the semiconductor substrate; In the third step, an oxide film covering the first conductivity region and the first second conductivity region is formed on the first main surface of the semiconductor substrate; The fourth step involves selectively removing the oxide film, thereby forming a first opening in the oxide film that exposes the first second conductivity type region. In the fifth step, a first nickel film, an aluminum film, and a metal film with a melting point higher than that of aluminum are sequentially stacked at the first opening of the oxide film to form a metal material film. In the sixth step, the metal material film is reacted with the semiconductor substrate through a first heat treatment, and a compound layer is self-aligned and generated on the first main surface of the semiconductor substrate located in the first opening of the oxide film, using the oxide film as a mask. The seventh step, after the sixth step, is to remove the remaining portion of the metal material film except for the compound layer; In the eighth step, after the seventh step, a second heat treatment at a temperature higher than that of the first heat treatment is performed to generate nickel silicide inside the compound layer, thereby forming a nickel silicide film that is ohmically bonded to the semiconductor substrate. The ninth step, after the eighth step, is to remove the oxide film sandwiched by the nickel silicide film, thereby forming a contact hole that connects all the first openings. In the tenth step, inside the contact hole, a titanium film and an aluminum-containing metal electrode film are sequentially stacked on the first main surface of the semiconductor substrate to form a first electrode, which are in contact with the first conductive region and are Schottky bonded to the first conductive region. as well as In the eleventh step, a second electrode is formed on the second main surface of the semiconductor substrate.

2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, characterized in that, The metal film with a melting point higher than that of aluminum is the second nickel film.

3. The method for manufacturing a silicon carbide semiconductor device according to claim 2, characterized in that, The ratio of the thickness of the aluminum film to the thickness of the metal material film is more than 20% and less than 55%.

4. The method for manufacturing a silicon carbide semiconductor device according to claim 3, characterized in that, The thickness of the first nickel film is greater than 50 nm and less than 120 nm. The thickness of the aluminum film is greater than 25nm and less than 250nm. The thickness of the second nickel film is greater than 50 nm and less than 120 nm.

5. The method for manufacturing a silicon carbide semiconductor device according to claim 1, characterized in that, The metal film with a melting point higher than that of aluminum is a titanium film, a molybdenum film, or a tungsten film.

6. The method for manufacturing a silicon carbide semiconductor device according to claim 5, characterized in that, The ratio of the thickness of the aluminum film to the thickness of the metal material film is more than 33% and less than 63%.

7. The method for manufacturing a silicon carbide semiconductor device according to claim 6, characterized in that, The thickness of the first nickel film is greater than 50 nm and less than 120 nm. The thickness of the aluminum film is above 25nm and below 210nm.

8. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 7, characterized in that, In the sixth step, the temperature of the first heat treatment is set to be above 500°C and below 700°C.

9. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 7, characterized in that, In the eighth step, the temperature of the second heat treatment is set to above 900°C and below 1100°C.

10. The method for manufacturing a silicon carbide semiconductor device according to claim 8, characterized in that, In the eighth step, the temperature of the second heat treatment is set to above 900°C and below 1100°C.

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