Reverse charging system, reverse charging method and terminal device

Abstract

The embodiments of the present application provide a reverse charging system, a reverse charging method and a terminal device, which relate to the field of communications. The method includes: a master terminal device can output an electrical signal on a D-line of an OTG line connected to a slave terminal device during reverse charging of a slave terminal device, so that the slave terminal device identifies a USB port as a CDP based on a high level on the D-line, thereby enabling the slave terminal device to charge under a CDP with a greater current transmission capability, thereby improving the charging efficiency.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of terminal technology, and in particular to a reverse charging system, a reverse charging method and a terminal device. Background Art

[0002] With the continuous development of communication technology, the functions of mobile phones are becoming more and more powerful. Among them, one function of mobile phones is to power other mobile phones or devices, so as to provide a charging method in special circumstances, such as when a charging power source cannot be found in time, which is the reverse charging method.

[0003] In the prior art, when a mobile phone or tablet is used to reverse charge other devices, as the main device providing current, the mobile phone or tablet can provide 1.5A or even 2A of current. However, based on the BC1.2 protocol requirements of USB, the device to be charged usually identifies the USB port as a standard downstream port (Standard Downstream Port, SCP). In this case, the device to be charged only charges at a current of 500mA after identifying the SCP port according to the current correspondence relationship specified by BC1.2. Summary of the invention

[0004] The present application provides a reverse charging method, a reverse charging system and a terminal device, which can enable the terminal device to be charged at a current size corresponding to a CDP port.

[0005] In order to achieve the above objectives, this application adopts the following technical solutions:

[0006] In the first aspect, an embodiment of the present application provides a reverse charging method, which is applied to a slave terminal device, wherein the slave terminal device is connected to the master terminal device via an OTG line, wherein the OTG line includes a D+ line, a D- line, and a VBUS line, and the method includes: the slave terminal device responds to the power supply signal output by the master terminal device on the detected VBUS line, and outputs a first electrical signal on the D+ line, wherein the first electrical signal makes the level on the D+ line high. Then, the slave terminal device responds to the second electrical signal output by the master terminal device on the detected D- line, and obtains the level on the D- line. Wherein, if the level on the D- line obtained by the slave terminal device is a high level, the slave terminal device stops outputting the first electrical signal on the D+ line, and outputs a third electrical signal on the D- line, and obtains the level on the D+ line. If the level on the D+ line obtained by the slave terminal device is a low level, the slave terminal device determines that the USB port type connected to the master terminal device via the OTG line is CDP, and charges according to the current size corresponding to the CDP.

[0007] Based on the above method, it is achieved that after detecting a high level on the D-line, the slave device can determine that the USB port is not an SDP, and based on the result, can further determine that the USB port is a CDP. Then, the slave terminal device can be charged based on the current size corresponding to the CDP under the power supply signal provided by the master terminal device. Compared with the current transmission capacity of the SDP, the CDP has a larger current transmission capacity, that is, the slave device can be charged at a larger current, thereby improving the charging efficiency and shortening the charging time.

[0008] In a possible implementation, the D+ line is connected to a first comparator in the master terminal device, and the voltage of the first electrical signal is greater than a first reference voltage of the first comparator.

[0009] Based on the above method, the slave terminal device can output a first electrical signal with a voltage greater than a first reference voltage, so that the output result of the first comparator indicates that the level on the D+ line becomes a high level.

[0010] In one possible implementation, the D-line is connected to a second comparator in a terminal device, and the voltage of the second electrical signal is greater than a second reference voltage of the second comparator; obtaining the level on the D-line includes: reading a first output value of the second comparator from the terminal device as a first preset value, determining that the level on the D-line is a high level, and confirming that the USB port type is CDP or DCP, wherein the first output value is a result of the second comparator comparing the voltage of the second electrical signal with the second reference voltage.

[0011] Based on the above method, the output value of the second comparator is read from the terminal device to determine that the level on the D-line is a high level, thereby confirming that the USB port is not an SDP, that is, the USB port is a CDP or a DCP.

[0012] In one possible implementation, the D+ line is connected to a third comparator in a slave terminal device; obtaining the level on the D+ line includes: reading a second output value of the third comparator from the terminal device as a second preset value, and determining that the level on the D+ line is a low level.

[0013] Based on the above method, it is achieved that the slave terminal device can determine that the level on the D+ line is a low level by reading the output value of the third comparator.

[0014] In a possible implementation, the current corresponding to CDP is 1.5A.

[0015] Based on the above method, it is achieved that the terminal device can be charged based on the current corresponding to the CDP, that is, 1.5A, so as to obtain a larger transmission current than the SCP.

[0016] In the second aspect, an embodiment of the present application provides a reverse charging method, which is applied to a master terminal device, wherein the master terminal device is connected to a slave terminal device via an OTG line, wherein the OTG line includes a D+ line, a D- line, and VBUS, and the method includes: after the master terminal device outputs a power supply signal on the VBUS line, in response to a first electrical signal detected on the D+ line output by the slave terminal device, obtaining the electrical level on the D+ line; if the electrical level on the D+ line is a high level, the master terminal device controls the first power supply module to output a second electrical signal on the D- line, and the second electrical signal makes the electrical level on the D+ line a high level.

[0017] Based on the above method, the master terminal device can output an electrical signal on the D- line to make the level on the D+ line high, so that the slave device can determine that the USB port is not an SDP port after detecting that the D- line is high, so as to further charge the slave device at the current corresponding to the CDP.

[0018] In one possible implementation, the D+ line is connected to a first comparator in a main terminal device, and the voltage of the first electrical signal is greater than a first reference voltage of the first comparator; obtaining the level on the D+ line includes: the main terminal device reads a first output value of the first comparator as a first preset value, and determines that the level on the D+ line is a high level, wherein the first output value is a result of the first comparator comparing the voltage of the first electrical signal with the first reference voltage.

[0019] Based on the above manner, the master terminal device can obtain that the level on the D+ line is a high level based on the output value of the first comparator read.

[0020] In a possible implementation manner, the method further includes: the master terminal device stops outputting the second electrical signal on the D-line after a preset time period.

[0021] Based on the above method, the main terminal device restores the original state in the main device after waiting for a preset period of time, that is, stops outputting the second electrical signal to wait for the next reverse charging process and repeats the steps in this application.

[0022] In a third aspect, an embodiment of the present application provides a reverse charging system, which includes a master terminal device and a slave terminal device connected via an OTG line, the master terminal device including a first processor, a first power module, a second power module and a first comparator, and the slave terminal device including a second processor, a third power module, a fourth power module, a fifth power module and a second comparator; the first power module is connected to the third power module via the VBUS line of the OTG line, and is used to output a power supply signal on the VBUS line; the fourth power module is connected to the second processor and is connected to the first comparator via the D+ line of the OTG line, and is used to respond to the power supply signal on the VBUS line detected by the second processor, Output a first electrical signal on the D+ line, and the first electrical signal makes the level on the D+ line a high level; the first processor is connected to the first comparator, and is used to determine the level on the D+ line in response to the first output result of the first comparator read, wherein the first output result is the result of the first comparator comparing the voltage on the D+ line with the first reference voltage of the first comparator; the second power module is connected to the first The first processor is connected to the second comparator, and the second comparator is connected to the D- line through the D- line of the OTG line, and is used to output a second electrical signal on the D- line if the level on the D+ line determined by the first processor is a high level, and the second electrical signal makes the level on the D+ line a high level; the second processor is connected to the second comparator, and is used to determine the level on the D- line in response to the second output result of the second comparator read, wherein the second output result is the result of the second comparator comparing the voltage on the D- line with the second reference voltage of the second comparator; if the level on the D+ line is a high level, the fourth power supply module stops outputting the first electrical signal on the D+ line; the fifth power supply module is connected to the D- line and is used to output a third electrical signal on the D- line; the second processor is also used to obtain the level on the D+ line; if the level on the D+ line is a low level, it is determined that the USB port type connected to the main terminal device through the OTG line is CDP, and the third power supply module is instructed to charge according to the current size corresponding to the CDP; the third power supply module is used to charge according to the current size corresponding to the CDP in response to the instruction of the second processor.

[0023] In one possible implementation, the voltage of the first electrical signal is greater than the first reference voltage of the first comparator; the first processor determines the level on the D+ line in response to the first output result of the first comparator read, including: the first processor reads the first output value of the first comparator as a first preset value, and determines that the level on the D+ line is a high level.

[0024] In one possible implementation, the voltage of the second electrical signal is greater than the second reference voltage of the second comparator; the second processor determines the level on the D-line in response to the second output result of the second comparator read, including: the second processor reads the second output value of the second comparator as a first preset value, determines that the level on the D-line is a high level, and confirms that the USB port type is CDP or a dedicated charging port DCP.

[0025] In one possible implementation, the slave terminal device also includes a third comparator, which is connected to the D+ line; the second processor obtains the level on the D+ line, including: the second processor reads the third output value of the third comparator as a second preset value, and determines that the level on the D+ line is a low level.

[0026] In a possible implementation, the current corresponding to CDP is 1.5A.

[0027] In a fourth aspect, an embodiment of the present application provides a reverse charging system, the system comprising a master terminal device and a slave terminal device connected via an OTG line, the slave terminal device comprising a first processor, a first power module, a second power module, a third power module and a first comparator; the master terminal device is connected to the first power module via a VBUS line of the OTG line, and is used to output a power supply signal on the VBUS line; the second power module is connected to the first processor and is connected to the master terminal device via a D+ line of the OTG line, and is used to respond to the power supply signal on the VBUS line detected by the first processor, output a first electrical signal on the D+ line, and the first electrical signal makes the level on the D+ line a high level; the master terminal device is also used to obtain the level on the D+ line in response to the first electrical signal detected on the D+ line; the master terminal device is also connected to the first comparator via the D- line of the OTG line, and the master terminal device is also used to output a second electrical signal on the D- line if the level on the D+ line is a high level. an electrical signal, and a second electrical signal makes the level on the D+ line a high level; a first processor is connected to the first comparator, and is used to determine the level on the D- line in response to the first output result of the first comparator read, wherein the first output result is the result of the first comparator comparing the voltage on the D- line with the first reference voltage of the first comparator; if the level on the D+ line is a high level, the first power module stops outputting the first electrical signal on the D+ line; a third power module is connected to the D- line, and is used to output the third electrical signal on the D- line; the first processor is also used to obtain the level on the D+ line; if the level on the D+ line is a low level, it is determined that the type of the universal serial bus physical layer USB port connected to the main terminal device through the OTG line is a charging downstream port CDP, and the first power module is instructed to charge based on the current size corresponding to the CDP; the first power module is used to charge based on the current size corresponding to the CDP in response to the instruction of the first processor.

[0028] In one possible implementation, the D+ line is connected to a second comparator in a master terminal device, and the voltage of the first electrical signal is greater than a second reference voltage of the second comparator; the master terminal device obtains the level on the D+ line, including: the master terminal device reads a first output value of the first comparator as a first preset value, and determines that the level on the D+ line is a high level, wherein the first output value is a result of the first comparator comparing the voltage of the first electrical signal with the first reference voltage.

[0029] In one possible implementation, the voltage of the second electrical signal is greater than the second reference voltage of the second comparator; the first processor determines the level on the D-line in response to the first output result of the first comparator read, including: the first processor reads the second output value of the first comparator as a first preset value, determines that the level on the D-line is a high level, and confirms that the USB port type is CDP or DCP.

[0030] In one possible implementation, the D+ line is connected to a third comparator in a slave terminal device; obtaining the level on the D+ line from the terminal device includes: a first processor reads a third output value of the third comparator as a second preset value, and determines that the level on the D+ line is a low level.

[0031] In a possible implementation, the current corresponding to CDP is 1.5A.

[0032] In a fifth aspect, an embodiment of the present application provides a slave terminal device, which is connected to a master terminal device via an OTG line, wherein the OTG line includes a D+ line, a D- line, and a VBUS line, and the slave terminal device includes a processor, a first power module, a second power module, a third power module, and a first comparator; wherein the first power module is connected to the master terminal device via the VBUS line, and is used to receive a power supply signal output by the master terminal device on the VBUS line; the second power module is connected to the processor and is connected to the master terminal device via the D+ line, and is used to output a first electrical signal on the D+ line in response to a power supply signal received by the first power module detected by the processor, and the first electrical signal makes the level on the D+ line a high level; the first comparator is connected to the processor and is connected to the master terminal device via the D- line, and is used to generate a first electrical signal on the D+ line based on the power supply signal received by the master terminal device. The first power module is used to compare the voltage of the second electrical signal output on the D-line with the first reference voltage of the first comparator to obtain a first output result; the processor is used to determine the level on the D-line in response to the first output result of the first comparator read; if the level on the D-line determined by the processor is a high level, the second power module stops outputting the first electrical signal on the D+ line; the third power module is connected to the D-line and is used to output the third electrical signal on the D-line; the processor is also used to obtain the level on the D+ line; if the level on the D+ line is a low level, it is determined that the USB port type connected to the main terminal device through the OTG line is CDP, and the first power module is instructed to charge according to the current corresponding to the CDP; the first power module is used to charge according to the current corresponding to the CDP in response to the instruction of the processor.

[0033] In a possible implementation, the second power supply module is connected to the second comparator of the master terminal device through a D+ line, and the voltage of the first electrical signal is greater than the second reference voltage of the second comparator.

[0034] In one possible implementation, the voltage of the second electrical signal is greater than the first reference voltage of the first comparator; the processor is specifically used to read the first output value of the first comparator as a first preset value, determine that the level on the D-line is a high level, and confirm that the USB port type is CDP or DCP.

[0035] In a possible implementation, the slave terminal device also includes a third comparator connected to the D+ line; the processor is specifically used to read the second output value of the third comparator as a second preset value, and determine that the level on the D+ line is a low level.

[0036] In a possible implementation, the current corresponding to CDP is 1.5A.

[0037] In a sixth aspect, an embodiment of the present application provides a master terminal device, wherein the master terminal device is connected to a slave terminal device via an OTG line, wherein the OTG line includes a D+ line, a D- line, and a VBUS line, and the master terminal device includes a processor, a first power module, a second power module, and a first comparator; the first power module is connected to the slave terminal device via the VBUS line, and is used to output a power supply signal on the VBUS line; the first comparator is connected to the processor and is connected to the slave terminal device via the D+ line, and is used to compare the voltage of a first electrical signal output by the slave terminal device on the D+ line with a first reference voltage of the first comparator to obtain an output result; the processor is used to determine the level on the D+ line in response to the output result of the first comparator read; the second power module is connected to the processor and is connected to the slave terminal device via the D- line, and is used to output a second electrical signal on the D- line if the level on the D+ line determined by the processor is a high level, and the second electrical signal makes the level on the D+ line a high level.

[0038] In a possible implementation, the voltage of the first electrical signal is greater than the first reference voltage of the first comparator; the processor is specifically configured to read the output value of the first comparator as a first preset value and determine that the level on the D+ line is a high level.

[0039] In a possible implementation manner, the second power supply module is connected to a second comparator of the slave terminal device through a D-line, and a voltage of the second electrical signal is greater than a second reference voltage of the second comparator.

[0040] In a possible implementation, the second power supply module stops outputting the second electrical signal on the D-line after a preset time period.

[0041] In the seventh aspect, an embodiment of the present application provides a slave terminal device, which is connected to a master terminal device via an OTG line, the OTG line including a D+ line, a D- line and a VBUS line, the slave terminal device including a processor and a memory, the processor being coupled to the memory, the memory being used to store program instructions, and when the program instructions are executed by the slave terminal device, the slave terminal device performs the following steps: in response to a power supply signal output by the master terminal device on the detected VBUS line, a first electrical signal is output on the D+ line, the first electrical signal makes the level on the D+ line a high level; in response to a second electrical signal output by the master terminal device on the detected D- line, the level on the D- line is obtained; if the level on the D- line is a high level, the output of the first electrical signal on the D+ line is stopped, and a third electrical signal is output on the D- line, and the level on the D+ line is obtained; if the level on the D+ line is a low level, it is determined that the type of the USB port connected to the master terminal device via the OTG line is CDP, and charging is performed according to the current size corresponding to the CDP.

[0042] In a possible implementation, the D+ line is connected to a first comparator in the master terminal device, and the voltage of the first electrical signal is greater than a first reference voltage of the first comparator.

[0043] In one possible implementation, the D-line is connected to a second comparator in a slave terminal device, and the voltage of the second electrical signal is greater than a second reference voltage of the second comparator; when the program instructions are executed by the slave terminal device, the slave terminal device performs the following steps: reading a first output value of the second comparator as a first preset value, determining that the level on the D-line is a high level, and confirming that the USB port type is CDP or DCP, wherein the first output value is a result of the second comparator comparing the voltage of the second electrical signal with the second reference voltage.

[0044] In one possible implementation, the D+ line is connected to a third comparator in a slave terminal device; when the program instruction is executed by the slave terminal device, the slave terminal device performs the following steps: reading a second output value of the third comparator as a second preset value, and determining that the level on the D+ line is a low level.

[0045] In a possible implementation, the current corresponding to CDP is 1.5A.

[0046] In an eighth aspect, an embodiment of the present application provides a master terminal device, wherein the master terminal device is connected to a slave terminal device via an OTG line, wherein the OTG line includes a D+ line, a D- line, and a VBUS, and wherein the master terminal device includes a processor and a memory, wherein the processor is coupled to the memory, and the memory is used to store program instructions, and when the program instructions are executed by the master terminal device, the master terminal device performs the following steps: after outputting a power supply signal on the VBUS line, in response to a first electrical signal output by the slave terminal device on the D+ line detected, obtaining a level on the D+ line; if the level on the D+ line is a high level, outputting a second electrical signal on the D- line, and the second electrical signal makes the level on the D+ line a high level.

[0047] In one possible implementation, the D+ line is connected to a first comparator in a master terminal device, and the voltage of the first electrical signal is greater than a first reference voltage of the first comparator; when the program instructions are executed by the master terminal device, the master terminal device performs the following steps: reading a first output value of the first comparator as a first preset value, and determining that the level on the D+ line is a high level, wherein the first output value is a result of the first comparator comparing the voltage of the first electrical signal with the first reference voltage.

[0048] In a possible implementation, when the program instructions are executed by the master terminal device, the master terminal device executes the following steps: after a preset time period, stop outputting the second electrical signal on the D-line.

[0049] In a ninth aspect, an embodiment of the present application provides a computer-readable medium for storing a computer program, wherein the computer program includes instructions for executing the method in the first aspect or any possible implementation of the first aspect.

[0050] In a tenth aspect, an embodiment of the present application provides a computer-readable medium for storing a computer program, wherein the computer program includes instructions for executing the method in the second aspect or any possible implementation of the second aspect.

[0051] In an eleventh aspect, an embodiment of the present application provides a computer program comprising instructions for executing the method in the first aspect or any possible implementation of the first aspect.

[0052] In a twelfth aspect, an embodiment of the present application provides a computer program comprising instructions for executing the method in the second aspect or any possible implementation of the second aspect.

[0053] In a thirteenth aspect, an embodiment of the present application provides a chip, the chip comprising a processing circuit and a transceiver pin, wherein the transceiver pin and the processing circuit communicate with each other through an internal connection path, and the processing circuit executes the method in the first aspect or any possible implementation of the first aspect to control the receiving pin to receive a signal and control the sending pin to send a signal.

[0054] In a fourteenth aspect, an embodiment of the present application provides a chip, the chip comprising a processing circuit and a transceiver pin, wherein the transceiver pin and the processing circuit communicate with each other through an internal connection path, and the processing circuit executes the method in the second aspect or any possible implementation of the second aspect to control the receiving pin to receive a signal, and to control the sending pin to send a signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0056] Figure 1 A schematic diagram of an application scenario is shown as an example;

[0057] Figure 2 A structural block diagram of a reverse charging system provided in an embodiment of the present application;

[0058] Figure 3 An operation schematic diagram exemplarily shown for this application;

[0059] Figure 4 A schematic diagram of the internal circuits of a master device and a slave device provided in an embodiment of the present application;

[0060] Figure 5 A schematic diagram of a reverse charging method provided in an embodiment of the present application;

[0061] Figure 6 A schematic diagram of the structure of a device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0062] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0063] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0064] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0065] Before describing the technical solution of the embodiment of the present application, the application scenario of the embodiment of the present application is first described in conjunction with the accompanying drawings. Figure 1 , is a schematic diagram of an application scenario provided in an embodiment of the present application. The application scenario includes a terminal device 100 and a terminal device 200. The terminal device (including the terminal 100 and the terminal 200) may include but is not limited to a mobile phone, a personal digital assistant (PDA), a tablet computer, a portable device (e.g., a portable computer) and other mobile communication devices. The terminal device 100 and the terminal device 200 may be connected via an On-The-Go (OTG) line between different devices.

[0066] Combination Figure 1 ,like Figure 2 FIG. 1 is a block diagram of a reverse charging system in an embodiment of the present application, wherein the terminal device 100 and the terminal device 200 are connected via an OTG line. Figure 2 The OTG line in the embodiment of the present application includes a voltage bus (VBUS), a D+ line (also called a data line positive electrode or a data positive signal line), a D- line (also called a data line negative electrode or a data negative signal line), an identification (ID) line (also called a configuration channel (cc) line) and a ground (GND) line. The D+ line and the D- line can be used for data transmission and can also be used for charging.

[0067] In the embodiment of the present application, the ID line is used to provide an OTG insertion interrupt signal. Specifically, when the OTG line is inserted into the terminal device 100 and / or the terminal device 200, the device can detect the OTG insertion interrupt signal on the ID line. In addition, the terminal device 100 and the terminal device 200 are also connected via GND to provide a ground signal.

[0068] Still refer to Figure 2 In the embodiment of the present application, the terminal device 100 includes an AP processor 110, a charging chip power supply module 120, a Universal Serial Bus Physical (USB PHY) 130, and a battery 140. The AP processor 110, the charging chip power supply module 120, and the USB PHY 130 are connected, and the charging chip power supply module 120 is connected to the battery 140, for example, through a bus. In the embodiment of the present application, the connection may include various interfaces, transmission lines, or buses, etc., which are not limited in this embodiment.

[0069] The AP processor 110 in the embodiment of the present application can be used to implement various functions for the terminal, such as processing communication protocols and communication data, or controlling the entire terminal device, executing software programs, and processing software program data; or assisting in completing computing tasks, such as graphics and image processing or audio processing, etc.; or the processor 110 is used to implement one or more of the above functions.

[0070] The charging chip power supply module 120 in the embodiment of the present application can be used to output a power supply signal or input a power supply signal. Optionally, the charging chip power supply module 120 can be used to output a power supply signal with a specified current and voltage or input a power supply signal with a specified current and voltage based on the instruction of the AP processor 110, wherein the input refers to inputting into the battery, that is, charging the battery. For example: the AP processor 110 can send an output instruction to the charging chip power supply module 120 to instruct the charging management module to output a power supply signal (for example: 5V 1.5A), and the charging chip power supply module 120 will output a power supply signal with a voltage value of 5V and a current value of 1.5A based on the output instruction. The AP processor 100 can also send an input instruction to the charging chip power supply module 120 to instruct the charging management module to input a power supply signal (for example: 5V 1.5A), which can also be understood as that no matter how much current the external device provides to the charging chip power supply module 120, the charging chip power supply module 120 only charges at a specified current according to the instruction of the AP processor 110, that is, inputting a specified current to the battery 140. Optionally, the remaining current can be used as system power supply, for example, to power a display screen.

[0071] Reference Figure 2 The charging chip module 120 in the terminal device 100 is connected to the charging chip power supply module 220 in the terminal device 200 through the VBUS line. The VBUS line transmits the power supply current, that is, the VBUS line can power the device. In other words, if the terminal device 100 is a device that powers the terminal device 200, the charging chip power supply module 120 can provide a power supply signal and input it into the charging chip power supply module through the VBUS line.

[0072] Reference Figure 2 The terminal device 100 also includes a USB PHY 130, which includes a D+ source voltage (D+SourceVoltage, VDP_SRC) module 131, a data positive signal (DATA PLUS, DP) comparator module 132, a D-source voltage (D-Source Voltage, VDM_SRC) module 133, and a data negative signal (DATA MINUS, DM) comparator module 134.

[0073] The VDP_SRC module 131 in the embodiment of the present application is connected to the DP comparator module 232 in the terminal device 200 via the D+ line. The VDP_SRC module 131 can be used to output a VDP_SRC electrical signal on the D+ line.

[0074] The DP comparator module 132 in the embodiment of the present application is connected to the VDP_SRC module 231 in the terminal device 200 via the D+ line. The DP comparator module 132 can be used to compare the voltage input to the DP comparator module 132 with the reference voltage in the DP comparator module 132, and output the comparison result. The input voltage of the DP comparator module 132 is equal to the voltage on the D+ line.

[0075] The following is a brief introduction to the principle of the comparator: When the voltage input to the comparator is greater than the reference voltage in the comparator, the comparator outputs a first preset value, which may be 1, indicating that the input to the comparator is at a high level. When the voltage input to the comparator is less than the reference voltage in the comparator, the comparator outputs a second preset value, which may be 0, indicating that the input to the comparator is at a low level.

[0076] The VDM_SRC module 133 in the embodiment of the present application is connected to the DM comparator module 234 in the terminal device 200 via the D-line. The VDM_SRC module 133 can be used to output a VDM_SRC electrical signal on the D-line.

[0077] The DM comparator module 134 in the embodiment of the present application is connected to the VDM_SRC module 233 of the terminal device 200 via the D-line. The DM comparator module 134 can be used to compare the voltage input to the DM comparator module 134 with the reference voltage in the DM comparator module 134, and output the comparison result. Among them, the input voltage of the DM comparator module 134 is equal to the voltage on the D-line. The working principle of the DM comparator module 134 is the same as that of the DP comparator module 132, which will not be repeated here.

[0078] The processor 110 in the embodiment of the present application may be used to read the output results of the DP comparator module 132 and / or the DM comparator module 134 , and may also be used to control each power module to output a corresponding electrical signal.

[0079] Still refer to Figure 2 The terminal device 200 includes an AP processor 210, a charging chip power supply module 220, a USB PHY 230, and a battery 240. The AP processor 210, the charging chip power supply module 220, and the USB PHY 230 are connected, and the charging chip power supply module 220 is connected to the battery 240. The functions of the AP processor 210 and the charging chip power supply module 220 can refer to the description of the terminal device 100 above, and will not be repeated here.

[0080] The USB PHY 230 in the terminal device 200 includes a VDP_SRC module 231, a DP comparator module 232, a VDM_SRC module 233, and a DM comparator module 234. The functions of the components in the terminal 200 can refer to the description of the terminal 100, which will not be repeated here. It should be noted that the connection relationship between the modules in the terminal device 200 and the terminal device 100 can refer to the description in the terminal device 100, which will not be repeated here.

[0081] The VDP_SRC module 231 in the embodiment of the present application may be used to output a VDP_SRC electrical signal on the D+ line.

[0082] The DP comparator module 232 in the embodiment of the present application can be used to compare the voltage input to the DP comparator module 232 with the reference voltage in the DP comparator module 232, and output the comparison result. Among them, the input voltage of the DP comparator module 232 is equal to the voltage on the D+ line. The working principle of the DP comparator module 232 is the same as that of the DP comparator module 132, which is not repeated here.

[0083] The VDM_SRC module 233 in the embodiment of the present application may be used to output a VDM_SRC electrical signal on the D-line.

[0084] The DM comparator module 234 in the embodiment of the present application can be used to compare the voltage input to the DM comparator module 234 with the reference voltage in the DM comparator module 234, and output the comparison result. The input voltage of the DM comparator module 234 is equal to the voltage on the D- line. The working principle of the DM comparator module 234 is the same as that of the DP comparator module 132, which will not be repeated here.

[0085] The processor 210 in the embodiment of the present application may be used to read the output results of the DP comparator module 232 and / or the DM comparator module 234 , and may also be used to control each power module to output a corresponding electrical signal.

[0086] Optionally, in this application, Figure 2 The connection relationship in the figure is represented as terminal device 100 being a power supply (or charging) device, which may also be referred to as a master device, and terminal device 200 being a device to be charged, which may also be referred to as a slave device.

[0087] In order to more clearly illustrate the technical solution in the present application, in the following embodiments of the present application, the terminal device 100 is taken as the main device and the terminal device 200 is taken as the slave device for detailed description.

[0088] Optionally, the master device 100 and the slave device 200 in the present application can be manually specified by the user. For example, when the master device and the slave device are connected via an OTG cable, a user selection interface can be provided on the master device and / or the slave device to enable the user to select the master device and the slave device, such as Figure 3 shown.

[0089] Optionally, the master device 100 and the slave device 200 can also be determined by the properties of the OTG cable. For example, one end of the OTG cable is a power supply port for connecting to the master device, and the other end is a charging port for connecting to the slave device. The terminal device can determine whether it is a master device or a slave device by detecting the port type of the OTG cable inserted into its port. If it is determined to be a master device, reverse charging is performed through the OTG cable, that is, power is supplied to the slave device. If it is confirmed to be a slave device, forward charging is performed through the OTG cable, that is, charging is performed through the master device.

[0090] Combination Figure 2 The reverse charging method in the embodiment of the present application is described below with a specific example.

[0091] Specifically, the master device 100 is connected to the slave device 200 via an OTG line. In the embodiment of the present application, the AP processor 110 of the master device 100 is installed with program instructions, and when the program instructions are executed by the AP processor 110, the master device 100 can execute the technical solution implemented by the master device 100 described in the present application.

[0092] Specifically, after the master device 100 is connected to the slave device 200 via the OTG line, the AP processor 110 in the master device 100 detects the OTG insertion interrupt signal and determines that there is a connection event, which specifically refers to the master device 100 being connected to the external device via the OTG line. For example, the external device can be the slave device 200 in this application. The AP processor 110 can control the charging chip power supply module 120 to output a power supply signal on the VBUS line. As described above, the power supply signal includes an output current and an output voltage. For example, the current of the power supply signal can be 1.5A and the voltage can be 5V. For example, it can be expressed as a power supply signal (5V 1.5A).

[0093] Specifically, the power supply signal output by the charging chip power supply module 120 is input into the charging chip power supply module 220 of the slave device 200 via the VBUS line.

[0094] Specifically, after the AP processor 210 of the slave device 200 detects the power supply signal on the VBUS line, the AP processor 210 controls the VDP_SRC module 231 in the slave device 200 to output VDP_SRC on the D+ line. Specifically, in an embodiment of the present application, after the power supply signal on the VBUS line is input to the charging chip power supply module 220 of the slave device 200, the AP processor 210 of the slave device 200 detects the power supply signal on the VBUS line through the charging chip power supply module 220, determines that there is a charging event (or can also be called a connection event), and the slave device 200 enters the first detection stage, which can also be called the primary detection stage (PrimaryDetection). It should be noted that the output current or output voltage of the master device 100 on the VBUS line can be called the input current or input voltage for the slave device 200. It should be further explained that the VDP_SRC involved in the present application, for example, including the VDP_SRC output by the master device 100 and / or the VDP_SRC output by the slave device 200, can be referred to as a VDP_SRC electrical signal, and the VDP_SRC electrical signal can include a combination of different currents or voltages. In other embodiments, VDP_SRC can also be referred to as a VDP_SRC current or a VDP_SRC voltage. For example, VDP_SRC can be a 0.6V voltage, which is not limited in the present application.

[0095] In the first detection phase, the AP processor 210 in the slave device 200 controls the internal circuit of the VDP_SRC module 231 to be closed to output VDP_SRC on the D+ line. Specifically, after the internal circuit of the VDP_SRC module 231 is closed, VDP_SRC is output at the D+ pin connected to the D+ line. Exemplarily, the voltage of VDP_SRC output by the VDP_SRC module 231 may be 0.5V to 0.7V. Exemplarily, in the embodiment of the present application, the voltage of VDP_SRC is 0.6V. Accordingly, the VDP_SRC module 231 of the slave device 200 outputs VDP_SRC (0.6V voltage) to the D+ line of the OTG line through the D+ pin, which is input to the D+ pin of the master device 100 through the D+ line, and is input to the DP comparator module 132 of the master device 100 through the D+ pin of the master device 100. It can be understood that the 0.6V voltage on the D+ pin of the master device 100 can also be understood as the voltage on the D+ line, which is used as the input voltage of the DP comparator 132 for comparison with the reference voltage in the DP comparator module 132.

[0096] Specifically, the DP comparator module 132 of the master device 100 compares the input voltage, ie, the voltage of VDP_SRC, with the reference voltage of the DP comparator module 132 and outputs a comparison result. Exemplarily, the reference voltage of the DP comparator module 132 may be set to 0.375V.

[0097] Specifically, in the embodiment of the present application, the voltage of VDP_SRC output by the VDP_SRC module 231 in the slave device 200 is configured to be greater than the reference voltage in the DP comparator module 132 in the master device 100. Therefore, the voltage of the VDP_SRC electrical signal is used as the input of the DP comparator module 132, and the voltage of the VDP_SRC electrical signal is higher than the reference voltage of the DP comparator 132. In the embodiment of the present application, the output result of the DP comparator module 132 is 1.

[0098] Optionally, in an embodiment of the present application, the master device 100 may wait for a predetermined period of time after outputting a power supply signal, and after the predetermined period of time, read the output result of the DP comparator module 132 to detect the electrical configuration on the D+ line, for example, the electrical configuration may be a voltage or a level.

[0099] Specifically, in the embodiment of the present application, after the predetermined time period ends, the AP processor 110 reads the output result of the DP comparator module 132 as 1, and determines that the input of the DP comparator module 132, that is, the D+ line is at a high level, which can also be understood as the D+ line being pulled high (or pulled up). It should be noted that the input of the DP comparator 132 is actually the voltage on the D+ pin of the master device 100. In the embodiment of the present application, the D+ pin of the master device 100 is connected to the D+ line of the OTG line, so it can also be considered that the voltage or level of the D+ pin is equivalent to the voltage or level on the D+ line.

[0100] Next, the master device 100 outputs VDM_SRC on the D- line. Specifically, in the embodiment of the present application, after the AP processor 110 in the master device 100 determines that the D+ line is at a high level, it can control the internal circuit of the VDM_SRC module 133 in the master device 100 to be closed to output VDM_SRC on the D- line. Specifically, after the internal circuit of the VDM_SRC module 133 is closed, VDM_SRC is output at the D-pin connected to the D-line. Exemplarily, the voltage of the VDM_SRC output by the VDM_SRC module 133 may be 0.5V to 0.7V. Exemplarily, in the embodiment of the present application, the voltage of VDM_SRC is 0.6V. Accordingly, the VDM_SRC module 133 of the master device 100 outputs VDM_SRC (0.6V voltage) to the D-line of the OTG line through the D-pin, which is input to the D-pin of the slave device 200 through the D-line, and is input to the DM comparator module 234 of the slave device 200 through the D-pin of the slave device 200. It can be understood that the 0.6V voltage on the D-pin of the slave device 200 can also be understood as the voltage on the D-line, which is used as the input voltage of the DM comparator module 234 for comparison with the reference voltage in the DM comparator module 234.

[0101] It should be noted that the VDM_SRC involved in the present application, for example, including the VDM_SRC output by the master device 100 and / or the VDM_SRC output by the slave device 200, can be referred to as a VDM_SRC electrical signal, and the VDM_SRC electrical signal can include a combination of different currents or voltages. In other embodiments, VDM_SRC can also be referred to as a VDM_SRC current or a VDM_SRC voltage, for example, VDM_SRC can be a 0.6V voltage, which is not limited in the present application.

[0102] Specifically, the DM comparator module 234 of the slave device 200 compares the input voltage, ie, the voltage of VDM_SRC, for example, 0.6V, with the reference voltage of the DM comparator module 234 and outputs a comparison result. Exemplarily, the reference voltage of the DM comparator module 234 may be set to 0.375V.

[0103] Specifically, in the embodiment of the present application, the voltage of VDM_SRC output by the VDM_SRC module 133 of the master device 100 is configured to be greater than the reference voltage in the DM comparator module 234 in the slave device 200. Therefore, the voltage of the VDM_SRC electrical signal is used as the input of the DM comparator module 234, and the voltage of the VDM_SRC electrical signal is higher than the reference voltage of the DM comparator module 234. In the embodiment of the present application, the output result of the DM comparator module 234 is 1. The specific principle is referred to above and will not be repeated here.

[0104] Specifically, the output result of the DM comparator 234 read by the AP processor 210 of the slave device 200 is 1, and it is determined that the D-line is at a high level, which can also be understood as the D-line being pulled high (or pulled up).

[0105] In accordance with the requirements of the BC1.2 protocol, it is stipulated that in the first detection stage, when the D-line is at a high level, the USB port type is a charging downstream port (CDP) or a dedicated charging port (DCP). It can also be understood that the first detection stage is actually to detect whether the USB is an SDP port or a charging port (Charging Port). If it is determined that the USB port is a charging port, it is necessary to further detect the type of the USB port through the second detection stage, whether it is a CDP port or a DCP port.

[0106] In the embodiment of the present application, after the AP processor 210 determines that the D-line is at a high level, the AP processor 210 can determine that the current USB port type is a CDP port or a DCP port, the first detection phase is completed, and the second detection phase is entered.

[0107] It should be noted that after the first detection phase is completed, the AP processor 210 controls each component to be restored, including: the internal circuit of the VDM_SRC module 133 is disconnected, and the DM comparator module 234 is disabled.

[0108] Specifically, in the second detection stage, which may also be referred to as the secondary detection stage (Secondary Detection), the AP processor 210 in the slave device 200 controls the internal circuit in the VDM_SRC module 233 to be closed, so as to output VDM_SRC on the D-line, and controls the DP comparator module 232 to be enabled. It should be noted that the specific working process of each comparator module, such as enabling, comparing the output results and stopping enabling, will be described in detail in the following embodiments, and will not be repeated here.

[0109] Specifically, since the first stage is over, the internal circuit in the VDP_SRC module 231 is disconnected, that is, the VDP_SRC module 231 stops outputting VDP_SRC on the D+ line. Therefore, the voltage on the D+ pin connected to the D+ line in the slave device 200 is 0V, and the voltage on the D+ pin is used as the input of the DP comparator module 232 in the slave device 200, and its voltage (0V) is less than the reference voltage of the DP comparator module 232, for example, 0.375V, so the output result of the DP comparator module 232 is 0. Specifically, the AP processor 210 in the slave device 200 can read the output result of the DP comparator module 232 as 0, and determine that the D+ line is at a low level, that is, the D+ line is pulled low (or pulled down).

[0110] In accordance with the BC1.2 protocol requirements of USB, in the second detection phase, after the AP processor 210 pulls the D- line to a high level, the D+ line is at a low level, indicating that the D+ line and the D- line are not short-circuited, and the USB port type is a CDP port. In other words, the AP processor 210 of the slave device 200 can determine that the current USB port type is a CDP port, and the second detection phase is completed.

[0111] Specifically, after the AP processor 210 of the slave device 200 determines that the type of the USB port is a CDP port, the current size of the input power signal corresponding to the CDP port can be determined through a preset mapping relationship. The AP processor 210 sends an input instruction to the charging chip power supply module 220 to instruct the charging chip power supply module 220 to control the input of a power supply signal with a specified current. It should be noted that the mapping relationship recorded by the AP processor 210 is a combination of the current and voltage corresponding to the CDP port specified in the BC1.2 protocol. Exemplarily, the current corresponding to the CDP port can be 1.5A, and the voltage can be 5V. In response to the input instruction sent by the AP processor 210, the charging chip power supply module 220 inputs a power supply signal with a specified current (1.5A) and voltage (5V) to the battery 240 in the slave device 200, that is, the slave device 200 is charged at a current of 1.5A. It should be noted that the current size described in the present application is only for illustrative purposes. In other embodiments, when the master device 100 supplies 1.5A of power to the outside, after the slave device 200 identifies the CDP port, the current size corresponding to the CDP port may be 1A, and the AP processor 210 may instruct the charging chip power supply module 220 to charge based on a power supply signal of 1A current. Based on the instruction of the AP processor 210, the charging chip power supply module 220 may input 1A current to the battery 240 for charging, and use the remaining 500mA current as system power supply, for example, to power the display screen.

[0112] In summary, in the present application, program instructions are set in the AP processor of the main device 100. The program instructions control the AP processor in the main device 100 to configure the voltage on the D- line to a high level after detecting that the D+ line is at a high level. This allows the slave device 200 to charge the USB port as a CDP port when reading the USB port, so as to obtain the current and voltage corresponding to the CDP port, thereby improving the charging efficiency of the slave device 200.

[0113] It is understandable that the voltage state on the D+ line and / or D- line is used for explanation in the present application. In other embodiments, the AP processor, such as the AP processor 110 and the AP processor 210, can also determine the state of the USB port by confirming the current state on the D+ line and / or D- line. The present application does not limit this.

[0114] In order to make those skilled in the art better understand the solution of the present application, the following is combined with Figure 4 The internal circuit diagram of the master device 100 and the slave device 200 shown in FIG. 1 is used to explain the technical solution of the above method embodiment in detail. It should be noted that: Figure 4 The combination shown in Figure 2The internal circuit diagram of each module is only a schematic example. In fact, the circuits in the terminal device include but are not limited to Figure 4 The components and circuits shown in the figure are not limited in this application.

[0115] Combination Figure 4 ,like Figure 5 FIG. 1 is a flow chart of a reverse charging method in an embodiment of the present application, wherein: Figure 5 The left half is a flow chart of the main device 100 side. Figure 5 The right half of is a flow chart of the slave device 200, specifically:

[0116] Step S21 : the master device 100 supplies power to the outside.

[0117] Specifically, after the master device 100 is connected to the slave device 200 via the OTG line, the AP processor 110 of the master device 100 detects the OTG insertion interrupt signal on the ID line, and the AP processor 110 sets the power supply mode of the master device 100 to the boost mode. Exemplarily, the boost mode can supply power to the charging chip power supply module 120 in the master device 100, and the output current is 1.5A and the output voltage is 5V.

[0118] In step S22 , the master device 100 starts the DP comparator module 132 .

[0119] Specifically, the AP processor 110 controls the DP comparator module 132 of the master device 100 to start. Specifically, the AP processor 110 can turn on the D-sink current (D-Sink Current, IDM_SINK) in the DP comparator module 132. For example, the output current of IDM_SINK can be 25μA to 175μA. Among them, IDM_SINK is used to prevent electrical signal drift.

[0120] And, the AP processor 110 controls the DP comparator in the DP comparator module 132 to be enabled. Specifically, the AP processor 110 sets the reference voltage of the DP comparator in the DP comparator module 132, exemplarily, the reference voltage is 0.375V, the DP comparator in the DP processor module 132 is enabled, and the switch 1 in the DP processor module 132 is closed.

[0121] After the AP processor 110 starts the DP comparator module 132, it waits for a predetermined time period, which can be set based on actual needs, for example, 5 ms. It should be noted that the AP processor 110 sets the predetermined time period to wait for the operation of the slave device 200.

[0122] Reference Figure 5The right half, i.e., the flowchart of the slave device 200, is as follows:

[0123] Step S31 , the slave device 200 detects the connection with the master device 100 .

[0124] Specifically, the AP processor 210 of the slave device 200 reads the voltage input of the charging chip power supply module 220 , determines the voltage (5V) on the VBUS line, and confirms that there is a charging event (or connection event), that is, the slave device 200 is connected to the master device 100 .

[0125] Optionally, after detecting a charging event, ie, connecting to the master device 100, the slave device 200 may perform a data connection detection (Date Contact Detect, DCD) detection. The specific detection process may refer to the existing technology and will not be described in detail here.

[0126] It should be noted that there is no particular order for step S31 and step S22.

[0127] In step S32, the slave device 200 controls the VDP_SRC module 231 to output VDP_SRC on the D+ line.

[0128] Specifically, after the AP processor 210 of the slave device 200 detects the voltage on the VBUS line through the charging chip power supply module 220, it is determined that there is a charging event, and the slave device 200 enters the first detection phase. Specifically, the AP processor 210 in the slave device 200 controls the switch 2 in the VDP_SRC module 231 to close, and the VDP_SRC voltage is input to the DP comparator module 132 of the master device 100 through the D+ pin, D+ line, and D+ pin of the slave device 200. Exemplarily, in this embodiment, the VDP_SRC voltage output by the VDP_SRC module 231 is 0.6V as an example for description.

[0129] Specifically, in the present application, after the slave device 200 closes switch 2, that is, outputs the VDP_SRC voltage, the IDM_SINK in the slave device 200 may be opened. For example, the current range provided by IDM_SINK is between 25μA and 175μA, which is not limited in the present application. Next, the AP processor 210 may set the reference voltage of the DM comparator in the DM comparator module 234. For example, the reference voltage is 0.375V. The AP processor 210 enables the DM comparator, and the switch 3 in the DM comparator module 234 is closed.

[0130] Still refer to Figure 5 The left half, i.e., the flowchart of the master device 100, is as follows:

[0131] In step S23 , the master device 100 reads whether the output result of the DP comparator module 132 is 1.

[0132] Specifically, after the master device 100 waits for a predetermined period of time, the AP processor 110 reads the output result of the DP comparator in the DP comparator module 132 .

[0133] In a possible implementation, as described in step 32, the VDP_SRC voltage output from the device 200 is input to the DP comparator module 132 through the D+ line, and the DP comparator in the DP comparator module 132 compares the reference voltage (0.375V) with the input voltage, that is, the voltage on the D+ line (0.6V). Since the voltage on the D+ line is higher than the reference voltage of the DP comparator, the output result of the DP comparator is 1. The AP processor 110 reads the output result of the DP comparator in the DP comparator module 132 as 1, determines that the D+ line is at a high level, and executes step S25.

[0134] In another possible implementation, if the slave device 200 is not a device to be charged, in this scenario, the slave device 200 will not pull up (or pull up) the D+ line. Then the AP processor 110 reads the output result of the DP comparator in the DP comparator module 132 as 0, determines that the D+ line is at a low level, and executes step S24.

[0135] Optionally, after reading the output value of the DP comparator, the AP processor 110 of the master device 100 turns off the DP comparator module 132, including: stopping the DP comparator enable, turning off IDP_INK, and disconnecting the switch 1 in the DP comparator module 132. It can also be understood that after reading the output value of the DP comparator, the AP processor 110 no longer reads the output result of the DP comparator module 132.

[0136] In step S24 , the master device 100 reads whether the output result of the DM comparator module 134 is 1.

[0137] Specifically, the AP processor 110 starts the DM comparator module 134, including: opening the IDM_SINK in the DM comparator module 134, setting the reference voltage of the DM comparator, enabling the DM comparator, and closing the switch 4. Optionally, the reference voltage is 0.375V. Subsequently, the AP processor 110 waits for a predetermined time and then reads the output result of the DM comparator in the DM comparator module 132. The predetermined time can be set according to actual needs, such as 10ms, and is not limited in this application.

[0138] Optionally, if the slave device 200 is a low-speed device such as a keyboard or a mouse, the slave device 200 will pull up the D-line so that the output result of the DM comparator in the DM comparator module 132 is 1. For specific details, please refer to the existing technology and this application will not repeat them.

[0139] Optionally, when the master device 100 is inserted with the OTG line but the slave device 200 is not inserted, the AP processor 110 reads that the output result of the DM comparator in the DM comparator module 132 is 0, that is, the D- line is at a low level and the D+ line is configured as a low level, then the AP processor restores each component and re-executes step S22.

[0140] In step S25 , the host device 100 controls the VDM_SRC module 134 to output VDM_SRC on the D-line.

[0141] Specifically, after the AP processor 110 in the master device 100 detects that the output result of the DP comparator module 132 is 1, it determines that the D+ line is at a high level. Subsequently, the AP processor 110 controls the switch 5 in the VMD_SRC module 133 to close, and the VDM_SRC voltage output by the VDM_SRC module 134 is input to the DM comparator 234 of the slave device 200 through the D-pin of the master device 100, the D-line, and the D-pin of the slave device 200. Exemplarily, in this embodiment, the VDM_SRC voltage output by the VDM_SRC module 134 is 0.6V.

[0142] Optionally, in the present application, the AP processor 110 closes switch 5, and after waiting for a preset time, opens switch 5, that is, the AP processor 110 outputs VDM_SRC on the D-line within the preset time, and stops outputting VDM_SRC on the D-line after the preset time ends, so as to restore the circuit in the master device 100. Exemplarily, the preset time can be 100ms, which is not limited in the present application.

[0143] It should be noted that, when the host device 100 executes each step, the host device 100 is always in boost mode, that is, the charging chip power supply module 120 of the host device 100 is performing reverse charging, that is, outputting a power supply signal with a voltage of 5V and a current of 1.5A.

[0144] Still refer to Figure 5 The right half, i.e., the flowchart of the slave device 200, is as follows:

[0145] Step S33 , the slave device 200 reads whether the output result of the DM comparator module 234 is 1.

[0146] Specifically, the output result of the DM comparator module 234 is read from the AP processor 210 in the device 200 .

[0147] In a possible implementation, if the output result of the DM comparator is 1, that is, the VDM_SRC on the D-line makes the output result of the DM comparator module 234 1, then the AP processor 210 determines that the D-line is at a high level, and the AP processor 210 can confirm that the type of the USB port is a CDP port or a DCP port. The specific principle is referred to above and will not be repeated here. The first detection phase of the slave device 200 ends. Optionally, after the first detection phase ends, the AP processor 210 in the slave device 200 controls the restoration of each component, including: turning off the DM comparator module 234 and disconnecting switch 2 to stop outputting VDP_SRC. Among them, turning off the DM comparator module 234 includes: stopping the DM comparator enable, disconnecting switch 3, and turning off IDM_SINK. The slave device 200 enters the second detection phase and executes step S34.

[0148] In another possible implementation, if the output result is 0, the AP processor 210 determines that the D-line is at a low level. In accordance with the BC1.2 protocol requirements of the USB, when D- is at a low level, the AP processor 210 can confirm that the type of the USB port is an SDP port. The AP processor 210 interacts with the main device 100 in accordance with the provisions of the standard downstream port, for example, charging at a current of 500mA, that is, inputting a current of 500mA into the battery 240, and the remaining 1A current is used as system power supply. The specific interaction process can refer to the existing technology, and this application will not repeat it.

[0149] In step S34, the slave device 200 controls the VDM_SRC module 233 to output VDM_SRC on the D-line.

[0150] Specifically, in accordance with the BC1.2 protocol requirements, the slave device 200 performs the second detection phase to further determine whether the USB port is a CDP port or a DCP port.

[0151] In the second detection phase, the AP processor 210 enables VDM_SRC, that is, closes the switch 6 in the VDM_SRC module 233, and the VDM_SRC voltage output by the VDM_SRC module 233 is input to the DM comparator 134 of the master device 100 through the D-pin and D-line of the slave device 200 and the D-pin of the master device 100. Exemplarily, the VDM_SRC voltage output by the VDM_SRC module 233 is 0.6V.

[0152] Step S35 , the output result of the DP comparator module 232 read from the device 200 is 0.

[0153] Specifically, the AP processor 210 starts the DP comparator module 232 , including: turning on the IDP_SINK power supply in the DP comparator module 232 , setting the reference voltage of the DP comparator, for example, the reference voltage may be 0.375V, enabling the DP comparator, and closing the switch 7 .

[0154] Specifically, as described above, after the first stage ends, after the switch 2 in the VDP_SRC module 231 is disconnected, the VDP_SRC module 231 stops outputting the VDP_SRC voltage. Since the voltage of VDP_SRC on the D+ line is 0V, the output result of the DP comparator module 232 is 0. The specific principle is referred to above and will not be repeated here. The AP processor 210 in the slave device 200 reads the output result of the DP comparator module 232 in the slave device 200 as 0, confirming that the D+ line is at a low level.

[0155] It should be noted that, as described above, after reading the output result of the DP processor module 132, the AP processor 110 in the main device 100 stops enabling the DP processor module 132. Therefore, in this step, after the VDP_SRC voltage on the D+ line becomes 0, since the AP processor 110 no longer reads the output result of the DP processor module 132, the AP processor no longer takes other actions.

[0156] Step S36, the slave device 200 determines that the USB port is a CDP port, and inputs a 1.5A current for charging.

[0157] Specifically, in the second detection phase, the AP processor 210 closes the switch 6, and the VDM_SRC module 233 outputs VDM_SRC on the D- line, that is, the AP processor 210 pulls the D- line high. Also, the AP processor 210 detects that the D+ line is at a low level, and it can be confirmed that the D- line and the D+ line are not short-circuited. According to the BC1.2 protocol requirements of the USB, the AP processor 210 determines that the type of the USB port is a CDP port.

[0158] Optionally, after the second detection phase ends and the AP processor 210 determines that the type of the USB port is a CDP port, the AP processor 210 may send an input instruction to the charging chip power supply module 220 based on the mapping relationship between the CDP port and the input power signal, for example, the voltage is 5V and the current is 1.5A, to instruct the charging chip power supply module 220 to input a power supply signal (5V 1.5A). That is, when the AP processor 210 confirms the USB port as a CDP port, the charging chip power supply module 220 may transmit the power supply signal of the main device 100, specifically the charging chip power supply module 120 in the main device 100, to the slave device 200 through the VBUS line, for example, 1.5A current is input into the battery 240, so that the slave device 200 is charged at a charging current of 1.5A.

[0159] The following describes a device 300 provided in an embodiment of the present application. Figure 6 As shown:

[0160] The device 300 includes a processing module 310 and a communication module 320. Optionally, the device 300 also includes a storage module 330. The processing module 310, the communication module 320 and the storage module 330 are connected via a communication bus.

[0161] The communication module 320 may be a device with transceiver functions, and is used to communicate with other network devices or communication networks.

[0162] The storage module 330 may include one or more memories, and the memory may be a device in one or more devices or circuits for storing programs or data.

[0163] The storage module 330 may exist independently and be connected to the processing module 310 via a communication bus. The storage module may also be integrated with the processing module 310.

[0164] The apparatus 300 may be a terminal device in an embodiment of the present application, such as the terminal device 100 or the terminal device 200. Optionally, the communication module 320 of the apparatus 300 may include an antenna and a transceiver of the terminal. Optionally, the communication module 320 may also include an output device and an input device.

[0165] The device 300 may be a chip in the terminal device in the embodiment of the present application. The communication module 320 may be an input or output interface, a pin or a circuit, etc. Optionally, the storage module may store computer execution instructions of the method on the terminal side so that the terminal device executes the steps executed by the master device 100 and / or the slave device 200 in the embodiment of the present application.

[0166] The storage module 330 may be a register, a cache or a RAM, etc., and the storage module 330 may be integrated with the processing module 310; the storage module 330 may be a ROM or other types of static storage devices that can store static information and instructions, and the storage module 330 may be independent of the processing module 310.

[0167] In the embodiment of the present application, the apparatus 300 may be a terminal device or a chip in the terminal device in the embodiment of the present application, and the apparatus 300 may implement the method executed by the master device or the slave device in the above embodiment. Figure 5 The relevant contents in will not be repeated here.

[0168] The embodiment of the present application provides a reverse charging system, which includes a master terminal device and a slave terminal device connected via an OTG line, the master terminal device includes a first processor, a first power module, a second power module and a first comparator, and the slave terminal device includes a second processor, a third power module, a fourth power module, a fifth power module and a second comparator; the first power module is connected to the third power module via a VBUS line of the OTG line, and is used to output a power supply signal on the VBUS line; the fourth power module is connected to the second processor and is connected to the first comparator via a D+ line of the OTG line, and is used to respond to the power supply signal on the VBUS line detected by the second processor, and output a first electrical signal on the D+ line, and the first electrical signal makes the level on the D+ line a high level; the first processor is connected to the first comparator, and is used to determine the level on the D+ line in response to the first output result of the first comparator read, wherein the first output result is the result of the first comparator comparing the voltage on the D+ line with the first reference voltage of the first comparator based on the voltage; the second power module is connected to the first processor The first processor is connected to the second comparator, and the second comparator is connected to the D- line through the D- line of the OTG line, and is used to output a second electrical signal on the D- line if the level on the D+ line determined by the first processor is a high level, and the second electrical signal makes the level on the D+ line a high level; the second processor is connected to the second comparator, and is used to determine the level on the D- line in response to the second output result of the second comparator read, wherein the second output result is the result of the second comparator comparing the voltage on the D- line with the second reference voltage of the second comparator; if the level on the D+ line is a high level, the fourth power supply module stops outputting the first electrical signal on the D+ line; the fifth power supply module is connected to the D- line, and is used to output a third electrical signal on the D- line; the second processor is also used to obtain the level on the D+ line; if the level on the D+ line is a low level, it is determined that the USB port type connected to the main terminal device through the OTG line is CDP, and the third power supply module is instructed to charge according to the current size corresponding to the CDP; the third power supply module is used to charge according to the current size corresponding to the CDP in response to the instruction of the second processor.

[0169] The embodiment of the present application also provides a reverse charging system, the system includes a master terminal device and a slave terminal device connected via an OTG line, the slave terminal device includes a first processor, a first power module, a second power module, a third power module and a first comparator; wherein the master terminal device is connected to the first power module via the VBUS line of the OTG line, and is used to output a power supply signal on the VBUS line; the second power module is connected to the first processor and connected to the master terminal device via the D+ line of the OTG line, and is used to respond to the power supply signal on the VBUS line detected by the first processor, and output a first electrical signal on the D+ line, and the first electrical signal makes the level on the D+ line high; the master terminal device is also used to respond to the first electrical signal on the D+ line detected, and obtain the level on the D+ line; the master terminal device is also connected to the first comparator via the D- line of the OTG line, and the master terminal device is also used to output a second electrical signal on the D- line if the level on the D+ line is high. signal, and the second electrical signal makes the level on the D+ line a high level; the first processor is connected to the first comparator, and is used to determine the level on the D- line in response to the first output result of the first comparator read, wherein the first output result is the result of the first comparator comparing the voltage on the D- line with the first reference voltage of the first comparator; if the level on the D+ line is a high level, the first power module stops outputting the first electrical signal on the D+ line; the third power module is connected to the D- line, and is used to output the third electrical signal on the D- line; the first processor is also used to obtain the level on the D+ line; if the level on the D+ line is a low level, it is determined that the type of the universal serial bus physical layer USB port connected to the main terminal device through the OTG line is a charging downstream port CDP, and the first power module is instructed to charge based on the current size corresponding to the CDP; the first power module is used to charge based on the current size corresponding to the CDP in response to the instruction of the first processor.

[0170] An embodiment of the present application also provides a computer-readable storage medium, which stores a computer program. The computer program includes at least one section of code, and the at least one section of code is executed by a computer to execute the reverse charging method described in the above embodiment.

[0171] The embodiment of the present application further provides a computer program, which, when executed by a computer, is used to execute the reverse charging method described in the above embodiment.

[0172] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk and other media that can store program codes.

[0173] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A reverse charging system, characterized in that: The system comprises a master terminal device and a slave terminal device connected via an active OTG line, wherein the master terminal device comprises a first processor, a first power module, a second power module and a first comparator, and the slave terminal device comprises a second processor, a third power module, a fourth power module, a fifth power module and a second comparator; The first power supply module is connected to the third power supply module via a voltage bus VBUS line of the OTG line, and is used to output a power supply signal on the VBUS line; The fourth power supply module is connected to the second processor and connected to the first comparator through the data positive signal D+ line of the OTG line, and is used to respond to the power supply signal on the VBUS line detected by the second processor and output a first electrical signal on the D+ line, wherein the first electrical signal makes the level on the D+ line high; The first processor is connected to the first comparator, and is used to determine the level on the D+ line in response to a first output result of the first comparator read, wherein the first output result is a result of the first comparator comparing the voltage on the D+ line with a first reference voltage of the first comparator; The second power supply module is connected to the first processor and connected to the second comparator through the negative data signal D- line of the OTG line, and is used to output a second electrical signal on the D- line if the level on the D+ line determined by the first processor is a high level, and the second electrical signal makes the level on the D- line a high level; The second processor is connected to the second comparator, and is used to determine the level on the D-line in response to a second output result of the second comparator, wherein the second output result is a result of the second comparator comparing the voltage on the D-line with a second reference voltage of the second comparator; If the level on the D- line is high, the fourth power supply module stops outputting the first electrical signal on the D+ line; The fifth power supply module is connected to the D-line and is used to output a third electrical signal on the D-line; The second processor is further configured to obtain a level on the D+ line; if the level on the D+ line is a low level, determine that the type of the universal serial bus physical layer USB port connected to the main terminal device through the OTG line is a charging downstream port CDP, and instruct the third power module to charge according to the current size corresponding to the CDP; The third power supply module is used to charge according to the current size corresponding to the CDP in response to the instruction of the second processor.

2. The system according to claim 1, characterized in that The voltage of the first electrical signal is greater than the first reference voltage of the first comparator; The first processor determines the level on the D+ line in response to the read first output result of the first comparator, including: The first processor reads a first output value of the first comparator as a first preset value, and determines that the level on the D+ line is a high level.

3. The system according to claim 1, characterized in that The voltage of the second electrical signal is greater than the second reference voltage of the second comparator; The second processor determines the level on the D-line in response to the second output result of the second comparator read, including: The second processor reads the second output value of the second comparator as a first preset value, determines that the level on the D-line is a high level, and confirms that the USB port type is a CDP or a dedicated charging port DCP.

4. The system according to claim 1, characterized in that The slave terminal device further includes a third comparator, and the third comparator is connected to the D+ line; The second processor obtains the level on the D+ line, including: The second processor reads the third output value of the third comparator as a second preset value, and determines that the level on the D+ line is a low level.

5. The system according to claim 1, characterized in that The current corresponding to the CDP is 1.5A.

6. A slave terminal device, characterized in that: The slave terminal device is connected to the master terminal device via an OTG line, the OTG line includes a D+ line, a D- line and a VBUS line, and the slave terminal device includes a processor, a first power module, a second power module, a third power module and a first comparator; The first power supply module is connected to the main terminal device through the VBUS line, and is used to receive the power supply signal output by the main terminal device on the VBUS line; The second power supply module is connected to the processor and connected to the main terminal device through the D+ line, and is used to output a first electrical signal on the D+ line in response to the power supply signal received by the first power supply module detected by the processor, wherein the first electrical signal makes the level on the D+ line high; The master terminal device is used to obtain the level on the D+ line in response to the first electrical signal output by the slave terminal device on the D+ line; The master terminal device is further configured to output a second electrical signal on the D- line if the level on the D+ line is a high level, wherein the second electrical signal causes the level on the D- line to be a high level; The first comparator is connected to the processor and connected to the master terminal device through the D-line, and is used to compare the voltage of the second electrical signal output by the master terminal device on the D-line with the first reference voltage of the first comparator to obtain a first output result; The processor is configured to determine a level on the D-line in response to the first output result of the first comparator read; If the level on the D- line determined by the processor is a high level, the second power supply module stops outputting the first electrical signal on the D+ line; The third power supply module is connected to the D-line and is used to output a third electrical signal on the D-line; The processor is further configured to obtain a level on the D+ line; if the level on the D+ line is a low level, determine that the type of the USB port connected to the main terminal device through the OTG line is CDP, and instruct the first power module to charge according to a current size corresponding to the CDP; The first power supply module is used to charge according to the current size corresponding to the CDP in response to the instruction of the processor.

7. The terminal device according to claim 6, characterized in that: The second power supply module is connected to the second comparator of the master terminal device through the D+ line, and the voltage of the first electrical signal is greater than the second reference voltage of the second comparator.

8. The terminal device according to claim 6, characterized in that: The voltage of the second electrical signal is greater than the first reference voltage of the first comparator; The processor is specifically configured to read the first output value of the first comparator as a first preset value, determine that the level on the D-line is a high level, and confirm that the USB port type is CDP or DCP.

9. The terminal device according to claim 6, characterized in that: The slave terminal device further includes a third comparator, and the third comparator is connected to the D+ line; The processor is specifically used to read the second output value of the third comparator as a second preset value, and determine that the level on the D+ line is a low level.

10. The terminal device according to claim 6, characterized in that: The current corresponding to the CDP is 1.5A.

11. A master terminal device, characterized in that: The master terminal device is connected to the slave terminal device via an OTG line, the OTG line includes a D+ line, a D- line and a VBUS line, and the master terminal device includes a processor, a first power module, a second power module and a first comparator; The first power supply module is connected to the slave terminal device via the VBUS line and is used to output a power supply signal on the VBUS line; The slave terminal device is used to output a first electrical signal on the D+ line in response to a power supply signal output by the master terminal device on the VBUS line, wherein the first electrical signal makes the level on the D+ line high; The first comparator is connected to the processor and connected to the slave terminal device through the D+ line, and is used to compare the voltage of the first electrical signal output by the slave terminal device on the D+ line with the first reference voltage of the first comparator to obtain an output result; The processor is configured to determine a level on the D+ line in response to the output result of the first comparator read; The second power supply module is connected to the processor and connected to the slave terminal device through the D- line, and is used to output a second electrical signal on the D- line if the level on the D+ line determined by the processor is a high level, and the second electrical signal makes the level on the D- line a high level; The slave terminal device is further configured to obtain a level on the D-line in response to the second electrical signal output by the master terminal device on the D-line; The slave terminal device is further configured to stop outputting the first electrical signal on the D+ line and output a third electrical signal on the D- line if the level on the D- line is a high level; The slave terminal device is also used to obtain the level on the D+ line. If the level on the D+ line is low, the USB port type connected to the master terminal device through the OTG line is CDP, and charging is performed according to the current size corresponding to the CDP.

12. The terminal device according to claim 11, characterized in that: The voltage of the first electrical signal is greater than the first reference voltage of the first comparator; The processor is specifically configured to read the output value of the first comparator as a first preset value, and determine that the level on the D+ line is a high level.

13. The terminal device according to claim 11, characterized in that: The second power supply module is connected to the second comparator of the slave terminal device through the D-line, and the voltage of the second electrical signal is greater than the second reference voltage of the second comparator.

14. The terminal device according to claim 11, characterized in that: The second power supply module stops outputting the second electrical signal on the D- line after a preset time period.

15. A reverse charging method, characterized in that: Applied to a slave terminal device, the slave terminal device is connected to a master terminal device via an OTG line, the OTG line includes a D+ line, a D- line and a VBUS line, the method includes: The slave terminal device outputs a first electrical signal on the D+ line in response to a power supply signal output by the master terminal device on the detected VBUS line, wherein the first electrical signal makes the level on the D+ line high; The master terminal device is used to obtain the level on the D+ line in response to the first electrical signal output by the slave terminal device on the D+ line; The master terminal device is further configured to output a second electrical signal on the D- line if the level on the D+ line is a high level, wherein the second electrical signal causes the level on the D- line to be a high level; The slave terminal device acquires the level on the D-line in response to the second electrical signal output by the master terminal device on the D-line; If the level on the D-line is high, the slave terminal device stops outputting the first electrical signal on the D+ line, outputs a third electrical signal on the D-line, and acquires the level on the D+ line; If the level on the D+ line is a low level, the slave terminal device determines that the type of the USB port connected to the master terminal device through the OTG line is CDP, and charges according to the current size corresponding to the CDP.

16. The method according to claim 15, characterized in that The D+ line is connected to a first comparator in the master terminal device, and a voltage of the first electrical signal is greater than a first reference voltage of the first comparator.

17. The method according to claim 15, characterized in that The D-line is connected to a second comparator in the slave terminal device, and a voltage of the second electrical signal is greater than a second reference voltage of the second comparator; The step of obtaining the level on the D-line comprises: The first output value of the second comparator is read from the terminal device as a first preset value, the level on the D-line is determined to be a high level, and the USB port type is confirmed to be CDP or DCP, wherein the first output value is the result of the second comparator comparing the voltage of the second electrical signal with the second reference voltage.

18. The method according to claim 15, characterized in that The D+ line is connected to a third comparator in the slave terminal device; The obtaining of the level on the D+ line includes: The second output value of the third comparator is read from the terminal device as a second preset value, and the level on the D+ line is determined to be a low level.

19. The method according to claim 15, characterized in that The current corresponding to the CDP is 1.5A.

20. A reverse charging method, characterized in that: Applied to a master terminal device, the master terminal device is connected to a slave terminal device via an OTG line, the OTG line includes a D+ line, a D- line and VBUS, the method includes: After the master terminal device outputs a power supply signal on the VBUS line, the master terminal device obtains a level on the D+ line in response to detecting a first electrical signal output by the slave terminal device on the D+ line; The slave terminal device is used to output a first electrical signal on the D+ line in response to a power supply signal output by the master terminal device on the VBUS line, wherein the first electrical signal makes the level on the D+ line high; If the level on the D+ line is high, the master terminal device outputs a second electrical signal on the D- line, and the second electrical signal makes the level on the D- line high; The slave terminal device is further configured to obtain a level on the D-line in response to the second electrical signal output by the master terminal device on the D-line; The slave terminal device is further configured to stop outputting the first electrical signal on the D+ line and output a third electrical signal on the D- line if the level on the D- line is a high level; The slave terminal device is also used to obtain the level on the D+ line. If the level on the D+ line is low, it is determined that the USB port type connected to the master terminal device through the OTG line is CDP, and charging is performed according to the current size corresponding to the CDP.

21. The method according to claim 20, characterized in that The D+ line is connected to a first comparator in the master terminal device, and a voltage of the first electrical signal is greater than a first reference voltage of the first comparator; The obtaining of the level on the D+ line includes: The master terminal device reads a first output value of the first comparator as a first preset value, and determines that the level on the D+ line is a high level, wherein the first output value is a result of the first comparator comparing the voltage of the first electrical signal with the first reference voltage.

22. The method according to claim 20, characterized in that The method further comprises: The master terminal device stops outputting the second electrical signal on the D-line after a preset time period.

23. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and the computer program is executed by a terminal device to control the terminal device to execute the method according to any one of claims 15 to 19.

24. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and the computer program is executed by a terminal device to control the terminal device to execute the method according to any one of claims 20 to 22.

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