Coverage-based microelectronic circuit and method for providing a design of a microelectronic circuit

Abstract

A microelectronic circuit includes a plurality of logic cells and register circuits arranged in a plurality of processing paths, and a plurality of monitoring cells associated with individual ones of the processing paths. Each monitoring cell is configured to generate an observation signal in response to abnormal operation of the individual processing path. Each of the plurality of logic cells belongs to one of a plurality of delay levels, depending on the amount of delay that may be generated. The delay levels include first, second, and third levels, wherein the first level covers logic cells that may generate the longest delay, the second level covers logic cells that may generate shorter delays than the first level, and the third level covers logic cells that may generate shorter delays than the second level. At least some of the plurality of processing paths include logic cells that belong to the second level but do not have monitoring cells. At least some of the plurality of processing paths include logic cells that belong to the third level but have monitoring cells associated with them.

Description

Technical Field

[0001] The invention relates to a technique for microelectronic circuits comprising multiple processing paths and, in particular, to a method in which different levels of delay criticality of the processing paths can be taken into account. Background Art

[0002] The processing path in a microelectronic circuit runs through logic cells and register circuits, such that the register circuit stores the output value of the previous logic cell at the rising or falling edge of a trigger signal (if the register circuit is a flip-flop) or at a high or low level of the trigger signal (if the register circuit is a latch). The trigger edge of the trigger signal or some other control event defines an allowable time limit before which a digital value must appear at the data input of the register circuit in order to be properly stored. The allowable time limit is not necessarily the exact instant of the trigger edge, but is defined to have some relationship to the exact instant of the trigger edge due to physical effects such as the finite rate at which voltage levels can change.

[0003] Time borrowing in microelectronic circuits occurs when a circuit component is temporarily allowed to borrow time from a subsequent stage, i.e., change a digital value later than intended, if subsequent circuit components on the same processing path can process it without corrupting the processed data. Instances of time borrowing should be detected as timing events.

[0004] A monitor circuit is one way to detect timing events. A monitor circuit is a circuit component or functionality added to or associated with a register circuit and configured to generate a timing event observation (TEO) signal in response to a change in an input digital value that occurs later than the allowable time limit. In addition to the actual monitor circuit, the microelectronic circuit must include OR trees and / or other structures for collecting, processing, and analyzing the TEO signal from the monitor circuit.

[0005] Other types of monitoring units and methods exist. One example is the use of a replica path that emulates the delay of the actual processing path. A known input signal can be fed into the replica path; the known configuration of the replica path means that a known type of output signal should be generated. If the output of the replica path is not what it should be, it is very likely that some digital values are also changing later than in the actual processing path.

[0006] Monitoring, performed in one or another manner, can be combined with, for example, advanced voltage scaling (AVS), sometimes also called adaptive voltage scaling, so that an increase in the number of events detected during monitoring triggers an increase in the operating voltage, and vice versa. The number of detected events can also trigger other compensatory actions, typically involving changes in the values of other operating parameters of the circuit, such as clock frequency or temporarily changing the clock waveform.

[0007] A major drawback of circuit cells used for monitoring is that they consume circuit area and operating power. Placing monitor circuits, replica paths, and / or other monitoring cells within a designed microelectronic circuit involves tradeoffs. The more monitoring cells there are, the better the coverage for detecting timing events, but at the same time, more circuit area and operating power are consumed for other purposes compared to the original design of the microelectronic circuit.

[0008] Knowledge of how circuit components work allows designers of microelectronic circuits to perform delay profile analyses, which determine how much delay each circuit component will incur on data passing through the circuit component. A straightforward guide for placing monitoring units would involve categorizing circuit components into delay classes based on how long they incur, and deciding to monitor only those circuit components that belong to the longest delay class on the processing path. However, for a number of reasons, that would only provide a partial solution to the problem.

[0009] First, individual variations between manufactured microelectronic circuits make it impossible to determine which circuit component will actually be critical. A circuit component that, according to a delay profile analysis, only falls into the second or third longest delay class may actually be the most critical circuit component in a real-life manufactured circuit. Second, the executed software may (at least under certain circumstances) fail to use processing paths that pass through the most critical circuit component for extended periods of time, causing events that should actually be detected to occur on processing paths not considered critical in the delay profile analysis. Third, even when data is flowing through critical processing paths, it may happen that the data contains an extended sequence of constant (unchanging) digital values at a moment in time, which naturally makes it impossible to detect any exceptional events on those paths, because such events only occur when digital values change at the inputs of register circuits.

[0010] Additional complexity to the task of designing microelectronic circuits comes from the need for testing. The concepts of Design for Testability (DFT), or Design-For-Test (DFT), have become de facto industry standards, defining certain procedures for testing microelectronic circuits. For example, it should be possible to selectively couple register circuits contained in a microelectronic circuit into long chains that essentially function as shift registers; a string of digital values can be fed in at one end and read out at the other. Passing a known test pattern through such a chain of register circuits and checking its form at the output determines whether all register circuits in the chain are changing their states as expected, or whether any register circuits are stuck at some particular value (stuck-at fault testing). Fast fault testing involves slowly feeding in the test pattern at a low clock speed, then applying one or more clock pulses at full operating speed, causing the test pattern to progress through the chain at functional logic speed for as many steps as the clock pulses, and finally clocking out the test pattern again at a low clock speed. Fast testing can provide information about register circuits that are slower than expected. If monitor circuits and time borrowing capabilities, or other kinds of monitoring elements are involved, these should also be testable. Summary of the Invention

[0011] The aim here is to propose a microelectronic circuit that strikes an optimal balance between the number of monitoring cells and the coverage achieved thereby. Coverage refers to the rate at which processing paths can be monitored for the occurrence of sequential events.

[0012] Another object is to propose a method for producing a design of a microelectronic circuit having the above-mentioned characteristics.

[0013] Yet another objective is to ensure that the microelectronic circuit is compatible with standard DFT methodologies and capable of AVS.

[0014] These objectives are achieved by determining at least some locations for placing monitoring cells by considering the delay criticality of a processing path that travels through two or more logic cell levels between register circuits.

[0015] According to a first aspect, a microelectronic circuit is provided that includes a plurality of logic cells and register circuits, the logic cells and register circuits being arranged in a plurality of processing paths. The microelectronic circuit includes a plurality of monitoring cells associated with respective processing paths, each of the monitoring cells being configured to generate an observation signal in response to abnormal operation of the respective processing path. Each of the plurality of logic cells belongs to one of a plurality of delay levels, depending on the amount of delay that may be generated. The delay levels include a first, a second, and a third level, wherein the first level covers logic cells that may generate the longest delay, the second level covers logic cells that may generate a shorter delay than the first level, and the third level covers logic cells that may generate a shorter delay than the second level. At least some of the plurality of processing paths include logic cells that belong to the second level but do not have monitoring cells. At least some of the plurality of processing paths include logic cells that belong to the third level but have monitoring cells associated with them.

[0016] According to an embodiment, the monitoring unit includes a plurality of monitor circuits associated with respective ones of the plurality of register circuits, each of the plurality of monitor circuits being configured to generate a respective timing event observation signal in response to a change in a digital value at an input of the respective register circuit that occurs later than a permissible time limit defined by a trigger signal of the respective register circuit. At least some of the register circuits on the processing paths following the logic units belonging to the second level do not have monitor circuits, and at least some of the monitor circuits are associated with register circuits on the processing paths following the logic units belonging to the third level. The use of monitor circuits has the advantage of enabling the control unit of the microelectronic circuit to be aware of the occurrence of a timing event and to take appropriate measures.

[0017] According to an embodiment, at least some of the processing paths are adaptive processing paths whose performance can be configured by assuming operational parameters of the microelectronic circuit. This adaptability of the processing paths enables monitoring of timing events to achieve desired operating power savings.

[0018] According to an embodiment, the microelectronic circuit includes a first signal collection circuit configured to collect at least a timing event observation signal generated by a monitor circuit associated with a register circuit subsequent to a logic unit belonging to the first level on a processing path. This has the advantage of efficiently and promptly communicating information about the occurrence of the timing event to a control unit.

[0019] According to an embodiment, the first signal collection circuit is configured to also collect the timing event observation signal generated by the monitor circuit associated with the register circuit of the logic unit belonging to a level other than the first level on the processing path. This has the advantage of allowing a response to timing events regardless of the part of the circuit in which they occur.

[0020] According to an embodiment, the microelectronic circuit includes a second signal collection circuit configured to collect a timing event observation signal generated by the monitor circuit associated with a register circuit that follows a logic unit belonging to at least one of the second and third levels on the processing path. This has the advantage of enabling the microelectronic circuit to react differently depending on the portion of the microelectronic circuit in which the timing event is observed.

[0021] According to an embodiment, the microelectronic circuit is configured to collect a timing event observation signal through the first signal collection circuit, collect a timing event observation signal through the second signal collection circuit, adapt the operation of at least a portion of the microelectronic circuit by causing an operating parameter of the microelectronic circuit to take an operating parameter value in response to the timing event observation signal collected via the first signal collection circuit according to a first adaptation rule, and adapt the operation of at least a portion of the microelectronic circuit by causing the operating parameter of the microelectronic circuit to take an operating parameter value in response to the timing event observation signal collected via the second signal collection circuit according to a second adaptation rule. This has the advantage of adapting the operation of the microelectronic circuit in a particular manner depending on the portion of the microelectronic circuit in which the timing event is observed.

[0022] According to an embodiment, the first adaptation rule is based on a first number of timing event observation signals collected per unit time by the first signal collection circuit, while the second adaptation rule is based on a second, different number of timing event observation signals collected per unit time by the second signal collection circuit. This has the advantage of enabling different responses depending on how frequently timing events are observed in a more or less delay-critical portion.

[0023] According to an embodiment, the microelectronic circuit includes a test input device configured to controllably feed a test input signal consisting of a test input value into a plurality of circuit components of at least one of the processing paths; and a test output device configured to controllably collect test output values from the plurality of circuit components of the at least one of the processing paths. This has the advantage of making the microelectronic circuit compatible with standard DFT methodologies.

[0024] According to an embodiment, the microelectronic circuit includes an operating parameter value selector configured to select the operating parameter value based on the collected test output value. This has the advantage that the test results can be used to influence the AVS behavior of at least a portion of the circuit.

[0025] According to an embodiment, the test output device is configured to selectively collect the test output value, the test output value being derived from at least one of the data outputs of the plurality of register circuits and the timing event observation signal outputs of the plurality of monitor circuits. This has the advantage of enabling testing to be directed to a desired portion of the microelectronic circuit.

[0026] According to an embodiment, the test output device is configured to controllably collect test output values from a processing path where an intermediate stage includes register circuits not associated with corresponding monitoring units, while a subsequent stage includes register circuits associated with corresponding monitoring units. This has the advantage of enabling testing of multi-cycle critical paths.

[0027] According to an embodiment, the test output device is configured to controllably collect test output values from a processing path in which at least one intermediate stage includes a register circuit capable of time borrowing. This has the advantage of enabling testing the operation of a multi-cycle critical path regardless of the presence of monitors associated with its intermediate stages.

[0028] According to an embodiment, at least some of the monitoring units include a replica path configured to simulate the operation of a corresponding one of the plurality of processing paths with known input data. This has the advantage of providing an alternative way of checking the operation of the circuit for timing events.

[0029] According to a second aspect, there is provided a method for generating a design for a microelectronic circuit. The method comprises:

[0030] a) providing a preliminary first design of the microelectronic circuit, the first design defining processing paths through logic cells and register circuits within the microelectronic circuit,

[0031] b) performing a delay distribution analysis on the first design to classify the logic cells into delay classes according to the amount of delay that may be generated,

[0032] c) classifying a first subset of the logic cells as delay critical logic cells based on the occurrence of one or more longest delay levels in the delay distribution analysis,

[0033] d) generating an intermediate second design of the microelectronic circuit by associating a monitoring unit with a processing path containing said delay-critical logic unit,

[0034] e) generating a further third design of the microelectronic circuit by associating monitoring cells with processing paths that include logic cells that were not classified as delay critical logic cells in step c) and that contain at least a threshold number of processing paths without associated monitoring cells, and

[0035] f) outputting the third design as the design of the microelectronic circuit.

[0036] According to an embodiment, the threshold number of processing paths is defined as the number of register circuits without associated monitoring units, through which the corresponding processing path passes. This has the advantage that delay-critical paths of this type can be identified in a robust and straightforward manner.

[0037] According to an embodiment, the threshold number of processing paths is defined as the total delay that circuit components along the corresponding processing paths may produce based on the delay profile analysis. This has the advantage of being able to identify delay-critical paths in a very flexible and accurate manner.

[0038] According to an embodiment, step d) includes placing the monitor circuit in a register circuit that occurs after the delay-critical logic cell on the processing path, and step e) includes placing the monitor circuit in a register circuit that occurs after a logic cell that was not classified as a delay-critical logic cell in step c) on the processing path, but that is preceded by at least a threshold number of processing paths on the processing path that do not have a monitor-equipped register circuit. This has the advantage of being able to find an optimal location for the monitor circuit.

[0039] According to one embodiment, step e) includes adding one or more signal collection circuits to collect signals from the monitor circuit, the monitor circuit being placed in a register circuit that is located in the processing path after the logic cells that were not classified as delay-critical logic cells in step c). This has the advantage of enabling the control unit of the microelectronic circuit to be aware of the occurrence of a timing event and to take appropriate measures.

[0040] According to an embodiment, step e) includes associating monitoring units with processing paths that include a second subset of logic cells that were not classified as delay-critical logic cells in step c), and that include at least a first threshold number of processing paths without associated monitoring units, and associating monitoring units with processing paths that include a third subset of logic cells that were not classified as delay-critical logic cells in step c), and that include at least a second threshold number of processing paths that are not associated with monitoring units, which is different from the first threshold number. This has the advantage of being able to find optimal locations for monitoring unit placement.

[0041] According to an embodiment, associating the monitoring unit with the processing path includes placing a monitor circuit on a register circuit of the processing path, and step e) additionally includes adding a first signal collection circuit to collect signals from an output of the monitor circuit placed next to the register circuit of the logic units of the second subset, and adding a second signal collection circuit to collect signals from an output of the monitor circuit placed next to the register circuit of the logic units of the third subset. This has the advantage of enabling the microelectronic circuit to react differently depending on the portion of the microelectronic circuit in which the timing event is observed. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings are included to provide a further understanding of the invention and constitute a part of this specification, illustrate embodiments of the invention and together with the description help to explain the principles of the invention. In the drawings:

[0043] Figure 1 Schematically illustrating the register circuit,

[0044] Figure 2 Example Figure 1 The waveforms of some signals in the register circuit of the type shown are

[0045] Figure 3 Schematically illustrating the register circuit,

[0046] Figure 4 Schematically illustrating the register circuit,

[0047] Figure 5 Schematically illustrating the use of replication paths,

[0048] Figure 6 schematically illustrates a portion of a microelectronic circuit,

[0049] Figure 7 Schematically illustrate the method, and

[0050] Figure 8 The principle of using a signal collection circuit to adapt the operation of the microelectronic circuit is schematically illustrated. DETAILED DESCRIPTION

[0051] Below, we describe microelectronic circuits and methods for their design and operation. A typical microelectronic circuit includes multiple logic cells and register circuits arranged in multiple processing paths. A processing path is a sequence of circuit components through which digital data passes, allowing it to be processed in logic cells and temporarily stored in register circuits located between successive logic cells along the processing path. The software executed by the microelectronic circuit defines which processing path is used at any given time and in what manner.

[0052] To provide a better understanding of some of the details explained later, refer to Figure 1 Describe an example of a register circuit. Figure 1 The register circuit includes a first sub-register stage 101 and a second sub-register stage 102. The data input and data output of the first sub-register stage 101 are labeled i1 and q1, respectively, while the data input and data output of the second sub-register stage 102 are labeled i2 and q2, respectively. The data input D of the register circuit is coupled to the data input i1 of the first sub-register stage 101 via a multiplexer 103, such that a high level of the control signal SE causes the test input SI to be coupled to the data input i1 of the first sub-register stage 101. The data output q2 of the second sub-register stage 102 is coupled to the data output Q of the register circuit.

[0053] The register circuit includes two trigger signal inputs for trigger signals CP and CPD. The former may be referred to herein as the clock signal. For reasons explained in detail below, the other trigger signal CPD is a delayed version of the clock signal CP, preferably such that the delay does not exceed half the cycle of CP, and may therefore be referred to as a delayed clock signal. Depending on the value (low / high) of the control signal TTBEN, either the delayed clock signal CPD or the clock signal CP is coupled to the trigger signal input of the first sub-register stage 101. The clock signal CP is coupled to the trigger signal input of the second sub-register stage 102.

[0054] The register circuit includes or is associated with a monitor circuit 105 that is configured to generate a timing event observation (TEO) signal in response to a change in the digital value at the data input D of the register circuit that occurs later than an allowable time limit. The time limit is defined by the clock signal CP and by the physical characteristics of the appropriate circuit components. Simply put, the digital value at the data input D should assume its appropriate value just before the triggering edge of the clock signal CP, so that if a change that should have occurred before the triggering edge occurs after the triggering edge, the change is late. In practice, there are factors such as finite rise and fall times, which means that the allowable time limit is not exactly the instant of the triggering edge, but is usually slightly earlier. In some special cases, it may even be slightly later.

[0055] The data input DM of the monitor circuit 105 receives a copy of the data input i1 entering the first sub-register stage 101. The clock input CPP of the monitor circuit 105 receives a trigger signal that defines a permissible time limit after which a change in the digital value at the data input of the register circuit is late. The trigger signal received at the clock input CPP may define a so-called TEO window, such that it also defines an end limit after which the monitor circuit 105 no longer reacts to changes in the input data.

[0056] At its timing event output TE, monitor circuit 105 is configured to generate a TEO signal. Here, we can assume a signal level protocol according to which the TEO signal is normally low, but changes to a high level at the instant a timing event is observed, and remains high until the end of the frequency period in which the timing event is observed. By using an appropriate value for control signal TMTEOH, monitor circuit 105 can be caused to maintain a high value of the TEO signal (once it occurs) for a longer period than until the end of the clock cycle. This functionality is useful, for example, in test mode, where the maintained high value of the TEO signal can be collected for further processing and analysis.

[0057] Using the delayed clock signal CPD as the trigger signal for the first sub-register stage 101 enables the register circuit to borrow time. In other words, it temporarily allows the logic unit or other parts of the processing path preceding this type of register circuit to trigger a timing event, that is, a late change in the digital value, because Figure 1The register circuit can process it without corrupting the data being processed. As long as a late-arriving change in the digital value at data input D occurs before the trigger edge in delayed clock signal CPD, it will be correctly stored in the register circuit. (To be precise, this also involves rise and fall times, so the ultimate limit is some permissible time limit defined by delayed clock signal CPD, not necessarily the exact instant of its trigger edge.) Time borrowing can be disabled by setting the value of control signal TTBEN to high, in which case clock signal CP is used as the trigger signal for first sub-register stage 101.

[0058] The data input i2 of the second subregister stage 102 receives either the value at the data output q1 of the first subregister stage 101 or the value at the TE output of the monitor circuit 105, depending on the value of the control signal TMSE that controls the multiplexer 106. It is assumed here that the microelectronic circuit includes a so-called common scan chain, which is used to collect digital values produced by the circuit components under test during a test mode. A high value of the control signal TMSE causes the output value of the monitor circuit 105 to be directed to the common scan chain, while a low value of TMSE directs the actual, temporarily stored digital values entering the first and second subregister stages to the common scan chain. The control signal CDN to the second subregister circuit 102 is an asynchronous reset signal.

[0059] Figure 1 A possible way to generate the trigger signal CKP that enters the clock pulse input terminal CPP of the monitor circuit is illustrated. The associated waveform is as follows: Figure 2 As shown. Normally, signal TCPDG is low, and therefore its inverse is high. Therefore, delayed clock signal CPD passes through AND gate 107 to one input of NOR gate 108. The other input of the NOR gate receives the inverse of clock signal CP, CPN. Trigger signal CKP, which enters trigger input CPP of monitor circuit 105, is high during the period between the rising edges of clock and delayed clock signals CP and CPD. When signal TCPDG goes high, its inverse goes low, and the output of AND gate 107 remains low. This results in trigger signal CKP and the inverse of inverse clock signal CPN being equal to clock signal CP.

[0060] The exact manner in which the monitor circuit 105 is implemented internally is not that important, as long as it can implement the functionality described herein. An example of a physical implementation of a monitor circuit can be found, for example, in patent application number PCT / FI2017 / 050290.

[0061] To provide some further understanding of some of the details explained later, refer to Figure 3Describe another example of a register circuit. Figure 3 The register circuit is capable of time borrowing but does not contain or is not associated with the monitor circuit. Figure 1 The register circuits of the present invention share: a first sub-register stage 301 and a second sub-register stage 302 connected in series between a data input D and a data output Q, along with two multiplexers 303 and 304. Depending on the value of a control signal SE, the first multiplexer 303 is configured to couple either the data input D or the test input SI to the data input i1 of the first sub-register stage. Depending on the value of a control signal TTBEN, the second multiplexer 304 is configured to couple either the clock signal CP or the delayed clock signal CPD to the (inverted) trigger signal input of the first sub-register stage 301. The clock signal CP is coupled to the trigger signal input of the second sub-register stage 302, and the asynchronous reset signal CDN is coupled to the control input of the second sub-register stage 302.

[0062] The polarity of the control signal TTBEN at the second multiplexer 304 is such that a high value of the control signal TTBEN disables time borrowing by causing the clock signal CP to become the trigger signal for the first sub-register stage 301, but a low value of the control signal TTBEN enables time borrowing by causing the delayed clock signal CPD to become the trigger signal for the first sub-register stage 301. Because there is no monitor, any actual use of the time borrowing function will not result in any detected timing events. This type of register circuit may still have special uses, which will be described in more detail below.

[0063] For comparison's sake, Figure 4 The example shows a register circuit that is testable but does not support time borrowing. The same trigger signal CP clocks both sub-register stages 401 and 402. If the digital value at the data input D changes late, that is, only after the allowed time limit defined by the trigger signal CP, it will not be properly stored in the register. Figure 4 Multiplexer 403 may be used to couple test input SI instead of data input D.

[0064] Figure 3 and 4 Any register circuit can be associated with a monitor circuit; as an alternative feature, the monitor circuit can be placed in Figure 3or any register circuit of 4. In this sense, a monitor circuit is a circuit configured to generate a corresponding timing event observation signal in response to a change in the digital value at the input of the corresponding register circuit that occurs later than the allowable time limit defined by the trigger signal to the corresponding register circuit. A timing event is an example of abnormal operation of the corresponding processing path, because normally, all circuit components in the processing path should ensure that any change in digital value proceeds through the processing path according to the timing defined by the appropriate trigger signal.

[0065] Using a monitor circuit to detect timing events is not the only way to detect abnormal operation of a processing path. Another example is shown schematically in Figure 5 It is assumed here that the microelectronic circuit includes multiple processing paths, one of which is as follows Figure 5 , a processing path 501 is shown. The microelectronic circuit includes a so-called replica path 502, whose task is to emulate the operation of processing path 501, but with known input data. The processing of the known input data in replica path 502 should result in test data of a known form being output from replica path 502. If the output test data differs from what it should be, the replica path will operate in some unusual manner. Therefore, it can be assumed with reasonable probability that the "real" processing path 501 will also operate unusually under the same operating conditions, that is, under the influence of the same values of operating parameters such as operating voltage, clock frequency, and the like.

[0066] The use of monitor circuits associated with register circuits, the use of replica paths, and other similar arrangements are generally described as storing monitoring units associated with corresponding ones of the processing paths. Each such monitoring unit is configured to generate an observation signal in response to abnormal operation of the corresponding processing path. In the case of a register circuit equipped with a monitor, the monitoring unit is the monitor circuit, and the observation signal is a timing event observation signal. In the case of a replica path, the monitoring unit is the replica path together with a circuit component that analyzes its output, and the observation signal is a signal indicating that the output of the replica path is not what it should be.

[0067] Use of monitor circuits (such as Figure 1The TEO signal generated can be used elsewhere in the microelectronic circuit to ignore or filter output data from a register circuit that received its input data late, as indicated by the TEO signal. There are even some applications in which output data can be allowed to pass through despite some uncertainty as to whether the output data was properly stored despite its late arrival. For example, if the processed data represents a video signal for viewing by a human user, some noise in the data may be acceptable because it will be barely noticeable in the reproduced video image.

[0068] Figure 6 This is a schematic diagram of a portion of a microelectronic circuit. It contains multiple logic cells shown as rounded rectangles, and multiple register circuits shown as sharp rectangles. These are arranged into multiple processing paths. Figure 6 For example, the processing path through register circuit 602 on the left is shown as successively passing through logic unit 611, register circuit 622, logic unit 631, register circuit 641, logic unit 651, and register circuit 661.

[0069] The microelectronic circuit includes a plurality of monitoring units associated with individual ones of the processing paths. Each monitoring unit is configured to generate an observation signal in response to abnormal operation of the corresponding processing path. In the possible alternatives listed above, Figure 6 The use of a monitor circuit associated with a respective register circuit of a plurality of register circuits is illustrated. The term "associated with" encompasses all possible ways in which the monitor circuit in question is configured to monitor the register circuit only for the occurrence of a timing event.

[0070] Not Figure 6 All register circuits of a microelectronic circuit have associated with them a monitor circuit. Figure 6 These are register circuits 622, 642, and 661. Each monitor circuit is configured to generate a respective timing event observation signal in response to a change in the digital value at the input of the respective register circuit that occurs later than an allowable time limit defined by a trigger signal to the respective register circuit.

[0071] Depending on the amount of delay that may occur, Figure 6Each logic cell shown in the figure belongs to one of several delay classes. The delay is the amount of time it takes for the output of a logic cell to take on the appropriate value after the corresponding input value has become available to the logic cell. Designers of microelectronic circuits can use any of a variety of analysis tools to generate a calculated estimate of the amount of delay a logic cell is expected to incur. The process of estimating delays is referred to as delay profile analysis.

[0072] The delay levels can include at least a first, second, and third level. In practice, there can be any number of such levels, but these levels are provided here as examples. The first level includes logic cells that are likely to produce the longest delays based on analysis. The second level includes logic cells that are likely to produce shorter delays than the first level, and the third level includes logic cells that have shorter delays than the second level.

[0073] The concept of delay rank is used here as an umbrella concept that encompasses all the ways in which the circuit components being analyzed can be divided, allocated, or partitioned according to the amount of delay they are likely to incur. The logic cells in the first rank, i.e., those expected to incur the longest delays, are the most critical in view of the timing events that may occur during operation. Therefore, when considering the placement of monitor circuits, any register circuit that follows a logic cell belonging to the first rank on at least one processing path should be the most likely candidate for obtaining an associated monitor circuit. Here, "follow" means immediately following, i.e., the register circuit in question is the one in which the output value of the logic cell in the first rank should be temporarily stored upon the next trigger edge of the trigger signal.

[0074] Microelectronic circuits are displayed in Figure 6 A portion of the circuit includes only one logic unit belonging to the first level, namely, logic unit 611. All processing paths through logic unit 611 are followed by register circuit 622. In other words, register circuit 622 is followed by logic unit 611 on all processing paths. Therefore, the monitor circuit is associated with register circuit 622.

[0075] Figure 6 The microelectronic circuit is characterized in that at least some processing paths include logic cells belonging to the second level but without monitoring cells, and at least some processing paths include logic cells belonging to the third level but with monitoring cells associated therewith. This characteristic is described in more detail below.

[0076] Monitor circuits are also associated with register circuit 642, which follows logic cell 632 on all those processing paths that pass through that logic cell, even though logic cell 632 belongs to the third level, and even though at least some of the register circuits that follow logic cells belonging to the second level on the corresponding processing paths do not have monitor circuits (see logic cells 631 and 652, register circuits 641 and 662 follow logic cells 631 and 652). The logical explanation for this is that monitor circuits have been placed in the design of the microelectronic circuit by considering the number of processing paths preceding each register circuit. The number of processing paths can be defined as the number of register circuits that a corresponding processing path passes through. Additionally or alternatively, the number of processing paths can be defined as the total delay that circuit components along the corresponding processing path may incur based on a delay profile analysis.

[0077] Figure 7 A method for generating a design for a microelectronic circuit is schematically illustrated, the method following the principles outlined above. Step 701 represents providing a preliminary first design of the microelectronic circuit. This first design defines processing paths through logic cells and register circuits within the microelectronic circuit.

[0078] Step 702 represents performing a delay profile analysis on the first design. The goal of the delay profile analysis is to classify the logic cells of the microelectronic circuit into delay classes based on the amount of delay they are likely to incur. As a result of step 702, the logic cells to be designed in the microelectronic circuit are known to belong to a specific delay class.

[0079] Step 703 represents the classification of a subset of logic cells of the microelectronic circuit to be designed as delay critical logic cells. This subset may be referred to as the first subset for the sake of naming consistency, and the classification is based on their appearance in one or more longest delay classes in the delay distribution analysis. The expression "one or more longest delay classes" refers to the fact that although in the above Figure 6 The description of suggests that only the first level of logic cells are automatically considered critical, but the designer of the microelectronic circuit can decide that all logic cells belonging to the N longest delay levels are critical, where N is a positive integer. Figure 6 , we can assume that N=1 here.

[0080] Step 704 represents generating a second, intermediate design of the microelectronic circuit by associating the monitoring cell with the processing path containing the delay-critical logic cell. Figure 6 In the scheme of FIG. 7 , this refers to placing monitor circuits to the delay-critical register circuits found in step 703 : in step 704 , placing monitor circuits associated with register circuit 622 .

[0081] Step 705 represents finding logic units that are not classified as delay critical above but are located on processing paths that contain at least a threshold number of processing paths that do not have associated monitoring units. Figure 6 In the scheme of FIG, this is equivalent to finding a register circuit that (directly) follows a level 2 or 3 logic cell that is preceded by at least a threshold number of processing paths without a register circuit equipped with a monitor circuit. Step 706 represents the production of a third, alternative design of the microelectronic circuit by associating a monitor cell with the processing path found in this manner. Referring again to FIG. Figure 6 This means placing monitor circuits in register circuits following level 2 or 3 logic cells that are preceded by at least a threshold number of processing paths without register circuits equipped with monitor circuits. In other words, this means placing monitor circuits in register circuits 642 and 661. Step 707 represents outputting a third design as a result of this method.

[0082] It has been pointed out above that one way of defining what is the critical number of preceding processing paths is to define it as a number of register circuits (without the associated monitoring units passed by the corresponding processing paths). Figure 6 , we can assume that this so-called step size is two. Thus, for example, a monitor circuit has been placed on register circuit 642 because there is a processing path that passes through it and passes through two preceding register circuits without a monitor: for example, the processing path through circuit elements 601, 612, 623, and 632; or the processing path through circuit elements 604, 613, 624, and 632. A monitor has been placed on register circuit 661 because there is a processing path that passes through it and passes through two preceding register circuits without a monitor (through circuit elements 612, 631, 641, and 651).

[0083] Another way to define what is the critical number of the preceding processing path is to define it as the total delay that the circuit components along the individual processing paths may produce based on the delay distribution analysis. And this definition can also produce Figure 6 6. For example, even if logic units 612 and 632 are both fast enough to belong to the third delay class, the sum of the delays they are expected to produce may be greater than the threshold amount of delay that becomes critical. Thus, for example, the total delay of the circuit components along processing path 603-612-623-632 may be large enough to justify placing a monitor on register circuit 642.

[0084] Defining the critical number of processing paths as the total delay, rather than just the number of steps through the preceding register circuit without a monitor, is referred to as finding a multi-cycle critical path (MCCP). An MCCP is a processing path that passes through specific circuit components such that the time it takes for a piece of digital data to pass through these circuit components is two or more clock cycles. Specifically, the word "critical" indicates that the total delay that these circuit components may incur along the MCCP is longer than a threshold.

[0085] It should be noted that the definition of MCCP is not limited to how rising or falling edges occur in the trigger (clock) signal. Register circuits (like those in Figures 1, 3, and 4) are single-edge triggered: the actual value of the digital data at the input is stored in the register circuit at each rising edge of the trigger signal. If all register circuits in the processing path in question are of this type, then all delays are expressed as multiples of one clock period. If other types of register circuits are present, such as dual-edge-triggered flip-flops, latches, pulsed latches, and / or the like, the delay estimate must take that into account.

[0086] The more general case of an MCCP can be characterized as a Multiple Control Event Critical Path (MCECP), where the delay assessment must also take into account processing paths where the propagation time between circuit components can be a non-integer multiple of the clock cycle. For example, if the register circuit is a single-edge-triggered flip-flop, then three clock cycles are required to pass data through an MCCP that is three control events long. If the register circuit is a dual-edge-triggered flip-flop or latch, then one and a half clock cycles are required to pass data through an MCCP that is three control events long.

[0087] In order to utilize the TEO signal that the monitor circuit can generate in those embodiments that use a monitor circuit, a signal collection circuit should be added. Figure 8 , a first signal collection circuit 801 may be configured to collect at least TEO signals generated by monitor circuits associated with delay-critical register circuits. These are register circuits that follow logic units belonging to the first level on the processing path (i.e., logic units that are expected to generate the longest delays). A second signal collection circuit 802 may be configured to collect TEO signals generated by monitor circuits associated with other register circuits. These are register circuits that follow logic units belonging to the second and / or third levels on the processing path. An example of a signal collection circuit is an OR tree that generates an indication that a timing event has been detected if at least one TEO signal becomes high in any monitor circuit connected to that OR tree.

[0088] There may be a single, general signal collection circuit configured to collect not only TEO signals generated by monitor circuits associated with register circuits that follow logic cells belonging to a first level on the processing path, but also TEO signals generated by monitor circuits associated with register circuits that follow logic cells belonging to any other level other than the first level. However, it may be advantageous to have at least some separate detection capabilities for detecting timing events occurring in delay-critical register circuits (signal collection circuit 801) and for detecting timing events occurring in those register circuits that are preceded by only a critical number of processing paths (signal collection circuit 802). The detected timing events may be used to adapt the operation of the microelectronic circuit or its components, and such adaptation may be performed according to different adaptation rules based on the number of timing events (if any) observed per unit time in the delay-critical register circuits and the number of timing events (if any) observed per unit time in the other register circuits.

[0089] To be adaptable, a microelectronic circuit must include one or more adaptable processing paths. A processing path is an adaptable processing path if one or more of its circuit components is adaptable, such that the processing path becomes adaptively responsive to the values of the available operating parameters of the one or more circuit components.

[0090] exist Figure 8 In the example, block 803 schematically illustrates the ability of the microelectronic circuit to adapt at least a portion of its operation. This is achieved by causing the operating parameters of the microelectronic circuit to take values according to a first adaptation rule in response to the timing event observation signals collected by the first signal collection circuit 801, and according to a second adaptation rule in response to the timing event observation signals collected by the second signal collection circuit 802.

[0091] Adapting the operation of the microelectronic circuit or a portion thereof may also be accomplished in embodiments where the monitoring unit is not a register circuit equipped with a monitor, but rather, for example, a replicated path. For example, this may include causing an operating parameter of the microelectronic circuit to take on an operating parameter value according to a first adaptation rule in response to abnormal operation detected via a first group of replicated paths, and according to a second adaptation rule in response to abnormal operation detected via a second group of replicated paths.

[0092] There may be more elaborate strategies for placing register circuits or other monitoring elements and collecting TEO signals or other indications of abnormal operation. As an example, we can consider a case in which Figure 7Step 706 in the method may include placing monitor circuits based on two different threshold numbers of preceding processing paths. First, the monitor circuits may be placed on a subset of register circuits that was not classified as delay critical in step 703 but that is preceded on the processing path by at least a first threshold number of processing paths that do not have monitor circuits. The monitor circuits may be placed on another subset of register circuits that was not classified as delay critical in step 703 but that is preceded on the processing path by at least a second threshold number (different from the first number) of processing paths that are not equipped with monitor circuits. The method may include adding a first signal collection circuit to collect signals from outputs of monitor circuits placed on the register circuits of the first-mentioned subset, and adding a second signal collection circuit to collect signals from outputs of monitor circuits placed on the register circuits of the next-mentioned subset.

[0093] The more signal collection circuits there are that collect TEO signals from variously placed monitor circuits, the more diverse the possibilities for adapting the operation of the microelectronic circuit based on detected timing events. An example of adapting the operation of a microelectronic circuit is advanced (or adaptive) voltage regulation, known as AVS (Adaptive Voltage Scaling). Basically, it means that if more timing events or other indicators of abnormal operation are detected, the operating voltage of the adaptive portion of the microelectronic circuit is increased, and vice versa. If different signal collection circuits are present (such as those described above), different thresholds for the acceptable number of timing events or other indicators of abnormal operation per unit time can be used depending on where the anomaly is observed. Furthermore, the operating mode of the microelectronic circuit can have an impact: for example, if the microelectronic circuit is in standby mode, the AVS control configuration may decide not to reduce the operating voltage even if no timing events are observed in the latency-critical register circuit and very few timing events are observed in other register circuits. This is because standby mode means that very little data processing is taking place, so the detection of a low number of timing events may not alone reveal the entire situation.

[0094] Reference above Figure 1 It has been mentioned that the microelectronic circuit can be designed for testability (DFT), that is, design-for-testing. For this purpose, the microelectronic circuit can include a test input device configured to controllably feed a test input signal consisting of a test input value into at least one of the plurality of circuit components of the processing path. Figure 1 and 3In the register circuits of those in the processing path, the test input signal will be passed through the test input SI. Then, the microelectronic circuit can include a test output device configured to controllably collect test output values from the plurality of circuit components of the at least one processing path. The test output configuration will include the scan chain mentioned earlier.

[0095] A fast test can be performed on a processing path that contains register circuits with monitor circuits (such as in Figure 1 ) and register circuits without monitor circuits (such as in Figure 3 (in) both. The test input signal (i.e., a series of test input values) can be slowly clocked in, but maintaining the TTBEN signal high will disable time borrowing. Thereafter, the TTBEN signal can be set low, enabling time borrowing, and multiple clock cycles can be provided at functional logic speed. This is done to capture timing events; providing at least as many clock cycles as the step from the register circuit without a monitor on the processing path to the next register circuit equipped with a monitor on the processing path. Thus, collecting the test output signal can include collecting TEO signals that may have been triggered by timing events occurring during the clock cycles at functional logic speed.

[0096] A test output device enabling fast testing of an MCCP can be described, configured to controllably collect test output values from a processing path where an intermediate stage includes register circuitry not associated with a corresponding monitoring unit, and a subsequent stage includes register circuitry associated with a corresponding monitoring unit. In other words, fast testing of the MCCP can be performed by first clocking a test input signal slowly until the start of the MCCP. Thereafter, a clock period equal to the clock period required to propagate the test input signal through the MCCP at full functional speed is given, after which the output of the MCCP is captured as a test output value.

[0097] Another test output device for enabling rapid testing of an MCCP can be described, such that it is configured to controllably collect test output values from a processing path in which at least one intermediate stage includes a register circuit capable of time borrowing. The definition of time borrowing here is the same as that used above, namely, the ability of a circuit component to temporarily allow a digital value to change later than expected without corrupting the processed data. The register circuit capable of time borrowing thus temporarily allows a preceding logic unit in the processing path to provide its output value later in response to a trigger signal.

[0098] The concepts of DFT and adaptability can be combined. At the system level, that is, with respect to the entire microelectronic circuit, this means that test results can be used to select and set one or more new values for one or more operating parameters of the adaptable microelectronic circuit and its components. The same is true at the circuit component level, so that testing one or several circuit components can result in selecting and setting one or more new values for one or more operating parameters of the circuit component.

[0099] As an example, performing a quick test of the MCCP provides information about whether it can operate properly at the clock speed and operating voltage used during the test. If so, and particularly if the test results are within an acceptable range, the clock frequency can be increased and / or the operating voltage can be reduced. At the circuit component level, an additional example of a parameter whose value can be changed based on the test results is the length of the time window during which the timing event is detected. Adapting the length of the time window can be accomplished by varying the delay between the CP and CPD signals.

[0100] If the MCCPs of a microelectronic circuit are found and used as a basis for placing at least some monitor circuits for that microelectronic circuit, and additionally, if these MCCPs are DFTs, then these features may be used for characterization. Conceptually, characterizing a microelectronic circuit, processing path, or circuit component means identifying and quantifying its performance under different operating conditions relative to target performance. Characterized MCCPs can be used, for example, to identify: Figure 7 Whether the number and location of the monitor circuits placed in step 706 in the process are sufficient to enable the processing path to operate as expected.

[0101] Characterization can be performed, for example, in the following manner. The microelectronic circuit is placed in a test mode and a plurality of tests are performed according to the DFT method, varying the values of operating parameters such as the size (i.e., length) of the monitoring window or the amount of time borrowing required in one or more intermediate stages of one or more processing paths. In this manner, optimal values for the operating parameters can be found; optimal values are those that induce no more than an acceptable number of events in the test, while simultaneously minimizing the amount of operating power or other resources and / or maximizing performance in terms of clock speed or other measures. When the optimal values have been found, they are stored for use in the normal operating mode, and the microelectronic circuit is returned from the DFT mode to the normal operating mode.

[0102] It is obvious to a person skilled in the art having advanced technology that the basic idea of the invention can be implemented in various ways. The invention and its embodiments should therefore not be restricted to the examples described above, but they may vary within the scope of the claims.

Claims

1. A microelectronic circuit comprising: a plurality of logic cells and register circuits arranged in a plurality of processing paths, and a plurality of monitoring units associated with respective ones of the plurality of processing paths, each of the plurality of monitoring units being configured to generate an observation signal in response to abnormal operation of the respective one of the processing paths; in, Each of the plurality of logic cells belongs to one of a plurality of delay levels according to an amount of delay that may be generated, and wherein the delay levels include a first level, a second level, and a third level, wherein the first level covers logic cells that may generate the longest delay, the second level covers logic cells that may generate a shorter delay than the first level, and the third level covers logic cells that may generate a shorter delay than the second level, Its characteristics are: At least some of the plurality of processing paths include logic units belonging to the second level but without a monitoring unit, and At least some of the plurality of processing paths contain logic units belonging to the third level but having monitoring units associated with them.

2. The microelectronic circuit of claim 1 , wherein: the plurality of monitoring units comprising a plurality of monitor circuits associated with respective ones of the plurality of register circuits, each monitor circuit of the plurality of monitor circuits being configured to generate a respective timing event observation signal in response to a change in a digital value at an input of the respective register circuit, the change occurring later than an allowable time limit defined by a trigger signal of the respective register circuit; at least some of the register circuits following the logic cells belonging to the second level on the processing paths have no monitor circuits, and At least some of the monitor circuits are associated with register circuits of logic cells belonging to the third level following in the processing paths.

3. The microelectronic circuit according to claim 1 or 2, wherein: At least some of the processing paths are adaptive processing paths whose performance can be configured by causing operating parameters of the microelectronic circuit to take operating parameter values.

4. The microelectronic circuit of claim 2 , comprising: A first signal collection circuit is configured to collect at least a timing event observation signal generated by a monitor circuit associated with a register circuit subsequent to the logic unit belonging to the first level on the processing path.

5. The microelectronic circuit of claim 4, wherein: The first signal collection circuit is configured to also collect timing event observation signals generated by monitor circuits associated with register circuits following logic cells belonging to any other level than the first level on the processing path.

6. The microelectronic circuit of claim 4 , comprising: The second signal collection circuit is configured to collect a timing event observation signal generated by a monitor circuit associated with a register circuit following a logic unit belonging to at least one of the second and third levels on a processing path.

7. The microelectronic circuit of claim 6 , configured to: The first signal collection circuit collects the timing event observation signal, The second signal collection circuit collects the timing event observation signal, adapting the operation of at least a portion of the microelectronic circuit by causing an operating parameter of the microelectronic circuit to take an operating parameter value in response to a timing event observation signal collected via the first signal collection circuit according to a first adaptation rule, and Operation of at least a portion of the microelectronic circuit is adapted by causing an operating parameter of the microelectronic circuit to take an operating parameter value according to a second adaptation rule in response to the timing event observation signal collected via the second signal collection circuit.

8. The microelectronic circuit of claim 7, wherein: The first adaptation rule is based on a first number of timing event observation signals collected by the first signal collection circuit per unit time, and the second adaptation rule is based on a different second number of timing event observation signals collected by the second signal collection circuit per unit time.

9. The microelectronic circuit of claim 1 , comprising: a test input device configured to controllably feed a test input signal consisting of a test input value into a plurality of circuit elements of at least one of the processing paths, and A test output device is configured to controllably collect test output values of the plurality of circuit elements from the at least one processing path among the processing paths.

10. The microelectronic circuit of claim 2, comprising: a test input device configured to controllably feed a test input signal consisting of a test input value into a plurality of circuit elements of at least one of the processing paths, and A test output device is configured to controllably collect test output values of the plurality of circuit elements from the at least one processing path among the processing paths.

11. The microelectronic circuit of claim 3, comprising: a test input device configured to controllably feed a test input signal consisting of a test input value into a plurality of circuit elements of at least one of the processing paths, and A test output device is configured to controllably collect test output values of the plurality of circuit elements from the at least one processing path among the processing paths.

12. The microelectronic circuit of claim 11, comprising an operating parameter value selector configured to select the operating parameter value based on the collected test output values.

13. The microelectronic circuit of claim 10, wherein: The test output device is configured to selectively collect the test output values, which are obtained from at least one of the data outputs of the plurality of register circuits and the timing event observation signal outputs of the plurality of monitor circuits.

14. The microelectronic circuit according to any one of claims 9, 10 and 13, wherein: The test output device is configured to controllably collect test output values from a processing path where an intermediate stage includes a register circuit not associated with a corresponding monitoring unit and a subsequent stage includes a register circuit associated with a corresponding monitoring circuit.

15. The microelectronic circuit according to any one of claims 9, 10 and 13, wherein: The test output device is configured to controllably collect test output values from a processing path in which at least one intermediate stage includes a register circuit capable of time borrowing.

16. The microelectronic circuit according to claim 1 or 2, wherein: At least some of the monitoring units include a replica path configured to simulate operation of a corresponding one of the plurality of processing paths with known input data.

17. A method for generating a design for a microelectronic circuit, comprising: a) providing a preliminary first design of the microelectronic circuit, the first design defining processing paths through logic cells and register circuits within the microelectronic circuit, b) performing a delay distribution analysis on the first design to classify the logic cells into delay classes according to the amount of delay that may be generated, c) classifying a first subset of the logic cells as delay critical logic cells based on the occurrence of one or more longest delay levels in the delay distribution analysis, d) generating an intermediate second design of the microelectronic circuit by associating a monitoring cell with a processing path containing the delay critical logic cell, e) generating a further third design of the microelectronic circuit by associating monitoring cells with processing paths that include logic cells that were not classified as delay critical logic cells in step c) and that contain at least a threshold number of processing paths without associated monitoring cells, and f) outputting the third design as said design of the microelectronic circuit.

18. The method of claim 17, wherein: The threshold number of processing paths is defined as the number of register circuits without associated monitoring units, through which the corresponding processing path passes.

19. The method according to claim 17 or 18, wherein The threshold number of processing paths is defined as the total delay that circuit components along the corresponding processing path may incur based on the delay profile analysis.

20. The method of claim 17 or 18, wherein: Step d) comprises placing a monitor circuit in a register circuit that occurs after the delay-critical logic unit on the processing path, and Step e) comprises placing a monitor circuit to a register circuit that appears on the processing path after a logic cell that was not classified as a delay critical logic cell in step c), but that is preceded on the processing path by at least a threshold number of processing paths that are not equipped with a monitor register circuit.

21. The method of claim 20, wherein: Step e) comprises adding one or more signal collection circuits to collect signals from the monitor circuit, the monitor circuit being placed to a register circuit that appears on the processing path after the logic cells that were not classified as delay critical logic cells in step c).

22. The method of claim 17 or 18, wherein: Step e) comprises: e1) associating the monitoring unit with a processing path comprising a second subset of logic units that were not classified as delay-critical logic units in step c) and containing at least a first threshold number of processing paths that do not have associated monitoring units, and e2) associating monitoring units with processing paths that include a third subset of logic cells that were not classified as delay critical logic cells in step c) and that contain at least a second threshold number of processing paths that do not have associated monitoring units, different from the first threshold number.

23. The method of claim 20, wherein: Step e) comprises: e1) associating the monitoring unit with a processing path comprising a second subset of logic units that were not classified as delay-critical logic units in step c) and containing at least a first threshold number of processing paths that do not have associated monitoring units, and e2) associating monitoring units with processing paths that include a third subset of logic cells that were not classified as delay critical logic cells in step c) and that contain at least a second threshold number of processing paths that do not have associated monitoring units, different from the first threshold number.

24. The method of claim 23, wherein: Associating the monitoring unit with the processing path comprises placing a monitor circuit to a register circuit on that processing path, and step e) additionally comprises: e3) adding a first signal collection circuit to collect a signal from an output terminal of a monitor circuit placed to a register circuit next to the logic unit of the second subset, and e4) Adding a second signal collection circuit to collect signals from the output terminals of the monitor circuits placed to the register circuits next to the logic cells of the third subset.

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