Leakage Compensation for Memory Array

Abstract

This application is directed to leakage compensation for a memory array. For example, leakage current can be introduced from unselected memory cells onto a digital line. In some cases, a compensation component can be coupled to the digital line during a first stage of a read operation before the target memory cell has been coupled to the digital line. The compensation component can sample the current on the digital line and store a representation of the sampled current. During a second stage of the read operation, the target memory cell can be coupled to the digital line. During the second stage, the compensation component can compensate for leakage or other parasitic effects by outputting the current on the digital line based on the stored representation of the sampled current during the read operation.

Description

[0001] Cross-reference

[0002] This patent application claims priority to PCT Application No. PCT / US2019 / 063395, titled "Leakage Compensation for Memory Arrays," filed on November 26, 2019, by Vimercati et al., which claims priority to U.S. Patent Application No. 16 / 216,057, titled "Leakage Compensation for Memory Arrays," filed on December 11, 2018, by Vimercati, both of which are assigned to the assignee hereof and are hereby incorporated by reference in their entireties.

[0003] The technical field relates to leakage compensation for memory arrays. Background Art

[0004] The following generally relates to systems including at least one memory device and, more particularly, to leakage compensation for memory arrays.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, binary devices most often store one of two states, often represented by logic 1 or logic 0. In other devices, more than two states may be stored. To access the stored information, components of the device may read or sense at least one of the stored states in the memory device. To access information, components of the device may write or program the states in the memory device.

[0006] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), etc. Memory devices can be volatile or non-volatile. For example, non-volatile memories such as flash memory, MRAM, and FeRAM can maintain the stored logical state for a long time even in the absence of an external power source. Volatile memory devices such as DRAM and SRAM may lose their stored states when disconnected from an external power source. Dynamic memory devices such as DRAM and SDRAM can store charge on a capacitor or other passive storage element and will lose the stored state over time unless periodically refreshed. FeRAM can use a device architecture similar to that of volatile memory but can have non-volatile characteristics due to the use of ferroelectric capacitors as storage devices. FeRAM devices can thus provide some of the density advantages of dynamic or volatile memory while retaining the benefits of non-volatile memory.

[0007] In some cases, the digital line used to read the state of a memory cell can experience noise from various sources (e.g., parasitic effects). Such noise can include leakage current through unselected memory cells on the digital line or from other sources and can reduce the accuracy of the read operation. Specifically, noise such as leakage current can pose a challenge to increasing the memory density of FeRAM devices. Summary of the Invention

[0008] Disclosed is a method. The method may involve storing a representation of the leakage current of a digital line during a first stage of a read operation of a target memory cell. The method may involve coupling the target memory cell to the digital line during a second stage of the read operation. The method may involve outputting a current on the digital line based on the representation of the leakage current during the second stage of the read operation. The method may involve determining the logical state stored in the target memory cell based on a signal on the digital line during the second stage of the read operation.

[0009] Describe a device. The device may include a digital line; a plurality of memory cells configured to selectively couple to the digital line; a compensation component coupled to the digital line, the compensation component including: a storage component configured to store a representation of a leakage current on the digital line before coupling a target memory cell of the plurality of memory cells to the digital line during a read operation, and a driver configured to output a current to the digital line during the read operation based at least in part on the representation of the leakage current; and a sensing component coupled to the digital line and configured to determine a logical state stored in the target memory cell based on a signal on the digital line after the target memory cell is coupled to the digital line.

[0010] Describe a device. The device may include a plurality of memory cells configured to selectively couple to an access line; a compensation component configured to output a current on the access line; a sensing component coupled to the access line; and a controller configured to cause the device to: couple an input node of the compensation component to the access line during a first stage of a read operation of a target memory cell of the plurality of memory cells, the compensation component being configured to adjust the current to compensate for a leakage current on the access line; decouple the input node from the access line before a second stage of the read operation, the compensation component storing a representation of the compensated leakage current; couple the target memory cell to the access line during the second stage of the read operation; and enable the sensing component to sense a logical state stored in the target memory cell based on a signal on the access line during the second stage of the read operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 Illustrate examples of systems that support leakage compensation for memory arrays as disclosed herein.

[0012] Figure 2 Illustrate examples of memory dies that support leakage compensation for memory arrays as disclosed herein.

[0013] Figure 3A and 3B Illustrate an example hysteresis curve of a ferroelectric memory cell that supports leakage compensation for memory arrays as disclosed herein.

[0014] Figure 4 Illustrate example circuits that support leakage compensation for memory arrays as disclosed herein.

[0015] Figure 5 Illustrate example circuits that support leakage compensation for memory arrays as disclosed herein.

[0016] Figure 6 Illustrate an example timing diagram that supports leakage compensation for a memory array as disclosed herein.

[0017] Figure 7 Show a block diagram of a device that supports leakage compensation for a memory array as disclosed herein.

[0018] Figure 8 Show a flowchart that illustrates one or more methods that support leakage compensation for a memory array as disclosed herein. Detailed Description

[0019] A memory device may include a plurality of memory cells that are selectively coupled to digital lines. Each memory cell may include a cell selector component that may be activated during a read operation to select the memory cell and couple the memory cell to the digital line. The selected memory cell may transfer charge to (or from) the digital line, thereby causing a signal to be formed on the digital line. The signal may represent the logical state stored in the selected memory cell and may be available to a sensing component to determine the logical state of the selected memory cell during a read operation.

[0020] In some cases, a read operation may include one or more phases. For example, a read operation may include a first phase and a second phase. During the first phase, the digital line may be precharged to a specific voltage before the target memory cell is coupled to the digital line. During the second phase, the target memory cell is coupled to the digital line and a signal from the target memory cell is formed on the digital line. The sensing component may determine the logical state of the memory cell during or after the second phase.

[0021] In some cases, noise (e.g., parasitic or other unwanted charge, current, voltage, or other effects) may be present on the digital line during the first and second phases of a read operation. Such noise may originate from various sources, including leakage current through the cell selector components of unselected memory cells. In some cases, such noise may reduce the accuracy of the read operation by distorting the signal on the digital line.

[0022] According to various examples described herein, a memory device may include a compensation component that compensates for noise (e.g., leakage current) on the digital line. For simplicity, the term "leakage current" as used herein may refer to leakage current associated with unselected memory cells, leakage current from other components, or unwanted current from various other noise sources.

[0023] In some cases, a compensation component may sample a leakage current on a digitalline and store a representation of the leakage current during a first phase of a read operation (e.g., before a target memory cell is coupled to the digitalline). The compensation component may store the representation of the leakage current as a voltage or otherwise on a capacitor, for example. In some cases, the compensation component may compensate for the leakage current during a second phase (e.g., after the target memory cell is coupled to the digitalline) by removing some or all of the leakage current from the digitalline based on the stored representation of the leakage current. Thus, the compensation component may adjust its output current based on the stored representation of the leakage current.

[0024] In some cases, the compensation component may remove the leakage current by absorbing (or supplying, depending on the polarity of the circuit) a current that is substantially equivalent to the leakage current based on the stored representation of the leakage current. For example, the compensation component may include a transconductance circuit, whose input node may be coupled to the node of the capacitor that stores the representation of the leakage current, thereby providing the representation of the leakage current as an input to the transconductance circuit. The output node of the transconductance circuit may be coupled to the digitalline. Such an arrangement may cause the transconductance circuit to absorb (or supply) the noise current on the digitalline during a second part of the read operation, thereby providing leakage compensation. Other embodiments of the compensation component may be used; for example, a sample-and-hold circuit or a current mirror circuit may be used to provide similar functionality.

[0025] The leakage compensation method described herein may improve the reliability or speed of a read operation by reducing or eliminating the effects of leakage current or other noise on the digitalline during the read operation.

[0026] At first in reference Figure 1 -3 describes the features of the present disclosure in the context of the operation of a memory system and related components. The features of the present disclosure are further described in the context of a memory die that includes multiple memory cells, which may include ferroelectric memory cells as described in reference Figures 4-6 described. These and other features of the present disclosure are further illustrated and described by reference to timing diagrams, device diagrams, system diagrams, and flowcharts related to leakage compensation for a memory array as described in reference Figures 7-8 described.

[0027] Figure 1 An example of a system 100 that may include one or more memory devices as disclosed herein is illustrated. The system 100 may include an external memory controller 105, a memory device 110, and a plurality of channels 115 that couple the external memory controller 105 to the memory device 110. The system 100 may include one or more memory devices, but for ease of description, the one or more memory devices may be described as a single memory device 110.

[0028] System 100 may include features of an electronic device, such as a computing device, a mobile computing device, a wireless device, or a graphics processing device. System 100 may be an example of a portable electronic device. System 100 may be an example of a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, and so on. Memory device 110 may be a component of a system configured to store data for one or more other components of System 100. In some instances, System 100 is configured to perform two-way wireless communication with other systems or devices using a base station or an access point. In some instances, System 100 is capable of machine type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication.

[0029] At least a portion of System 100 may be an example of a host device. Such a host device may be an example of a device that uses memory to execute processes, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, some other fixed or portable electronic device, and so on. In certain cases, the host device may refer to hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 105. In certain cases, external memory controller 105 may be referred to as the host or the host device.

[0030] In some cases, memory device 110 may be an independent device or component configured to communicate with other components of System 100 and provide physical memory addresses / spaces that are available for System 100 to use or reference. In some instances, memory device 110 may be configured to cooperate with at least one or more different types of System 100. Messaging between the components of System 100 and memory device 110 may be used to support modulation schemes for modulating signals, different pin designs for transmitting signals, different packages for System 100 and memory device 110, clock messaging and synchronization between System 100 and memory device 110, timing conventions, and / or other factors.

[0031] The memory device 110 may be configured to store data for components of the system 100. In some cases, the memory device 110 may act as a slave device of the system 100 (e.g., respond to and execute commands provided by the system 100 via an external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. The memory device 110 may include two or more memory dies 160 (e.g., memory chips) that support a desired or specified capacity for data storage. A memory device 110 that includes two or more memory dies may be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package).

[0032] The system 100 may further include a processor 120, a basic input / output system (BIOS) component 125, one or more peripheral components 130, and an input / output (I / O) controller 135. The components of the system 100 may communicate with each other electronically using a bus 140.

[0033] The processor 120 may be configured to control at least a portion of the system 100. The processor 120 may be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or it may be a combination of these types of components. In such cases, the processor 120 may be an instance of a central processing unit (CPU), a graphics processing unit (GPU), or a system on a chip (SoC), among other instances.

[0034] The BIOS component 125 may be a software component that includes the BIOS operating as firmware, which may initialize and run various hardware components of the system 100. The BIOS component 125 may also manage the data flow between the processor 120 and various components of the system 100, such as the peripheral components 130, the I / O controller 135, etc. The BIOS component 125 may include a program or software stored in a read-only memory (ROM), flash memory, or any other non-volatile memory.

[0035] The peripheral components 130 may be any input device or output device, or an interface for such devices, which may be integrated into the system 100 or integrated with the system 100. Examples may include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a universal serial bus (USB) controller, a serial or parallel port, or a peripheral card slot, such as a peripheral component interconnect (PCI) or accelerated graphics port (AGP) slot. The peripheral components 130 may be other components understood by those skilled in the art as peripheral devices.

[0036] The I / O controller 135 can manage data communication between the processor 120 and the peripheral components 130, the input device 145, or the output device 150. The I / O controller 135 can manage peripheral devices that are not integrated into or not integrated with the system 100. In some cases, the I / O controller 135 can represent a physical connection or port to external peripheral components.

[0037] The input 145 can represent a device or signal external to the system 100 that provides information, signals, or data to the system 100 or its components. This can include a user interface or an interface with or between other devices. In some cases, the input 145 can be a peripheral device interfaced with the system 100 via one or more peripheral components 130, or can be managed by the I / O controller 135.

[0038] The output 150 can represent a device or signal external to the system 100 that is configured to receive output from the system 100 or any of its components. Examples of the output 150 can include a display, an audio speaker, a printing device, or another processor on a printed circuit board, etc. In some cases, the output 150 can be a peripheral device interfaced with the system 100 via one or more peripheral components 130, or can be managed by the I / O controller 135.

[0039] The components of the system 100 can be composed of general-purpose or special-purpose circuits designed to perform their functions. This can include various circuit elements configured to perform the functions described herein, such as wires, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements.

[0040] The memory device 110 can include a device memory controller 155 and one or more memory dies 160. Each memory die 160 can include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). The memory array 170 can be a collection (e.g., a grid) of memory cells, where each memory cell is configured to store at least one bit of digital data. Refer to Figure 2 The characteristics of the memory array 170 and / or the memory cells are described in more detail.

[0041] Memory device 110 may be an instance of a two-dimensional (2D) memory cell array or may be an instance of a three-dimensional (3D) memory cell array. For example, a 2D memory device may include a single memory die 160. A 3D memory device may include two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and / or any number of memory dies 160-N). In a 3D memory device, multiple memory dies 160-N may be stacked on top of each other. In some cases, the memory dies 160-N in a 3D memory device may be referred to as a stack, tier, layer, or die. A 3D memory device may include any number of stacked memory dies 160-N (e.g., a two-high stack of memory dies, a three-high stack of memory dies, a four-high stack of memory dies, a five-high stack of memory dies, a six-high stack of memory dies, a seven-high stack of memory dies, an eight-high stack of memory dies). This may increase the number of memory cells that can be positioned on a substrate compared to a single 2D memory device, which in turn may reduce production costs or increase the performance of the memory array, or both. In some 3D memory devices, different stacks may share at least one common access line such that some stacks may share at least one of word lines, digit lines, and / or plate lines.

[0042] Device memory controller 155 may include circuitry or components configured to control the operation of memory device 110. Thus, device memory controller 155 may include hardware, firmware, and software that enable memory device 110 to execute commands and may be configured to receive, transmit, or execute commands, data, or control information regarding memory device 110. Device memory controller 155 may be configured to communicate with external memory controller 105, one or more memory dies 160, or processor 120. In some cases, memory device 110 may receive data and / or commands from external memory controller 105. For example, memory device 110 may receive a write command indicating that memory device 110 is to store certain data on behalf of a component of system 100 (e.g., processor 120), or receive a read command indicating that memory device 110 is to provide certain data stored in memory die 160 to a component of system 100 (e.g., processor 120). In some cases, device memory controller 155 may control the operation of memory device 110 described herein in conjunction with local memory controller 165 of memory die 160. Examples of components included in device memory controller 155 and / or local memory controller 165 may include a receiver for demodulating signals received from external memory controller 105, a decoder for modulating and transmitting signals to external memory controller 105, logic, decoders, amplifiers, filters, etc.

[0043] The local memory controller 165 (e.g., local to the memory die 160) may be configured to control the operation of the memory die 160. Moreover, the local memory controller 165 may be configured to communicate (e.g., receive and transfer data and / or commands) with the device memory controller 155. The local memory controller 165 may support the device memory controller 155 to control the operation of the memory device 110 as described herein. In some cases, the memory device 110 does not include the device memory controller 155, and the local memory controller 165 or the external memory controller 105 may perform the various functions described herein. Thus, the local memory controller 165 may be configured to communicate with the device memory controller 155, communicate with other local memory controllers 165, or communicate directly with the external memory controller 105 or the processor 120.

[0044] The external memory controller 105 may be configured to effect the transfer of information, data, and / or commands between components of the system 100 (e.g., the processor 120) and the memory device 110. The external memory controller 105 may act as a liaison between the components of the system 100 and the memory device 110 such that the components of the system 100 may not need to know the operational details of the memory device. The components of the system 100 may present requests (e.g., read commands or write commands) to the external memory controller 105 that the external memory controller 105 satisfies. The external memory controller 105 may translate or transpose the communications exchanged between the components of the system 100 and the memory device 110. In some cases, the external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, the external memory controller 105 may include a common data clock that generates a common (source) data clock signal.

[0045] In some cases, the external memory controller 105 or other components of the system 100 or their functions described herein may be implemented by the processor 120. For example, the external memory controller 105 may be hardware, firmware, software, or some combination thereof implemented by the processor 120 or other components of the system 100. Although the external memory controller 105 is depicted as being external to the memory device 110, in some cases, the external memory controller 105 or its functions described herein may be implemented by the memory device 110. For example, the external memory controller 105 may be hardware, firmware, software, or some combination thereof implemented by the device memory controller 155 or one or more local memory controllers 165. In some cases, the external memory controller 105 may be distributed across the processor 120 and the memory device 110 such that portions of the external memory controller 105 are implemented by the processor 120 and other portions are implemented by the device memory controller 155 or the local memory controller 165. Similarly, in some cases, one or more functions attributed to the device memory controller 155 or the local memory controller 165 herein may in some cases be performed by the external memory controller 105 (separate from or included in the processor 120).

[0046] The components of the system 100 may exchange information with the memory device 110 using multiple channels 115. In some instances, the channels 115 may enable communication between the external memory controller 105 and the memory device 110. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with the components of the system 100. For example, the channel 115 may include a first terminal that includes one or more pins or pads at the external memory controller 105 and one or more pins or pads at the memory device 110. Pins may be examples of conductive input or output points of the devices of the system 100, and the pins may be configured to act as part of the channel. In some cases, the pins or pads of the terminals may be part of the signal path of the channel 115. Additional signal paths may be coupled to the terminals of the channel for routing signals within the components of the system 100. For example, the memory device 110 may include signal paths (e.g., signal paths internal to the memory device 110 or its components, such as within the memory die 160) that route signals from the terminals of the channel 115 to the various components of the memory device 110 (e.g., the device memory controller 155, the memory die 160, the local memory controller 165, the memory array 170).

[0047] Channel 115 (and associated signal paths and terminals) can be dedicated to transmitting a specific type of information. In some cases, channel 115 can be an aggregated channel and can thus contain multiple individual channels. For example, data channel 190 can be x4 (e.g., containing four signal paths), x8 (e.g., containing eight signal paths), x16 (containing sixteen signal paths), and so on.

[0048] In some cases, channel 115 can include one or more command and address (CA) channels 186. CA channel 186 can be configured to transmit commands between external memory controller 105 and memory device 110, including control information (e.g., address information) associated with the commands. For example, CA channel 186 can include a read command regarding the address of the desired data. In some cases, CA channel 186 can be latched on the rising clock signal edge and / or the falling clock signal edge. In some cases, CA channel 186 can include eight or nine signal paths.

[0049] In some cases, channel 115 can include one or more clock signal (CK) channels 188. CK channel 188 can be configured to transmit one or more common clock signals between external memory controller 105 and memory device 110. Each clock signal can be configured to oscillate between a high state and a low state and coordinate the actions of external memory controller 105 and memory device 110. In some cases, the clock signal can be a differential output (e.g., CK_t signal and CK_c signal) and the signal paths of CK channel 188 can be configured accordingly. In some cases, the clock signal can be single-ended. In some cases, the clock signal can be a 1.5 GHz signal. CK channel 188 can include any number of signal paths. In some cases, clock signal CK (e.g., CK_t signal and CK_c signal) can provide a timing reference for command and addressing operations of memory device 110 or other system-wide operations of memory device 110. Clock signal CK can thus be alternatively referred to as control clock signal CK, command clock signal CK, or system clock signal CK. System clock signal CK can be generated by a system clock, which can include one or more hardware components (e.g., oscillators, crystals, logic gates, transistors, etc.).

[0050] In some cases, channel 115 can include one or more data (DQ) channels 190. Data channel 190 can be configured to transmit data and / or control information between external memory controller 105 and memory device 110. For example, data channel 190 can transmit information (e.g., bidirectional) to be written to memory device 110 or information read from memory device 110. Data channel 190 can transmit signals that can be modulated using a variety of different modulation schemes (e.g., NRZ, PAM4).

[0051] In some cases, the channel 115 may include one or more other channels 192 that may be dedicated to other purposes. These other channels 192 may include any number of signal paths.

[0052] The channel 115 may couple the external memory controller 105 to the memory device 110 using a variety of different architectures. Examples of various architectures may include buses, point-to-point connections, crossbar switches, high-density interposers such as silicon interposers, or channels formed in organic substrates, or some combination thereof. For example, in some cases, the signal path may at least partially include a high-density interposer, such as a silicon interposer or a glass interposer.

[0053] A variety of different modulation schemes may be used to modulate the signals transmitted over the channel 115. In some cases, a binary symbol (or binary level) modulation scheme may be used to modulate the signals communicated between the external memory controller 105 and the memory device 110. The binary symbol modulation scheme may be an example of an M-ary modulation scheme, where M is equal to two. Each symbol of the binary symbol modulation scheme may be configured to represent one bit of digital data (e.g., the symbol may represent a logic 1 or a logic 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return-to-zero (NRZ), unipolar coding, bipolar coding, Manchester coding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), etc.

[0054] In some cases, a multi-symbol (or multi-level) modulation scheme may be used to modulate the signals transmitted between the external memory controller 105 and the memory device 110. The multi-symbol modulation scheme may be an example of an M-ary modulation scheme, where M is greater than or equal to three. Each symbol of the multi-symbol modulation scheme may be configured to represent more than one bit of digital data (e.g., the symbol may represent logic 00, logic 01, logic 10, or logic 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM4, PAM8, etc., quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), etc. A multi-symbol signal or a PAM4 signal may be a signal modulated using a modulation scheme that includes at least three levels to encode more than one bit of information. The multi-symbol modulation scheme and symbols may alternatively be referred to as non-binary, multi-bit, or high-order modulation schemes and symbols.

[0055] In some cases, system 100 or memory device 110 may be configured to store a representation of the leakage current of a digit line during a first stage of a read operation of a target memory cell. The system or memory device may be configured to couple the target memory cell to the digit line during a second stage of the read operation and, during the second stage of the read operation, output a current on the digit line based at least in part on the representation of the leakage current. The system or memory device may be configured to determine, during the second stage of the read operation, the logical state stored in the target memory cell based at least in part on the signal on the digit line.

[0056] Figure 2 An example of a memory device 200 in accordance with various examples of the present disclosure is illustrated. Memory die 200 may be an example of memory die 160 described with reference to Figure 1 In some cases, memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. Memory die 200 may include one or more memory cells 205 that are programmable to store different logical states. Each memory cell 205 may be programmable to store two or more states. For example, a memory cell 205 may be configured to store digital logic of one bit at a time (e.g., logic 0 and logic 1). In some cases, a single memory cell 205 (e.g., a multi-level memory cell) may be configured to store digital logic of more than one bit at a time (e.g., logic 00, logic 01, logic 10, or logic 11).

[0057] Memory cell 205 may store a state (e.g., a polarization state or a dielectric charge) representing digital data. In a FeRAM architecture, memory cell 205 may include a capacitor that includes a ferroelectric material to store a charge and / or polarization representing a programmable state. In a DRAM architecture, memory cell 205 may include a capacitor that includes a dielectric material to store a charge representing a programmable state.

[0058] Operations such as read and write may be performed on memory cell 205 by activating or selecting access lines such as word line 210, digit line 215, and / or plate line 220. In some cases, digit line 215 may also be referred to as a bit line. References to access lines, word lines, digit lines, plate lines, or the like may be interchangeable without affecting understanding or operation. Activating or selecting word line 210, digit line 215, or plate line 220 may include applying a voltage to the corresponding line.

[0059] Memory die 200 may include access lines (e.g., word lines 210, digit lines 215, and plate lines 220) arranged in a grid pattern. Memory cells 205 may be located at the intersections of word lines 210, digit lines 215, and / or plate lines 220. By biasing the word lines 210, digit lines 215, and / or plate lines 220 (e.g., applying a voltage to the word lines 210, digit lines 215, and / or plate lines 220), a single memory cell 205 may be accessed at their intersection.

[0060] Access to the memory cells 205 may be controlled by a row decoder 225, a column decoder 230, and a plate driver 235. For example, the row decoder 225 may receive a row address from a local memory controller 265 and activate the word lines 210 based on the received row address. The column decoder 230 receives a column address from the local memory controller 265 and activates the digit lines 215 based on the received column address. The plate driver 235 may receive a plate address from the local memory controller 265 and activate the plate lines 220 based on the received plate address. For example, memory die 200 may include a plurality of word lines 210 labeled WL_1 to WL_M, a plurality of digit lines 215 labeled DL_1 to DL_N, and a plurality of plate lines labeled PL_1 to PL_P, where M, N, and P depend on the size of the memory array. Thus, by activating the word lines 210, digit lines 215, and plate lines 220 (e.g., WL_1, DL_3, and PL_1), the memory cell 205 may be accessed at their intersection. The intersection of the word lines 210 and digit lines 215 in a two-dimensional or three-dimensional configuration may be referred to as the address of the memory cell 205. In some cases, the intersection of the word lines 210, digit lines 215, and plate lines 220 may be referred to as the address of the memory cell 205.

[0061] Memory cell 205 may include a logic storage component, such as a capacitor 240, and a cell selector component 245. Capacitor 240 may be an example of a ferroelectric capacitor. A first node of capacitor 240 may be coupled to cell selector component 245 and a second node of capacitor 240 may be coupled to plate line 220. Cell selector component 245 may be a device that selectively couples or decouples memory cell 205 from digit line 215. In some cases, cell selector component 245 may be a p-type transistor or an n-type transistor. In some cases, cell selector component 245 may be a thin film transistor (TFT). In some cases, for example, the TFT transistor may include a transistor formed in an epitaxial layer or a transistor formed using silicon-on-insulator technology.

[0062] Selecting or deselecting the memory cell 205 can be achieved by activating or deactivating the cell selector component 245. The capacitor 240 can be in electronic communication with the digit line 215 using the cell selector component 245. For example, when the cell selector component 245 is deactivated, the capacitor 240 can be isolated from the digit line 215, and when the cell selector component 245 is activated, the capacitor 240 can be coupled to the digit line 215. In some cases, the cell selector component 245 can be a switching component such as a transistor, and its operation is controlled by applying a voltage to the transistor gate, where the voltage differential between the transistor gate and the transistor source is greater than or less than the threshold voltage of the transistor. As described herein, in some cases, when the cell selector component 245 is deactivated, the cell selector component 245 can experience a leakage current. The leakage current can contribute to noise on the digit line 215.

[0063] The word line 210 can be a conductive wire in electronic communication with the memory cell 205 for performing access operations on the memory cell 205. In some architectures, the word line 210 can be in electronic communication with the cell selector component 245 of the memory cell 205 and can be configured to control the cell selector component 245 of the memory cell. The word line 210 can activate / deactivate the cell selector component 245 based on the voltage applied to the word line 210. In some cases, for example, the word line 210 can be coupled to the gate of the transistor of the cell selector component 245. Each word line 210 can activate multiple cell selector components 245 for a certain number of columns.

[0064] The digit line 215 can be a conductive wire connecting the memory cell 205 to the sensing component 250. In some architectures, the memory cell 205 can be selectively coupled to the digit line 215 during portions of an access operation (e.g., a read operation or a write operation). For example, the word line 210 and the cell selector component 245 of the memory cell 205 can be configured to selectively couple and / or isolate the capacitor 240 of the memory cell 205 from the digit line 215.

[0065] In some cases, when the memory cell 205 is not selected (e.g., when the cell selector component 245 is not activated), the cell selector component 245 may permit leakage current to flow through the cell selector component 245 onto the digit line 215. For example, if the cell selector component 245 is a transistor, the leakage current across the cell selector component 245 may include leakage current from the drain to the source (or from the source to the drain) through the channel of the transistor (e.g., off-state current), and / or leakage current from the gate to the drain or source. Such leakage current may constitute a relatively small amount of current for each memory cell 205, but the sum of the leakage currents of multiple memory cells 205 coupled to the digit line 215 may cause the sum of the leakage current flowing onto the digit line 215 to be sufficient to distort or corrupt the signal on the digit line and reduce the accuracy of the read operation of the memory cells 205 associated with the digit line 215. For example, TFTs and other types of switching components (including cell selector components) fabricated with relatively small feature sizes and operating at relatively low voltages may be particularly prone to experiencing leakage current.

[0066] According to various examples, the memory die 200 or another portion of the memory device may include a compensation component 270, which may compensate for the leakage current through the cell selector component 245 during a read operation of the memory cell 205, as described in more detail with respect to Figure 4 More detailed description.

[0067] The plate line 220 may be a wire in electronic communication with the memory cell 205 and is used to perform access operations on the memory cell 205. The plate line 220 may be in electronic communication with a node (e.g., the bottom of the cell) of the capacitor 240. The plate line 220 is configured to cooperate with the digit line 215 to bias the capacitor 240 during an access operation of the memory cell 205.

[0068] The sensing component 250 can be configured to detect a state (e.g., polarization state or charge) stored on the capacitor 240 of the memory cell 205 and determine the logical state of the memory cell 205 based on the detected state. In some cases, the charge stored by the memory cell 205 may be extremely small. Thus, the sensing component 250 can include one or more sense amplifiers to amplify the signal output of the memory cell 205, and the signal output can be a charge signal, a current signal, or a voltage signal. For example, the sense amplifier can detect a subtle change in the charge of the digit line 215 during a read operation and can generate a signal corresponding to a logic 0 or a logic 1 based on the detected charge. The sensing component 250 can be configured to compare the signal on the digit line 215 or the generated signal with a reference signal 255 (e.g., a reference voltage). The sensing component 250 can determine the storage state of the memory cell 205 based on the comparison. For example, for a memory cell capable of storing one of two states, if the digit line 215 or the corresponding signal generated by the sense amplifier has a voltage higher than the reference signal 255, then the sensing component 250 can determine that the stored state of the memory cell 205 is a logic 1, and if the digit line 215 or the corresponding signal generated by the sense amplifier has a voltage lower than the reference signal 255, then the sensing component 250 can determine that the stored state of the memory cell 205 is a logic 0.

[0069] The sensing component 250 can include various transistors or amplifiers to detect and amplify a signal difference (e.g., the difference between a signal from the memory cell and the reference signal). However, if there is noise (e.g., from leakage current or other sources) on the digit line 215 during a read operation, then the sensing component 250 may not be able to accurately determine the state stored on the memory cell. According to various examples, the memory device can include a compensation component 270 to compensate for the noise on the digit line 215 and provide a cleaner signal to the sensing component 250.

[0070] The detected logical state of the memory cell 205 can be output as an output 260 through the column decoder 230. In some cases, the sensing component 250 can be part of another component (e.g., the column decoder 230, the row decoder 225). In certain cases, the sensing component 250 can communicate electronically with the row decoder 225, the column decoder 230, and / or the board driver 235.

[0071] The local memory controller 265 can control the operation of the memory cell 205 through various components (e.g., the row decoder 225, the column decoder 230, the board driver 235, and the sensing component 250). The local memory controller 265 can be a reference Figure 1An example of the local memory controller 165 described. In some cases, one or more of the row decoder 225, column decoder 230, board driver 235, and sense component 250 may be in the same location as the local memory controller 265. The local memory controller 265 may be configured to receive one or more commands and / or data from the external memory controller 105 (or the device memory controller 155 as described in reference Figure 1 ), translate the commands and / or data into information usable by the memory die 200, perform one or more operations on the memory die 200, and communicate data from the memory die 200 to the external memory controller 105 (or the device memory controller 155) in response to performing the one or more operations. The local memory controller 265 may generate row, column, and / or board line address signals to activate the target word line 210, target digit line 215, and target board line 220. The local memory controller 265 may also generate and control the various voltages or currents used during the operation of the memory die 200. In general, the magnitude, shape, or duration of the applied voltage or current discussed herein may be adjusted or varied and may be different for the various operations discussed in operating the memory system 200.

[0072] In some cases, the local memory controller 265 may be configured to perform a precharge operation on the memory die 200. The precharge operation may include precharging one or more components and / or access lines of the memory die 200 to one or more predetermined voltage levels. In some cases, the memory cells 205 and / or portions of the memory die 200 may be precharged between different access operations. In some cases, the digit lines 215 and / or other components may be precharged prior to a read operation.

[0073] In some cases, as described herein, the digit lines 215 may be precharged using a compensation component 270 configured to compensate for leakage current on the digit lines 215. In some cases, the compensation component 270 may be used to precharge the digit lines 215 to a target voltage before coupling the memory cells 205 to the digit lines 215. In some cases, the digit lines 215 may initially be precharged to a first voltage using a voltage source, for example, that provides the target voltage and is coupled to the digit lines 215 via a switch, and once the switch disconnects the voltage source from the digit lines 215, the compensation component 270 may be used to complete the operation of precharging the digit lines 215 to the target voltage (e.g., compensating for leakage current).

[0074] In some cases, the local memory controller 265 may be configured to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During the write operation, the memory cells 205 of the memory die 200 may be programmed to store the desired logical state. In some cases, multiple memory cells 205 may be programmed during a single write operation. The local memory controller 265 may identify the target memory cells 205 on which the write operation is to be performed. The local memory controller 265 may identify the target word line 210, the target digit line 215, and / or the target plate line 220 that are in electronic communication with the target memory cells 205 (e.g., the address of the target memory cells 205). The local memory controller 265 may activate the target word line 210, the target digit line 215, and / or the target plate line 220 (e.g., apply a voltage to the word line 210, the digit line 215, or the plate line 220) to access the target memory cells 205. The local memory controller 265 may apply a specific signal (e.g., a voltage) to the digit line 215 and a specific signal (e.g., a voltage) to the plate line 220 during the write operation to store a specific state in the capacitor 240 of the memory cell 205, the specific state indicating the desired logical state.

[0075] In some cases, the local memory controller 265 may be configured to perform a read operation (e.g., a sensing operation) on one or more memory cells 205 of the memory die 200. During the read operation, the logical state stored in the memory cells 205 of the memory die 200 may be determined. In some cases, multiple memory cells 205 may be sensed during a single read operation. The local memory controller 265 may identify the target memory cells 205 on which the read operation is to be performed. The local memory controller 265 may identify the target word line 210, the target digit line 215, and / or the target plate line 220 that are in electronic communication with the target memory cells 205 (e.g., the address of the target memory cells 205). The local memory controller 265 may activate the target word line 210, the target digit line 215, and / or the target plate line 220 (e.g., apply a voltage to the word line 210, the digit line 215, or the plate line 220) to access the target memory cells 205. The target memory cells 205 may transfer a signal to the sensing component 250 in response to the biased access lines. The sensing component 250 may amplify the signal. The local memory controller 265 may activate the sensing component 250 (e.g., latch the sensing component) and thereby compare the signal received from the memory cell 205 with a reference signal 255. Based on the comparison, the sensing component 250 may determine the logical state stored on the memory cell 205. As part of the read operation, the local memory controller 265 may transfer the logical state stored on the memory cell 205 to the external memory controller 105 (or the device memory controller).

[0076] In some cases, the local memory controller 265, the device memory controller, or the external memory controller may cause the compensation component 270 to store a representation of the leakage current on the sense digit line 215 during a read operation and to compensate for the leakage current by outputting the leakage current on the sense digit line 215 during the read operation.

[0077] Figure 3A and 3B Illustrate example hysteresis curves 300-a and 300-b depicting the non-linear electrical properties of memory cells 205 that support leakage compensation for a memory array as disclosed herein. The hysteresis curves 300-a and 300-b may illustrate example write and read processes for memory cells 205 utilizing ferroelectric capacitors 240 as described with reference to Figure 2 The charge Q stored on the ferroelectric capacitor 240 varies with the voltage difference V between the terminals of the ferroelectric capacitor 240 (e.g., when charge is permitted to flow into or out of the ferroelectric capacitor 240 in accordance with the voltage difference V cap For example, the voltage difference V cap may represent the voltage difference between the sense digit line side and the plate line side of the capacitor 240. cap

[0078] Ferroelectric materials are characterized by spontaneous polarization, where the material can maintain a non-zero charge in the absence of an electric field. Examples of ferroelectric materials include barium titanate (BaTiO3), lead titanate (PbTiO3), lead zirconate titanate (PZT), and strontium bismuth tantalate (SBT). The ferroelectric capacitor 240 described herein may include these or other ferroelectric materials. The polarization within the ferroelectric capacitor 240 results in a net charge on the surface of the ferroelectric material, and opposite charges are attracted through the terminals of the ferroelectric capacitor 240. Thus, charge is stored at the interface of the ferroelectric material and the capacitor terminals. Since the polarization can be maintained for a relatively long time, even indefinitely, in the absence of an externally applied electric field, charge leakage can be significantly reduced compared to, for example, capacitors that do not have ferroelectric characteristics (e.g., capacitors used in some DRAM arrays). The use of ferroelectric materials can reduce the need to perform refresh operations as described above for some DRAM architectures, such that maintaining the logical state of a FeRAM architecture can be associated with significantly lower power consumption compared to maintaining the logical state of a DRAM architecture.

[0079] ​The hysteresis curves 300-a and 300-b can be understood from the perspective of a single terminal of the ferroelectric capacitor 240. By way of example, if the ferroelectric material has a negative polarization, then positive charge accumulates at the relevant terminal of the ferroelectric capacitor 240. Similarly, if the ferroelectric material has a positive polarization, then negative charge accumulates at the relevant terminal of the ferroelectric capacitor 240.

[0080] In addition, it should be understood that the voltages in the hysteresis curves 300-a and 300-b represent the voltage difference across the capacitor (e.g., the electric potential between the terminals of the ferroelectric capacitor 240) and are oriented. For example, a positive voltage can be achieved by applying a positive voltage to the first terminal 222 and maintaining the second terminal 221 at ground or virtual ground (or approximately zero volts (0V)). In some examples, a negative voltage can be applied by maintaining the first terminal at ground and applying a positive voltage to the second terminal 221 (e.g., via the plate voltage 220). In other words, a positive voltage can be applied to create a negative voltage difference V across the ferroelectric capacitor 240 cap and thereby polarize the terminal in question negatively. Similarly, two positive voltages, two negative voltages, or any combination of positive and negative voltages can be applied to the appropriate capacitor terminals to create the voltage differences V shown in the hysteresis curves 300-a and 300-b cap .

[0081] As depicted in the hysteresis curve 300-a, when there is no net voltage difference between the terminals of the ferroelectric capacitor 240, the ferroelectric material used in the ferroelectric capacitor 240 can maintain a positive or negative polarization. For example, the hysteresis curve 300-a illustrates two possible polarization states: the charge state 305-b and the charge state 310-b, which can represent the positive saturation polarization state and the negative saturation polarization state, respectively. The charge states 305-a and 310-a can be in physical states that illustrate the remanent polarization (Pr) value, which can refer to the polarization (or charge) that remains after removing an external bias (e.g., voltage). The coercive voltage is the voltage at which the charge (or polarization) is zero. According to the example of the hysteresis curve 300-a, the charge state 305-a can represent a logic 1 when no voltage difference is applied across the ferroelectric capacitor 240, and the charge state 310-a can represent a logic 0 when no voltage difference is applied across the ferroelectric capacitor 240. In some examples, the logic values of the corresponding charge states can be reversed to accommodate other schemes for operating the memory cell 205.

[0082] By applying a net voltage difference across ferroelectric capacitor 240, a logic 0 or 1 can be written to the memory cell by controlling the polarization of the ferroelectric material and thereby the charge on the capacitor terminals. For example, voltage 315 can be a voltage equal to or greater than the positive saturation voltage, and applying voltage 315 across ferroelectric capacitor 240 can cause charge accumulation until charge state 305-b is reached (e.g., writing a logic 1). After removing voltage 315 from ferroelectric capacitor 240 (e.g., applying a zero net voltage across the terminals of ferroelectric capacitor 240), the charge state of ferroelectric capacitor 240 can follow path 320 shown between charge state 305-b and charge state 305-a at zero voltage across the capacitor. In other words, charge state 305-a can represent the logic 1 state at the equilibrium voltage across the positively saturated ferroelectric capacitor 240.

[0083] Similarly, voltage 325 can be a voltage equal to or less than the negative saturation voltage, and applying voltage 325 across ferroelectric capacitor 240 can cause charge accumulation until charge state 310-b is reached (e.g., writing a logic 0). After removing voltage 325 from ferroelectric capacitor 240 (e.g., applying a zero net voltage across the terminals of ferroelectric capacitor 240), the charge state of ferroelectric capacitor 240 can follow path 330 shown between charge state 310-b and charge state 310-a at zero voltage across the capacitor. In other words, charge state 310-a can represent the logic 0 state at the equilibrium voltage across the negatively saturated ferroelectric capacitor 240. In some instances, voltage 315 and voltage 325 representing the saturation voltages can have the same magnitude but opposite polarities across ferroelectric capacitor 240.

[0084] To read or sense the stored state of ferroelectric capacitor 240, a voltage can be applied across ferroelectric capacitor 240. In response to the applied voltage, the stored continuous charge Q of the ferroelectric capacitor changes, and the degree of change can depend on the initial polarization state, the applied voltage, the intrinsic capacitance of the access line, and other factors. In other words, the charge state resulting from the read operation can depend on whether charge state 305-a or charge state 310-a or some other charge state was initially stored, as well as other factors.

[0085] Hysteresis curve 300-b illustrates an example of an access operation for reading stored charge states 305-a and 310-a. For example, via reference Figure 2The described digital line 215 and plate line 220 apply a read voltage 335 as a voltage difference. The hysteresis curve 300-b can illustrate a read operation in which the read voltage 335 is negative. The negative read voltage across the ferroelectric capacitor 240 can be referred to as a "plate high" read operation, where initially the plate line 220 is at a higher voltage (e.g., above ground voltage) and the digital line 215 is initially at a lower voltage (e.g., below the plate line, ground voltage). Although the read voltage 335 is shown as a negative voltage across the ferroelectric capacitor 240, in an alternative operation, the read voltage can be a positive voltage across the ferroelectric capacitor 240, which can be referred to as a "plate low" read operation.

[0086] When the memory cell 205 is selected (e.g., by activating the cell selector component 245 via the word line 210 as described above), the read voltage 335 can be applied across the ferroelectric capacitor 240. After applying the read voltage 335 to the ferroelectric capacitor 240, charge can flow into or out of the ferroelectric capacitor 240 via the associated digital line 215 and plate line 220, and depending on whether the ferroelectric capacitor 240 is in charge state 305-a (e.g., logic 1) or charge state 310-a (e.g., logic 0), different charge states can be produced. Figure 2 When the memory cell 205 is selected (e.g., by activating the cell selector component 245 via the word line 210 as described above), the read voltage 335 can be applied across the ferroelectric capacitor 240. After applying the read voltage 335 to the ferroelectric capacitor 240, charge can flow into or out of the ferroelectric capacitor 240 via the associated digital line 215 and plate line 220, and depending on whether the ferroelectric capacitor 240 is in charge state 305-a (e.g., logic 1) or charge state 310-a (e.g., logic 0), different charge states can be produced.

[0087] When a read operation is performed on the ferroelectric capacitor 240 in charge state 310-a (e.g., logic 0), additional negative charge can accumulate on the ferroelectric capacitor 240, and the charge state can follow path 340 until reaching the charge and voltage of charge state 310-c. The amount of charge δ Q0 345 flowing through the capacitor 240 can be related to the charge state and the read voltage 335.

[0088] When a read operation is performed on the ferroelectric capacitor 240 in charge state 305-a (e.g., logic 1), the stored charge can reverse polarity because a net negative charge accumulates across the ferroelectric capacitor 240, and the charge state can follow path 360 until reaching the charge and voltage of charge state 305-c. The amount of charge δ Q1 365 flowing through the ferroelectric capacitor 240 can also be related to the charge state and the read voltage 335. Thus, as indicated by the transition between charge state 305-a and charge state 305-c, the amount of charge δ Q1 365 can be different from the amount of charge δ Q0 345, which can be detected by the sensing component 250.

[0089] In some cases, the read operation may not change the remaining polarization of ferroelectric capacitor 240 for charge states 305-a and 310-a, and thus after performing the read operation, when the read voltage 335 is removed (e.g., by applying a zero net voltage across ferroelectric capacitor 240, by equalizing the voltage across ferroelectric capacitor 240), ferroelectric capacitor 240 may return to charge state 310-a or 310-a via the reverse of path 340 or 360.

[0090] In some instances, the read operation may cause the remaining polarization of capacitor 240 storing charge state 305-a or 310-a to be reduced or reversed. In other words, depending on the properties of the ferroelectric material, after performing the read operation, when the read voltage 335 is removed, ferroelectric capacitor 240 may not return to charge state 305-a or 310-a. Instead, after the read operation by read voltage 335, when a zero net voltage is applied across ferroelectric capacitor 240, an intermediate state may be produced in the charge state (e.g., a charge state with less positive polarization compared to the initial charge state 305-a, a charge state with less unfavorable polarization compared to the initial charge state 310-a). However, in some sensing schemes, the reduced remaining polarization can still be read as the same stored logic state as the saturated remaining polarization state (e.g., enabling the detection of logic 0 or logic 1 from both charge state 305-a or 310-a and the intermediate charge state, thereby providing a degree of non-volatility to memory cell 205 relative to the read operation.

[0091] The positions of charge states 305-c and 310-c after the initial read operation can depend on one or more different factors, including the particular sensing scheme and circuitry. In some cases, the final charge and voltage can depend on the net capacitance of digital line 215 coupled to memory cell 205, which can include the intrinsic capacitance, the capacitance associated with the integrating capacitor, and capacitances from other sources. The positions of charge states 305-c and 310-c on hysteresis curve 300-b after the initial read operation can be determined through load line analysis. In other words, charge states 305-c and 310-c can be defined relative to the net capacitance of digital line 215. Thus, the voltage of ferroelectric capacitor 240 after the initial read operation (e.g., voltage 350 when reading ferroelectric capacitor 240 storing charge state 310-a, voltage 355 when reading ferroelectric capacitor 240 storing charge state 305-a) can be different and can depend on the initial state of ferroelectric capacitor 240.

[0092] In some cases, the voltage of digital line 215 (or the sensing line in the sense amplifier, if applicable) generated by the read operation can be compared with a reference voltage (e.g., via a reference Figure 2The described reference line 255, or via a common access line), is compared to determine the initial state of the ferroelectric capacitor 240. In some cases, the initial state of the ferroelectric capacitor 240 can be determined by current or charge sensing such that the voltage of the digital line 215 is not used for comparison with the reference line 255. That is, the charge from the ferroelectric capacitor 240 can be sensed, and the resulting signal formed based on the charge (e.g., via an integration circuit) can be compared with a reference voltage to determine the initial state of the ferroelectric capacitor 240.

[0093] During a sensing operation, the signals obtained from reading the respective memory cells 205 can vary due to manufacturing or operational variations between the respective memory cells 205. For example, the capacitors 240 of the respective memory cells 205 can have different amounts of capacitance or saturation polarization such that a logic 1 can be associated with different amounts of charge from one memory cell to the next, and a logic 0 can be associated with different amounts of charge from one memory cell to the next. These variations provide a margin sufficient to provide acceptable memory performance in the face of the challenge of reading the initial charge state of the ferroelectric capacitor 240.

[0094] In some instances, in accordance with the present disclosure, the cell selector component 245 of the unselected memory cell 205 can be deactivated, but leakage charge (e.g., leakage current) can still flow through the deactivated cell selector component 245 during access operations associated with different selected memory cells 205. This leakage current can exacerbate the challenge of providing sufficient read margin in the memory array, especially for increasing memory density. According to various aspects, the memory device can include a compensation component 270 to compensate for the leakage current on the digital line 215 during a read operation.

[0095] Figure 4 An example of a circuit 400 that illustrates techniques supporting leakage compensation for a memory array as disclosed herein. Circuit 400 illustrates a simplified circuit configuration highlighting several circuit components that work together during a read operation, as will be described in more detail with reference to Figures 5-6 more specifically.

[0096] Circuit 400 includes a digital line 215-a and multiple memory cells 205, including memory cells 205-a, 205-b. Memory cells 205-a, 205-b can be part of a larger memory array such as, for example, the memory array 170 described with reference to Figure 1 Each memory cell 205-a, 205-b includes a corresponding cell capacitor 240-a, 240-b and a cell selector component 245-a, 245-b. The digital line 215-a, the memory cells 205-a, 205-b, and the cell selector components 245-a, 245-b can be as described with reference to Figure 2Examples of the digital line 215, the memory cell 205, and the cell selector component 245 described. The number of memory cells 205 in the circuit 400 can vary and may require increasing the array size of the memory array by increasing the number of memory cells 205. Thus, the circuit 400 can have hundreds or thousands of memory cells 205 coupled to the digital line 215-a via corresponding cell selector components 245.

[0097] As previously discussed, the memory cell 205 can be configured to selectively couple to the digital line 215 by activating the cell selector component 245 of the memory cell 205. In some cases, the cell selector component 245 can be activated by activating (e.g., asserting, biasing) a word line (WL) signal on the word line 210 associated with the cell selector component 245. In some cases, the cell selector component 245 can be a switch component that can include one or more transistors.

[0098] In some cases, selecting a memory cell (e.g., memory cell 205-a) and coupling the memory cell 205-a to the digital line 215-a can cause charge 465 to transfer between the capacitor 240-a of the selected memory cell 205-a and the digital line 215-a, as Figure 4 depicted. The amount of charge transferred can depend on the logic state stored on the memory cell 205-a. Thus, the charge transfer between the cell capacitor 240-a and the digital line 215-a can produce a signal (e.g., a charge signal, a voltage signal, and / or a current signal) on the digital line 215-a that is related to the logic state stored in the memory cell 205-a. Such a signal can be used to determine the logic state stored in the memory cell 205-a directly or indirectly (e.g., via a sensing component).

[0099] The circuit 400 includes a compensation component 405. The compensation component 405 can be configured to compensate for noise (e.g., leakage current) on the digital line 215-a before or during a read operation of the memory cell 205 (e.g., during at least a portion or a stage of the read operation).

[0100] In some cases, the output node 415 of the compensation component 405 can be coupled to the digital line 215-a, for example, via a conductive line 425. Although the output node 415 is depicted as being directly coupled to the digital line 215-a, in some cases, the output node 415 can be coupled to the digital line 215-a via one or more other components, such as through additional switch components, resistors, etc. For example, the output node 415 can be coupled to the digital line 215-a through an activated switch component (e.g., an activated transistor).

[0101] In some cases, input node 420 of compensation component 405 can be configured to selectively couple with digital line 215-a via switch component 410. Switch component 410 can be activated (e.g., closed to create an electrical connection) by activating or biasing switch signal SW. When switch component 410 is activated, input node 420 and output node 415 of compensation component 405 can be coupled with digital line 215-a and with each other, thereby creating a feedback loop.

[0102] The circuit 400 includes a sensing element 250-a, which may be a reference Figures 1-2 An example of a sensing component 250 is discussed. The sensing component 250-a can be configured to determine the logic state stored by the target memory cell 205 during a read operation.

[0103] As previously discussed, in some cases, when the cell selector component 245 is not selected or activated, e.g., when the cell selector component 245 is in an off state, the cell selector component 245 may permit leakage current to flow through the cell selector component 245 onto the digit line 215-a. Such leakage current may introduce noise onto the digit line 215-a, which may reduce the accuracy of a read operation of the memory cell 205.

[0104] Circuit 400 also includes noise sources 430, which may represent respective sources of unwanted or undesired current that may appear on digit line 215-a attributable to parasitic effects, leakage current from components other than memory cell 205, crosstalk, etc.

[0105] In some cases, the compensation component 405 can be configured to compensate for noise (eg, undesired current, leakage current) introduced onto the digit line 215 - a through the unselected cell selector components 245 and / or through the noise source 430 .

[0106] In some cases, a read operation of a target memory cell may include coupling compensation component 405 to digit line 215-a prior to coupling target memory cell 205 to digit line 215-a (e.g., by activating switch component 410). Compensation component 405 may sample a leakage current that may be present on digit line 215-a on digit line 215-a prior to coupling target memory cell 205 to digit line 215-a. In some cases, the sampled leakage current may include the sum of leakage currents associated with non-target memory cells 205 and may also include a leakage current associated with target memory cell 205.

[0107] In some cases, the compensation component 405 may store a representation of the sampled leakage current before coupling the target memory cell 205 to the digit line 215-a. In some cases, for example, the compensation component 405 may store the representation of the leakage current by storing a voltage representative of the leakage current on a capacitor. In some cases, the voltage on the capacitor may be based on the leakage current; that is, the leakage current may induce or cause a voltage to be formed across the capacitor.

[0108] In some cases, the compensation component 405 may output a current on the digit line 215-a based on the representation of the leakage current.

[0109] In some cases, the compensation component 405 may output a current on the digit line 215-a by sinking (e.g., removing, transferring) current from the digit line 215-a, or by sourcing (e.g., providing, supplying, adding) current to the digit line 215-a. In some cases, the compensation component 405 may output a current based on the stored representation of the leakage current and may be substantially equivalent to the leakage current but with an opposite polarity to the leakage current. Thus, in some cases, outputting a current to the digit line 215-a may substantially eliminate or reduce the leakage current on the digit line 215-a based on the leakage current sampled on the digit line 215-a before the target memory cell 205 is coupled to the digit line 215-a.

[0110] As previously described, in some cases, the representation of the leakage current may include the leakage current associated with the target memory cell as well as the leakage current associated with non-target memory cells. For this and other reasons, the leakage current sampled during the first phase of the read operation may not be the same as the leakage current on the digit line during the second phase of the read operation. Assuming such differences are substantially negligible, compensation may be required, for example, during the read operation view by scaling the output current of the compensation component by a fraction of the unselected cells or by another multiple. For example, the scaling factor may depend on the leakage current probability distribution.

[0111] In some cases, the compensation component 405 may output a current on the digit line 215-a before and / or after coupling the target memory cell 205 to the digit line 215-a during a read operation. That is, in some cases, the compensation component 405 may begin outputting a current on the digit line 215-a before the target memory cell 205 is coupled to the digit line 215-a, and the compensation component 405 may continue to output a current on the digit line 215-a after the target memory cell 205 is coupled to the digit line 215-a during the read operation to compensate for the leakage current. In some cases, the sensing component 250-a may determine the logical state of the memory cell based on the signal on the digit line when the compensation component 405 outputs a current to the digit line 215-a.

[0112] In some cases, as described in more detail with reference to Figures 5-6 the input node 420 of the compensation component 405 may be coupled to the digit line 215-a during a first phase of a read operation (before the target memory cell 205 is coupled to the digit line 215-a) to sample and store a representation of the leakage current on the digit line 215-a. The input node 420 may be decoupled from the digit line 215-a during a second phase of the read operation (after the target memory cell 205 is coupled to the digit line 215-a), during which the compensation component 405 may continue to output current to the digit line 215-a based on the stored representation of the leakage current.

[0113] In some cases, the input node 420 of the compensation component 405 may be coupled to the digit line 215-a during a first phase of each of a plurality of read operations. Alternatively, the input node 420 of the compensation component 405 may be coupled to the digit line 215-a during a first phase of a subset of the plurality of read operations, while other read operations may use a previously stored representation of the leakage current on the digit line (e.g., where a plurality of consecutive read operations are applied to the same set of digit lines 215).

[0114] Figure 5 An example of a circuit 500 that illustrates techniques supporting leakage compensation for a memory array as disclosed herein. The circuit 500 illustrates a simplified circuit configuration highlighting several circuit components that may work together during a read operation, as will be described in more detail with reference to Figure 6 more detail.

[0115] The circuit 500 includes a compensation component 405-a, which may be an example of the compensation component 405 described with reference to Figure 4 The output node 415-a of the compensation component 405-a is coupled to the digit line 215-d. The input node 420 of the compensation component 405-a is configured to be selectively coupled to the digit line 215-d via a switch component 410.

[0116] Optionally, digital line 215-d can be selectively coupled via multiplexer 560 to one of a plurality of digital lines including digital lines 215-b, 215-c. In some cases, multiplexer 560 can select a target digital line to couple to digital line 215-d. Thus, in some cases, digital line 215-d corresponds to one of the plurality of digital lines 215. In some cases, multiplexer 560 can be used to enable sharing of sense component 250-a and / or compensation component 405-a among the plurality of digital lines 215. Such component sharing can be possible for a memory device based on ferroelectric memory cells because unselected ferroelectric memory cells can be biased such that both plates of the capacitor in the ferroelectric memory cell are at the same or substantially the same voltage (e.g., the plate line voltage) to reduce unselected cell leakage and maintain the state of the unselected cells. In contrast, a memory device based on DRAM cells may not include multiplexer 560 because DRAM cells may involve a sense component for each digital line to refresh the state of the DRAM cells.

[0117] Circuit 500 includes a plurality of memory cells 205, including memory cells 205-c, 205-d, 205-e, and 205-f, which can be coupled to associated digital lines 215 including digital lines 215-b, 215-c.

[0118] Compensation component 405-a includes a transconductance circuit 510, which can be configured to output a current at an output node 515 of the transconductance circuit 510 based on voltages at a first input node 520 and a second input node 525 of the transconductance circuit 510. That is, in some cases, transconductance circuit 510 can output a current at output node 515 that is proportional to the voltages on input nodes 520, 525. In some cases, the first input node 520 can be referred to as the inverting node, and the second input node 525 can be referred to as the non-inverting node. In some cases, connecting output node 515 to input node 520 (e.g., via switch component 410) can establish a feedback loop (e.g., a negative feedback loop) through transconductance circuit 510. In some cases, transconductance circuit 510 can be or can include a transconductance amplifier.

[0119] In some cases, the output node 515 of transconductance circuit 510 is coupled to or the same as the output node 415-a of compensation component 405-a. In some cases, the first input node 520 of transconductance circuit 510 is coupled to or the same as the input node 420 of compensation component 405-a.

[0120] The transconductance circuit 510 can be coupled to a first voltage source 540 and a second voltage source 545 to supply power to the transconductance circuit 510. The first voltage source 540 and the second voltage source 545 can provide voltages selected to achieve the desired operating range of the transconductance circuit 510. For example, the first voltage source 540 can supply approximately 1.0 volts, and the second voltage source can supply approximately -0.6 volts. Other voltage supply values are possible.

[0121] In some cases, when the voltages on the input nodes 520, 525 are positive (the input node 525 has a higher voltage compared to the input node 520), the output node 515 can emit current, and when the voltages on the input nodes 520, 525 are negative, the output node 515 can absorb current. Thus, the transconductance circuit 510 can emit or absorb current based on the polarity of the voltages on the input nodes 520, 525. The transconductance circuit 510 can include a driver for outputting current, such as a current driver.

[0122] The compensation component 405-a includes a capacitor 530. The first node 550 of the capacitor 530 can be coupled to the first input node 520 of the transconductance circuit and to the switch component 410. The second node 555 of the capacitor 530 can be coupled to the second input node 525 of the transconductance circuit 510. Thus, the capacitor 530 can be coupled across the input nodes 520, 525 of the transconductance circuit 510.

[0123] In some cases, the second input node 525 of the transconductance circuit 510 can be coupled to a voltage source 535, which can be a precharge voltage source for precharging the digit line 215-d during a read operation of the memory cell 205. In some cases, initially, the digit line 215-d can be directly coupled to the voltage source 535 by activating a switch component between the voltage source 535 and the digit line 215-d (not shown) to precharge the digit line 215-d to a first voltage. Then the switch component can be deactivated, and the voltage source 535 can continue to be used to indirectly precharge the digit line 215-d via the transconductance circuit 510 such that the transconductance circuit 510 can emit or absorb the leakage current on the digit line 215-d.

[0124] The circuit 500 includes a sensing component 250-a for determining the state stored in a target memory cell during a read operation. The sensing component 250-a can determine the state based on the signal on the digit line 215-d. In some cases, the sensing component 250-a can be directly coupled or connected to the digit line 215-d, while in other cases, the sensing component 250-a can be coupled to the digit line 215-d via one or more additional components such as a switch component, a capacitor, an amplifier, etc.

[0125] During a read operation, compensation component 405-a may compensate for leakage current on digit line 215-d as follows.

[0126] During a first phase of the read operation (e.g., before the target memory cell 205 can be coupled to digit line 215-d by means of multiplexer 560), switch component 410 may be activated to couple a first node 550 of capacitor 530 and a first input node 520 of transconductance circuit 510 to digit line 215-d, thereby establishing a feedback loop via conductive line 425-a. A second input node 525 of the transconductance circuit and a second node of capacitor 530 may be coupled to voltage source 535, which may provide a precharge voltage to transconductance circuit 510 for precharging digit line 215-d before the target memory cell is coupled to digit line 215-d. During this phase, the voltage of a plate line (e.g., plate line 220) associated with the target memory cell may be set to a high voltage (e.g., 1.5 volts) and digit line 215-d may be precharged to a different voltage, e.g., 0 volts, using compensation component 405-a to bias the circuit in preparation for the read operation.

[0127] During the first phase, leakage current from unselected memory cells 205 and / or other unwanted currents from noise source 430 may flow onto digit line 215-d. When the transconductance circuit is connected in the feedback loop, capacitor 530 may begin to generate a voltage across capacitor 530 that is proportional to the current flowing into (or out of) output node 515 of transconductance circuit 510 (and thus proportional to the amount of leakage current on digit line 215-d). Thus, the voltage on capacitor 530 may be based on the leakage current on digit line 215-d.

[0128] After a period of time, circuit 500 may approach or may reach an equilibrium condition (e.g., may approach or reach a steady state), in which the leakage current flowing into or out of output node 515 is substantially constant and the corresponding voltage on capacitor 530 is also substantially constant; that is, the current flowing into / out of output node 515 and / or the voltage on capacitor 530 may reach a steady state. The voltage of digit line 215-d may also be substantially constant and may be approximately equal to the precharge voltage supplied by voltage source 535.

[0129] In some cases, capacitor 530 may be precharged to an initial voltage before switch component 410 is activated. For example, precharging capacitor 530 may enable circuit 500 to reach the equilibrium condition more quickly during the first phase of the read operation.

[0130] At the end of the first stage of the read operation, the switch component 410 can be deactivated to decouple the first node 550 of the capacitor 530 and the first node 520 of the transconductance circuit 510 from the digital line 215-d. At this time, the voltage on the capacitor 530 and thus the voltage on the input nodes 520, 525 of the transconductance circuit 510 can be a voltage representing the leakage current that existed on the digital line 215-d before the target memory cell 205 was coupled to the digital line 215-d (e.g., can be based on or proportional to the leakage current). Therefore, the representation of the leakage current can be stored as the voltage on the capacitor 530. Assuming that the charge leakage from the capacitor 530 is negligible, since the capacitor 530 is now decoupled from the digital line 215-d, the voltage on the capacitor 530 will remain substantially constant.

[0131] When the target memory cell 205 is coupled to the digital line 215-d (possibly with the help of the multiplexer 560), the second stage of the read operation can begin. The target memory cell 205 can be coupled to the digital line 215-d by, for example, activating the cell selector component 245 of the target memory cell 205, as described, for example, with reference to Figure 2 After the target memory cell 205 is coupled to the digital line 215-d, the target memory cell 205 can begin to transfer charge through the digital line 215-d, thereby causing a signal (e.g., a voltage) to be formed on the digital line 215-d. The signal can depend on or can represent the logical state stored in the target memory cell 205.

[0132] During the second stage of the read operation, when the target memory cell 205 is coupled to the digital line 215-d, the transconductance circuit 510 can continue to output (e.g., sink or source) current to the digital line 215-d based on the voltage on the input nodes 520, 525, e.g., based on the representation of the leakage current stored on the capacitor 530. In this way, the transconductance circuit 510 can substantially compensate for (e.g., remove) the leakage current from the digital line 215-d, such that the signal formed on the digital line 215-d is mainly or entirely due to the charge transfer from the target memory cell 205; that is, the signal on the digital line 215-d can exclude some or all of the leakage current.

[0133] The sensing component 250-a can then determine the logical state stored in the target memory cell 205 by, for example, comparing the signal on the digital line 215-d with a reference Figure 2 value as described. In some cases, the controller can enable the sensing component 250-a to determine the logical state, for example, by asserting a control signal or otherwise activating or triggering the sensing component.

[0134] Figure 6Describe an example of a timing diagram 600 that supports leakage compensation for a memory array as disclosed herein. The timing diagram 600 illustrates the voltage V associated with the signal on digital line 215 during a read operation SEN . V SEN 605 shows a sense voltage that can be generated (e.g., by a sense amplifier) during a read operation based on the signal on digital line 215 (e.g., a voltage signal, a current signal, a charge signal). In some cases, a sensing component can receive the signal on digital line 215 and amplify the signal to generate V SEN 605, which can then be compared with a reference voltage. Such amplification can provide a larger sensing window (e.g., a larger difference between the "1" state voltage and the "0" state voltage) for determining the state of the selected memory cell. In some cases, the charge from the selected ferroelectric memory cell can be transferred between the cell capacitor and the integration capacitor via digital line 215 in the sensing component during a read operation. Such charge transfer can cause a voltage to be formed on the integration capacitor in the sensing component. The voltage formed on the integration capacitor can depend on the state stored in the selected memory cell and can be compared with a reference voltage to determine the state. In this case, V SEN 605 can represent the voltage on the integration capacitor or the voltage at the node of the integration capacitor (e.g., the output of the signal forming circuit including the integration capacitor).

[0135] The timing diagram 600 also illustrates the voltage V of the word line signal WL that can be used to activate a cell selector component (e.g., cell selector component 245) to couple a target memory cell to the digital line during a read operation WL , and the voltage Vsw of the switch signal SW that can be used to activate a switch component (e.g., switch component 410) to couple a compensation component (e.g., compensation components 405, 505) to the digital line. The polarities shown for the signals in Figure 6 are shown as positive values to close the switch component or activate the cell selector component, and can be reversed without loss of meaning for different types of switch components and cell selector components.

[0136] The timing diagram 600 can illustrate the operation of a circuit similar to circuits 400, 500 described in reference Figures 4-5 . Thus, the timing diagram 600 can illustrate the operation of one or more components described herein with reference to Figures 1-5 . For example, the timing diagram 600 can illustrate the voltage V associated with the signal on a digital line (e.g., digital lines 215, 215-a, 215-d) that is received by or applied to a sensing component (e.g., sensing components 250, 250-a described in reference Figures 1-5 ) during a read operation of a memory cell SEN605。

[0137] In an example of the timing diagram 600, the memory cell 205 may initially store a logic state as described herein (e.g., a logic 0 state, a logic 1 state). Certain signals illustrated in the timing diagram 600 thus show alternatives associated with reading different logic states indicated by an annotation state = 1 or state = 0 (e.g., associated with the respective logic states), where such signals are different.

[0138] In some examples, the read operation illustrated by the timing diagram 600 may begin at t0 as an initial state in which the word line 210 associated with the target memory cell 205 is not asserted (e.g., the logic signal WL is deactivated) and the voltage of the digit line 215 may float, or may be set to a predetermined voltage, such as may be the same as the board voltage. The switch component (e.g., the switch component 410) may be deactivated such that the first input nodes of the compensation components 405, 405-a are not coupled to the digit line.

[0139] At time t0, the first stage 620 of the read operation may begin, as described with respect to Figures 4-5 At t0, the switch component (e.g., the switch component 410) may be activated by asserting the switch signal SW (e.g., by raising the voltage Vsw 615) to couple the input node 420 of the compensation component (e.g., the compensation components 405, 405-a) to the digit line 215. In the example depicted in Figure 5 During the first stage 620, the compensation component 405-a outputs (absorbs or sources) current to the digit line based on the voltage on the capacitor 530. In an example of the compensation component 405-a, the transconductance circuit 510 is connected in a negative feedback loop during the first stage and thus attempts to maintain a zero voltage difference across the input nodes 520, 525 by absorbing or sourcing output current to drive the first node 520 to the same voltage as the second node 525 (e.g., to the precharge voltage supplied by the voltage source 535, which may be 0 volts).

[0140] During the first stage 620, the board line associated with the target memory cell may be set to a high voltage, such as 1.5 volts, and the digit line may be precharged to a different voltage, such as 0 volts. In this case, if the cell selector component is an n-type metal oxide semiconductor (NMOS) transistor, for example, the drains of all source electrodes of the cell selector component may be set to the digit line voltage (e.g., 0 volts) below the board voltage (e.g., 1.5 volts). It should be understood that for some types of transistors or implementations, the drain and source may be reversed. Thus, due to defects in the transistor and because the drain and source are set to different voltages, there may be a leakage current flowing through the cell selector component to the digit line.

[0141] At or near the end of the first phase 620, the circuit 500 may have reached an equilibrium condition in which the current output by the compensation components 405, 405-a is substantially constant and compensates for the leakage current through the cell selector component, and the voltage of the digital line may have been precharged to an initial voltage, such as at or near 0, using the compensation components 405, 405-a. Thus, V SEN 605 may also be at or near 0 volts. At Figure 5 In an example, the voltage on the capacitor 530 of the compensation component 405-a may also be substantially constant. Thus, by time t1, the compensation components 405, 405-a may have stabilized the representation of the leakage current as, for example, the voltage on the capacitor 530. The compensation components 405, 405-a may be configured to compensate for the leakage current by outputting a current to the digital line 215 based on the stored representation of the leakage current.

[0142] At time t1, the switch component 410 may be deactivated by deasserting the switch signal SW (e.g., by lowering the voltage Vsw 615), thereby decoupling the input node 420 of the compensation components 405, 405-a from the digital line. In Figure 5 the example depicted, deactivating the switch component 410 decouples the capacitor 530 from the digital line 215-d and stores the representation of the leakage current on the capacitor 530.

[0143] At time t2, the second phase 625 of the read operation may begin, as described with respect to Figures 4-5 At time t2, the word line signal WL may be asserted (e.g., by raising V WL 610) to couple the target memory cell 205 to the digital line 215. For example, the word line signal WL may be coupled to (e.g., drive) the gate of the cell selector component 245 of the target memory cell 205.

[0144] After time t2, signals may begin to form on the digital line (e.g., charge may begin to transfer between the selected memory cell and the digital line), thereby causing the voltage V SEN 605 to form based on the state stored in the target memory cell 205. During the second phase, the compensation components 405, 405-a may continue to compensate for the leakage current on the digital line 215 by outputting a current to the digital line 215 based on the stored representation of the leakage current, e.g., based on the voltage of the capacitor 530.

[0145] At time t3, the sense component 250 may determine the logical state stored in the target memory cell 205. For example, the sense component may determine the logical state by comparing V SEN 605 to a reference voltage V REFCompare with 630 to determine (e.g., sense) the logical state. For example, if V SEN is higher than V REF , then the sensing component can determine that the logical state is "1", and if V SEN is lower than V REF , then the sensing component can determine that the logical state is "0".

[0146] Figure 7 FIG. 700 shows a block diagram 700 of an apparatus 705 that supports leakage compensation for a memory array as disclosed herein. The apparatus 705 can include a storage component 710, a coupling component 715, a driver component 720, and a sensing component 725. Each of these components can communicate directly or indirectly with one another (e.g., via one or more buses, conductive lines, etc.).

[0147] The storage component 710 can store a representation of the leakage current of the digit line during a first stage of a read operation of a target memory cell. In some cases, for example, the storage component 710 can use a capacitor to store the representation.

[0148] The coupling component 715 can couple the target memory cell to the digit line during a second stage of the read operation. In some cases, the coupling component 715 can couple the target memory cell to the digit line by activating a word line signal associated with the target memory cell to, for example, activate a cell selector component of the target memory cell.

[0149] The driver component 720 can output a current on the digit line based on the representation of the leakage current during a second stage of the read operation. In some cases, the driver component 720 can output a current on the digit line by sinking current from the digit line or supplying current to the digit line. In some cases, the driver component 720 can output a current that can be adjusted to a fraction of the leakage current.

[0150] The sensing component 725 can determine the logical state stored in the target memory cell based on a signal on the digit line during a second stage of the read operation.

[0151] Figure 8 FIG. 800 shows a flow diagram 800 of a method that supports leakage compensation for a memory array as disclosed herein. The operations of the method 800 can be implemented by a controller or its components as described herein. For example, the operations of the method 800 can be performed by a controller (e.g., a local memory controller, a device memory controller, an external memory controller, or a host controller) described with reference to Figures 1-6 . In some instances, the controller can execute an instruction set to control functional elements of the memory device to perform the functions described below. Additionally or alternatively, the controller can use dedicated hardware to perform portions of the functions described below.

[0152] At 805, the controller may cause the memory device to store a representation of the leakage current of the digit line during a first phase of a read operation of a target memory cell. The operation of 805 may be performed according to the methods described herein. In some instances, portions of the operation of 805 may be performed by the memory component described by reference Figure 7 described herein.

[0153] At 810, the controller may cause the memory device to couple the target memory cell to the digit line during a second phase of the read operation. The operation of 810 may be performed according to the methods described herein. In some instances, portions of the operation of 810 may be performed by the coupling component described by reference Figure 7 described herein.

[0154] At 815, the controller may cause the memory device to output a current on the digit line based on the representation of the leakage current during a second phase of the read operation. The operation of 815 may be performed according to the methods described herein. In some instances, portions of the operation of 815 may be performed by the driver component described by reference Figure 7 described herein.

[0155] At 820, the controller may cause the memory device to determine a logical state stored in the target memory cell based on a signal on the digit line during a second phase of the read operation. The operation of 820 may be performed according to the methods described herein. In some instances, portions of the operation of 820 may be performed by the sense component described by reference Figure 7 described herein.

[0156] Note that the methods described above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Additionally, portions from two or more of the methods may be combined.

[0157] In some instances, one or more devices, as described herein, can perform one or more methods, such as method 800. The device can include features, controllers, circuitry, means, or instructions (e.g., instructions executable by a processor stored on a non-transitory computer-readable medium) for: storing a representation of a leakage current of a digit line during a first phase of a read operation of a target memory cell; coupling the target memory cell to the digit line during a second phase of the read operation; outputting a current on the digit line during the second phase of the read operation, at least in part based on the representation of the leakage current; and determining a logical state stored in the target memory cell during the second phase of the read operation, at least in part based on a signal on the digit line. In some cases, outputting the current on the digit line includes using a compensation component coupled to the digit line to sink the current from the digit line or supply the current to the digit line. In some cases, storing the representation of the leakage current includes storing a voltage, at least in part based on the leakage current, on a capacitor of the compensation component, wherein activating the switching component couples the digit line to a node of the capacitor.

[0158] Some instances of the methods, devices, and non-transitory computer-readable media described herein can further include operations, features, controllers, circuitry, means, or instructions for: activating a switching component to couple the digit line to an input node of the compensation component during the first phase, wherein the digit line is coupled to an output node of the compensation component.

[0159] Some instances of the methods, devices, and non-transitory computer-readable media described herein can further include operations, features, controllers, circuitry, means, or instructions for: deactivating the switching component to decouple the digit line from the capacitor before coupling the target memory cell to the digit line.

[0160] In some cases, the compensation component includes a transconductance circuit for outputting the current to the digit line.

[0161] In some cases, the digit line is associated with a plurality of memory cells including the target memory cell, and the leakage current includes a leakage current associated with the plurality of memory cells.

[0162] In some cases, coupling the target memory cell to the digit line causes the signal on the digit line to change, at least in part based on the logical state stored in the target memory cell.

[0163] A method is described. The method may include storing a representation of a leakage current of a digit line during a first stage of a read operation of a target memory cell; coupling the target memory cell to the digit line during a second stage of the read operation; outputting a current on the digit line based on the representation of the leakage current during the second stage of the read operation; and determining a logic state stored in the target memory cell based on a signal on the digit line during the second stage of the read operation.

[0164] An apparatus is described. The apparatus may include a processor, a memory in electronic communication with the processor, and instructions stored in the memory. The instructions may be executed by the processor to cause the apparatus to store a representation of a leakage current of a digit line during a first stage of a read operation of a target memory cell; couple the target memory cell to the digit line during a second stage of the read operation; output a current on the digit line based on the representation of the leakage current during the second stage of the read operation; and determine a logic state stored in the target memory cell based on a signal on the digit line during the second stage of the read operation.

[0165] Another apparatus is described. The apparatus may include means for storing a representation of a leakage current of a digit line during a first stage of a read operation of a target memory cell; means for coupling the target memory cell to the digit line during a second stage of the read operation; means for outputting a current on the digit line based on the representation of the leakage current during the second stage of the read operation; and means for determining a logic state stored in the target memory cell based on a signal on the digit line during the second stage of the read operation.

[0166] A non-transitory computer-readable medium storing code is described. The code may include instructions executable by a processor to perform the following operations: storing a representation of a leakage current of a digit line during a first stage of a read operation of a target memory cell; coupling the target memory cell to the digit line during a second stage of the read operation; outputting a current on the digit line based on the representation of the leakage current during the second stage of the read operation; and determining a logic state stored in the target memory cell based on a signal on the digit line during the second stage of the read operation.

[0167] In some examples of the methods, apparatuses, and non-transitory computer-readable media described herein, outputting the current on the digital line can include operations, features, apparatuses, or instructions for: using a compensation component coupled to the digital line to absorb the current from the digital line or supply the current to the digital line.

[0168] Some examples of the methods, apparatuses, and non-transitory computer-readable media described herein can additionally include operations, features, apparatuses, or instructions for: during the first phase, activating a switch component to couple the digital line to an input node of the compensation component, wherein the digital line can be coupled to an output node of the compensation component.

[0169] In some examples of the methods, apparatuses, and non-transitory computer-readable media described herein, storing the representation of the leakage current can include operations, features, apparatuses, or instructions for: storing a voltage based on the leakage current on a capacitor of the compensation component, wherein activating the switch component couples the digital line to a node of the capacitor.

[0170] Some examples of the methods, apparatuses, and non-transitory computer-readable media described herein can additionally include operations, features, apparatuses, or instructions for: before coupling the target memory cell to the digital line, deactivating the switch component to decouple the digital line from the capacitor.

[0171] In some examples of the methods, apparatuses, and non-transitory computer-readable media described herein, the compensation component includes a transconductance circuit for outputting the current to the digital line.

[0172] In some examples of the methods, apparatuses, and non-transitory computer-readable media described herein, the digital line can be associated with a set of memory cells including the target memory cell, and the leakage current includes a leakage current associated with the set of memory cells.

[0173] Some examples of the methods, apparatuses, and non-transitory computer-readable media described herein can additionally include operations, features, apparatuses, or instructions for: coupling the target memory cell to the digital line causes the signal on the digital line to change based on the logic state stored in the target memory cell.

[0174] A device is described. The device may include a digital line; a set of memory cells configured to selectively couple with the digital line; and a compensation component coupled with the digital line, the compensation component including: a storage component configured to store a representation of a leakage current on the digital line before coupling a target memory cell of the set of memory cells with the digital line during a read operation; a driver configured to output a current to the digital line based on the representation of the leakage current during the read operation; and a sensing component coupled with the digital line and configured to determine a logic state stored in the target memory cell based on a signal on the digital line after the target memory cell is coupled with the digital line.

[0175] Some examples of the device may include a switching component for selectively coupling an input node of the compensation component with the digital line.

[0176] In some examples, the compensation component includes a transconductance circuit configured to output the current to the digital line by absorbing or supplying the current through an output node of the transconductance circuit, the transconductance circuit including the driver.

[0177] In some examples, the storage component includes a capacitor coupled between a first input node of the transconductance circuit and a second input node of the transconductance circuit, and the representation of the leakage current includes a voltage on the capacitor.

[0178] In some examples, a node of the capacitor may be coupled with the switching component.

[0179] Some examples of the device may include a voltage source coupled with the first input node of the transconductance circuit for precharging the digital line before the target memory cell is coupled with the digital line.

[0180] In some examples, the set of memory cells includes a set of cell selector components for coupling the set of memory cells with the digital line, and the leakage current includes a leakage current associated with the set of cell selector components.

[0181] A device is described. The device may include a set of memory cells configured to selectively couple to an access line; a compensation component configured to output a current on the access line; a sensing component coupled to the access line; and a controller configured to cause the device to: prior to a second phase of the read operation, decouple the input node from the access line, and the compensation component stores a representation of the compensated leakage current; during a second phase of the read operation, couple a target memory cell to the access line; and enable the sensing component to sense a logical state stored in the target memory cell based on a signal on the access line during the second phase of the read operation.

[0182] Some examples may further include decoupling the input node of the compensation component from the access line before coupling the target memory cell to the access line.

[0183] Some examples may further include coupling the input node of the compensation component to the access line by activating a switch component; and decoupling the input node of the compensation component from the access line by deactivating the switch component.

[0184] In some examples, the compensation component includes a transconductance circuit and a capacitor coupled between a first input node of the transconductance circuit and a second input node of the transconductance circuit, and an output node of the transconductance circuit may be coupled to the access line.

[0185] In some examples, the controller may be configured to cause the device to decouple the compensation component from the access line based on the voltage on the capacitor reaching a substantially steady state.

[0186] In some examples, the representation of the leakage current includes the voltage on the capacitor, and the transconductance circuit is configured to output the current to the access line based on the voltage on the capacitor.

[0187] In some examples, the set of memory cells includes a set of transistors, and the leakage current includes a sum of off-state currents through respective channels of the set of transistors.

[0188] Some examples of the device may include a multiplexer between the sensing component and an access line set including the access line.

[0189] Any of a variety of different technologies and techniques may be used to represent the information and signals described herein. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some of the figures may illustrate a signal as a single signal; however, one of ordinary skill in the art will understand that the signal may represent a signal bus, where the bus may have a variety of bit widths.

[0190] As used herein, the term "virtual ground" refers to a node of a circuit that is held at a voltage approximately equal to zero volts (0V) but is not directly coupled to ground. Thus, the voltage of the virtual ground may fluctuate over time and return to approximately 0V in a steady state. A virtual ground may be implemented using various electronic circuit elements such as, for example, a voltage divider consisting of an operational amplifier and a resistor. Other implementations are possible. "Virtual ground" or "virtual earth ground" refers to being connected to approximately 0V.

[0191] The terms "electronically communicate", "electrically contact", "connect", and "couple" may refer to a relationship between components that supports the flow of electrons between the components. Components are considered to be electronically communicating (or electrically contacting, or connected, or coupled) with each other if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, based on the operation of the device that includes the connected components, the conductive path between components that are electronically communicating (or electrically contacting or connected or coupled) with each other may be an open circuit or a closed circuit. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some cases, the flow of signals between the connected components may be interrupted for a period of time using, for example, one or more intermediate components such as switches or transistors.

[0192] The term "couple" refers to the condition of moving from an open circuit relationship between components, where a signal cannot currently be communicated between the components through a conductive path, to a closed circuit relationship between the components, where a signal can be communicated between the components through a conductive path. When a component such as a controller couples other components together, the component initiates a change that allows a signal to flow between the other components via a conductive path that previously did not permit signal flow.

[0193] The term "isolated" refers to the relationship between components where a signal cannot currently flow between the components. If there is an open circuit between components, the components are isolated from each other. For example, components separated by a switch positioned between the two components are isolated from each other when the switch is open. When a controller isolates two components from each other, the controller effects the following change: preventing a signal from flowing between the components using a conductive path that previously permitted signal flow.

[0194] As used herein, the term "substantially" means that the modified characteristic (e.g., a verb or adjective modified by the term substantially) need not be absolute but should be close enough to achieve the advantage of the characteristic.

[0195] The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate can be controlled by doping using various chemicals including but not limited to phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0196] The switching components or transistors discussed herein may represent field effect transistors (FETs) and include three-terminal devices, the three-terminal devices including a source, a drain, and a gate. The terminals may be connected to other electronic components by a conductive material such as metal. The source and drain may be conductive and may include heavily doped, e.g., degenerate, semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0197] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and does not mean "preferred over" or "better than" other examples. The detailed description includes specific details to provide an understanding of the described technologies. However, the technologies may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0198] In the figures, similar components or features may have the same reference label. Additionally, various components of the same type may be distinguished by following the reference label with a dash and a second label that differentiates among the similar components. If only the first reference label is used in the specification, the description applies to any one of the similar components having the same first reference label, regardless of the second reference label.

[0199] Any of a variety of different technologies and techniques may be used to represent the information and signals described herein. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0200] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or executed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0201] The techniques described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination of these. The features implementing the functions may also be physically located at various positions, including being distributed such that portions of the functions are implemented at different physical locations. Also, as used herein, including in the claims, the term "or" as used in a list of items (e.g., a list of items that begins with phrases such as "at least one of..." or "one or more of...") refers to an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of the present disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0202] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. Non-transitory storage media may be any available media that can be accessed by a general or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory media that can be used to carry or store the desired program code in the form of instructions or data structures and that can be accessed by a general or special purpose computer or a general or special purpose processor. Also, any connection is properly termed a computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically, while discs reproduce data optically with a laser. Combinations of the above are also included within the scope of computer-readable media.

[0203] Providing the description herein enables those skilled in the art to make or use the present disclosure. Those skilled in the art will appreciate various modifications to the present disclosure, and the general principles defined herein can be applied to other variations without departing from the scope of the present disclosure. Thus, the present disclosure is not limited to the examples and designs described herein, but is accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method, comprising: During a first stage of a read operation of a target memory cell, storing a representation of a leakage current of a digital line in a compensation component, wherein the compensation component includes a capacitor coupled between a first input node of a transconductance circuit and a second input node of the transconductance circuit, and the representation of the leakage current includes a voltage on the capacitor; During a second stage of the read operation, coupling the target memory cell to the digital line; During the second stage of the read operation, outputting a current on the digital line from the compensation component at least in part based on the representation of the leakage current; And During the second stage of the read operation, determining a logic state stored in the target memory cell at least in part based on a signal on the digital line.

2. The method according to claim 1, wherein outputting the current on the digital line comprises: Using the compensation component coupled to the digital line to absorb the current from the digital line or supply the current to the digital line.

3. The method according to claim 2, further comprising: During the first stage, activating a switch component to couple the digital line to an input node of the compensation component, wherein during the first stage the digital line is coupled to an output node of the compensation component, and wherein the compensation component outputs the representation of the leakage current during the first stage.

4. The method according to claim 3, wherein storing the representation of the leakage current comprises: Storing the voltage at least in part based on the leakage current on the capacitor of the compensation component, wherein activating the switch component couples the digital line to a node of the capacitor.

5. The method according to claim 4, further comprising: Before coupling the target memory cell to the digital line, deactivating the switch component to disconnect the digital line from the capacitor.

6. The method according to claim 2, wherein the compensation component includes the transconductance circuit for outputting the current to the digital line.

7. The method according to claim 1, wherein the digital line is associated with a plurality of memory cells including the target memory cell, and the leakage current includes leakage currents associated with the plurality of memory cells.

8. The method according to claim 1, wherein coupling the target memory cell to the digital line causes the signal on the digital line to change at least in part based on the logic state stored in the target memory cell.

9. An apparatus, comprising: A digital line; A plurality of memory cells configured to selectively couple to the digital line; A compensation component coupled to the digital line, the compensation component including: A storage component configured to store a representation of a leakage current on the digital line before coupling a target memory cell of the plurality of memory cells to the digital line during a read operation, wherein the storage component includes a capacitor coupled between a first input node of a transconductance circuit and a second input node of the transconductance circuit, and the representation of the leakage current includes a voltage on the capacitor, and A driver configured to output a current to the digital line during the read operation based at least in part on the representation of the leakage current; and A sensing component coupled to the digital line and configured to determine a logic state stored in the target memory cell based at least in part on a signal on the digital line after the target memory cell is coupled to the digital line.

10. The apparatus according to claim 9, further comprising: A switching component for selectively coupling an input node of a compensation component to the digital line.

11. The apparatus according to claim 10, wherein the compensation component includes the transconductance circuit configured to absorb or supply the current through an output node of the transconductance circuit to output the current to the digital line, and the transconductance circuit includes the driver.

12. The apparatus according to claim 10, wherein a node of the capacitor coupled to the second input node of the transconductance circuit is coupled to the switching component.

13. The apparatus according to claim 9, further comprising: A voltage source coupled to the first input node of the transconductance circuit for precharging the digital line before the target memory cell is coupled to the digital line.

14. The apparatus according to claim 9, wherein the plurality of memory cells includes a plurality of cell selector components for coupling the plurality of memory cells to the digital line, and the leakage current includes leakage currents associated with the plurality of cell selector components.

15. An apparatus comprising: A plurality of memory cells configured to selectively couple to an access line; A compensation component configured to output a current on the access line, wherein the compensation component includes a transconductance circuit and a capacitor coupled between a first input node of the transconductance circuit and a second input node of the transconductance circuit, and an output node of the transconductance circuit is coupled to the access line; A sensing component coupled to the access line; and A controller configured to cause the apparatus to: During a first stage of a read operation of a target memory cell of the plurality of memory cells, couple an input node of the compensation component to the access line, the compensation component being configured to adjust the current to compensate for a leakage current on the access line; Before a second stage of the read operation, decouple the input node from the access line, and the compensation component stores a representation of the compensated leakage current; During the second stage of the read operation, couple the target memory cell to the access line; and Enable the sensing component to sense the logical state stored in the target memory cell during the second phase of the read operation, at least partially based on the signal on the access line.

16. The apparatus according to claim 15, wherein the controller is configured to cause the apparatus to: Before coupling the target memory cell to the access line, decouple the input node of the compensation component from the access line.

17. The apparatus according to claim 16, wherein the controller is configured to cause the apparatus to: Couple the input node of the compensation component to the access line by activating a switch component; and Decouple the input node of the compensation component from the access line by deactivating the switch component.

18. The apparatus according to claim 15, wherein the controller is configured to cause the apparatus to decouple the compensation component from the access line at least partially based on the voltage on the capacitor reaching a substantially stable state.

19. The apparatus according to claim 15, wherein the representation of the leakage current includes the voltage on the capacitor, and the transconductance circuit is configured to output the current to the access line at least partially based on the voltage on the capacitor.

20. The apparatus according to claim 15, wherein the plurality of memory cells includes a plurality of transistors, and the leakage current includes the sum of the off-state currents through the respective channels of the plurality of transistors.

21. The apparatus according to claim 15, further comprising: A multiplexer disposed between the sensing component and a plurality of access lines including the access line.

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