Devices including vertical transistors with hydrogen barrier materials and related methods

Abstract

The present application relates to devices including vertical transistors having hydrogen barrier materials and related methods. A device includes a vertical transistor including a source region and a drain region each individually including at least one conductive material configured to inhibit hydrogen permeation therethrough and including a channel region vertically between the source region and the drain region. The vertical transistor further includes at least one gate electrode laterally adjacent to the channel region of a semiconductive pillar, and a dielectric material between the semiconductive pillar and the at least one gate electrode. Related devices, electronic systems, and methods are also disclosed.

Description

[0001] Priority claim

[0002] This application claims the benefit of the filing date of U.S. Provisional Patent Application No. 62 / 743,133, filed on October 9, 2018, for "Semiconductor Devices Including Vertical Transistors Having Hydrogen Barrier Materials, and Related Methods." Technical Field

[0003] Embodiments of the present invention relate to the field of semiconductor device design and fabrication. More specifically, embodiments disclosed herein relate to semiconductor device structures including vertical transistors having materials configured to inhibit hydrogen species from permeating therethrough, and to related semiconductor devices, electronic systems, and methods. Background Art

[0004] Memory devices are typically provided as internal integrated circuits in computers or other electronic devices. There are many types of memory, including but not limited to random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), flash memory, and resistance variable memory. Non-limiting examples of resistance variable memory include resistive random access memory (ReRAM), conductive bridge random access memory (conductive bridge RAM), magnetic random access memory (MRAM), phase change material (PCM) memory, phase change random access memory (PCRAM), spin torque transfer random access memory (STTRAM), oxygen vacancy-based memory, and programmable conductor memory.

[0005] A typical memory cell of a memory device includes at least one access device, such as a transistor, and at least one memory storage structure, such as a capacitor.Modern applications of semiconductor devices may employ massive memory cells arranged in memory arrays exhibiting rows and columns of memory cells.

[0006] Capacitors (e.g., sometimes referred to as "cell capacitors" or "storage capacitors") are configured to store a logic state (e.g., a binary value of "0" or "1") defined by the stored charge in the capacitor. Transistors may be referred to in the art as "access transistors." Transistors conventionally include a channel region between a pair of source / drain regions and further include a gate configured to electrically connect the source / drain regions to each other through the channel region. The channel region conventionally includes a semiconductor material, such as silicon.

[0007] Conventional processes for forming conventional memory cells typically include performing a hydrogen annealing process in which one or more features of the fabricated memory cell are exposed to hydrogen while annealing at a low temperature (e.g., less than 450° C.). However, during the hydrogen annealing process, hydrogen may diffuse into the channel region of the access device of the memory cell, thereby degrading the performance and / or reliability of the resulting memory device. Therefore, new methods and structures are needed to reduce or even prevent this undesirable hydrogen diffusion. Summary of the invention

[0008] In some embodiments, a device includes a vertical transistor. The vertical transistor includes a semiconductive pillar including a source region and a drain region each individually including at least one conductive material configured to inhibit hydrogen permeation therethrough, and includes a channel region vertically between the source region and the drain region. The vertical transistor further includes at least one gate electrode laterally adjacent to the channel region of the semiconductive pillar, and a dielectric material between the semiconductive pillar and the at least one gate electrode.

[0009] In an additional embodiment, a device includes a vertical transistor. The vertical transistor includes: a drain region including at least one conductive material configured to inhibit hydrogen permeation therethrough; a semiconductive pillar above the drain region, the semiconductive pillar including: a source region including at least one additional conductive material configured to inhibit hydrogen permeation therethrough; and a channel region vertically interposed between the source region and the drain region; at least one gate electrode laterally adjacent to the channel region of the semiconductive pillar; and a dielectric material laterally interposed between the semiconductive pillar and the at least one gate electrode.

[0010] In a further embodiment, a method of manufacturing a device includes forming a stack, the stack including: a first conductive material; a drain region including a second conductive material above the first conductive material; and a semiconductive material above the second conductive material, the second conductive material being configured to inhibit hydrogen species from permeating therethrough. The semiconductive material is patterned to form a semiconductive pillar. A gate dielectric material and a gate electrode are formed to be laterally adjacent to the semiconductive pillar, the gate dielectric material being interposed between the gate electrode and the semiconductive pillar. An electrically insulating material configured to inhibit hydrogen species from permeating therethrough is formed above the gate dielectric material, the gate electrode, and the semiconductive pillar. An opening is formed in the electrically insulating material to expose an upper surface of the semiconductive pillar. A source region is formed within the opening of the electrically insulating material, the source region including a third conductive material configured to inhibit hydrogen species from permeating therethrough.

[0011] In yet a further embodiment, a method of manufacturing a semiconductor device includes forming a stack including: a first conductive material; a second conductive material over the first conductive material; a semiconductive material over the second conductive material; and a third conductive material over the semiconductive material, wherein each of the second conductive material and the third conductive material is configured to inhibit hydrogen permeation therethrough. At least a portion of the semiconductive material and at least a portion of the third conductive material are selectively removed. A semiconductive pillar including a remaining portion of the semiconductive material and a remaining portion of the third conductive material is formed. A gate dielectric material and a gate electrode are formed to be laterally adjacent to the semiconductive pillar, the gate dielectric material being between the gate electrode and the semiconductive pillar. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a simplified cross-sectional view of a semiconductor device structure according to an embodiment of the present invention;

[0013] Figures 2A to 2F It is the description of the formation Figure 1 Simplified cross-sectional views of various stages of a method for manufacturing a semiconductor device structure;

[0014] Figures 3A to 3G are simplified cross-sectional views illustrating various stages in a method of forming a semiconductor device structure according to an additional embodiment of the present invention;

[0015] Figures 4A to 4I are simplified cross-sectional views illustrating various stages of another fabrication process for forming a semiconductor device structure in accordance with a further embodiment of the present invention; and

[0016] Figure 5 is a schematic block diagram illustrating an electronic system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The diagrams contained herein are not intended to be actual views of any particular system, semiconductor structure, or semiconductor device, but are merely idealized representations used to describe the embodiments herein. Elements and features common between the figures may retain the same numerical designations, except in the following cases: To facilitate following the description, in most cases, the reference number begins with the number of the figure on which the element is introduced or most fully described.

[0018] The following description provides specific details (such as material type, material thickness, and processing conditions) in order to provide a thorough description of the embodiments described herein. However, it will be understood by a person of ordinary skill in the art that the embodiments disclosed herein may be practiced without adopting these specific details. In fact, the embodiments may be practiced in conjunction with conventional manufacturing techniques employed in the semiconductor industry. In addition, the description provided herein does not form a complete description of a semiconductor device structure, a complete description of the tools used during the processing of a semiconductor device structure, or a complete description of a process flow for manufacturing a semiconductor device. The structures described below do not form a complete semiconductor device structure, or a tool or system for processing a semiconductor device structure. Only those process actions and structures necessary for understanding the embodiments described herein are described in detail below. Additional actions to form a complete semiconductor device structure or a tool or system for processing a semiconductor device structure may be performed by conventional techniques.

[0019] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and encompasses to the extent that one of ordinary skill in the art would understand that the given parameter, property, or condition meets a degree of variance (e.g., within acceptable manufacturing tolerances). By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be met by at least 90.0%, met by at least 95.0%, met by at least 99.0%, even met by at least 99.9%, or even met by 100.0%.

[0020] As used herein, "about" or "approximately" with respect to a numerical value of a particular parameter includes the numerical value and a degree of difference from the numerical value within an acceptable tolerance for the particular parameter as would be understood by one of ordinary skill in the art. For example, "about" or "approximately" with respect to a numerical value may include additional numerical values ​​within a range from 90.0% to 110.0% of the numerical value (e.g., within a range from 95.0% to 105.0% of the numerical value, within a range from 97.5% to 102.5% of the numerical value, within a range from 99.0% to 101.0% of the numerical value, within a range from 99.5% to 100.5% of the numerical value, or within a range from 99.9% to 100.1% of the numerical value).

[0021] As used herein, spatially relative terms (e.g., "below," "beneath," "lower," "bottom," "above," "up," "top," "front," "rear," "left," "right," etc.) may be used for ease of description to describe the relationship of one element or feature to another element or features as illustrated in the figures. Unless otherwise specified, the spatially relative terms are intended to encompass different material orientations other than the orientation depicted in the figures. For example, if the material in the figure is reversed, an element described as being "below" or "below" or "under" or "on the bottom" of other elements or features would then be oriented "above" or "on the top" of the other elements or features. Thus, the term "below" may encompass both above and below orientations, depending on the context in which the term is used, as will be apparent to one of ordinary skill in the art. The material may be oriented in other ways (e.g., rotated 90 degrees, reversed, flipped, etc.) and the spatially relative descriptors used herein interpreted accordingly.

[0022] As used herein, "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] As used herein, the term "configured" refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device to facilitate operation of the one or more of the structure and the device in a predetermined manner.

[0024] According to embodiments described herein, a semiconductor device includes a vertical transistor. The vertical transistor includes a semiconductive pillar including a source region and a drain region each individually including at least one conductive material configured to inhibit hydrogen permeation therethrough, and includes a channel region vertically between the source region and the drain region. The vertical transistor further includes at least one gate electrode laterally adjacent to the channel region of the semiconductive pillar, and a dielectric material between the semiconductive pillar and the at least one gate electrode.

[0025] According to additional embodiments described herein, the vertical transistor of the semiconductor device includes a drain region and a semiconductive pillar above the drain region. The drain region includes at least one conductive material configured to inhibit hydrogen permeation therethrough. The semiconductive pillar includes: a source region, the source region including at least one additional conductive material configured to inhibit hydrogen permeation therethrough; and a channel region vertically interposed between the source region and the drain region. The vertical transistor further includes: at least one gate electrode laterally adjacent to the channel region of the semiconductive pillar; and a dielectric material interposed between the semiconductive pillar and the at least one gate electrode.

[0026] A method for manufacturing a semiconductor device according to an embodiment of the present invention includes forming a stack, the stack including: a first conductive material; a drain region including a second conductive material above the first conductive material; and a semiconductive material above the second conductive material. The method further includes: patterning the semiconductive material to form a semiconductive pillar; and forming a gate electrode laterally adjacent to the semiconductive pillar and a gate dielectric material between the gate electrode and the semiconductive pillar. The method also includes: forming an electrically insulating material configured to inhibit hydrogen species from permeating therethrough over the gate dielectric material, the gate electrode, and the semiconductive pillar; and forming an opening in the electrically insulating material to expose an upper surface of the semiconductive pillar. A source region including a third conductive material configured to inhibit hydrogen species from permeating therethrough is formed within the opening of the electrically insulating material. The second conductive material and the third conductive material are each configured to inhibit hydrogen species from permeating therethrough.

[0027] A method of manufacturing a semiconductor device according to an additional embodiment of the present invention includes forming a stack, the stack including: a first conductive material; a second conductive material, which is above the first conductive material; a semiconductive material, which is above the second conductive material; and a third conductive material, which is above the semiconductive material. The second conductive material and the third conductive material are each configured to inhibit hydrogen species from permeating therethrough. At least a portion of the semiconductive material and at least a portion of the third conductive material are selectively removed, and a semiconductive pillar including a remaining portion of the semiconductive material and a remaining portion of the third conductive material is formed. The method also includes forming a gate electrode laterally adjacent to the semiconductive pillar and a gate dielectric material between the gate electrode and the semiconductive pillar.

[0028] Figure 1 A simplified cross-sectional view of a semiconductor device structure 140 according to an embodiment of the present invention is illustrated. The semiconductor device structure 140 includes a digital line 104 (e.g., a data line, a bit line) overlying an electrically insulating material 102. The electrically insulating material 102 includes a material configured to inhibit hydrogen from penetrating into a channel region of a transistor of the semiconductor device structure 140 during a hydrogen annealing step. Therefore, the electrically insulating material 102 may also be referred to herein as a barrier material. The electrically insulating material 102 may include one or more of the following: boron nitride (BN), boron nitride carbon (BCN), silicon aluminum oxynitride (SiAlON), silicon carbide (SiC), silicon nitride carbon (SiCN), silicon nitride (SiN), silicon aluminum nitride (SiAlN), aluminum oxynitride (AlON), and aluminum oxide (Al2O3). In some embodiments, the electrically insulating material 102 includes aluminum oxide (Al2O3).

[0029] The vertical transistor 130 overlies the digit line 104. The vertical transistor 130 includes a semiconductive pillar 101, wherein the semiconductive pillar 101 includes a drain region 106, a source region 108, and a channel region 110 vertically disposed between the drain region 106 and the source region 108. Figure 1 , the digit line 104 is electrically connected to the drain region 106 of the semiconductive pillar 101. In addition, the vertical transistor 130 further includes a gate dielectric material 112 at least partially surrounding the lateral surface of the semiconductive pillar 101, and one or more gate electrodes 114 (e.g., word lines) laterally adjacent to the gate dielectric material 112. The gate dielectric material 112 may be laterally interposed between the gate electrode 114 and the channel region 110 of the semiconductive pillar 101.

[0030] Digital line 104 may include a conductive material such as, for example, tungsten, titanium, nickel, platinum, rhodium, ruthenium, aluminum, copper, molybdenum, iridium, silver, gold, metal alloys; metal-containing materials (e.g., metal nitrides, metal silicides, metal carbides, metal oxides); including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrO x ), ruthenium oxide (RuO x ), or at least one of their alloys; conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.); polysilicon; other materials exhibiting conductivity, or a combination thereof.

[0031] The channel region 110 of the semiconductive pillar 101 may include a semiconductive material 109 (eg, a semiconductor material 109 configured and arranged to conduct current in response to applying a voltage (eg, a threshold voltage, a set bias voltage, a read bias voltage) to the vertical transistor 130. Figure 2A For example, the channel region 110 may include a semiconductive material having a band gap greater than that of polysilicon (e.g., a band gap greater than 1.65 electron volts (eV)). In some embodiments, the channel region 110 includes an oxide semiconductor material such as, for example, zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO x ), Indium Gallium Zinc Oxide (IGZO), Indium Gallium Silicon Oxide (IGSO), Indium Oxide (InO x , In2O3), tin oxide (SnO2), titanium oxide (TiO x ), zinc oxynitride (Zn x O y N z ), magnesium zinc oxide (Mg x Zn y O z ), Indium Zinc Oxide (In x Zn y Oz ), Indium Gallium Zinc Oxide (In x Ga y Zn z O a ), zirconium indium zinc oxide (Zr x In y Zn z O a ), Hafnium Indium Zinc Oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum tin indium zinc oxide (Al x Sn y In z Zn a O d ), Silicon Indium Zinc Oxide (Si x In y Zn z O a ), zinc tin oxide (Zn x Sn y O z ), aluminum zinc tin oxide (Al x Zn y Sn z O a ), gallium zinc tin oxide (Ga x Zn y Sn z O a ), zirconium zinc tin oxide (Zr x Zn y Sn z O a ), indium gallium silicon oxide (InGaSiO) and other similar materials. In some embodiments, the channel region 110 includes IGZO.

[0032] The drain region 106 and the source region 108 of the semiconductive pillar 101 may each individually include at least one conductive material. The conductive material may be configured to inhibit hydrogen from penetrating therethrough during the hydrogen annealing step. In some embodiments, the drain region 106 and the source region 108 are each substantially homogeneous. For example, the drain region 106 and the source region 108 may each individually be formed by a single (e.g., only one) material having a substantially uniform (e.g., non-variable) composition throughout its dimensions (e.g., lateral dimensions, vertical dimensions). In other embodiments, at least one (e.g., each) of the drain region 106 and the source region 108 is inhomogeneous. For example, one or more of the drain region 106 and the source region 108 may have a substantially non-uniform (e.g., variable) material composition throughout its dimensions (e.g., lateral dimensions, vertical dimensions). In some embodiments, one or more of the drain region 106 and the source region 108 include a composite structure including a stack (eg, a buildup) of two or more (eg, three or more) different conductive barrier materials configured to inhibit hydrogen permeation therethrough.

[0033] For example, Figure 1 As illustrated in , the drain region 106 and the source region 108 may each individually include a stack of conductive materials, including a first barrier material 103, a second barrier material 105, and a third barrier material 107. The barrier materials 103, 105, 107 of the drain region 106 may be arranged in a different order than the barrier materials 103, 105, 107 of the source region 108, such that, for example, the barrier materials 103, 105, 107 of the drain region 106 may be arranged in an inverted order relative to the barrier materials 103, 105, 107 of the source region 108, as shown in FIG. Figure 1 . In additional embodiments, the first, second and third barrier materials 103, 105, 107 may be arranged in any other order to form the drain region 106 and the source region 108, respectively. In further embodiments, the drain region 106 may include one or more barrier materials not included in the source region 108, or vice versa. In some embodiments, the first barrier material 103 includes elemental iridium (Ir), the second barrier material 105 includes iridium oxide (IrO2), and the third barrier material 107 includes titanium aluminum nitride (TiAlN). In other embodiments, one or more of the drain region 106 and the source region 108 are inhomogeneous and include a stack including elemental iridium (Ir) and iridium oxide (IrO2). In further embodiments, one or more of the drain region 106 and the source region 108 are substantially homogeneous and include titanium aluminum nitride (TiAlN).

[0034] Each of the drain region 106 and the source region 108 may be formed to have a thickness from about To date (For example, from about To date Or from about To date ). In some embodiments, the drain region 106 and the source region 108 are formed to have different thicknesses from each other. In other embodiments, the drain region 106 and the source region 108 are formed to have the same thickness.

[0035] The gate dielectric material 112 may include one or more electrically insulating materials, such as phosphosilicate glass, borosilicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass, silicon dioxide, titanium dioxide, zirconium dioxide, hafnium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, niobium oxide, molybdenum oxide, strontium oxide, barium oxide, yttrium oxide, a nitride material (e.g., silicon nitride (Si3N4)), an oxynitride (e.g., silicon oxynitride), another gate dielectric material, a dielectric carbonitride material (e.g., silicon carbon nitride (SiCN)), a dielectric carbon oxynitride material (e.g., silicon oxycarbonitride (SiOCN)), another material, or a combination thereof.

[0036] Gate electrode material 113 ( Figure 2C ) may include one or more conductive materials, such as, for example, tungsten, titanium, nickel, platinum, ruthenium, aluminum, copper, molybdenum, gold, metal alloys; metal-containing materials (e.g., metal nitrides, metal silicides, metal carbides, metal oxides); including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), elemental titanium (Ti), elemental platinum (Pt), elemental rhodium (Rh), elemental ruthenium (Ru), elemental molybdenum (Mo), elemental iridium (Ir), iridium oxide (IrO x ), ruthenium oxide (RuO x ), elemental tungsten (W), elemental aluminum (Al), elemental copper (Cu), elemental gold (Au), elemental silver (Ag), polycrystalline silicon, and at least one of their alloys; conductive doped semiconductor materials (for example, conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.); polycrystalline silicon; other materials exhibiting conductivity or a combination thereof.

[0037] like Figure 1, another electrically insulating material 116 may at least partially surround lateral surfaces of the gate electrode 114 and the gate dielectric material 112. The electrically insulating material 116 may fill the space between adjacent gate electrodes 114 of adjacent vertical transistors 130. In some embodiments, the electrically insulating material 116 comprises the same material composition as the electrically insulating material 102 and the gate dielectric material 112. In other embodiments, one or more of the electrically insulating material 116, the electrically insulating material 102, and the gate dielectric material 112 comprises a different material composition than one or more others of the electrically insulating material 116, the electrically insulating material 102, and the gate dielectric material 112.

[0038] like Figure 1 , in some embodiments, a first portion of another electrically insulating material 118 overlies vertical transistor 130, another electrically insulating material 120 overlies electrically insulating material 118, and a second portion of another electrically insulating material 118 overlies another electrically insulating material 120. In other embodiments, the first portion of another electrically insulating material 118 is omitted. For example, additional electrically insulating material 120 may overlie vertical transistor 130, and the entire other electrically insulating material 118 overlies additional electrically insulating material 120. Additional electrically insulating material 120 may include a barrier material configured to inhibit hydrogen from permeating therethrough during a hydrogen annealing step. The material composition of additional electrically insulating material 120 may be substantially the same as or different from the material composition of electrically insulating material 102. Therefore, the channel region 110 of the semiconductive pillar 101 of the vertical transistor 130 can be surrounded (for example, encapsulated) by the drain region 106 and the source region 108 of the semiconductive pillar 101 and the electrically insulating material 102 and the additional electrically insulating material 120 and is substantially protected by the drain region 106 and the source region 108 of the semiconductive pillar 101 and the electrically insulating material 102 and the additional electrically insulating material 120 from the penetration of hydrogen species.

[0039] Continue to refer Figure 1 , the semiconductor device structure 140 may further include a conductive material 122 (e.g., a conductive contact material) filling an opening 124 extending through the other electrically insulating material 118 and the additional electrically insulating material 120. For example, the conductive material 122 may electrically couple the source region 108 of the vertical transistor 130 to a conductive line structure (e.g., a source line).

[0040] Figures 2A to 2F Describe the formation of some embodiments according to the present invention Figure 1 The various stages of the manufacturing process of the semiconductor device structure 140 are shown in FIG. Figure 2A The stacked structure 200 may be formed to include an electrically insulating material 102, a digit line 104 formed above the electrically insulating material 102, and a drain region 106 formed above the electrically insulating material 102. Figure 1 ) of the conductive barrier materials 103, 105, 107, one or more (for example, each) of the conductive barrier materials 103, 105, 107, becomes a channel region 110 ( Figure 1 ) of a semiconductive material 109 and forming a source region 108 ( Figure 1 ) of one or more (e.g., each) of the conductive barrier materials 103, 105, 107.

[0041] refer to Figure 2B , so that the stacked structure 200( Figure 2A ) is subjected to at least one material removal process (eg, at least one etching process) to form a semiconducting pillar 101 including a drain region 106, a channel region 110, and a source region 108. Figure 2B As shown in , the material removal process may expose the upper surface 126 of the digit line 104 .

[0042] Next reference Figure 2C , a gate dielectric material 112 may be formed (e.g., conformally formed) over the upper surface 126 of the digit line 104 and the surface (e.g., upper surface, side surface) of the semiconductive pillar 101. The gate dielectric material 112 may be formed by, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), another deposition method, or a combination thereof. After forming the gate dielectric material 112, a gate electrode 114 ( Figure 1 ) of gate electrode material 113.

[0043] refer to Figure 2D , the gate electrode material 113 can be patterned ( Figure 2C ) and gate dielectric material 112 to form a vertical transistor 130 including a semiconducting pillar 101, a gate dielectric material 112 and a gate electrode 114. The gate dielectric material 112 and the gate electrode material 113 ( Figure 2C ) can be patterned using conventional processes (e.g., chemical mechanical planarization processes, etching processes) not described in detail herein.

[0044] Next reference Figure 2E, an electrically insulating material 116 may be formed over at least a portion of the gate electrode 114 and the gate dielectric material 112. The electrically insulating material 116 may fill the space between adjacent gate electrodes 114 of adjacent vertical transistors 130. The electrically insulating material 116 may be formed using conventional processes (e.g., conventional material deposition processes, conventional chemical mechanical planarization (CMP) processes) that are not described in detail herein.

[0045] Next reference Figure 2F , another electrically insulating material 118 and additional electrically insulating material 120 may be formed (e.g., deposited) over vertical transistor 130 and electrically insulating material 116, and portions of electrically insulating material 118 and additional electrically insulating material 120 may then be selectively removed to form opening 124. Conductive material 122 ( Figure 1 ) fills the opening 124 to form a semiconductor device structure 140 ( Figure 1 The further electrically insulating material 118 , the additional electrically insulating material 120 , and the opening 124 may be formed using conventional processes (eg, conventional material deposition processes, conventional etching processes) which are not described in detail herein.

[0046] Figures 3A to 3G 1 is a simplified cross-sectional view illustrating various stages of a manufacturing process for forming a semiconductor device structure according to an additional embodiment of the present invention. Throughout the remaining description and drawings, functionally similar features (e.g., structures, devices) are referred to by similar reference numerals incremented by 100. To avoid repetition, not all features shown in the remaining figures are described in detail herein. Rather, unless otherwise described below, features designated by reference numerals that are increments of 100 of the reference numeral of a previously described feature (whether the previously described feature is first described before this paragraph, or first described after this paragraph) will be understood to be substantially similar to the previously described feature.

[0047] refer to Figure 3A , forming a material stack 300 to include an electrically insulating material 302, a digit line 304 above the electrically insulating material 302, a drain region 306 including one or more (e.g., each) of conductive barrier materials 303, 305, 307 above the digit line 304, and a channel region 310 ( Figure 3B ) and forming a source region 308 ( Figure 3B ) of one or more (e.g., each) of the conductive barrier materials 303, 305, 307.

[0048] refer to Figure 3B, subjecting the stack 300 to at least one material removal process (eg, at least one etching process) to form a semiconducting pillar 301 including a source region 308 and a channel region 310. Figure 3B , the material removal process may expose the upper surface 311 of the drain region 306. In some embodiments, one or more conductive barrier materials 303, 305, 307 of the drain region 306 are substantially maintained above the digit line 304 during the removal process and are not removed. Figure 3B As shown in , digit line 304 is in electrical communication with a drain region 306 that extends continuously over digit line 304 .

[0049] Next reference Figure 3C A gate dielectric material 312 may be formed (e.g., conformally formed) above the upper surface 311 of the drain region 306 and the surface (e.g., upper surface, side surface) of the semiconductive pillar 301. After the gate dielectric material 312 is formed, a gate electrode 314 ( Figure 3D ) of the gate electrode material 313. In some embodiments, the gate dielectric material 312 is formed by Figure 2C The crystalline silicon substrate may be formed by one or more deposition processes as described.

[0050] Next reference Figure 3D , the gate electrode material 313 may be patterned ( Figure 3C ) and gate dielectric material 312 to form a vertical transistor 330 ( Figure 3E ), the vertical transistor 330 includes a semiconductive pillar 301 (including a source region 308 and a channel region 310), a drain region 306, a gate electrode 314 laterally adjacent to the channel region 310 of the semiconductive pillar 301, and a gate dielectric material 312 extending between the gate electrode 314 and each of the semiconductive pillar 301 and the drain region 306. The gate electrode material 313 and the gate dielectric material 312 can be patterned using conventional processes (e.g., CMP processes, etching processes) not described in detail herein.

[0051] Next reference Figure 3E , an electrically insulating material 316 may be formed (e.g., selectively formed) over at least a portion of the gate electrode 314 and the gate dielectric material 312. The electrically insulating material 316 may fill the space between adjacent gate electrodes 314 of adjacent vertical transistors. The electrically insulating material 316 may be patterned using conventional processes (e.g., CMP processes, etching processes) not described in detail herein.

[0052] Next reference Figure 3F, a first portion of another electrically insulating material 318 may be formed (e.g., deposited) over vertical transistor 330, an additional electrically insulating material 320 may be formed over the first portion of another electrically insulating material 318, and a second portion of another electrically insulating material 318 may be formed over another electrically insulating material 320. In other embodiments, the first portion of another electrically insulating material 318 is omitted, additional electrically insulating material 320 may overlie vertical transistor 330, and the entire another electrically insulating material 318 overlies additional electrically insulating material 320. Additional electrically insulating material 320 may include a barrier material configured to inhibit hydrogen from permeating therethrough during the hydrogen annealing step.

[0053] Continue to refer Figure 3F , at least a portion of the other electrically insulating material 318 and the additional electrically insulating material 320 may be selectively removed to form an opening 324 .

[0054] Next reference Figure 3G The opening 324 may then be filled with a conductive material 322 to form a semiconductor device structure 340. A conductive line structure (eg, a source line) may then be electrically coupled to the source region 308 of the vertical transistor 330 through the conductive material 322.

[0055] After forming semiconductor device structure 340, semiconductor device structure 340 may be subjected to a hydrogen annealing process. During the hydrogen annealing process, channel region 310 is surrounded (e.g., encapsulated) by drain region 306, source region 308, electrically insulating material 302, and additional electrically insulating material 320 and protected from penetration of hydrogen species by drain region 306, source region 308, electrically insulating material 302, and additional electrically insulating material 320. Because drain region 306 is maintained in semiconductor device structure 340 and remains unetched, the method of forming semiconductor device structure 340 is simplified by reducing the number of etching steps that must be performed. Furthermore, drain region 306 provides extended protection to channel region 310 from hydrogen species that may diffuse through digit line 304 and gate dielectric material 312 during the hydrogen annealing process.

[0056] Figures 4A to 4I is a simplified cross-sectional view illustrating various stages of a fabrication process for forming a semiconductor device structure in accordance with a further embodiment of the present invention. Figure 4A , material stack 400 includes an electrically insulating material 402, a digit line 404 above the electrically insulating material 402, a drain region 406 including one or more (e.g., each) of conductive barrier materials 403, 405, 407 above the digit line 404, and a channel region 410 ( Figure 4B ) of semiconductive material 409.

[0057] refer to Figure 4B , making the stack 400 ( Figure 4A ) is subjected to at least one material removal process (eg, at least one etching process) to form a semiconducting pillar 401 including a channel region 410. Figure 4B , the material removal process may expose at least a portion of the upper surface 411 of the drain region 406. The drain region 406 remains above the digit line 404 during the material removal. Figure 4B As shown in , digit line 404 is in electrical communication with a drain region 406 that extends continuously over digit line 404 .

[0058] Next reference Figure 4C A gate dielectric material 412 may be formed (e.g., conformally formed) over at least a portion of an upper surface 411 of the drain region 406 and a surface (e.g., an upper surface, a side surface) of the semiconductive pillar 401. After the gate dielectric material 412 is formed, a gate electrode 414 ( Figure 4D ) of gate electrode material 413.

[0059] Next reference Figure 4D , the gate electrode material 413 may be patterned ( Figure 4C ) and gate dielectric material 412 to expose the upper surface 419 of the channel region 410 and form a gate electrode 414. The gate electrode material 413 and the gate dielectric material 412 may be patterned using conventional processes (eg, CMP processes, etching processes) not described in detail herein.

[0060] Continue to refer Figure 4D , an electrically insulating material 416 may be formed over the gate dielectric material 412, the gate electrode 414, and the upper surface 419 of the semiconductive pillar 401. The electrically insulating material 416 may fill the space between adjacent gate electrodes 414 of adjacent vertical transistors. In other embodiments, the electrically insulating material 416 is not formed over one or more upper surfaces of the gate dielectric material 412, the gate electrode 414, and the semiconductive pillar 401, such as by Figure 4D As indicated by the dotted line in .

[0061] Next reference Figure 4E, in embodiments where electrically insulating material 416 is formed over upper surface 419, a portion of electrically insulating material 416 may be removed to form openings 423 therein that expose upper surface 419 of channel region 410. In other embodiments, additional electrically insulating material 420 may optionally (as indicated by dashed lines) be formed over gate dielectric material 412, gate electrode 414, and semiconductive pillar 401. In such embodiments, a portion of additional electrically insulating material 420 may be removed to form openings 423 therein that expose upper surface 419 of channel region 410.

[0062] Then, if Figure 4F As shown in FIG. 4 , the remaining portion of electrically insulating material 416 or the remaining portion of additional electrically insulating material 420 may be above opening 423 ( Figure 4E ) is formed above the channel region 410 within one or more conductive barrier materials 403, 405, 407.

[0063] Next reference Figure 4G , the barrier materials 403, 405, 407 may be subjected to at least one material removal process to remove at least a portion of the barrier materials 403, 405, 407 outside the opening 423 and form a source region 408. Figure 4G As shown in , forming the source region 408 can form a vertical transistor 430, which includes the source region 408, the channel region 410, the drain region 406, a gate electrode 414 laterally adjacent to the channel region 410, and a gate dielectric material 412 extending between the gate electrode 414 and each of the channel region 410 and the drain region 406.

[0064] Next reference Figure 4H , another electrically insulating material 418 may be formed (eg, deposited) over the vertical transistor 430 and the electrically insulating material 420 , and then portions of the another electrically insulating material 418 may be selectively removed to form an opening 424 .

[0065] Next reference Fig. 4I , the opening 424 may then be filled with a conductive material 422 ( Figure 4H ) to form a semiconductor device structure 440. Conductive material 422 may be employed to electrically couple the source region 408 of the vertical transistor 430 to a conductive line structure (eg, a source line).

[0066] After forming semiconductor device structure 440, semiconductor device structure 440 may be subjected to a hydrogen annealing process. Channel region 410 of vertical transistor 430 may be surrounded (e.g., encapsulated) by drain region 406, source region 408, electrically insulating material 416, and electrically insulating material 402 and protected from penetration of hydrogen species by drain region 406, source region 408, electrically insulating material 416, and electrically insulating material 402. Because drain region 406 is maintained in semiconductor device structure 440 and remains unetched and because etching is not required to form source region 408, the method of forming semiconductor device structure 440 is simplified by reducing the number of etching steps that must be performed. Furthermore, drain region 406 provides extended protection to channel region 410 from hydrogen species that may diffuse through digit line 404 and gate dielectric material 412 during the hydrogen annealing process.

[0067] According to an embodiment of the present invention, a semiconductor device structure (eg, previously referred to as Figure 1 , 3G 4I) can be used in embodiments of the electronic system of the present invention. For example, Figure 5 5 is a block diagram of an illustrative electronic system 550 according to an embodiment of the present invention. For example, electronic system 550 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular enabled tablet computer (e.g., or The electronic system 550 includes at least one memory device 555. The at least one memory device 555 may include, for example, an embodiment including a semiconductor device structure (e.g., structures 140, 340, 440 previously described herein). The electronic system 550 may further include at least one electronic signal processor device 560 (commonly referred to as a "microprocessor"). The electronic system 550 may further include one or more input devices 565 for inputting information into the electronic system 550 by a user, such as, for example, a mouse or other pointing device, a keyboard, a touch pad, buttons, or a control panel. The electronic system 550 may further include one or more output devices 570 for outputting information (e.g., visual or audio output) to the user, such as, for example, a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device 565 and the output device 570 may include a single touch screen device that can be used to both input information to the electronic system 550 and output visual information to the user. One or more input devices 565 and output devices 570 may be in electronic communication with at least one of the memory device 555 and the electronic signal processor device 560 .

[0068] Additional non-limiting example embodiments of the invention are described below.

[0069] Embodiment 1: A device comprising a vertical transistor, the vertical transistor comprising: a semiconductive pillar comprising: a source region and a drain region, each of which individually comprises at least one conductive material configured to inhibit hydrogen permeation therethrough; and a channel region vertically interposed between the source region and the drain region; at least one gate electrode laterally adjacent to the channel region of the semiconductive pillar; and a dielectric material laterally interposed between the semiconductive pillar and the at least one gate electrode.

[0070] Embodiment 2: The device of Embodiment 1, wherein at least one of the source region and the drain region is inhomogeneous.

[0071] Embodiment 3: The device of any one of embodiments 1 and 2, wherein the at least one conductive material of at least one of the source region and the drain region comprises the elements Ir, IrO, x and one or more of TiAlN.

[0072] Embodiment 4: The device of any one of embodiments 1 and 2, wherein the at least one conductive material of at least one of the source region and the drain region comprises elements Ir and IrO x .

[0073] Embodiment 5: The device of any of Embodiments 1 and 2, wherein the at least one conductive material of at least one of the source region and the drain region comprises TiAlN.

[0074] Embodiment 6: The device of any one of embodiments 1 to 5, wherein the source region and the drain region each individually have a width from about To date The thickness is within the range of .

[0075] Embodiment 7: The device of any one of embodiments 1 to 6, wherein the source region and the drain region have different material compositions from each other.

[0076] Embodiment 8: The device of any one of embodiments 1 to 7, wherein the channel region comprises ZTO, IZO, ZnO x , IGZO, IGSO, InO x 、In2O3、SnO2、TiO x 、Zn x O y N z Mg x Zn y O z 、In x Zn y O z 、In x Ga y Zn z O a 、Zr x In y Zn z O a , Hf x In y Zn z O a Sn x In y Zn z O a 、Al x Sn y In z Zn a O d 、Si x In y Zn z O a 、Zn x Sn y O z 、Al x Zn y Sn z Oa , Ga x Zn y Sn z O a 、Zr x Zn y Sn z O a and one or more of InGaSiO.

[0077] Embodiment 9: The device of any one of embodiments 1 to 7, wherein the channel region comprises IGZO.

[0078] Embodiment 10: The device of any of Embodiments 1-9, wherein an electrically insulating material configured to inhibit permeation of hydrogen therethrough overlies at least a portion of the vertical transistor.

[0079] Embodiment 11: The device of Embodiment 10, wherein the electrically insulating material comprises Al2O3.

[0080] Embodiment 12: The device of any of embodiments 10 and 11, further comprising a digit line overlying the electrically insulating material and in electrical communication with the semiconducting support.

[0081] Embodiment 13: A device comprising a vertical transistor, the vertical transistor comprising: a drain region, the drain region comprising at least one conductive material configured to inhibit hydrogen permeation therethrough; a semiconductive pillar, which is above the drain region, the semiconductive pillar comprising: a source region, the source region comprising at least one additional conductive material configured to inhibit hydrogen permeation therethrough; and a channel region, which is vertically between the source region and the drain region; and at least one gate electrode, which is laterally adjacent to the channel region of the semiconductive pillar; and a dielectric material, which is laterally between the semiconductive pillar and the at least one gate electrode.

[0082] Embodiment 14: The device of Embodiment 13, further comprising an electrically insulating material over the vertical transistor, the electrically insulating material configured to inhibit permeation of hydrogen gas therethrough.

[0083] Embodiment 15: The device of any of Embodiments 13 and 14, wherein the drain region extends continuously over a digit line.

[0084] Embodiment 16: A method for manufacturing a device, comprising: forming a stack, the stack comprising: a first conductive material; a drain region comprising a second conductive material above the first conductive material; and a semiconductive material above the second conductive material, the second conductive material being configured to inhibit hydrogen species from penetrating therethrough; patterning the semiconductive material to form a semiconductive pillar; forming a gate dielectric material and a gate electrode to be laterally adjacent to the semiconductive pillar, the gate dielectric material being between the gate electrode and the semiconductive pillar; forming an electrically insulating material configured to inhibit hydrogen species from penetrating therethrough above the gate dielectric material, the gate electrode, and the semiconductive pillar; forming an opening in the electrically insulating material to expose the upper surface of the semiconductive pillar; and forming a source region within the opening in the electrically insulating material, the source region comprising a third conductive material configured to inhibit hydrogen species from penetrating therethrough.

[0085] Embodiment 17: The method of Embodiment 16, further comprising selecting at least one of the second conductive material and the third conductive material to include Ir and IrO x .

[0086] Embodiment 18: The method of Embodiment 16, further comprising selecting at least one of the second conductive material and the third conductive material to include the elements Ir, IrO, x and one or more of TiAlN.

[0087] Embodiment 19: The method of Embodiment 18, further comprising selecting the second conductive material and the third conductive material to have different material compositions from each other.

[0088] Embodiment 20: A method of manufacturing a device, comprising: forming a stack, the stack comprising: a first conductive material; a second conductive material, which is above the first conductive material; a semiconductive material, which is above the second conductive material; and a third conductive material, which is above the semiconductive material, wherein each of the second conductive material and the third conductive material is configured to inhibit hydrogen from permeating therethrough; selectively removing at least a portion of the semiconductive material and at least a portion of the third conductive material; forming a semiconductive pillar comprising a remaining portion of the semiconductive material and a remaining portion of the third conductive material; and forming a gate dielectric material and a gate electrode to be laterally adjacent to the semiconductive pillar, the gate dielectric material being between the gate electrode and the semiconductive pillar.

[0089] Embodiment 21: The method of Embodiment 20, further comprising: selecting one of the first conductive material and the second conductive material to include TiAlN; and selecting the other of the first conductive material and the second conductive material to include a stack of elements Ir and IrO2.

[0090] Embodiment 22: The method of Embodiment 20, further comprising selecting the first conductive material to include one or more of BN, BCN, SiAlON, SiC, SiCN, SiN, SiAlN, AlON, and Al2O3.

[0091] Embodiment 23: The method of any one of embodiments 20 to 22, further comprising selecting the semiconductive material to include ZTO, IZO, ZnO x , IGZO, IGSO, InO x 、In2O3、SnO2、TiO x 、Zn x O y N z Mg x Zn y O z 、In x Zn y O z 、In x Ga y Zn z O a 、Zr x In y Zn z O a , Hf x In y Zn z O a Sn x In y Zn z O a 、Al x Sn y In z Zn a O d 、Si x In y Zn z O a 、Zn x Sn y O z 、Al x Zn y Sn z O a , Ga x Zny Sn z O a 、Zr x Zn y Sn z O a and one or more of InGaSiO.

[0092] Although specific illustrative embodiments have been described in conjunction with the figures, those of ordinary skill in the art will recognize and appreciate that the embodiments encompassed by the present invention are not limited to those embodiments explicitly shown and described herein. Rather, many additions, deletions, and modifications to the embodiments described herein may be made without departing from the scope of the embodiments encompassed by the present invention (such as the scope claimed below, including legal equivalents). In addition, features from one disclosed embodiment may be combined with features of another disclosed embodiment while still being encompassed within the scope of the present invention.

Claims

1. A semiconductor device comprising: A vertical transistor comprising: A semiconductive structure comprising: a source region and a drain region, the source region and the drain region each individually comprising at least one conductive material configured to inhibit permeation of hydrogen gas therethrough, wherein the at least one conductive material in the drain region includes a conductive material not included in the source region; and a channel region vertically disposed between the source region and the drain region; at least one gate electrode laterally adjacent to the channel region of the semiconducting structure; and A dielectric material is laterally interposed between the semiconducting structure and the at least one gate electrode. 2 . The semiconductor device of claim 1 , wherein at least one of the source region and the drain region is inhomogeneous.

3. The semiconductor device of claim 1 , wherein the at least one conductive material in one or more of the source region and the drain region comprises the elements Ir, IrO, x and one or more of TiAlN.

4. The semiconductor device of claim 1 , wherein the at least one conductive material in one or more of the source region and the drain region comprises elements Ir and IrO. x . 5 . The semiconductor device of claim 1 , wherein the at least one conductive material of one or more of the source region and the drain region comprises TiAlN.

6. The semiconductor device according to claim 1, wherein the source region and the drain region each have a arrive The thickness is within the range of . 7 . The semiconductor device according to claim 1 , wherein the source region and the drain region have different material compositions from each other.

8. The semiconductor device of claim 1, wherein the channel region comprises one or more of zinc tin oxide, indium zinc oxide, zinc oxide, indium gallium zinc oxide, indium gallium silicon oxide, indium oxide, tin oxide, titanium oxide, zinc oxynitride, magnesium zinc oxide, zirconium indium zinc oxide, hafnium indium zinc oxide, tin indium zinc oxide, aluminum tin indium zinc oxide, silicon indium zinc oxide, zinc tin oxide, aluminum zinc tin oxide, gallium zinc tin oxide, zirconium zinc tin oxide, and indium gallium silicon oxide.

9. The semiconductor device of claim 1, further comprising an electrically insulating material configured to inhibit hydrogen gas from permeating therethrough overlying at least a portion of the vertical transistor.

10. The semiconductor device of claim 9, wherein the electrically insulating material comprises Al2O3.

11. The semiconductor device of claim 9, further comprising a digit line overlying the electrically insulating material and in electrical communication with the semiconductive structure. 12 . The semiconductor device of claim 1 , wherein the semiconductive structure comprises a semiconductive pillar including the source region, the drain region, and the channel region.

13. The semiconductor device according to claim 1, wherein the semiconducting structure comprises: the drain region; and The semiconductive pillar includes the source region and the channel region, and the semiconductive pillar has a lateral dimension smaller than that of the drain region. The semiconductor device according to claim 13 , wherein the drain region extends continuously over a digit line.

15. A method for manufacturing a semiconductor device, comprising: A stack is formed, the stack comprising: a first conductive material; a second conductive material overlying the first conductive material, the second conductive material configured to inhibit permeation of hydrogen species therethrough; a semiconductive material overlying the second conductive material; and a third conductive material overlying the semiconductive material, the third conductive material configured to inhibit permeation of hydrogen species therethrough, wherein the third conductive material is different from the second conductive material; patterning at least the semiconductive material and the third conductive material to form a pillar structure; and A gate dielectric material and a gate electrode are formed to be laterally adjacent to the pillar structure, with the gate dielectric material interposed between the gate electrode and the pillar structure.

16. The method of claim 15, wherein patterning at least the semiconductive material and the third conductive material to form the pillar structure comprises patterning the second conductive material, the semiconductive material, and the third conductive material to form the pillar structure.

17. The method according to claim 15, further comprising: forming an electrically insulating material over the gate dielectric material, the gate electrode, and the pillar structure configured to inhibit permeation of hydrogen species therethrough; and An opening is formed in the electrically insulating material to expose an upper surface of the support structure.

18. The method of claim 15, further comprising selecting the second conductive material to include the elements Ir, IrO x and one or more of TiAlN.

19. The method of claim 15, further comprising selecting the semiconductive material to include one or more of zinc tin oxide, indium zinc oxide, zinc oxide, indium gallium zinc oxide, indium gallium silicon oxide, indium oxide, tin oxide, titanium oxide, zinc oxynitride, magnesium zinc oxide, zirconium indium zinc oxide, hafnium indium zinc oxide, tin indium zinc oxide, aluminum tin indium zinc oxide, silicon indium zinc oxide, zinc tin oxide, aluminum zinc tin oxide, gallium zinc tin oxide, zirconium zinc tin oxide, and indium gallium silicon oxide.

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