Methods and systems for flexible circuits

Abstract

The present invention provides various methods and systems for forming a flexible circuit (1300). In one example, a method includes forming a flexible circuit (1300) that includes a plurality of contact pads (908, 1112, 1122) arranged in a plurality of rows, each contact pad (908, 1112, 1122) in a given row being electrically coupled to each other via an electrical trace (406), and each contact pad including a via hole (902, 1110, 1120), electroplating the flexible circuit (1300) with at least a first material, including electroplating each via hole (902, 1110, 1120), and at least partially cutting (1302, 1304, 1306) at least some of the electrical traces (406) while verifying the connectivity of each via hole.

Description

Technical Field

[0001] Embodiments of the subject matter disclosed herein relate to flexible circuits for ultrasonic transducer arrays and, more particularly, to testing flexible circuit interconnects. Background Art

[0002] Ultrasonic transducer assemblies are commonly used in applications including non-destructive testing (NDE) and medical diagnostic imaging, such as ultrasound applications and computed tomography (CT). An ultrasonic transducer assembly typically includes an ultrasonic transducer array coupled to an array of electronics. The ultrasonic transducer array typically includes hundreds or thousands of individual transducers. Piezoelectric transducers (e.g., PZT) are a widely used type of ultrasonic transducer. Piezoelectric sensors typically include a piezoelectric material capable of changing physical dimensions when subjected to electrical stress or mechanical stress. Additionally, a piezoelectric sensor may include a matching material layer and a damping material layer.

[0003] Similarly, the array of electronics includes hundreds or thousands of integrated interface circuits (or “cells”) that are electrically coupled to provide electrical control of the transducers for beamforming, signal amplification, control functions, signal processing, etc. Specifically, each transducer sub-array in the transducer array is typically coupled to an integrated circuit chip to provide individual control of each sensor. In some examples, communication between the integrated circuit chip and the transducer may occur via a flexible circuit including high density interconnects. Summary of the Invention

[0004] In one embodiment, a method includes forming a flexible circuit that includes a plurality of contact pads arranged in a plurality of rows, each contact pad in a given row being electrically coupled to each other via an electrical trace, and each contact pad including a via hole, electroplating the flexible circuit with at least a first material, including electroplating each via hole, and at least partially cutting at least some of the electrical traces when confirming the connectivity of each via hole.

[0005] It should be understood that the above summary is provided to introduce in a simplified form a selection of concepts that are further described in the detailed description. This is not meant to identify key or essential features of the claimed subject matter, the scope of which is uniquely defined by the claims that follow the detailed description. Furthermore, the claimed subject matter is not limited to embodiments that solve any disadvantages noted above or in any part of this disclosure. Brief Description of the Drawings

[0006] The present invention will be better understood from the following description of non-limiting embodiments read in conjunction with the accompanying drawings, wherein:

[0007] Figure 1 An exemplary ultrasound imaging system in accordance with an embodiment of the present invention is shown.

[0008] Figure 2 An exemplary ultrasonic transducer array is shown.

[0009] Figure 3 A method for forming a flexible circuit for an ultrasonic transducer array is shown.

[0010] Figures 4 to 13 is shown in accordance with Figure 3 a cross-sectional view of a flexible circuit formed by the method, where the flexible circuit is in various stages of forming the flexible circuit.

[0011] Figure 14 is shown in accordance with Figure 3 a top view of an exemplary flexible circuit formed by the method.

[0012] Figure 15 is Figure 13 a partially enlarged view of the flexible circuit.

[0013] Figure 16 and Figure 17 show Figure 13 additional views of the flexible circuit. DETAILED DESCRIPTION

[0014] The following description relates to various embodiments of flexible circuits that may be incorporated in a transducer array of an ultrasonic probe (such as the ultrasonic probe shown in Figure 1 ). Specifically, systems and methods for forming a flexible circuit are provided that include electrical traces that allow testing of the connectivity of a plurality of interconnects (also referred to as vias) of the flexible circuit before the flexible circuit is coupled to one or more transducers of the ultrasonic probe. Examples of a plurality of transducers of the ultrasonic probe are shown in Figure 2 , which shows an acoustic stack component including an ultrasonic transducer coupled to a flexible circuit. A flowchart is shown in Figure 3 , which shows a method for forming a flexible circuit for a transducer array, including testing vias of the flexible circuit. Figures 4 to 13 shows Figure 3 a cross-sectional view of a flexible circuit and / or transducer stack at various stages of the method shown. Figure 14 shows a top view of a flexible circuit including formed electrical traces, where Figure 15 shows Figure 14 a partially enlarged view of the flexible circuit. Figure 16 and Figure 17 show additional layers of the flexible circuit including electrical traces.

[0015] Now turning to Figure 1, showing a block diagram of an ultrasonic imaging system 100 according to an embodiment. As shown, the system 100 includes a plurality of components. These components may be coupled to each other to form a single structure, may be separate but located in a common room, or may be remote from each other. For example, one or more of the modules described herein may operate in a data server that has a different and remote location relative to other components of the system 100 such as the probe and the user interface. Optionally, in the case of an ultrasonic system, the system 100 may be a single system capable of being moved (e.g., portably) from one room to another. For example, the system 100 may include wheels or be transported on a vehicle.

[0016] In the illustrated embodiment, the system 100 includes a transmit beamformer 101 and a transmitter 102 that drives an array of elements 104 (e.g., piezoelectric crystals) within the ultrasonic probe 106 (or transducer) to transmit pulsed ultrasonic signals into the body or volume (not shown) of a subject. Additionally, as further described below, the probe is equipped with one or more actuators 105 that are capable of receiving signals from the system controller 116 in order to output haptic feedback to the user. The elements 104, one or more actuators 105, and the probe 106 may have a variety of geometries. In some examples, one or more of the actuators 105 may be omitted.

[0017] The ultrasonic signals transmitted by the elements 104 are backscattered from internal body structures such as blood vessels and surrounding tissue to produce echoes that return to the elements 104. The echoes are received by the receiver 108. The received echoes are provided to a beamformer 110 that performs beamforming and outputs an RF signal. The RF signal is then provided to an RF processor 112 that processes the RF signal. Alternatively, the RF processor 112 may include a complex demodulator (not shown) that demodulates the RF signal to form an IQ data pair representative of the echo signal. Then, the RF or IQ signal data may be directly provided to the memory 114 for storage (e.g., temporarily).

[0018] The system controller (e.g., an electronic controller) 116 of system 100 includes a plurality of modules, which may be part of a single processing unit (e.g., a processor) or distributed across multiple processing units. The system controller 116 is configured to control the operation of system 100. For example, the system controller 116 may include an image processing module that receives image data (e.g., RF signal data or ultrasound signals in the form of IQ data pairs) and processes the image data. For example, the image processing module may process the ultrasound signals to generate slices or frames of ultrasound information (e.g., an ultrasound image) for display to an operator. In system 100, the image processing module may be configured to perform one or more processing operations according to a plurality of selectable ultrasound modalities of the acquired ultrasound information. By way of example only, the ultrasound modalities may include color flow, acoustic radiation force imaging (ARFI), B-mode, A-mode, M-mode, spectral Doppler, acoustic streaming, tissue Doppler module, C-scan, and elastography. The generated ultrasound image may be two-dimensional (2D) or three-dimensional (3D). When a plurality of two-dimensional (2D) images are obtained, the image processing module may also be configured to stabilize or register the images.

[0019] When an echo signal is received, the acquired ultrasound information may be processed in real time during an imaging session (or a scanning session). In addition or alternatively, the ultrasound information may be temporarily stored in the memory 114 during the imaging session and processed in a sub-real-time manner in real-time or offline operations. An image memory 120 is included for storing processed slices of the acquired ultrasound information that are not scheduled to be displayed immediately. The image memory 120 may include any known data storage medium, e.g., a permanent storage medium, a removable storage medium, etc. Additionally, the image memory 120 may be a non-transitory storage medium.

[0020] In operation, the ultrasound system may acquire data, e.g., a volume data set, by various techniques (e.g., 3D scanning, real-time 3D imaging, volume scanning, 2D scanning using a probe with a positioning sensor, freehand scanning using voxel correlation techniques, scanning using a 2D or matrix array probe, etc.). The ultrasound image of system 100 may be generated (at the system controller 116) from the acquired data and displayed to an operator or user on the display device 118.

[0021] The system controller 116 is operatively connected to a user interface 122 that enables an operator to control at least some operations of the system 100. The user interface 122 can include hardware, firmware, software, or a combination thereof that enables a user (e.g., an operator) to directly or indirectly control the operation of the system 100 and its various components. As shown, the user interface 122 includes a display device 118 having a display area 117. In some embodiments, the user interface 122 can also include one or more input devices 115, such as a physical keyboard, mouse, and / or touchpad. In an exemplary embodiment, the display device 118 is a touch-sensitive display (e.g., a touchscreen) that can detect the presence of a touch by an operator on the display area 117 and can also identify the location of the touch in the display area 117. The touch can be applied by, for example, at least one of an individual's hand, a glove, a stylus, etc. Thus, the touch-sensitive display can also be characterized as an input device configured to receive input from an operator. The display device 118 also conveys information from the system controller 116 to the operator by displaying information to the operator. The display device 118 and / or the user interface 122 can also communicate audibly. The display device 118 is configured to present information to the operator during an imaging session. The presented information can include ultrasound images, graphical elements, user-selectable elements, and other information (e.g., administrative information, personal information of the patient, etc.).

[0022] Figure 2 An exemplary transducer array 200 composed of a plurality of transducer elements 201 is shown. The transducer array 200 can be included in an ultrasound probe, such as Figure 1 probe 106, so the transducer elements 201 are Figure 1 non-limiting examples of the elements 104 of Figure 2 Although six transducer elements are shown, it should be understood that the array 200 can include hundreds or thousands of transducer elements arranged in a linear or 2D array. The plurality of transducer elements 201 includes a first transducer element 202 and additional transducer elements similarly constructed to the transducer element 202. For simplicity, only the transducer element 202 is described herein, but it should be understood that other transducer elements in the transducer array 200 can be similarly constructed, and the description of the transducer element 202 applies equally to other transducer elements.

[0023] The transducer element 202 includes a piezoelectric layer 206 that has at least one acoustic impedance mismatch layer 208 and has a support layer 204 to form an acoustic stack. In some embodiments, the piezoelectric layer 206 can comprise lead zirconate titanate (PZT) and can be single-crystal PZT or polycrystalline PZT. Non-limiting examples of the mismatch layer include dense high-modulus metals (such as molybdenum or tungsten) and high-density ceramics (such as tungsten carbide). The acoustic impedance of the mismatch layer 208 is greater than the acoustic impedance of the piezoelectric layer 206. ForFigure 2 In the configuration shown, the support layer 204 may have an acoustic impedance between that of water and the piezoelectric layer 206. In some embodiments, the support layer 204 includes a graphite support layer. Other candidate materials for the support layer 204 include, but are not limited to, ceramics, silicon, flexible organic polymers, metal-filled graphite, ceramic powder-filled epoxy resins, glass, and glass-ceramics.

[0024] The acoustic stack (e.g., support layer 204, piezoelectric layer 206, and impedance-matching layer 208) may be formed as a continuous block and coupled to a flexible circuit 216 (see below) in the continuous block. Then, after being coupled to the flexible circuit, the acoustic stack may be sliced, for example, into rectangles to form Figure 2 the individual transducer elements shown. The transducer elements may be separated by cuts formed by the slicing.

[0025] The transducer array 200 also includes a common ground electrode 214 coupled to each transducer element. For example, a suitable metal electrode may be attached to the support layer 204 together with an external matching layer 212 attached to the electrode 214 to provide a common ground electrode for all acoustic elements. Non-limiting examples of suitable materials for the external matching layer 212 include ABS plastic, polyethylene, polystyrene, and unfilled epoxy resins. Other materials with similar acoustic impedance may also be used. In some examples, the electrode 214 and / or the matching layer 212 may be sliced together with the acoustic stack, or the electrode 214 and / or the matching layer 212 may be coupled after the acoustic stack has been sliced. Additionally, in examples where the electrode is a common electrode coupled to multiple transducer elements, the electrode (and in some examples, the matching layer) may be coupled to a subset of the transducer elements (e.g., 6, 10, 20 transducer elements), such that the array 200 may include multiple electrodes and / or matching layers. Although not shown in Figure 2 , it should be understood that there are other elements present in the transducer stack, such as electrodes on the bottom surface of each piezoelectric layer and vias within each impedance-matching layer to electrically couple the piezoelectric layer to the underlying flexible circuit.

[0026] The transducer elements 202 are coupled to the flexible circuit 216. As Figure 2As shown, other transducer elements among the plurality of transducer elements 201 are also coupled to the flexible circuit 216. The transducer element 202 (and other transducer elements) is coupled to the flexible circuit 216 via a suitable connection member. As shown, the transducer element 202 is coupled to the flexible circuit 216 via an electrical contact 210 that is coupled to a conductive pad 218 of the flexible circuit 216. The electrical contact 210 may include a suitable electrical connection member, such as an anisotropic conductive film (ACF), but may also include other connection members, such as a bump contact (e.g., under-bump metallization (UBM) deposited on the de-matching layer 208 and solder bumps on the under-bump metallization). The anisotropic conductive film may be used to couple the acoustic stack to the flexible circuit before the acoustic stack is sliced into transducer elements. In some examples, the anisotropic conductive film may be sliced together with the acoustic stack.

[0027] The transducer array 200 further includes an application specific integrated circuit (ASIC) die 220 that is coupled to the flexible circuit 216. The ASIC die 220 may be coupled to the flexible circuit 216 using a suitable mechanism such as an anisotropic conductive film (ACF). Although Figure 2 only one die 220 is shown, it should be understood that the array 200 may include multiple dies, where each die may be operatively coupled to one or more transducer elements (e.g., as shown, six transducer elements are operatively coupled to the die 220).

[0028] The ASIC die 220 provides acoustic sensor interface electronics, while the flexible circuit 216 provides electrical interconnections from the ASIC die to the transducer array and from the ASIC die to an external data processing system (not shown). Thus, the flexible circuit 216 includes a plurality of vias as vertical interconnects to electrically couple the transducer elements to the ASIC die, such as vias 219 that extend from the top of the flexible circuit 216 to the bottom of the flexible circuit 216. As described above, Figure 2Only a subset of the transducer elements that may be present in the array 200 is shown, and the array 200 may include hundreds or thousands of transducer elements, each transducer element being coupled to the ASIC die using vias in the flexible circuit 216. Thus, the flexible circuit 216 may include hundreds or thousands of vias that are electrically isolated from each other. As described in detail below, the flexible circuit 216 may be formed of multiple patterned conductive layers, and the vias may be formed by drilling through the multiple conductive layers. The exposed surfaces of the flexible circuit are then plated with a conductive material to form conductive vias through the flexible circuit. If any one of the vias is not properly plated or not properly drilled, conductivity through the via may not be provided, which may result in non-functional transducer elements and may lead to reliability issues if the connections are not robust. Thus, the connectivity of each via may be tested before the acoustic stack is laminated onto the flexible circuit. However, performing connectivity checks on all vias may be challenging. For example, until the ASIC die is coupled to the bottom of the flexible circuit and the acoustic stack is coupled to the top of the flexible circuit, there may not be an electrical connection through the vias, at which point it may be difficult to address any unconnected vias. Additionally, the topographical features of the flexible circuit, particularly the top surface of the flexible circuit, may pose challenges if one or more contact pads are not filled or planarized. Thus, before coupling the acoustic stack to the flexible circuit, a dual-sided probe or a temporary shorting plate may be used to test the connectivity of the vias. Such test configurations may be challenging because the dual-sided probe or the shorting plate may cause degradation or other issues with the flexible circuit.

[0029] Thus, according to the embodiments disclosed herein and described in more detail below, the flexible circuit 216 can form electrical traces that electrically connect the vias to a power source. In this way, the vias can electrically connect to the conductive material layer of the flexible circuit in the absence of the ASIC die or the acoustic stack. This can allow for easier testing of the connectivity of the vias before coupling the ASIC die and / or the acoustic stack. Additionally, after copper plating, the surface of the flexible circuit 216 can be plated with nickel and gold. Generally, nickel-gold plating can be performed using an electroless plating process, such as electroless nickel immersion gold (ENIG) or electroless nickel palladium immersion gold (ENEPIG). However, considering the presence of electrical traces in the flexible circuit, an electrolytic process can be used to plate the flexible circuit with nickel and gold, which requires the vias to be conductive for plating. Since the color of gold plating is different from that of copper plating, if any vias are not plated with nickel and gold, the non-plated interconnects will have a different color from the plated interconnects, allowing for optical / visual inspection of the non-connected interconnects. After the flexible circuit has been formed and its interconnect connectivity has been tested, the ASIC die and the acoustic stack can be coupled to the flexible circuit. As described above, the acoustic stack can be coupled to the flexible circuit as a continuous block / group of layers and then sliced to form individual transducer elements. During slicing, at least some of the electrical traces in the flexible circuit can be cut or otherwise severed, which can maintain the electrical isolation of the vias.

[0030] Figure 3 A method 300 for forming a flexible circuit configured to be coupled to a transducer array for an ultrasonic probe is shown. For example, method 300 can be used to produce Figure 2 the flexible circuit of the transducer array 200 that can be incorporated in Figure 1 the probe 106.

[0031] At 302, vias are drilled in a dielectric panel. The dielectric panel can be composed of an insulating material (such as polyimide or polyetheretherketone) coupled between two layers of conductive material (such as copper). Holes can be drilled in the dielectric panel using laser ablation, plasma etching, or other suitable drilling techniques. In some examples, multiple holes are drilled in the dielectric panel. Figure 4 A cross-sectional view of an exemplary dielectric panel 400 composed of an insulating layer 404, a first copper layer 402, and a bottom copper layer 406 is shown. The overall thickness of the dielectric panel can be, for example, 50 μm, and each copper layer can have a thickness of 5 - 10 μm. Figure 5 A view of the Figure 4 dielectric panel 400 in a drilling state 500 is shown, where a hole 502 is drilled in the dielectric panel. The hole 502 can have a suitable width, such as 750 μm, and can extend across the entire thickness of the dielectric panel (e.g., from the first copper layer 402 to the bottom copper layer 406).

[0032] At 304, method 300 includes patterning / etching a desired pattern on a conductive material on a first side (e.g., top side) of a dielectric panel. The patterning / etching can be performed using, for example, a photolithography process. Figure 6 The patterned dielectric panel 600 is shown, where the drilled dielectric panel from Figure 5 has been subjected to a patterning / etching process on the first copper layer 402. Thus, a pattern is formed in the first copper layer 402, including areas (such as area 602) where the original copper plating has been removed, thereby exposing the underlying insulating material.

[0033] At 306, a copper sheet is laminated on the first side of the patterned drilled dielectric panel. The copper sheet can include a copper layer on an insulating layer, where an adhesive layer is located at the bottom of the insulating layer. The adhesive layer can be used to laminate the insulating layer and the copper layer on the dielectric panel, thereby forming a multi - layer flexible circuit panel. Figure 7 The exemplary multi - layer flexible circuit panel 700 is shown, including the Figure 6 drilled patterned dielectric panel laminated with the copper sheet 702. The copper sheet 702 includes an outer copper layer 704 on an insulating layer 706. The outer copper layer 704 can have a thickness in the range of, for example, 5 - 10 μm, and the insulating layer 706 can also have a thickness in the range of 5 - 10 μm. The insulating layer 706 can be made of the same material as the insulating layer 404, such as polyimide. The copper sheet 702 also includes an adhesive layer 708, which can couple the insulating layer 706 and the outer copper layer 704 to the dielectric panel. When the adhesive layer is heated and / or pressed, the adhesive layer can fill the gaps formed during the etching / patterning of the first copper layer 402. For example, once the copper sheet 702 is laminated to the dielectric panel, the area 602 (as Figure 6 shown) is filled with adhesive. Additionally, as Figure 7 shown, the hole 502 is covered by the copper sheet 702 such that the hole 502 is open on the bottom side but covered on the top side.

[0034] At 308, method 300 includes drilling through the copper sheet to form registration vias. The copper sheet can be drilled (e.g., using laser ablation or plasma etching) at the locations where the dielectric panel is drilled under the copper sheet coverage such that through - holes are formed. Thus, the holes extend from the outer copper layer of the copper sheet to the bottom copper layer of the dielectric panel. Figure 8Shows a drilled multi-layer flexible circuit panel 800 having holes 802 aligned with holes 502 formed by drilling holes 804. The holes 804 may have a diameter smaller than that of the holes 502, such as a diameter of 500 μm. Thus, the holes 802 may include regions without material (e.g., voids) that extend from the outer copper layer 704 through the insulating layer 706, the adhesive layer 708, the first copper layer 402, the insulating layer 404, and the bottom copper layer 406. However, since the diameter of the holes 804 is smaller than that of the holes 502, the surface of the first copper layer 402 is not exposed in the holes 802 but is covered by the adhesive layer 708. By drilling the holes 804 to have a diameter smaller than that of the holes 502, alignment inspection of individual drilled layers can be performed.

[0035] At 310, method 300 includes drilling blind holes on the bottom side of the dielectric panel. The blind holes may drill through the bottom copper layer and the insulating layer of the dielectric panel and terminate at the bottom surface of the first copper layer (i.e., now in the middle of the flexible circuit). The blind holes may be drilled at positions where electrical connection to the overlying acoustic stack (described in more detail below) is required. At 312, method 300 includes drilling aligned blind holes through the copper sheet and reaching the top side of the first copper layer of the dielectric panel (e.g., reaching the top surface of the copper layer in the middle of the flexible circuit). As shown at 314, drilling the blind holes includes holding the copper layer between the blind holes. For example, when forming the blind holes, the middle copper layer of the flexible circuit is not drilled through.

[0036] Figure 9 Is a cross-sectional view of a flexible circuit 900 having blind holes as shown in a multi-layer structure. Figure 9 The shown flexible circuit includes aligned blind holes 902 formed by top blind holes 904 and bottom blind holes 906. The top blind holes 904 extend from the outer copper layer 704 through the insulating layer 706 and the adhesive layer 708 and terminate at the first copper layer 402. The bottom blind holes 906 extend from the bottom copper layer 406 and pass through the insulating layer 404 and terminate at the first copper layer 402. Each of the top blind holes 904 and the bottom blind holes 906 may have a suitable diameter, such as 40 μm. The section of the first copper layer 402 spanning the aligned blind holes 902 forms the first intermediate layer 908. The aligned blind holes 902 form through-holes that form electrical connections from the top to the bottom of the multi-layer flexible circuit to form connections from the overlying acoustic stack (described in more detail below) to the underlying ASIC chip. Each patterned trace in the center copper is a through-element connector or a routing trace carrying surface conductors for passive components, ground connections, and system connectors.

[0037] At 316, the exposed surfaces of the flexible circuit (e.g., the exposed surfaces of the copper sheet and the dielectric panel, including the exposed surfaces of the blind holes) are plated with copper. The copper can be plated using a suitable process, such as electroless plating (which can be followed by electroplating to ensure a stable coating of copper). For example,Figure 10 shows a plated flexible circuit 1000, wherein Figure 9 the flexible circuit is plated with copper, so that a plating layer of copper 1002 is formed on all exposed surfaces of the flexible circuit, including the top surface of the flexible circuit, the bottom surface of the flexible circuit, and the inner surfaces of aligned blind vias (e.g., aligned blind via 902). The through-hole 802 may not be plated.

[0038] At 318, method 300 includes etching / patterning the external copper layers (e.g., the bottom copper layer and the top (external) copper layer) of the flexible circuit according to a desired pattern. Lithography or other suitable processes may be used to perform the patterning in order to form contact pads for accommodating ASIC dies, which will be positioned under the flexible circuit and provide the required connection / accommodation space for an acoustic stack that will be coupled to the top of the flexible circuit. Figure 11 shows a patterned flexible circuit 1100, wherein Figure 10 the flexible circuit is patterned / etched on both the external copper layer 704 and the bottom copper layer 406. Specifically, both the external copper layer 704 and the insulating layer 706 have been etched / patterned such that both the external copper layer 704 and the insulating layer 706 have been removed in some areas (such as area 1102) that expose the adhesive layer 708. On the bottom side, the bottom copper layer 406 may also be removed in some areas that expose the insulating layer 404. The patterning may form contact pads, each of which includes a blind via. In addition, one of the layers (e.g., layer 406) may be patterned to include a de-bus line. As Figure 14 shown, the flexible circuit may include a central array 1402 of contact pads (e.g., blind vias drilled as described above and contact pads formed via patterning as described above, wherein each contact pad includes a blind via) formed according to the method described herein. The central array 1402 may include multiple rows of contact pads, such as row 1404. Generally, each contact pad in a given row may be electrically isolated from each other, at least before additional components are coupled to the flexible circuit. However, as Figure 14 shown and as explained herein, each row may include a de-bus line, such as de-bus line 1410, which electrically couples each contact pad in that row (and other components coupled to the flexible circuit), such as contact pad 1406 and contact pad 1408. The de-bus line may be formed via patterning. For example, the patterning may leave a line of layer 406 that extends between each contact pad in a given row, rather than patterning layer 406 to isolate each contact pad.

[0039] Return Figure 11 , Figure 11The view of the flexible circuit shown is an expanded view showing additional blind vias formed in a multi-layer flexible circuit. For example, the aligned blind via 902 may be the first blind via, and the circuit may include a second blind via 1110 and a third blind via 1120. The second blind via 1110 includes a second intermediate layer 1112 formed in the copper layer 402, and the third blind via 1120 includes a third intermediate layer 1122 formed in the copper layer 402. It should be understood that the flexible circuit may include hundreds or thousands of blind vias arranged in an array (e.g., arranged in multiple rows of blind vias) and similar to Figure 11 the blind vias shown.

[0040] Figure 11 The blind vias shown may be located in a central array of the flexible circuit (such as the central array 1402), where multiple connectors of the acoustic element are formed vertically to the ASIC through the flexure. The vertical feedthroughs will be connected through the ASIC chip. The intermediate layer (e.g., layer 402) routes the component signals from the center of the stack to the ends of the flexure and back to the outer layer to contact the connector, which transmits the signals to the system and other supporting electronics.

[0041] At 320, the flexible circuit is plated with nickel and gold using an electroplating process. The electroplating process may include immersing the flexible circuit in an electrolyte containing dissolved metal salts and ions for conduction. The flexible circuit acts as the cathode and the nickel (and subsequently gold) to be plated is the anode, which is also immersed in the electrolyte. A power supply provides direct current to the anode, thereby oxidizing the metal atoms it contains and dissolving them in the solution. At the flexible circuit where current is simultaneously supplied, the metal ions dissolved in the electrolyte solution are reduced at the interface between the solution and the flexible circuit, where they are plated onto the flexible circuit in any region of the electrical connection (and thus in the flowing current). This process may be first performed to plate nickel, and then the process may be performed again to plate gold on the nickel. Due to the de-bussing lines (e.g., Figure 14 the de-bussing line 1410) connecting the contact pads of the flexible circuit, the blind vias (such as Figures 9 - 11 the blind via 902) are conductive, so if the vias are properly formed, the inner surfaces of the vias will be plated with nickel and gold. If one or more vias are not properly formed, for example, if copper is not plated along the entire surface of the via, or if the top copper layer or the bottom copper layer does not contact the copper plating the inner surface of the via, those vias will not be plated with nickel and gold during the electrolytic plating.

[0042] At 322, a surface protection layer and / or solder mask layer is formed on the flexible circuit to encapsulate the external circuit layer of the flexible circuit. For example, polyimide can be laminated to the outer surface of the flexible circuit. The contact pads or connection points can be exposed by lithography, drilling, stamping, etc. through the surface protection layer / solder mask layer. The surface protection layer / solder mask layer is then opened at all electrical connection points for bonding and connection, at the central array elements that connect the acoustic stack to the ASIC bonding pads, passive component assembly pads (e.g., resistors, capacitors, inductors), and the assembly pads for connectors.

[0043] At 324, the connectivity of the vias is tested. As described above, due to the presence of the de-bussing lines that electrically couple the contact pads of the flexible circuit, the flexible circuit can be plated with nickel and gold using an electrolytic process. If the vias are not properly formed or otherwise do not electrically couple the top copper layer of the flexible circuit to the bottom copper layer of the flexible circuit, the vias will not be plated with nickel and gold, but copper plating can be seen. Due to the color difference between gold and copper, the unplated gold vias can be detected by optical / visual testing. For example, an RGB camera or other image sensor can be used to image the flexible circuit, and computer vision / image recognition can be performed to detect if any vias are not plated with gold. In another example, a user can perform a visual inspection to determine if any vias are not plated with gold. If the flexible circuit includes any vias that are not plated with gold, the flexible circuit can be discarded, or the flexible circuit can be modified to try to address any issues that led to the non-connected vias. The connectivity can be determined through multiple test points during the process (such as post-FPC manufacturing). In the case of enabling the temporary connection of the FPC, there is also a certain degree of post-ASIC test attachment. These two gates can reduce waste generation, streamline the product, and lower the assembly cost. Before attaching the ASIC and before attaching the acoustic stack layer, the components can be screened. The post-FPC test is visible for non-plating, and an electrical automated flying probe test that can test for open circuits can be performed (however, the presence of the de-bussing lines forms short-circuit elements, so only specific grids or adjacent elements can be tested for short circuits). The post-ASIC attachment allows additional tests from an automated tester that allows basic ASIC connectivity verification and certain evaluations of specific nets.

[0044] At 326, the acoustic stack is added to the flexible circuit. The acoustic stack can include an acoustic element, such as a piezoelectric layer, that is configured to generate charge in response to mechanical stress (e.g., sound waves impinging on the element from an impact), and conversely, output sound waves when charge is provided. As described above with respect to Figure 2As explained, the acoustic element can be coupled to a matching layer, a backing / dematching layer, a ground electrode, etc. When adding an acoustic stack to a flexible circuit, the acoustic element can be electrically coupled to a via in the flexible circuit. For example, the backing / dematching layer of the acoustic stack can include electrical connectors (e.g., vias) that extend through the backing / dematching layer to corresponding vias in the flexible circuit.

[0045] Figure 12 An exemplary flexible circuit / acoustic stack in a first configuration 1200 is shown, which includes Figure 11 the flexible circuit (after nickel / gold plating, formation of the surface protection layer, and testing to confirm the connectivity of the vias), where the acoustic stack 1202 is coupled (e.g., on the surface protection layer 1201). It should be understood that the orientation of the flexible circuit board is Figure 12 in Figure 11 flipped such that layer 406 is on top and layer 704 is on the bottom. Additionally, Figure 12 a de-bus line formed by segments of layer 406 (including segment 1210, segment 1212, segment 1214, and segment 1216) is shown in Figure 2 . Thus, segment 1212 can connect blind via 902 to blind via 1110, segment 1214 can connect blind via 1110 to blind via 1120, etc. The acoustic stack 1202 is positioned on top of layer 406. As explained above with respect to Figure 2 the acoustic stack 1202 includes a support layer 1204, a piezoelectric layer 1206, and a dematching layer 1208. The dematching layer can include vias or other connectors through which an electrical connection is established between the piezoelectric layer 1206 and the blind vias in the flexible circuit. However, other configurations of the acoustic stack can also be employed. The acoustic stack 1202 extends continuously across the flexible circuit such that the blind vias 902, 1110, and 1120 are covered by the acoustic stack.

[0046] Returning to Figure 3, Method 300 includes performing acoustic stack slicing along multiple slicing lines to form individual transducer elements. The acoustic stack can be sliced to form incisions between individual transducer elements. The acoustic stack can be sliced in two directions. A first plurality of slicing lines can extend along parallel axes extending from one side of the acoustic stack to an opposite second side of the acoustic stack. A second plurality of slicing lines can extend along parallel axes perpendicular to the first plurality of slicing lines and can extend from a third side of the acoustic stack to an opposite fourth side of the acoustic stack. The slicing can cut through the acoustic stack through the support layer, through the acoustic element layer, and through the decoupling layer. Additionally, for a set of slicing lines (e.g., the first plurality of slicing lines or the second plurality of slicing lines), the slicing can continue through the table protection layer / solder mask 1201, through layer 406, and partially into layer 404 to electrically isolate each contact pad and allow for individual transducer element control and signal reception. A suitable slicing saw or other isolation method (which can include laser profiling, chemical etching, or plasma processing) can be used to cut the acoustic stack and traces.

[0047] Figure 13 An exemplary flexible circuit / acoustic stack in a second slicing configuration 1300 is shown, where Figure 12 the flexible circuit / acoustic stack has been sliced to form individual transducer elements. The slicing forms incisions between the transducer elements, such as incision 1302. Incision 1302 extends through the copper layer 406 of the flexible circuit such that section 1210 is cut. Similarly, incision 1304 extends through the copper layer 406 such that section 1212 is cut and thus no longer provides a connection between the first contact pad (e.g., including blind via 902) and the second contact pad (e.g., including blind via 1110) of the flexible circuit. However, slicing of the acoustic stack in another perpendicular direction may not extend beyond the top of the flexible circuit. Thus, the slicing penetrates the piezoelectric stack and the top-side metal of the flexible circuit. The slicing stops in the top dielectric layer. The slicing does not go through the entire flexible circuit and is a controlled depth cut.

[0048] When a section of the de-bus line / copper layer 406 is cut, the surfaces of the section of the copper layer 406 facing at least some of the corresponding incisions are not plated with copper, nickel, or gold. Since the de-bus lines were not cut during copper plating and during nickel and gold plating, the top and bottom surfaces of the de-bus lines can be plated with copper, nickel, and gold, but the interior of the de-bus lines consists only of copper. When the de-bus lines are cut, the interior of the de-bus lines is exposed and not plated with nickel and gold. Thus, after slicing, a gap (e.g., incision 1304) is formed to electrically separate the first contact pad from the second contact pad (and to separate the individual transducer elements).

[0049] Thus, during slicing, the first contact pad 1310 and the second contact pad 1320 are partially separated from each other by a gap (e.g., notch 1304), and the second contact pad 1320 and the third contact pad 1330 are partially separated from each other by another gap (e.g., notch 1306). Each contact pad includes a corresponding first conductive layer (layer 406), a corresponding second conductive layer (layer 402), a corresponding third conductive layer (layer 704), and corresponding blind vias (e.g., blind vias 902, 1110, and 1120) extending through the first and third conductive layers. At the gap, the first conductive layer of the first contact pad and the first conductive layer of the second contact pad form a discontinuous conductive path between the first and second contact pads. The discontinuous conductive path is constituted by a section (e.g., section 1212) of layer 406 that is cut or otherwise severed. After slicing, the discontinuous conductive path is made up of a first section and a second section separated by the gap, the first section including the first conductive layer of the first contact pad and terminating at the gap, and the second section including the first conductive layer of the second contact pad and terminating at the gap, wherein the first and second sections are coplanar. The first transducer element is coupled to the top surface of the first contact pad, and the second transducer element is coupled to the top surface of the second contact pad, and at least one application-specific integrated circuit is configured to be coupled to the bottom surface of the first contact pad and the bottom surface of the second contact pad.

[0050] An enlarged view 1500 of a portion of the flexible circuit 1400 is shown in Figure 15 FIG. In the enlarged view, the first contact pad 1502, the second contact pad 1504, and the third contact pad 1506 are arranged in a row, and the fourth contact pad 1508, the fifth contact pad 1510, and the sixth contact pad 1512 are arranged in a second row. Each contact pad includes a plated-through hole (e.g., copper plated with nickel and gold) surrounded by a pad substrate. The pad substrate includes a conductive material layer (e.g., copper) and an insulator layer. For example, the second contact pad 1504 includes a through hole 1505 surrounded by a pad substrate 1503. Each contact pad is coupled to an adjacent conductive pad in the row of that pad by a de-bussing line (e.g., an electrical trace). For example, the second contact pad 1504 is coupled to the first contact pad 1502 by a trace 1507, and the second contact pad 1504 is coupled to the third contact pad 1506 by a trace 1509. The traces coupling adjacent contact pads allow power to be provided to the corners / surfaces of the flexible circuit during electroplating to flow through all of the through holes of the flexible circuit, and thus the through holes can be plated with nickel and gold. If no through holes are hole-plated, as described above, those through holes will have a different color (e.g., copper-colored) from the other through holes that are plated (which will be gold-colored), which can allow for quick detection of degraded / incompletely formed through holes. After the connectivity test, along a suitable slicing line such as Figure 15a dicing trace (the dashed line shown) while performing an acoustic stack slice to form individual transducer elements.

[0051] Electrical traces may be present in other portions of the flexible circuit. For example, Figure 16 and Figure 17 shows traces that may be diced after connectivity testing. Figure 16 shows a bus line 1600 that may be present in an inner layer of the flexible circuit. Traces 1602 and 1604 may be added to connect some of the bus lines to enable galvanics during plating. These traces may be diced after connectivity testing. Figure 17 shows a set of conductive pads 1700 present in an inner layer of the flexible circuit, with additional traces coupling adjacent conductive pads.

[0052] Thus, the disclosure provided herein allows for testing and inspection of high - density vertical interconnect structures, including the manufacture of high - density vertical interconnect structures, testing of the interconnects, and isolation of the contact pads. The present invention also allows for an increase in the testability of direct ASIC attachment to a flexible substrate, which enables sub - assemblies to be screened prior to completion of the entire acoustic laminate structure. The manufacturing process includes electroplating metalworking using a bus method.

[0053] The present disclosure provides a simplified test of direct vertical interconnect structures that previously had to be performed by applying a temporary shorting plate or dual - sided probing. The present disclosure also allows for more controlled electro - polished plating by using a bus connection process. Bus removal is accomplished through an in - situ process step that currently isolates the acoustic material, thereby forming an isolation element for acoustic sensing.

[0054] The configurations described herein allow for the utilization of known good flexible substrate materials in the manufacture of acoustic probes. The present disclosure also allows for an increase in the testability of ASIC attachment to a flexible substrate, which was previously limited in what could be tested. Previous flexible circuit configurations manufactured with ENIG or ENIPIG plating finishes did not allow for visual inspection of the vias described herein because traditional automated optical inspection could not determine if the vertical interconnects were in good condition. The bus handling described herein allows for visual inspection of the plated metal on the bottom side of the circuit indicative of vertical interconnects. As a result, a higher yield of probes can be obtained, each with a known good test flex for assembly. Additionally, the flexible circuits described herein increase the ductility and elongation of the metal finish.

[0055] The nickel-gold bus plating (NGB) on the nickel-gold surface described in this article utilizes connectorized "bus" plating. The NGB bus is designed to connect all top center array pads and some features to the temporary metal shorting traces and connect the bottom pads through vias. This process enables visual inspection after plating to indicate that via interconnections have been made. Those short traces are laser cut during the de-bussing and acoustic stack slicing processes.

[0056] Figure 2 and Figures 4 to 17 An exemplary configuration showing the relative positioning of various components is presented. At least in one example, such elements may be referred to as being in direct contact or directly coupled if shown as being in direct contact or directly coupled to each other. Similarly, at least in one example, elements adjacent or adjoining each other may be adjacent or adjoining to each other respectively. For example, components arranged to be in coplanar contact may be referred to as being in coplanar contact. Again, at least in one example, elements positioned to be spaced apart from each other and having only space therebetween without other components may be so described. Again, elements shown as being above / below each other, on opposite sides of each other, or between the left / right sides of each other may be so described relative to each other. Further, as shown, at least in one example, the topmost element or point of an element may be referred to as the "top" of the component, and the bottommost element or point of an element may be referred to as the "bottom" of the component. As used herein, top / bottom, upper / lower, above / below may be with respect to the vertical axis of the figure and may be used to describe the positioning of elements in the figure relative to each other. Thus, in one example, an element shown as being above other elements is vertically positioned above the other elements. Again, the shapes of the elements shown in the figure may be referred to as having those shapes (e.g., such as being circular, straight, planar, curved, rounded, chamfered, angled, etc.). Further, at least in one example, elements shown as intersecting each other may be referred to as intersecting elements or intersecting each other. Additionally, in one example, an element shown as being within another element or shown as being outside another element may be so described.

[0057] The technical effect of manufacturing a flexible circuit having traces that couple adjacent contact pads is the ability to perform electroplating of nickel and gold rather than relying on electroless plating processes, which can be time-consuming and wasteful. Another technical effect is the ability to visually confirm the connectivity of the vias in the flexible circuit without having to couple a shorting plate or electrical clip to the flexible circuit.

[0058] As used herein, an element or step recited in the singular and preceded with the word "a" or "an" should be understood as not excluding a plurality of said elements or steps, unless expressly stated to the contrary. In addition, a reference to "one embodiment" of the present invention is not to be construed as excluding the existence of additional embodiments that also include the recited features. Further, unless expressly stated to the contrary, an embodiment that "comprises," "includes," or "has" an element or elements with a particular property may include additional such elements that do not have that property. The terms "comprising" and "in which" are used as the plain-language equivalents of the respective terms "including" and "wherein." Further, the terms "first," "second," and "third," etc. are used merely as labels, and are not intended to impose numerical requirements or a particular positional order on their objects.

[0059] This written description uses examples to disclose the invention, including the best mode, and also enables one of ordinary skill in the relevant art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the present invention is defined by the claims, and may include other examples that occur to one of ordinary skill in the art. Such other examples are intended to fall within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal language of the claims.

Claims

1. A method for a flexible circuit, comprising: forming a flexible circuit including a plurality of contact pads arranged in a plurality of rows, each contact pad in a given row being electrically coupled to each other via a trace, and each contact pad including a via hole formed by aligned blind holes, the aligned blind holes including a first blind hole formed on a first side of the flexible circuit and a second blind hole formed on a second side of the flexible circuit, the first blind hole extending through a first conductive layer of the flexible circuit and terminating at a second conductive layer of the flexible circuit, and the second blind hole extending through a third conductive layer of the flexible circuit and terminating at the second conductive layer; electroplating the flexible circuit with at least a first material, including electroplating each via hole; and at least partially cutting at least some of the traces when confirming the connectivity of each via hole, wherein forming the flexible circuit further includes plating each via hole with a second material before electroplating the flexible circuit, and wherein the first material and the second material have different colors.

2. The method according to claim 1, wherein each trace is constituted by a corresponding section of the first conductive layer.

3. The method according to claim 1, the method further comprising coupling an acoustic stack to the flexible circuit, the acoustic stack including acoustic elements.

4. A method for a flexible circuit, comprising: forming a plurality of aligned blind holes in a flexible circuit substrate, each aligned blind hole including a first blind hole formed on a first side of the flexible circuit substrate, the first blind hole extending through a first conductive layer of the flexible circuit and terminating at a second conductive layer, and a second blind hole formed on a second side of the flexible circuit substrate and terminating at the second conductive layer; electroplating the flexible circuit substrate and the aligned blind holes with a first material to form the flexible circuit; coupling the flexible circuit to an acoustic stack; and slicing the acoustic stack to form transducer elements, including slicing through the first conductive layer, the method further including plating a second material on the flexible circuit substrate and the aligned blind holes before electroplating the first material, the second material and the first material having different colors.

5. The method according to claim 4, wherein the second material is different from the first material.

6. The method according to claim 4, the method further comprising coupling the flexible circuit to a plurality of application specific integrated circuits.

7. The method according to claim 4, wherein forming the plurality of aligned blind holes includes forming the plurality of aligned blind holes arranged in rows, each aligned blind hole in a row being electrically coupled via the first conductive layer until the first conductive layer is sliced.

8. A flexible circuit, comprising: a first contact pad; and A second contact pad, the second contact pad being partially separated from the first contact pad by a gap, each contact pad including a first conductive layer, a second conductive layer, a third conductive layer, a first blind via extending through the first conductive layer and terminating at the second conductive layer, and a second blind via extending through the third conductive layer and terminating at the second conductive layer, the first blind via and the second blind via forming aligned blind vias, and at the gap, the first conductive layer of the first contact pad and the first conductive layer of the second contact pad forming a discontinuous conductive path between the first contact pad and the second contact pad, wherein the blind vias are electroplated successively with different materials having different colors.

9. The flexible circuit according to claim 8, wherein the discontinuous conductive path includes a first segment and a second segment separated by the gap, the first segment including the first conductive layer of the first contact pad and terminating at the gap, and the second segment including the first conductive layer of the second contact pad and terminating at the gap, wherein the first segment and the second segment are coplanar.

10. The flexible circuit according to claim 8, wherein each blind via includes plating layers of at least a first material and a second material.

11. The flexible circuit according to claim 8, the flexible circuit further including a first transducer element coupled to the top surface of the first contact pad and a second transducer element coupled to the top surface of the second contact pad.

12. The flexible circuit according to claim 8, the flexible circuit further including at least one application specific integrated circuit coupled to the bottom surface of the first contact pad and the bottom surface of the second contact pad.

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