Non-volatile static random access memory and corresponding control method

Abstract

Embodiments of the present disclosure relate to non-volatile static random access memories and corresponding control methods. An example integrated circuit includes a memory device, the memory device including at least one memory dot, the at least one memory dot having a volatile memory cell and a single non-volatile memory cell that are together coupled to a common node.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of French Application No. 2000761, filed on January 27, 2020, which is incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to integrated circuits and methods, and more particularly to integrated circuits and methods including memory devices such as non-volatile static random access memory devices. Background Art

[0004] A non-volatile static random access memory "NVSRAM" is a memory that combines a static random access memory "SRAM" cell and a non-volatile memory (such as an electrically erasable programmable type), such as an electrically erasable programmable read-only memory "EEPROM", in a single memory point for storing binary data.

[0005] NVSRAM memories have the advantages of both technologies, that is, they do not lose information from binary data when the circuit is turned off and have unlimited write durability.

[0006] In fact, during operation, the write operation of the memory is performed on the volatile cells, while the write operation in the non-volatile cells is only performed when the integrated circuit is powered off to save the data present in the volatile memory cells.

[0007] Conventionally, almost the only drawback of non-volatile static random access memory NVSRAM is the surface area occupied by the memory points.

[0008] In fact, in the conventional art, a dozen transistors are used in each memory point. For example, a typical SRAM cell has six transistors, which are assembled with a differential pair of non-volatile cells (such as flash memory type), and usually each non-volatile cell includes three transistors.

[0009] Another drawback is that when the memory is powered off, there is a capacitor for supplying energy for non-volatile storage operations. Its value is typically about one hundred microfarads (μF), which has a negative impact on the congestion and cost of these memories.

[0010] Therefore, it is desirable to benefit from a more compact non-volatile static random access memory. Summary of the Invention

[0011] Accordingly, in one aspect, there is provided an integrated circuit comprising: a memory device including at least one memory cell having a volatile memory cell and a single non-volatile memory cell coupled together to a common node; and a single select transistor coupled between the common node and a single bit line, a first output of the volatile memory cell being coupled to the common node, and a second output of the volatile memory cell complementary to the first output not being connected to any node external to the volatile memory cell.

[0012] In other words, one of the two outputs of the volatile memory cell is coupled to the single non-volatile memory cell, and the other of the two outputs of the volatile memory cell is not coupled to the non-volatile memory cell and thus not even coupled to any node that does not belong to the volatile memory cell.

[0013] Thus, different from conventional differential methods in which two non-volatile cells storing reverse data are each coupled to one of the two outputs of the volatile memory cell, it is proposed that a single non-volatile memory cell is used per memory cell.

[0014] In addition, instead of a pair of bit lines conventionally used in differential methods, a single bit line is coupled to the memory cell for accessing the memory cell particularly during read and write operations.

[0015] Accordingly, the number of transistors in each NVSRAM memory cell is reduced, and the size of the memory device is decreased.

[0016] According to one embodiment, the volatile memory cell includes a bistable latch including two inverters mounted in anti-parallel, and the non-volatile memory cell includes a state transistor having a command gate and a floating gate, and an access transistor serially coupled between the common node and the state transistor.

[0017] Thus, a non-volatile memory cell corresponding to EEPROM-type technology is proposed, which is particularly advantageous in terms of energy consumption during read and write operations.

[0018] Accordingly, the memory cell can advantageously include a number of transistors equal to 7.

[0019] According to one embodiment, at least one memory cell further includes an isolation transistor serially coupled between the common node and the volatile memory cell, for example to facilitate a read operation in the non-volatile memory cell.

[0020] Accordingly, the memory cell can advantageously include a number of transistors equal to 8.

[0021] According to an advantageous embodiment, a memory device includes: a memory plane including a plurality of memory dots arranged in at least one memory word; and a local decoder per memory word, including power lines coupled to power terminals of volatile memory cells of a corresponding memory word and configured to store a power state in a status register, a first value of the power state indicating a non-operating state of the volatile memory cells of the corresponding memory word, and a second value of the power state indicating an operating state of the volatile memory cells of the corresponding memory word.

[0022] The power state allows, for example, regulating the activation of the volatile or non-volatile memory cells of a corresponding memory word, and the power lines of the local decoder allow providing a power voltage to the volatile memory cells of a corresponding memory word.

[0023] In the embodiments defined hereinafter, multiple sets of power voltages are provided on the power lines of the decoder, each set including a high-level power voltage and a low-level power voltage. For example, specifically according to the power state, these power voltages can be generated specifically for read or write operations in a corresponding memory word.

[0024] According to one embodiment, the local decoder is configured to maintain, on the power lines, a first set of power voltages suitable for powering the functions of the volatile memory cells as long as the power state has the second value.

[0025] Thus, only when necessary, that is, if a memory word has been written or modified according to the power state, power is supplied to the volatile memory cells in groups arranged in the memory word. In the non-operating state, the volatile memory cells of other memory words are not powered.

[0026] According to one embodiment, the memory device further includes reading means configured to generate a first read signal suitable for timing a read operation in the non-volatile memory cells of a selected memory word if the corresponding power state has the first value, and to generate a second read signal suitable for timing a read operation in the volatile memory cells of a selected memory word if the corresponding power state has the second value.

[0027] Thus, the reading means is capable of reading directly from the non-volatile memory cells and directly from the volatile memory cells.

[0028] Also, as long as there is no data written in the volatile memory cells, data is read in the non-volatile memory cells, otherwise power will not be supplied to the volatile memory cells; and once data is written into the volatile memory cells, data is read in the volatile memory cells.

[0029] According to one embodiment, a read device is configured to generate a second set of power voltages on the power lines of a selected memory word among the first read signals, the second set of power voltages being adapted to apply a high-impedance floating potential on the output of a common node coupled to a volatile memory cell.

[0030] Thus, during the reading of non-volatile memory cells, the volatile memory cells are placed in a high-impedance state on the positive output in order to avoid disturbing the signal originating from the common access node of the volatile memory cells.

[0031] According to one embodiment, a read device includes a sense amplifier configured to generate a precharge voltage on the bit lines of a memory point being read among the first read signal and the second read signal, and to detect a change in current or voltage on the bit lines during a read operation in a non-volatile memory cell and during a read operation in a volatile memory cell.

[0032] In other words, the volatile memory cells are read in the same manner as non-volatile memory cells by the sense amplifier, thus advantageously allowing a reliable and controlled reading.

[0033] Furthermore, the precharge voltage can be advantageously selected to avoid causing parasitic switching of the data stored in the volatile memory cells.

[0034] According to one embodiment, the memory device further includes: a write device configured to generate first write signals adapted to time a write operation in the volatile memory cells of a selected memory word independently of the value of the power state, and a local decoder of the corresponding memory word is configured to provide a power state with a second value after the write operation.

[0035] For example, during normal operation of the integrated circuit, all writes are performed in the volatile memory cells, and furthermore, these volatile memory cells are permanently powered by the first write. At each modification, the non-volatile memory cells are not used to store data, which limits their wear.

[0036] According to one embodiment, the write device is configured to generate a third set of power voltages among the first write signals on the power lines of a selected memory word adapted to abort the function of the volatile memory cells, then generate a data signal to be stored on the common node applied via the bit lines of the memory point of the selected memory word, and then generate a first set of power voltages on the power lines adapted to power the function of the volatile memory cells.

[0037] This write operation allows data to be written in a volatile memory cell in the following cases: with a single asymmetric bit line, without differential writing on complementary outputs, in a reliable manner, and without an electrical conflict between the power line and the output of the volatile memory cell.

[0038] According to one embodiment, the write device is configured to generate a fourth set of power voltages on the power line of the selected memory word among the first write signals, the fourth set of power voltages being adapted to cause the polarization discharge of the internal node of the volatile memory cell of the selected memory word before generating the third set of power voltages.

[0039] According to one embodiment, the write device is configured to generate second write signals in all memory words whose corresponding power states have a second value in the case of the shutdown of the memory device, the second write signals being adapted to time the write operation of the non-volatile memory cell using the data recorded in the volatile memory cell of the corresponding memory point.

[0040] Therefore, when performing non-volatile writing, the non-volatile memory cell is automatically written using the current data stored in the corresponding volatile memory cell.

[0041] For example, the shutdown of the integrated memory circuit can come from a stop command or from an unexpected power outage, such as in the case of a power failure or disconnection.

[0042] Optionally, the non-volatile writing can be performed simultaneously on all memory words of the memory plane, the corresponding states of which represent the operating states of the volatile memory cells.

[0043] The write operation of the non-volatile memory cell can include an erase cycle, followed by a programming cycle, each cycle including injecting charge into the floating gate of the state transistor through the Fowler-Nordheim effect.

[0044] Therefore, according to one embodiment, the write device is configured to generate an erase voltage on the command gate of the state transistor and a first programming voltage on the command gate of the state transistor among the second write signals, and a fifth set of power voltages on the power line of the volatile memory cell in the memory word, the corresponding power state of the memory word having a second value, the fifth set of power voltages being adapted to place the common node at the second programming voltage.

[0045] In other words, the erase voltage applied only to the command gate of the state transistor itself allows the implementation of the erase through the Fowler-Nordheim effect.

[0046] According to a technique known as shared voltage technique, the programming voltage is further configured on two components, one component being applied to the command gate of the status transistor and the other component being applied to the drain of the status transistor from the positive output of the volatile memory cell. These two components are selected such that high-level data on the positive output causes programming through the Fowler-Nordheim effect, and low-level data on the positive output does not generate the Fowler-Nordheim effect with respect to the first component.

[0047] According to one embodiment, the integrated circuit further includes a power device, which includes: a main power stage, intended to supply a first power voltage suitable for the operation of the memory device; and a secondary power stage, intended to supply a second power voltage suitable for powering the write operation of the non-volatile memory cells in the case where the memory device is shut down.

[0048] Advantageously, the secondary power stage includes: a capacitor, intended to be charged with the second power voltage; and a first charge pump circuit, configured to generate the second power voltage from the first power voltage, the level of the second power voltage being higher than the level of the first power voltage.

[0049] Increasing the level of the second power voltage to charge the capacitor allows reducing the capacitance value, thereby allowing storing a sufficient amount of energy and thus reducing the size and cost of the capacitor.

[0050] The power device may further include: at least one high-voltage generator, incorporated into the write means of the memory device for generating a second write signal suitable for timing the write operation of the non-volatile memory cells, and the high-voltage generator advantageously includes a plurality of basic charge pump stages, these stages being suitable for being coupled in series to accumulate the corresponding amplification factors of the second power voltage; and command means, configured to measure the current value of the second power voltage and, after the current value of the second power voltage decreases, command the successive coupling of a series of basic charge pump stages.

[0051] The high-voltage generator including such a charge pump device with variable number of stages not only allows adapting to the possible faster drop of the second power voltage from a smaller capacitor, but also allows optimally using the available energy supplied by the capacitor. Optimizing the use of energy limits energy losses and allows further reducing the size of the capacitor.

[0052] According to another aspect, a method for commanding a memory device as defined above is proposed, the memory device including a memory plane that includes a plurality of memory points arranged in at least one memory word. The method includes storing the power state of each memory word, a first value of the power state representing the non-operating state of the volatile memory cells of the corresponding memory word, and a second value of the power state representing the operating state of the volatile memory cells of the corresponding memory word.

[0053] According to one embodiment, the method includes: maintaining a first set of power voltages that power the volatile memory cells of all memory words having a second value for their power state in an operating state.

[0054] According to one embodiment, the method further includes: generating a first read signal that times a read operation in the non-volatile memory cells of the selected memory word if the corresponding power state has a first value; and generating a second read signal that times a read operation in the volatile memory cells of the selected memory word if the corresponding power state has a second value.

[0055] According to one embodiment, the method includes generating a second set of power voltages among the first read signals, the second set of power voltages applying a high impedance floating potential on an output coupled to a common node in the volatile memory cells of the selected memory word.

[0056] According to one embodiment, the method includes: generating a precharge voltage on a bit line at a memory point among the first read signal and the second read signal, and detecting a change in current or voltage on the bit line during a read operation in the volatile memory cells and during a read operation in the non-volatile memory cells.

[0057] According to one embodiment, the method further includes: generating first write signals that time a write operation in the volatile memory cells of the selected memory word regardless of the value of the power state, and providing a corresponding power state having a second value after the write operation.

[0058] According to one embodiment, the method includes: generating a third set of power voltages among the first write signals that power the volatile memory cells of the selected memory word to abort the function of the volatile memory cells, then generating a data signal to be stored on the common node that is applied via a bit line of a memory point of the selected memory word, and then generating the first set of power voltages that power the volatile memory cells of the selected memory word in an operating state.

[0059] According to one embodiment, the method further includes: generating a fourth set of power voltages among the first write signals that power the volatile memory cells of the selected memory word to discharge the polarization of an internal node of the volatile memory cells of the selected memory word before each generation of the third set of power voltages.

[0060] According to one embodiment, the method further includes: in the case of the memory device being powered off, generating second write signals in all memory words whose corresponding power states have a second value, and these second write signals use the data recorded in the volatile memory cells of the corresponding memory dots to time the write operations of the non-volatile memory cells.

[0061] According to one embodiment, the method includes, among the second write signals generated in the memory words whose corresponding power states have a second value, an erase voltage on the command gate of the state transistor and a first programming voltage on the command gate of the state transistor, and a fifth set of power voltages for powering the volatile memory cells to place the common node at the second programming voltage.

[0062] Some of the functions mentioned above for the NVSRAM type memory device (especially the write and read operations in the volatile memory cells) can thus also be applied to the SRAM type memory device having a "single bit line" structure (that is, configured to perform read and write access to the memory cells through a single bit line).

[0063] In addition, according to another aspect, an integrated circuit is proposed, including a static volatile memory device, and the static volatile memory device includes: at least one memory dot, having static volatile memory cells coupled to a single bit line, and the static volatile memory cells include a first output and a second output complementary to the first output; and a single selection transistor, coupled between the first output and the single bit line, and the second output of the static volatile memory cell is not connected to any node outside the static volatile memory cell.

[0064] Therefore, this kind of memory dot is different from the conventional method that provides a differential structure with two bit lines.

[0065] According to one embodiment, the volatile memory cell includes a bistable latch, and the bistable latch includes two inverters installed in anti-parallel.

[0066] According to one embodiment, the memory device includes: a memory plane, including a plurality of memory dots arranged in at least one memory word; and a local decoder per memory word, including power lines, and these power lines are coupled to the power terminals of the volatile memory cells of the corresponding memory word, and the power lines are configured to store the power state in a state register, and the first value of the power state represents the non-operating state of the volatile memory cells of the corresponding memory word, and the second value of the power state represents the operating state of the volatile memory cells of the corresponding memory word.

[0067] According to one embodiment, the local decoder is configured to maintain, on the power line, a first set of power voltages suitable for powering the functions of the volatile memory cells as long as the power state has a second value.

[0068] According to one embodiment, the memory device further includes reading means configured to generate a read signal suitable for timing a read operation in the volatile memory cells of the selected memory word if the corresponding power state has a second value.

[0069] According to one embodiment, the reading means includes a sense amplifier configured to generate a pre-charge voltage on the bit line of the memory point being read among the read signals and to detect a change in current or voltage on the bit line during a read operation in the volatile memory cells.

[0070] According to one embodiment, the memory device further includes: writing means configured to generate write signals suitable for timing a write operation in the volatile memory cells of the selected memory word regardless of the value of the power state, and the local decoder of the corresponding memory word is configured to provide a power state having a second value after the write operation.

[0071] According to one embodiment, the writing means is configured to generate, among the write signals, a third set of power voltages on the power line of the selected memory word suitable for aborting the functions of the volatile memory cells, then generate a data signal to be stored on the access node applied via the bit line of the memory point of the selected memory word, and then generate a first set of power voltages on the power line suitable for powering the functions of the volatile memory cells.

[0072] According to another aspect, there is also provided another method for commanding such a memory device, the memory device including a memory plane including a plurality of memory points arranged in at least one memory word, the method including storing a power state for each memory word, a first value of the power state representing a non-operating state of the volatile memory cells of the corresponding memory word, and a second value of the power state representing an operating state of the volatile memory cells of the corresponding memory word.

[0073] According to one embodiment, the method includes: maintaining a first set of power voltages that power the volatile memory cells of the memory words in an operating state, the power states of these memory words having a second value.

[0074] According to one embodiment, the method further includes generating a read signal suitable for timing a read operation in the volatile memory cells of the selected memory word if the corresponding power state has a second value.

[0075] According to one embodiment, the method includes generating a precharge voltage on a bit line of a memory cell among read signals and, during a read operation in a volatile memory cell, detecting a change in current or voltage on the bit line.

[0076] According to one embodiment, the method further includes generating write signals that time a write operation in a volatile memory cell of a selected memory word independently of the value of a power state and providing a corresponding power state having a second value after the write operation.

[0077] According to one embodiment, the method includes generating a third set of power voltages among write signals to power a volatile memory cell of a selected memory word to disable the function of the volatile memory cell, then generating a data signal to be stored on an access node that is applied via a bit line of a memory cell of the selected memory word, and then generating a first set of power voltages to power the volatile memory cell of the selected memory word in an operating state.

[0078] According to one embodiment, the method further includes generating a fourth set of power voltages among write signals that power a volatile memory cell of a selected memory word to discharge the polarization of an internal node of the volatile memory cell of the selected memory word prior to each generation of the third set of power voltages.

[0079] Finally, the power devices mentioned above can also be considered independently.

[0080] Furthermore, according to another aspect, an integrated circuit is proposed that includes a power device, the power device including: a main power stage configured to supply a first power voltage suitable for the operation of a memory device; and a secondary power stage configured to supply a second power voltage in the case where the memory device is powered off, wherein the secondary power stage includes: a capacitor configured to be charged at the second power voltage; and a first charge pump circuit configured to generate the second power voltage from the first power voltage, the level of the second power voltage being higher than the level of the first power voltage.

[0081] According to one embodiment, the power device further includes at least one high-voltage generator that includes a plurality of basic charge pump stages adapted to be coupled in series to accumulate a corresponding amplification of the second power voltage; and a command device configured to measure a current value of the second power voltage and, after the current value of the second power voltage decreases, command the successive coupling of a series of basic charge pump stages. Description of the Drawings

[0082] Other advantages and features of the present invention will become apparent upon examination of the detailed description of non-limiting embodiments and the accompanying drawings, in which:

[0083] Figure 1 Illustrates memory points;

[0084] Figure 2A Illustrates a memory device including a local word decoder;

[0085] Figure 2B Illustrates logic circuitry for generating the state of each local decoder;

[0086] Figure 2C Illustrates a memory word state selection communication circuit;

[0087] Figure 2D Illustrates a command circuit of a command gate latch;

[0088] Figure 3 Illustrates different states of volatile memory cells according to multiple sets of voltages applied to power lines;

[0089] Figure 4 Illustrates the implementation of a command method in a memory device;

[0090] Figure 5 Illustrates the generation of second read signals adapted to time read operations in volatile memory cells of a selected memory word;

[0091] Figure 6 Illustrates the generation of first read signals adapted to time read operations in non-volatile memory cells of a selected memory word;

[0092] Figure 7 Illustrates the generation of first write signals adapted to time write operations in volatile memory cells of a selected memory word;

[0093] Figure 8 Illustrates the generation of first write signals adapted to time a first write operation in volatile memory cells of a selected memory word;

[0094] Figure 9 Illustrates generating second write signals in a memory word using data recorded in volatile memory cells of corresponding memory points, the second write signals timing write operations in non-volatile memory cells, all of the volatile memory cells of these memory words storing data;

[0095] Figure 10 Illustrates the organization of a memory plane including multiple memory points;

[0096] Figure 11Illustrated is an integrated circuit chip incorporating a non-volatile static random access memory device that incorporates memory planes; and

[0097] Figure 12 Illustrated is a power device that can be incorporated Figure 11 into the integrated circuit chip. Detailed Description

[0098] Figure 1 Illustrated is an example of a memory point BTCL of a non-volatile static random access memory device NVSR that can store binary data. The memory point BTCL is of the "NVSRAM" type (for "non-volatile static random access memory") and includes a volatile memory cell FF ("flip-flop") of the "SRAM" type (for "static random access memory") and a non-volatile memory cell EE of the "EEPROM" (for "electrically erasable programmable read-only memory") type.

[0099] In this example, the volatile memory cell FF includes a bistable latch that includes two inverters mounted in anti-parallel and thus has two outputs Q and QN with opposite polarities. The output Q is arbitrarily defined as the positive output of the bistable latch and stores binary data, while the other output QN (called the complementary output) stores the reverse of the binary data.

[0100] The first inverter of the bistable latch FF consists of a PMOS (for "P-type metal oxide semiconductor", a term well known to those skilled in the art) transistor MP1 and an NMOS (for "N-type metal oxide semiconductor") transistor MN1. The transistor MP1 is coupled between the high-level power line SPLUS and the complementary output node QN, and the transistor MN1 is coupled between the complementary output node QN and the low-level power line SMINUS. The transistors MP1 and MN1 of this inverter are commanded by the positive output Q of the other inverter. The other inverter of the bistable latch FF also consists of a PMOS transistor MP2 and an NMOS transistor MN2. The PMOS transistor MP2 is coupled between the high-level power line SPLUS and the positive output node Q, and the NMOS transistor MN2 is coupled between the positive output node Q and the low-level power line SMINUS. The transistors MP2 and MN2 of this inverter are commanded by the complementary output QN of the first inverter.

[0101] The memory cell BTCL further includes a single non-volatile memory cell EE coupled to the positive output Q at the common node NC. The non-volatile memory cell EE of the EEPROM type includes a state transistor TE having a command gate and a floating gate and an access transistor TA serially coupled between the common node NC and the drain of the state transistor TE. The source of the state transistor TE is also coupled to the source line SL.

[0102] In the memory cell BTCL, a selection transistor MN3 is serially coupled between the common node NC and a single bit line BL.

[0103] The bit line BL allows data to be transferred to the memory cell BTCL that is to be stored in the volatile memory cell FF and reads data stored in either the volatile FF or the non-volatile EE memory cell.

[0104] Therefore, Figure 1 the memory cell BTCL illustrated in includes a transistor count equal to seven.

[0105] According to an alternative, an additional isolation transistor (not shown) serially coupled between the common access node NC and the positive output Q of the volatile memory cell FF constitutes a total of eight transistors per memory cell BTCL. The isolation transistor allows isolation of the volatile memory cell FF, particularly when reading data stored in the non-volatile memory cell EE.

[0106] Reference Figure 10 and 11 .

[0107] Figure 10 illustrates an example of a favorable organization of a memory plane PM including a plurality of memory cells BTCL as described in connection with Figure 1 . The memory cells BTCL are arranged in the memory plane PM, and a memory word WD, for example 8, 16, or 32 bits, includes 8, 16, or 32 memory cells BTCL, respectively. Bits of an error correction code ("ECC") are typically provided additionally in each memory word WD.

[0108] The selection transistors MN3 belonging to the same memory word WD are commanded on a common word selection line WLLOCAL; just as the access transistors TA of the non-volatile memory cells EE belonging to the same memory word WD are commanded on a common word line ERWL; and just as the state transistors TE of the non-volatile memory cells EE belonging to the same memory word WD are commanded on a common command grid line CG.

[0109] The gate regions of the transistors of the volatile memory cell FF are not shared by the memory word WD, and these gate regions substantially occupy twice the width of the select MN3, access TA, and status TE transistors.

[0110] Thus, the PMOS transistor pairs MP1, MP2 of the memory points of the first type of architecture BTCL_A are arranged in a staggered manner with respect to the PMOS transistor pairs MP1, MP2 of the memory points of the second type of architecture BTCL_B in the same N-type doped semiconductor well NW.

[0111] Similarly, the NMOS transistor pairs MN1, MN2 of the memory points of the first type of architecture BTCL_A are arranged in a staggered manner with respect to the NMOS transistor pairs MN1, MN2 of the memory points of the second type of architecture BTCL_B in the same P-type doped semiconductor well PW.

[0112] "Staggered" here means a regular and repeated arrangement between one element and the next, where considering the different elements in each memory point being aligned in strips with a length of half a unit width, the position of one element is offset by one unit in the length direction and by half a unit in the width direction with respect to the position of the other element.

[0113] Two metal lines belonging to the first metal layer are provided to form the high-level power line SPLUS of the PMOS transistor pair arranged in a staggered manner in the well PW; two metal lines of the first metal layer are provided to form the low-level power line SMINUS of the NMOS transistor pair arranged in a staggered manner in the well NW.

[0114] In Figure 10 are shown the possibilities of electrical installation on three metal layers for the two types of memory point architectures BTCL_A, BTCL_B by the following: the first metal line M1 coupled to the source, drain, and grid regions through the contact CNT; the second metal line M2 coupled to the first metal line M1 through the first via V12; and the third metal line M3 coupled to the second metal line M2 through the second via V23. Figure 1 Of course, various possibilities of installation in the metal layers can be considered.

[0115] Of course, various possibilities of installation in the metal layers can be considered. Figure 1 of the installation.

[0116] Figure 11 An integrated circuit chip is shown, which incorporates a non-volatile static random access memory device NVSR and incorporates a memory plane PM as described in connection with Figure 10 as described.

[0117] The device NVSR also incorporates a power stage ALM (e.g., advantageously as described hereinafter in connection withFigure 12 the described power stage) and command stage MCMD and row DECX and column DECY decoders for accessing the memory points BTCL of the memory plane PM.

[0118] The device NVSR in chip form can be bonded to the metal attachment surface ATT ("die attachment"), which is intended to be packaged in an example of an eight-pin package numbered 1 to 8 and connected to different power and input / output terminals of the power ALM and command MCMD stages.

[0119] Thus, in combination Figure 1 the described memory points BTCL have the smallest structure among multiple transistors and thus the smallest unit area. Regarding the size reduction, the use of a locally more complex word decoder than in a conventional structure to activate SRAM cells will be described in connection with FIGS. 2 to 9. If the word is large enough, e.g., at least eight bytes, the size loss of the local decoder is compensated by the unit area gain of the memory points BTCL multiplied by the number of memory points BTCL per word.

[0120] Thus, in combination Figure 11 the presented chip can have, for example, a memory capacity of 1 Mb and a size less than 8 mm 2 .

[0121] Figure 2A , 2B , 2C and 2D together illustrate an example of a local word decoder WSW that is configured to control the memory points BTCL as described above in connection with Figure 1 the description.

[0122] Figure 2A Schematically shows a memory device NVSR including a local word decoder WSW. The local word decoder WSW includes state generation logic means PSLG (described below in connection with Figure 2B the description), a memory word state selection SS communication circuit (described below in connection with Figure 2C the description) and a command gate latch command circuit COMCGL (described below in connection with Figure 2D the description).

[0123] Thus, the memory device NVSR includes one local decoder WSW per memory word WD, and each local decoder WSW is configured to control the memory points BTCL belonging to the memory word WD, which memory nodes BTCL are dedicated to that memory word WD.

[0124] The memory device NVSR further includes a state machine ME for timing the operation of the memory in particular in response to external read or write commands.

[0125] In this regard, the state machine ME is configured to generate command signals, specifically the reset signal ResetN, the external control signal Ext_Ctrl, the column selection signal Col, the row selection signal Row, the programming condition signal PRC, the erasure condition signal ERC, the read condition signal RDC, the write command signal WriteN, and the read and write voltages or stimuli SPLINE, SNLINE, CPLUS, CMINUS. The write and read stimuli can have high voltage levels and can thus be generated by a voltage generator HVGEN provided for this purpose.

[0126] For example, the state machine ME belongs to the command level MCMD previously associated with Figure 11 as mentioned.

[0127] To partition the functions of the state machine ME, it is considered that the state machine ME is provided with a read device RDM for timing read operations and a write device WRM for timing write operations.

[0128] Figure 2B An example of a logic circuit device for generating the state PSLG of each local decoder WSW is illustrated.

[0129] Each local decoder WSW is configured to supply a power voltage to the volatile memory cells FF on the power lines SPLUS, SMINUS and to provide a power state PS to the corresponding memory word.

[0130] The local decoder WSW is also configured to transmit the read and write stimuli to the volatile memory cells FF or non-volatile memory cells EE (see Figure 2D ) in a manner suitable for the state of the corresponding memory word and specifically according to the selection conditions Col, Row of the memory word. The state of each memory word WD is defined by the power state PS recorded in the state register PSREG of the corresponding local decoder WSW.

[0131] As will be seen below, a first value of the power state PS (e.g., ground gnd) represents the non-operating state P0 of the volatile memory cells FF of the corresponding memory word WD, while a second value of the power state PS (e.g., power voltage Vdd) represents the operating state P1 of the volatile memory cells FF of the corresponding memory word WD.

[0132] In fact, a word is selected from the other memory words of the memory plane by the physical row address Row and the physical column address Col. The physical addresses of the row Row and the column Col are, for example, the result of decoding the logical addresses received in an external command by the state machine ME.

[0133] For convenience, the high and low logic levels of the various signals (especially the power state PS) will be designated below by "1" and "0", and these high and low logic levels can be the power supply voltage Vdd and the ground voltage gnd, respectively; in addition, references to structural elements (such as the power lines SPLUS, SMINUS) can also be used to designate the signal or the value of the signal applied thereto, and vice versa.

[0134] When the device is powered on, the status register PSREG is reset to PS = 0 by the signal ResetN generated by the state machine ME. The signal ResetN is active at "0", and in the absence of a reset command, the signal ResetN is at "1" (deactivated).

[0135] Triple input conditions are tested on the address signals Col, Row, and the external control signal Ext_Ctrl generated by the state machine ME. If these three signals Col, Row, Ext_Ctrl (all 1) are checked, the signal for selecting the word S is set to 1, and the complementary signal SN is set to 0. Conversely, if at least one of the three signals Col, Row, Ext_Ctrl is not checked (at least one is 0), then S = 0 and SN = 1.

[0136] When the selection signal S of the decoder dedicated to the word is equal to 1, S = 1, SN = 0, the memory word is selected.

[0137] Output conditions are tested on the word selection signal S and its complement SN to distribute the power supply voltages of the high level SPLUS and the low level SMINUS to the bistable latch of the volatile memory cell FF as described in Figure 1 the volatile memory cell FF.

[0138] The output conditions and voltage distribution can be implemented by a set of transistors MOS such that:

[0139] If S = 0 and SN = 1, then SPLUS = PS and SMINUS = gnd.

[0140] If S = 1 and SN = 0, then SPLUS = SPLINE, and SMINUS = SNLINE, where SPLINE and SNLINE are the lines across the memory plane PM, and the state machine ME generates read and write stimuli on these lines.

[0141] Thus, the external control signal Ext_Ctrl of the state machine ME conditionally controls the state machine ME on the power supplies SPLUS, SMINUS of the non-volatile memory cell FF of the memory word WD selected by Col, Row via the transmission lines SPLINE and SNLINE.

[0142] When S = 0 and SN = 1, the word selection signals regulate the power voltages SPLUS = PS and SMINUS = gnd.

[0143] First, due to the power-on reset (ResetN), PS = 0 = gnd.

[0144] In this case, SPLUS = gnd and SMINUS = gnd. This corresponds to the power-off state P0 of the volatile memory cell FF ( Figure 3 ).

[0145] Second, if PS = 1 = Vdd, and S = 0 and SN = 1, then SPLUS = PS = Vdd and SMINUS = gnd. This corresponds to the functional power supply state P1 of the volatile memory cell FF ( Figure 3 ).

[0146] As will be seen below, after the first write in the memory word is definitely made, the state PS is placed at the power voltage Vdd, PS = Vdd = 1.

[0147] Actually, when writing in the memory word, the state machine ME generates the external control signal Ext_Ctrl = 1 and the write signal WriteN (activated at 0).

[0148] The signals SN = 0 and WriteN = 0 constitute the only set condition (Set) of the state register PSREG, which clearly records (at least, as long as the reset signal ResetN is not restarted) that the power state signal PS is at 1, PS = 1 = Vdd.

[0149] Then, the state machine ME times the write operation, for example as described below in conjunction with Figure 4 and 8 .

[0150] During read and write operations, the common node NC is coupled to the bit line BL through the command WLLOCAL supplied on the local word line, and the command WLLOCAL is coupled to the gate MN3 of the selection transistor of the memory word. The command WLLOCAL is generated by the conditions on the word selection signal S or on its complement SN and on the word line command WLN (activated at 0) in order to transcribe the word line command WLN at the useful voltage VWL for operation in the selected memory word S = 1, SN = 0. The useful voltage VWL is again generated by the state machine ME or possibly by the generator HVGEN.

[0151] Therefore, the local decoder WSW is specifically configured to maintain the functional power P1 of the volatile memory cell FF of the memory word WD as long as the power state PS is recorded at the second value Vdd.

[0152] Figure 2C An example of a memory word state selection SS communication circuit is illustrated.

[0153] The local decoder WSW is actually configured to transfer the state of the memory word to the state machine ME on the state and select line SSLINE of the memory word state selection SS communication circuit.

[0154] The state and select line SSLINE includes three transistors connected in series between the input of the state machine ME and the ground terminal gnd, and each transistor is commanded by one of the select signals Col, Row, and power state PS on its grid.

[0155] Therefore, the state machine ME can detect the state and select line SSLINE and detect: the ground voltage gnd representing the operating state P1 of the selected memory word and its volatile memory cell FF (if the three transistors are turned on); the high-impedance disconnect switch terminal (HIMP, Figure 4 )(in the case where at least one of the three transistors is turned off) representing a memory word that is unselected or selected but whose volatile memory cell FF is non-operating (PS = 0).

[0156] Figure 2D An example of a command circuit for the command gate latch COMCGL is illustrated.

[0157] Therefore, the local word decoder WSW also includes a command circuit COMCGL for the command gate latch, which is dedicated to reading and writing in the non-volatile memory cell EE of the memory point BTCL of the memory word WD.

[0158] The command circuit COMCGL dedicated to reading and writing in the non-volatile memory cell EE includes a command gate latch CGL, which includes a first pair of complementary MOS transistors MVP1, MVN1 forming a first inverter and a second pair of complementary MOS transistors MVP2, MVN2 forming a second inverter. The two inverters are installed in anti-parallel to maintain a high-level voltage CPLUS or a low-level voltage CMINUS at the input of the third inverter. The third inverter includes a third pair of complementary MOS transistors MVP3, MVN3, and its output supplies the command gate signal CG with a high-level voltage CPLUS or a low-level voltage CMINUS.

[0159] The inputs of the first inverters MVP1, MVN1 can be forced to a low level by a cascode transistor MVN4 on the write command branch. The inputs of the second inverters MVP2, MVN2 can be forced to a low level by another cascode transistor MVN5 on the read command branch. The cascode transistors MVN4, MVN5 are commanded by a cascode command voltage VCASC.

[0160] The command circuit of the command gate latch CGL is configured to force the output state of the latch CGL by applying signals on the read and write command branches.

[0161] The transistor is coupled in series to ground gnd on the read command branch and is commanded by a read command signal RDC.

[0162] Thus, if the state machine ME activates the read command signal RDC (RDC = 1), the outputs of the second inverters MVP2, MVN2 are forced to a high voltage CPLUS, and a command gate signal CG at a low voltage CMINUS is transferred onto the command gate of the state transistor TE of the non-volatile memory cell of the corresponding memory word WD (see Figure 1 ).

[0163] Depending on the executed cycle (erase or program) and the state of the memory word PS = 0 or PS = 1, the state machine generates a programming condition PRC and an erase condition ERC signal in order to transfer a voltage to the command gate CG of the state transistor TE.

[0164] The write command branch can in turn be placed at ground gnd by: activating the programming condition signal PRC (PRC = 1) and the complementary power state PSN (PSN = 1, PS = 0); or activating the erase condition signal ERC (ERC = 1) and the power state PS (PS = 1, PSN = 0). The programming PRC and erase ERC condition signals are generated by the state machine ME.

[0165] Thus, during erasure, ERC = 1, and if PS = 0, then CG = CMINUS, while if PS = 1, then CG = CPLUS.

[0166] During programming, PRC = 1, and if PS = 0, then CG = CPLUS, while if PS = 1, then CG = MINUS.

[0167] The high voltage CPLUS and the low voltage CMINUS are generated by the read RDM and write WRM means of the state machine ME and allow timing of the read and write operations in the non-volatile memory cell EE, for example as described in particular below in connection with Figure 4 and 9 as described.

[0168] Now, with reference to Figures 3 to 9 the timing of read and write operations implemented in cooperation between the local decoder WSW of the memory word WD of the memory plane PM and the state machine ME will be described.

[0169] Figure 3 is shown according to different states of the volatile memory cells FF, such as previously described in connection with Figure 1 as described.

[0170] In the first state P1, the reference power supply potential Vdd of the device is applied to the high-level power line SPLUS of the volatile memory cells FF of the memory word; and the reference potential gnd of the device (i.e., ground) is applied to the low-level power line SMINUS of the volatile memory cells FF of the memory word.

[0171] Thus, the first set of power voltages Vdd, gnd is provided to power the volatile memory cells FF in the operating state P1, which is suitable for performing the memory function of the volatile memory cells FF.

[0172] The first set of power voltages Vdd, gnd can be generated by the state machine ME or by the corresponding local decoder WSW.

[0173] In the second state HZ, between the transistors of the bistable latch that makes up the volatile memory cells FF, the highest absolute threshold voltage value Vtmax is applied to both the high-level power line SPLUS and the low-level power line SMINUS of the volatile memory cells FF of the memory word.

[0174] Thus, the second set of power voltages Vtmax, Vtmax is provided to power the volatile memory cells FF in the high-impedance state HZ on the positive output Q.

[0175] The second set of power voltages Vtmax, Vtmax is generated by the state machine ME on the power lines SPLINE, SNLINE.

[0176] In the third state P0, the ground potential gnd is applied to both the high-level power line SPLUS and the low-level power line SMINUS of the volatile memory cells FF of the memory word.

[0177] Thus, the third set of power voltages gnd, gnd is provided to power the volatile memory cells FF in the power-off state P0, which is suitable for aborting the memory function of the volatile memory cells FF.

[0178] The third set of power voltages gnd, gnd can be generated by the state machine ME or by the corresponding local decoder WSW.

[0179] In the fourth state DS, the maximum threshold voltage Vtmax is applied to the high-level power line SPLUS, and gnd is applied to the low-level power line SMINUS.

[0180] Therefore, this fourth set of power voltages Vtmax, gnd is provided to power the volatile memory cells FF in the discharge state DS, which is suitable for polarizing and discharging the internal nodes of the volatile memory cells FF.

[0181] The fourth set of power voltages gnd, gnd is generated by the state machine ME on the power lines SPLINE, SNLINE.

[0182] In the fifth state PP, the high-level write voltage Vpp is applied to the high-level power line SPLUS, and the low-level write voltage Vlow is applied to the low-level power line SMINUS.

[0183] This fifth set of power voltages Vpp, Vlow is intended to power the volatile memory cells FF in the non-volatile programming state PP, which is suitable for placing the common node NC at a potential that allows a programming operation on the data recorded in the volatile memory FF in the non-volatile memory cell EE ( Figure 9 ).

[0184] The fifth set of power voltages Vpp, Vlow is generated by the state machine ME on the power lines SPLINE, SNLINE.

[0185] Therefore, the states commanded on the power supplies SPLUS, SMINUS of the volatile memory cells FF (referred to as the operation P1, high impedance HZ, power-off P0, non-volatile write PP, and discharge DS states) will allow read and write operations to be implemented in the memory plane as described below with reference to Figure 4 and reference Figures 5 to 9 as described.

[0186] Figure 4 is a functional diagram of an example of implementing a command method in the memory device NVSR as described above in conjunction with Figures 1 to 3 and with reference to Figure 10 and Figure 11 as described.

[0187] During the initialization phase 401, the state machine ME is waiting to receive a read RD or write WR command and supplies an external control signal Ext_Ctrl = 0.

[0188] This situation corresponds to leaving the memory plane PM in its data storage function, where the volatile memory cells FF of the memory words are powered by the local decoder WSW in the functional power state P1, and the power state PS of these memory words is at the second value PS = Vdd. The volatile memory cells FF of the memory words are powered by the local decoder WSW in the power-off state P0, and the power state PS of these memory words is at the first value PS = gnd. Any previous data of the memory words is stored in the non-volatile memory cells EE, and the power state of these memory words is at the first value PS = gnd.

[0189] In step 402, a command with an address at (Col, Row) of the memory word to be read or written is received. The Col and Row signals are transmitted to the local decoder to identify the selected memory word.

[0190] Then, in step 403, the state machine probes the selection and status of the local decoder WSW of the Rd SSLINE address Col, Row and the status SSLINE line. Depending on the power state PS, the selection and status SSLINE line can have a high impedance HIMP or a ground potential gnd. The high impedance HIMP and the ground potential gnd represent the non-powered state and the powered state of the volatile memory cells FF, respectively.

[0191] In step 404, a first condition is tested on the received command, which can be a read command RD or a write command WR.

[0192] If the command in step 404 is a read command RD, and if in step 405 the line SSLINE is probed to be coupled to the ground gnd, then the volatile memory cells FF store the data of the selected word and are powered by the local decoder WSW in the operating state P1.

[0193] As Figure 5 illustrated, a read operation 500 is performed in the volatile memory cells FF by a second read signal.

[0194] Figure 5 An example of generating the second read signals is shown, and these second read signals are suitable for timing the read operation in the volatile memory cells FF of the selected memory word Col, Row.

[0195] During the read 500, the power lines SPLUS and SMINUS are in the operating state P1, where for example SPLUS = Vdd = 3.3V and SMINUS = gnd.

[0196] First, in step 501, a precharge voltage PRCH, for example, at the threshold voltage of an NMOS transistor of substantially 1V, is generated on the bit line BL of the memory cell BTCL read in the selected memory word.

[0197] Then, in step 502, the local word line WLLOCAL is placed at a potential that turns on the select transistor MN3, for example, twice the precharge voltage PRCH, substantially 2V, so as to couple the common node NC to the precharge potential PRCH.

[0198] Finally, in step 503, the RD_FF data is read by measuring the current change on the bit line BL.

[0199] In this regard, a sense amplifier AMP commonly used for reading EEPROM memories can be used.

[0200] However, to avoid parasitic switching of the data recorded in the volatile memory cell FF, it is advantageous to provide a voltage (substantially 2V) on the local word line WLLOCAL that is fixed at twice the threshold voltage of the NMOS transistor at the memory cell BTCL. Thus, when the positive output Q of the cell FF is grounded gnd, due to the precharge of the read circuit and the additional limitation ensured by the limited gate voltage (WLLOCAL) of the transistor MN3, this positive output cannot be placed above the threshold voltage of the transistor MN1 (substantially 1V). This situation avoids the parasitic switching of the volatile memory cell FF that may be caused by the conducting transistor MN1. If the output Q is Vdd, there is no risk of parasitic switching.

[0201] This read operation 500 allows the data in the bistable latch of the volatile memory cell FF to be read with a single asymmetric bit line in a reliable manner and without an electrical conflict between the power lines SPLUS, SMINUS and the outputs Q, QN, without a differential write on the complementary output QN.

[0202] Refer again to Figure 4 .

[0203] In step 405, when the command 404 is a read command RD, if the line SSLINE has a high impedance, the volatile memory cell FF is in the power-off state P0 and does not store the data of the selected word. Therefore, the data must be read from the non-volatile memory cell EE.

[0204] As Figure 6 illustrated, a read operation 600 is performed in the non-volatile memory cell EE by a first read signal.

[0205] Figure 6An example of generating first read signals is shown, which are adapted to time a read operation 600 in non-volatile memory cells EE of a selected memory word Col, Row.

[0206] First, in step 601, the external control signal Ext_Ctrl is set to 1 by the state machine ME to control the power lines SPLUS, SMINUS.

[0207] Then, in steps 602, 603, the volatile memory cells FF are placed in a state that allows reading of the non-volatile memory cells EE without interference.

[0208] The volatile memory cells FF are initially in a power-off state P0, but the parasitic floating voltage can be maintained on the positive output Q.

[0209] Thus, optional step 602 includes placing the volatile memory cells FF in a discharge state DS, thereby discharging the polarization of the internal nodes of the volatile memory cells FF.

[0210] Then, in step 603, the volatile memory cells FF are placed in a high-impedance state HZ, thereby applying a high-impedance floating potential on the positive output Q of the volatile memory cells FF of the selected memory word.

[0211] Then, the data recorded in the non-volatile memory cells EE is read using a read amplifier AMP.

[0212] More specifically, in step 604, a precharge voltage PRCH is generated on the bit line BL, and in step 605, the local word line WLLOCAL is set to the potential Vdd.

[0213] In step 606, simultaneously with the command of the selection transistor WLLOCAL in step 605, the access transistor TA is turned on on the word line ERWL.

[0214] The word line commands ERWL, WLLOCAL are set to Vdd, for example, Vdd = 3.3V.

[0215] In step 607, a read RD_EE is performed in the non-volatile memory cells.

[0216] In Figure 6 the example of, it is further specified that after the read 607, optionally the power lines are returned to the state P0 through the discharge state DS.

[0217] Referring again to Figure 4 .

[0218] If in step 404 the command is the write command WR, the state machine ME places the external control signal Ext_Ctrl at 1, regardless of the value of the power state PS measured on the selection and status line SSLINE.

[0219] Then, in step 407, if it is detected that the line SSLINE is coupled to ground gnd, the volatile memory cell FF has been written to at least once and is powered by the local decoder WSW in the operating state P1.

[0220] As Figure 7 illustrated, a write operation 700 is performed in the volatile memory cell FF by the first write signal.

[0221] Figure 7 Examples of generating the first write signals are shown, which are adapted to time the write operation 700 in the volatile memory cell FF of the selected memory word Col, Row.

[0222] Thus, the volatile memory cell FF is initially in the operating state P1 and is advantageously placed in the power-off state P0 during step 702 through the discharge state DS during step 701 (optional).

[0223] In step 703, the volatile memory cell FF is in the power-off state P0, and the write device WRM places the bit line BL at a voltage representing the data DAT to be written. For example, if the data DAT is 1, the bit line BL is placed at Vdd = 3.3V, and if the data DAT is 0, the bit line is placed at gnd.

[0224] Then, in step 704, the selection transistor MN3 of the memory point of the memory word is turned on by the local word line voltage WLLOCAL, for example, at Vdd = 3.3V.

[0225] The common node NC of the memory point BTCL and the positive output Q of the volatile memory cell FF are placed at the potential of the data DAT.

[0226] If the data is "1", the potential of the data DAT can, for example, be worth substantially 2V, that is, the voltage on the common node NC rises to 3.3V minus the voltage of the selection transistor MN3 (affected by the substrate effect), in the case where the bit line voltage BL is at 3.3V and the local word line voltage WLLOCAL is at 3.3V.

[0227] If the data is "0", the potential of the data DAT is, for example, ground gnd.

[0228] At this time, in the same step 704, the volatile memory cell FF is commanded in the operating power state P1, and the value of the positive output Q applied before switching to the operating state P1 is recorded accordingly.

[0229] Then the bit line BL and the word line WLLOCAL voltages are released.

[0230] Refer again to Figure 4 .

[0231] In step 407, if the sense line SSLINE is probed at a high impedance HIMP, the volatile memory cell FF is never written by the local decoder WSW and is in the power-off state P0.

[0232] In step 801, the external control signal Ext_Ctrl and the address signals Col, Row satisfy the triple input condition (previously referred to in Figure 2B ), and the power state PS is definitely switched to the second value PS = 1.

[0233] Accordingly, the corresponding local decoder WSW is configured to provide the second value to the power state PS during the first write operation 800 in the memory word.

[0234] As Figure 8 illustrated, the first write operation is performed in the volatile memory cell FF by the first write signal.

[0235] Figure 8 Examples of generating the first write signals are shown, which are adapted to time the first write operation 800 in the volatile memory cell FF of the selected memory word Col, Row.

[0236] The timing of the first write operation is actually the same as the timing of the write operation 700 of the volatile memory cell FF that has already been written.

[0237] Accordingly, the volatile memory cell FF is initially in the power-off state P0 and is optionally kept in the power-off state P0 via the discharge state DS during step 701 starting from step 702.

[0238] The write is completed by putting the volatile memory cell FF into operation in the operating state P1 after charging the positive output Q to the value of the data DAT in the same manner as in steps 703 and 704.

[0239] Read operations 700 and 800 allow for writing to the bistable latch of the volatile memory cell FF in a reliable manner and without an electrical conflict between the power lines PSLUS, SMINUS and the outputs Q, QN, without a differential write on the complementary output QN, using a single asymmetric bit line.

[0240] Referring again to Figure 4 。

[0241] In step 408, thus, at the end of the respective steps 503, 607 and 704, the read operations 500, 600 and the write operations 700, 800 are completed, and the state machine ME returns the external control signal Ext_Ctrl to 0, then, by ending the access to the selected memory word (END@(Col,Row)) in step 409, loops back to the initial step 401.

[0242] Thus, as long as the memory device NVSR is powered on, a new write or read command can be received in step 402.

[0243] In the case where the memory device NVSR is powered off, the state machine ME is configured to record the data in the volatile memory cells FF of the respective memory points BTCL written to the memory plane PM in a non-volatile manner.

[0244] In this regard, reference is made to what is described below Figure 9 。

[0245] It will be noted that the read operation 500 and the write operations 700 and 800 are adapted for reading and writing in the bistable latch of the volatile memory cells FF, which volatile memory cells include only a single asymmetric bit line, the "unit line".

[0246] Thus, an integrated circuit can be provided that includes a static volatile memory device, the static volatile memory device including at least one memory point having a volatile memory cell FF, the volatile memory cell including an output referred to as the positive output Q and a complementary output referred to as the negative output QN, where the positive output Q is coupled to the access node NC, where the negative output QN is not connected to any node external to the volatile memory cell FF, and where the select transistor MN3 is coupled between the access node NC and the single bit line BL.

[0247] This corresponds to the memory point BTCL as described above in connection with Figure 1 but does not include the non-volatile memory cell EE coupled to the access node NC (or common node NC).

[0248] Of course, the memory dots can be organized into memory words in a memory plane, and the device includes a local decoder WSW dedicated to each memory word. Thus, the local decoder WSW and the state machine can be the same as those previously combined Figure 2A described, but, of course, excluding the command circuit of the command gate latch COMCGL, which is dedicated to reading and writing in the non-volatile memory cells EE and is combined Figure 2D described.

[0249] Strictly speaking, the read operation in the volatile memory cells FF described in combination with Figure 3 and 4 and 6 applies to this "single-line" static volatile memory device, and strictly speaking, the write operation in the volatile memory cells FF described in combination with Figure 3 and 4 and 7 and 8 applies to this "single-line" static volatile memory device.

[0250] Now reconsider, in particular, the framework of the non-volatile static random access memory device NVSR in Figure 1 .

[0251] Figure 9 It shows that second write signals are generated in the memory word WD using the data recorded in the volatile memory cells FF of the corresponding memory dots BTCL, and these second write signals time the write operation of the non-volatile memory cells EE, and the volatile memory cells FF of all these memory words store data.

[0252] The write means WRM of the state machine ME is configured to implement a write operation in the non-volatile memory cells. The write operation, which is called a non-volatile write operation, includes an erase cycle followed by a programming cycle.

[0253] Reference will be made to the elements of the command circuit of the command gate latch COMCGL, which is dedicated to reading and writing in the non-volatile memory cells EE belonging to the local decoder WSW of the memory word, as previously combined Figure 2D described.

[0254] It will be recalled that the conditional signals of the state machines ERC, PRC are generated depending on the cycle (erase or program) being executed and the state of the memory word defined by the state PS (PS = 0 or PS = 1) to transfer a voltage to the command gate CG of the state transistor TE.

[0255] The erase cycle includes applying an erase voltage between the command gate CG and the drain of the state transistor TE, and this erase voltage is sufficient to inject charge into the floating gate by the Fowler-Nordheim effect.

[0256] The positive erase voltage of 14V is generated by the high-voltage generator HVGEN( Figure 2A ), and is applied to the high-level power CPLUS of the command gate latch CGL. For example, the low-level power CMINUS of the command gate latch CGL is set to 3V.

[0257] During erasure, ERC = 1 and if PS = 0, then CG = CMINUS = 3V (by the mechanism of the command circuit of the command gate latch COMCGL described previously in Figure 2D ), and no erasure cycle is implemented in this word memory.

[0258] If PS = 1 then CG = CPLUS = 14V, and an erasure cycle is implemented in this word memory.

[0259] A conduction channel is created between the source and drain of the state transistor (the state transistor is considered to be N-type), and the source potential as ground gnd is transmitted to the drain through the channel.

[0260] Therefore, the voltage between the command gate and the drain is 14V, and erasure is generated by injecting charge into the floating gate.

[0261] During erasure, the access transistor TA is turned off by the ground gnd word line signal ERWL.

[0262] Then, the programming cycle includes applying a programming voltage between the command gate CG and the drain of the state transistor TE, which is sufficient or insufficient to inject relative charge into the floating gate by the Fowler-Nordheim effect if the data to be stored is (arbitrarily) 1.

[0263] The data to be stored is recorded on the output Q of the volatile memory cell FF and is thus powered in the operating state P1.

[0264] Then, during programming, the access transistor TA is turned on to couple the output Q to the drain of the state transistor TE.

[0265] The negative programming voltage of -8V is generated by the high-voltage generator HVGEN( Figure 2A ), and is applied to the low-level power CMINUS of the command gate latch CGL. For example, the high-level power CPLUS of the command gate latch CGL is set to 0V (gnd).

[0266] During programming, PRC = 1 and if PS = 0, then CG = CPLUS = gnd (by the mechanism of Figure 2Dthe mechanism of the command circuit of the described command gate latch COMCGL), and there is no implementation of a programming cycle in this word memory.

[0267] If PS = 1, then CG = MINUS = -8V, and a programming cycle in this word memory is possible and is regulated by the level on the drain of the state transistor TE (that is, by the output Q of the bistable latch of the volatile memory cell FF).

[0268] The writing device WRM is configured to place the volatile memory cell FF in a state called the non-volatile programming state PP( Figure 3 ) and generate a positive programming voltage of +6V on the high-level power line SPLUS.

[0269] The low-level power line SMINUS is placed at a potential Vlow, which is positive non-zero, for example, 0.5V, in order to reduce the leakage current in the bistable latch of the volatile memory cell FF. Thus, this allows reducing the total consumption in programming.

[0270] At the same time, the access transistor TA is turned on by the word line voltage ERWL, which follows the level of the voltage SPLUS, for example, at +8V.

[0271] Therefore, if the volatile memory cell FF contains data equal to "1", the positive output Q is placed at the positive programming voltage of +6V, and this positive programming voltage (+6V) is transmitted on the drain of the state transistor TE.

[0272] The first negative programming voltage (-8V) on the command gate CG and the second positive programming voltage (+6V) on the drain of the state transistor TE constitute the conditions for the Fowler-Nordheim effect, and the non-volatile memory cell EE records the data of the output Q equal to "1" in a permanent (non-volatile) manner.

[0273] And, if the volatile memory cell FF contains data equal to "0", the positive output Q is placed at the low-level power voltage SMINUS at Vlow = 0.5V.

[0274] The first negative programming voltage (-8V) on the command gate CG and the low-level power voltage Vlow on the drain of the state transistor TE do not constitute the conditions for the Fowler-Nordheim effect, and due to erasure and lack of programming, the non-volatile memory cell EE records the data of the output Q equal to "0" in a permanent (non-volatile) manner.

[0275] The non-volatile write operation is implemented in all memory words WD of the memory plane PM in which the power state PS has a second value, that is, in all memory words WD of the memory plane PM in which the volatile memory cells FF have been written and contain data. For example, the operation can be implemented simultaneously in the memory words WD of the memory plane PM.

[0276] The write operation can of course be commanded by the user, in which case the non-volatile write stimulus can be generated using the main power supply that is normally distributed to the device.

[0277] In addition, the write operation is systematically commanded in the case of the shutdown of the memory device NVSR, whether spontaneous or not, in which case a secondary power stage is advantageously provided to supply energy, thus allowing the generation of a non-volatile write stimulus.

[0278] In this regard, reference is made to Figure 12 .

[0279] Figure 12 illustrates an example of an advantageous power device ALM, which can for example be incorporated into the integrated circuit chip described previously in connection with Figure 11 .

[0280] The power device ALM includes a main power stage PWS, which is intended to supply a first power voltage Vdd at an external power node ExtVdd.

[0281] The first power voltage Vdd is suitable for the operation of the memory device (such as the non-volatile static random access memory device NVSR described previously in connection with Figures 1 to 11 ).

[0282] The power device ALM also includes a secondary power stage CAP_STG, which is intended to supply a second power voltage Vdd2 to the memory device NVSR in the case of the shutdown of the memory device NVSR.

[0283] The secondary power stage CAP_STG includes: a capacitor C, which is intended to be charged with the second power voltage Vdd2; and a first charge pump circuit CP_A, REG_A, which is configured to generate the second power voltage Vdd2 from the first power voltage Vdd, the level of the second power voltage being higher than the level of the first power voltage Vdd.

[0284] Thus, as will be seen below, by increasing the voltage for charging the capacitor C and advantageously by optimizing the efficiency of the charge pump (see CP_B below) of the high-voltage generator of the memory, a memory device with a low capacitance value of the capacitor C can be operated and low-voltage operation of the memory device is allowed.

[0285] In addition, since the required additional energy caused by the high-temperature leakage current is attenuated by the large amount of energy stored in the capacitor, high-temperature operation is also promoted.

[0286] This situation allows for cost reduction and expansion of the application range of non-volatile static random access memory devices that were previously limited by high prices.

[0287] The memory device NVSR in this example includes a state machine ME (such as described above in conjunction with Figures 1 to 11 ), and a high-voltage generator HVGEN incorporating a second charge pump circuit CP_B.

[0288] The state machine ME is powered by a constant regulated voltage Vdd1 at the output of the internal regulation stage IntREG.

[0289] The power supply device ALM includes a power management circuit PWMG, which is configured to command switches sw1, sw2, sw3, sw4 to supply power to the memory device NVSR using the main power stage PWS or the secondary power stage CAP_STG.

[0290] For example, in the first power mode, the first switches sw1 and sw2 are closed, and the second switches sw3 and sw4 are open. Thus, the first power voltage Vdd is supplied to the device NVSR and the first charge pump circuit CP_A, while the secondary power stage CAP_STG is disconnected from the device NVSR.

[0291] The first charge pump circuit CP_A is regulated, for example, by a closed-loop regulator REG_A.

[0292] The power management circuit PWMG is configured to detect the loss of the main power supply PWS, that is, shutdown or disconnection, for example, by the voltage drop on the node ExtVdd that receives the first power voltage. The node ExtVdd is, for example, an integrated circuit package pin.

[0293] If this is the case, the power management circuit PWMG is configured to immediately switch to the second power mode, in which switches sw1 and sw2 are open and switches sw3 and sw4 are closed. Thus, the second power voltage Vdd2 is supplied by the capacitor C on the power input VddCP of the second charge pump circuit CP_B and supplied to the state machine ME via the regulator IntREG, while the main power stage PWS is disconnected from the device NVSR.

[0294] Now, the size of the capacitor C will be discussed in view of its suitability for non-volatile write operations such as those described above in conjunction with Figure 9 as described.

[0295] In the following text, the reference sign C for the capacitor will also designate the capacitance value of the capacitor. Besides the usual addition "+", subtraction "-", and division " / " symbols, the character "*" represents the symbol for multiplication, and the character "^" represents the symbol for exponentiation (thus, the expression "the Nth power of A" is represented by "A^N").

[0296] If the capacitor C is charged with an initial power voltage Vi, the charge stored in the capacitor is equal to C*Vi, and represents 1 / 2*C*Vi 2 of the energy.

[0297] During a non-volatile write operation with an operation duration T, energy is supplied by the capacitor C.

[0298] The energy consumed for writing is Ww = 1 / 2*C*(Vi 2 -Vf 2 ).

[0299] Thus, where Vi is the initial voltage across the capacitor C, and Vf is the final voltage across the capacitor C after the duration T.

[0300] Vf = (Vi 2 -2*Ww / C)^ 1 / 2

[0301] However, the final voltage Vf across the capacitor C must be high enough to allow the correct execution of the write command, and specifically to allow the proper operation of the charge pump CP_B that generates the write stimulus.

[0302] The size of a conventional charge pump is designed to allow correct operation at the final voltage Vf at the end of the write cycle. Thus, a conventional charge pump is oversized at the beginning of the write cycle with the initial voltage Vi. Then, the efficiency of the conventional charge pump is not optimal throughout the duration of the write cycle, and deteriorates when the ratio between the initial voltage Vi and the final voltage Vf increases.

[0303] The following presents estimates of the energy Wi (1 ≤ i ≤ 8) consumed by the functions listed respectively in a memory device of the non-volatile static random access memory NVSR type as described above: Figures 1 to 11 pointed out by

[0304] – Consumption during the erase phase of the memory plane:

[0305] Charging the capacitor from 1 nF (command grid CG) to 15 V; W1 = 113 nJ (= 1 / 2*1 nF*15 V2)

[0306] Maintain a voltage of 15V for 2ms, with a leakage current of 20μA; W2 = 600nJ (= 2ms * 15V * 20μA)

[0307] Maintain a voltage of 3V for 2ms on the bistable latch FF, with a leakage current of 100μA; W3 = 600nJ (= 2ms * 3V * 100μA)

[0308] Total for the erase phase: 1313nJ

[0309] – Consumption of the memory plane during the programming phase:

[0310] Charge the capacitor from 1nF (CG) to -8V; W4 = 320nJ (= 1 / 2 * 1nF * 8V 2 )

[0311] Maintain a voltage of -8V for 2ms, with a leakage current of 10μA; W5 = 160nJ (= 2ms * 8V * 10μA)

[0312] Charge the capacitor from 10nf (FF) to 3V; W6 = 45nJ (= 1 / 2 * 10nF * 3V 2 )

[0313] Maintain a voltage of 5.5V for 2ms, with a leakage current of 100μA; W7 = 1100nJ (= 2ms * 5.5V * 100μA)

[0314] Total for the programming phase: 1625nJ

[0315] - Operation of the peripheral during the write operation:

[0316] 3V for 4ms, with a current of 200μA; W7 = 2400nJ (= 4ms * 3V * 200μA)

[0317] Therefore, the total energy Wtot supplied by the charge pump powered by the capacitor C is worth: Wtot = sum(Wi) = 5338nJ, which is rounded to Wtot = 6μJ by including various losses not mentioned in the above list.

[0318] In the case of a conventional charge pump, the average efficiency during the write operation is 20%, and the total energy consumed on capacitor C is estimated to be Wtotal = 25μJ.

[0319] However, particularly due to the use of EEPROM type non-volatile memory cells EE, which is different from the conventionally used flash type non-volatile memory cells, this estimated value of the energy Wtot is lower than that of a conventional non-volatile random access memory NVSRAM.

[0320] Recall that, Wtotal = 1 / 2*C*(Vi 2 -Vf 2 ) and thus Cmin = 2*Wtotal / (Vi 2 -Vf 2 ).

[0321] First, the sizing of a capacitor charged with an initial voltage Vi equal to the first power voltage Vdd is presented below. This corresponds to an example of a conventional power stage that does not particularly include the first charge pump circuit CP_A, REG_A at the input of the capacitor C.

[0322] If Vi = Vdd = 3V, Vf = 1.8V and Wtotal = 25 μJ, then Cmin = 8.7 μF, which is actually a capacitor C with a capacitance value C = 10 μF.

[0323] If Vi = Vdd = 1.8V, Vf = 1.6V and Wtotal = 25 μJ, then Cmin = 73 μF, which is actually a capacitor C with a capacitance value C = 100 μF.

[0324] Thus, in a conventional power device that powers the memory device NVSR described above, a capacitor C with a capacitance value of at least 10 μF must be provided for the first power voltage Vdd of 3V, and a capacitor C with a capacitance value of at least 100 μF must be provided for the first power voltage Vdd of 1.8V.

[0325] Secondly, if the capacitor C is charged with a second power voltage Vdd2 (= Vi), leaving the first charge pump CP_A, where Vdd2 > Vdd, then Cmin can be significantly reduced, and if Vdd is low, for example, if Vdd = 1.8V, the difference is more obvious.

[0326] Recall that, Cmin = 2*Wtotal / (Vi 2 -Vf 2 ) and the energy consumption estimate value Wtotal = 25 μJ is restored.

[0327] If Vi = Vdd2 = 5.5V, Vf = 1.6V and Wtotal = 25 μj, then Cmin = 1.81 μF, which is actually a capacitor C with a capacitance value C = 2.2 μF.

[0328] The charge pump CP_A stores more energy in the capacitor C and thus allows a significant reduction in the capacitance value of the capacitor C. This represents an important advantage with respect to the cost of the device and the surface used by the capacitor C.

[0329] Furthermore, the additional consumption in normal operation caused by the first charge pump CP_A (e.g., to compensate for the voltage drop due to internal leakage in the capacitor C) can be neglected.

[0330] In fact, in the case of a typical insulation resistance of 100 Ω.F (ohm farad), the current at 5.5 V for a 2.2 μF capacitor is 120 nA. The energy loss is 120 nA * 5.5 V = 666 nW. For a 25% charge pump CP_A efficiency, this gives a consumption of 2.66 μW for the charge pump CP_A, that is, 1.5 μA at 1.8 V, which can reasonably be neglected.

[0331] Furthermore, the power device ALM includes a high-voltage generator HVGEN incorporated into the second charge pump CP_B to generate the write excitation for the memory device NVSR.

[0332] Thus, the high-voltage generator HVGEN and the second charge pump CP_B of the power device ALM constitute the write means WRM of the memory device NVSR.

[0333] The second charge pump CP_B includes a plurality of basic charge pump stages CP_B1, ΦGEN_1; CP_B2, ΦGEN_2; CP_BN, ΦGEN_N, each stage of which can be added to a series of basic stages, where the amplified voltage leaving each stage is supplied at the input of the next stage.

[0334] Each basic charge pump stage CP_Bk, ΦGEN_k (1 ≤ k ≤ N) generally includes a charge pump circuit CP_Bk that is capable of increasing the voltage level by the reflection of charges in the capacitive node through switching commanded by the corresponding phase generator circuit ΦGEN_k. The phase generator circuit ΦGEN_k is timed by the clock signal generated by the oscillator circuit OSC.

[0335] Thus, these stages are suitable for being coupled in series in order to accumulate, for example, the respective amplification factors of the second power voltage Vdd2 by switches sw5, sw6, sw7, sw8 respectively coupled between the output (out) of one stage and the input (in) of the next stage.

[0336] For example (not shown), the switches can allow the output of a set of basic charge pump stages to be coupled in series with the input of the next similar set. In an equivalent manner, the switches sw5, sw6, sw7, sw8 can be commanded in groups rather than individually.

[0337] The regulating stage REG-B is configured to regulate a series of basic charge pump stages CP_Bk, ΦGEN_k in a closed loop by sending a command feedback to the phase generator ΦGEN_k.

[0338] The power management circuit constitutes a command device PWMG, which is capable of measuring the current value of the second power voltage Vdd2 and commanding a series of the following different charge pump stages to be continuously coupled: CP_B1, ΦGEN_1; CP_B2, ΦGEN_2; CP_BN, ΦGEN_N.

[0339] By following the decrease in the current value of the second power voltage Vdd2, a series of additional stages are commanded to be coupled one by one continuously and monotonically.

[0340] In fact, according to the above example of the capacitor C, with the size designed as C = 2.2 μF, the second voltage Vdd2 can be reduced from 5.5 V to 1.6 V.

[0341] Therefore, at the beginning, when the power supply Vdd2 is at its maximum, only the first stage (charge pump CP_B1) is used.

[0342] The command device PWMG measures the current value of the second power voltage Vdd2, for example, according to the value of the instantaneous voltage across the capacitor or according to the signal from the closed-loop regulator REG_A of the first charge pump CP_A.

[0343] If the circuit detects that the first charge pump stage CP_B1 can no longer supply the requested voltage, it connects the second stage CP_B2 in series with the first stage CP_B1.

[0344] The same process can be repeated until N basic stages, for example, N = 15.

[0345] At the end of the write operation, the series can be equipped with all the activated charge pump stages CP_B1, CP_B2,..., CP_BN.

[0346] The charge pump stages can be coupled in series in groups to particularly advantageously reduce the complexity related to fine granularity.

[0347] For example, if N = 15, 3 groups can be provided, with each group having five "basic" charge pump stages CP_Bk - CP_Bk+5.

[0348] Therefore, in the process described above, whenever the command device PWMG detects that the series CP_B1 - CP_Bk-1 can no longer supply the requested voltage, multiple basic charge pump stages CP_Bk are simultaneously coupled in series.

[0349] In summary, in combination herewith Figure 12The described power device ALM proposes to increase the initial charging voltage of the capacitor C to above the rated voltage Vdd, for example, doubling it, Vdd2 = 2 * Vdd; and also proposes to reduce the energy consumed by the high-voltage signal generator HVGEN during non-volatile write operations by dynamically optimizing the efficiency of the second charge pump CP_B.

[0350] The power device ALM particularly allows reducing the size of the capacitor C and operating at a very low power supply voltage (e.g., 1.8V).

[0351] Therefore, both the manufacturing cost is reduced, the congestion of the memory device is reduced, and it promotes the integration of the capacitor C into the memory device NVSRAM on the chip or inside the hybrid package.

[0352] Of course, in combination with Figure 12 the described power device ALM has its advantages for any type of memory device with similar requirements.

[0353] In this case, in combination with Figure 12 the described power device ALM is particularly advantageously suitable for combination with Figures 1 to 11 the described non-volatile static random access memory device NVSR. In fact, the memory device NVSR not only generates its own saved space but also allows amplifying the saved space obtained by reducing the size of the capacitor C of the power device ALM, because the memory device NVSR has reduced energy consumption due to the presence of a single non-volatile memory cell EE per memory point BTCL, and in addition, this single non-volatile memory cell is of the EEPROM type.

Claims

1. An integrated circuit, comprising: A memory device, including memory planes, the memory planes including a plurality of memory spots arranged in at least one memory word, each memory spot of the plurality of memory spots including: A volatile memory cell and a single non-volatile memory cell, together coupled to a common node; and A single select transistor, coupled between the common node and a single bit line, Wherein a first output of the volatile memory cell is coupled to the common node, and Wherein a second output of the volatile memory cell is not connected to any node external to the volatile memory cell, and the second output is complementary to the first output; Wherein the memory device further includes a local decoder, the local decoder including a power line, and the power line is configured to store a power state in a status register, a first value of the power state representing a non-operating state of the volatile memory cells of the corresponding memory word, a second value of the power state representing an operating state of the volatile memory cells of the corresponding memory word; and Wherein the local decoder is configured to maintain a first set of power voltages on the power line as long as the power state has the second value, the first set of power voltages being suitable for powering the functions of the volatile memory cells.

2. The integrated circuit according to claim 1, wherein the volatile memory cell includes a bistable latch, the bistable latch including two inverters mounted in anti-parallel, and the non-volatile memory cell includes a state transistor and an access transistor, the state transistor having a command gate and a floating gate, the access transistor being serially coupled between the common node and the state transistor.

3. The integrated circuit according to claim 1, wherein the memory spot includes a transistor number equal to 7.

4. The integrated circuit according to claim 1, wherein the at least one memory spot further includes an isolation transistor serially coupled between the common node and the volatile memory cell.

5. The integrated circuit according to claim 4, wherein the memory spot includes a transistor number equal to 8.

6. The integrated circuit according to claim 1, wherein the memory device includes one local decoder per memory word and the power line is coupled to the power terminals of the volatile memory cells of the corresponding memory word.

7. The integrated circuit according to claim 6, wherein the memory device further comprises: A read circuit arrangement, configured to generate a first read signal in response to the corresponding power state having the first value, the first read signal being suitable for timing a read operation in the non-volatile memory cell of the selected memory word, and to generate a second read signal in response to the corresponding power state having the second value, the second read signal being suitable for timing a read operation in the volatile memory cell of the selected memory word.

8. The integrated circuit according to claim 7, wherein the read circuit means is configured to generate a second set of power voltages on the power line of the selected memory word among the first read signals, the second set of power voltages being adapted to apply a high impedance floating potential on the first output coupled to the common node of the volatile memory cells.

9. The integrated circuit according to claim 7, wherein the reading circuit device comprises: A read amplifier, configured to generate a precharge voltage on the bit line of the memory point being read among the first read signal and the second read signal, and to detect a change in current or voltage on the bit line during a read operation in the non-volatile memory cell and during a read operation in the volatile memory cell, respectively.

10. The integrated circuit according to claim 6, wherein the memory device further comprises: A write circuit means, configured to generate a first write signal, the first write signal being adapted to time a write operation in the volatile memory cells of the selected memory word independently of any value of the power state, and the local decoder of the corresponding memory word being configured to provide the power state with the second value after the write operation.

11. The integrated circuit according to claim 10, wherein the write circuit means is configured to generate a third set of power voltages among the first write signals on the power line of the selected memory word, the third set of power voltages being adapted to abort the function of the volatile memory cells, then to generate a data signal to be stored on the common node, which is applied via the bit line of the memory point of the selected memory word, and then to generate a first set of power voltages on the power line, which is adapted to power the function of the volatile memory cells.

12. The integrated circuit according to claim 11, wherein the write circuit means is configured to generate a fourth set of power voltages among the first write signals on the power line of the selected memory word, the fourth set of power voltages being adapted to discharge the polarization of the internal nodes of the volatile memory cells of the selected memory word before generating the third set of power voltages.

13. The integrated circuit according to claim 11, wherein the write circuit means is configured to generate a second write signal in all the memory words having the second value in their respective power states in response to a shutdown of the memory device, the second write signal being adapted to time a write operation of the non-volatile memory cells with the data recorded in the volatile memory cells of the corresponding memory points.

14. The integrated circuit according to claim 13, wherein the volatile memory cells include bistable latches, the bistable latches include two inverters mounted in anti-parallel, and the non-volatile memory cells include a state transistor and an access transistor, the state transistor having a command gate and a floating gate, and the access transistor being serially coupled between the common node and the state transistor; and The write circuitry is configured to generate, among the second write signals, an erase voltage on the command gate of the state transistor, a first programming voltage on the command gate of the state transistor, and a fifth set of power voltages on the power line of the volatile memory cell, in the memory words having the second value in their respective power states, the fifth set of power voltages being adapted to place the common node at a second programming voltage.

15. The integrated circuit according to claim 13 further includes a power device, and the power device includes: A main power stage, adapted to supply a first power voltage for operating the memory device; And a secondary power stage, adapted to supply a second power voltage, the second power voltage being adapted to power the write operation of the non-volatile memory cell in response to the shutdown of the memory device.

16. The integrated circuit according to claim 15, wherein the secondary power stage comprises: A capacitor, adapted to be charged with the second power voltage; And a first charge pump circuit, configured to generate the second power voltage from the first power voltage, the level of the second power voltage being higher than the level of the first power voltage.

17. The integrated circuit according to claim 15, wherein the power device further comprises: At least one high voltage generator, incorporated in the write circuitry of the memory device, for generating the second write signals adapted to time the write operation of the non-volatile memory cell, wherein the high voltage generator includes a plurality of elementary charge pump stages, the elementary charge pump stages being adapted to be coupled in series so as to accumulate a respective amplification of the second power voltage; And a command circuitry, configured to measure a current value of the second power voltage and, after the current value of the second power voltage decreases, command the elementary charge pump stages to be successively coupled in series.

18. A method for commanding a memory device, the memory device comprising: At least one memory spot, including a volatile memory cell and a single non-volatile memory cell, the volatile memory cell and the single non-volatile memory cell being coupled together to a common node; A single selection transistor, coupled between the common node and a single bit line, a first output of the volatile memory cell being coupled to the common node and a second output of the volatile memory cell not being connected to any node external to the volatile memory cell, the second output being complementary to the first output; A memory plane, including a plurality of the memory spots arranged in at least one memory word, the method including: Storing a power state of each memory word, a first value of the power state representing a non-operating state of the volatile memory cell of the respective memory word and a second value of the power state representing an operating state of the volatile memory cell of the respective memory word; And Maintaining a first set of power voltages, the first set of power voltages powering the volatile memory cells of all the memory words having the second value in their power states in an operating state.

19. The method according to claim 18, further comprising: Generating a first read signal in response to the respective power state having the first value, the first read signal timing a read operation in the non-volatile memory cell of the selected memory word; And, in response to the corresponding power state having the second value, a second read signal is generated, and the second read signal times a read operation in the volatile memory cells of the selected memory word.

20. The method according to claim 19 further comprises: A second set of power voltages among the first read signals is generated, and the second set of power voltages applies a high-impedance floating potential on the first output coupled to the common node in the volatile memory cells of the selected memory word.

21. The method according to claim 19, further comprising: A precharge voltage on the bit line at the memory point among the first read signal and the second read signal is generated, and changes in current or voltage on the bit line are detected respectively during a read operation in the non-volatile memory cell and during a read operation in the volatile memory cell.

22. The method according to claim 18 further comprises: A first write signal is generated, and the first write signal times a write operation in the volatile memory cells of the selected memory word regardless of any value of the power state, and provides the corresponding power state having the second value after the write operation.

23. The method according to claim 22 further comprises: A third set of power voltages among the first write signals is generated to power the volatile memory cells of the selected memory word so as to abort the functions of the volatile memory cells, then a data signal to be stored on the common node is generated and applied via the bit line at the memory point of the selected memory word, and then a first set of power voltages to power the volatile memory cells of the selected memory word in an operating state is generated.

24. The method according to claim 23, further comprising: A fourth set of power voltages among the first write signals is generated to power the volatile memory cells of the selected memory word so as to polarize and discharge the internal nodes of the volatile memory cells of the selected memory word before each generation of the third set of power voltages.

25. The method according to claim 22, further comprising: In response to a shutdown of the memory device, a second write signal is generated in all the memory words whose corresponding power states have the second value, and the second write signal times a write operation of the non-volatile memory cell by using the data recorded in the volatile memory cells at the corresponding memory points.

26. The method according to claim 25, wherein the volatile memory cell includes a bistable latch, the bistable latch includes two inverters mounted in anti-parallel, and the non-volatile memory cell includes a state transistor and an access transistor, the state transistor has a command gate and a floating gate, the access transistor is serially coupled between the common node and the state transistor, and the method further includes: In the memory words whose corresponding power states have the second value, an erase voltage on the command gate of the state transistor, a first programming voltage on the command gate of the state transistor, and a fifth set of power voltages to power the volatile memory cells so as to place the common node at a second programming voltage among the second write signals are generated.

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