Semiconductor device

Abstract

The present disclosure relates to a semiconductor device. The semiconductor device includes two memory chips, one control chip for controlling each of the memory chips, a signal transmission path through which signal transmission between the control chip and each of the memory chips is performed, and a capacitance coupled to the signal transmission path. Furthermore, the capacitance (capacitor element) is greater than each of parasitic capacitances parasitic on each chip. Thus, signal transmission of the semiconductor device can be performed at high speed.

Description

[0001] Cross Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2020-11001 filed on January 27, 2020 (including the specification, drawings, and abstract) is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to a semiconductor device (or also referred to as an "electronic device") in which a plurality of semiconductor components are electrically connected with one semiconductor component. For example, the present application is applicable to a semiconductor device (or electronic device) in which two memory chips are controlled by one control chip. BACKGROUND

[0004] The disclosed technology is listed below.

[0005] [Patent Literature 1] Japanese Unexamined Patent Application Publication No. 2015-35159

[0006] [Patent Literature 2] Japanese Unexamined Patent Application Publication No. 2012-8920

[0007] There is a semiconductor device in which a plurality of memory chips and a control chip for controlling each of the plurality of memory chips are electrically connected with each other in a T-branch structure (T-branch topology) (for example, see Figure 10 of Patent Literature 1). In addition, there is a semiconductor device in which the above-described memory chips and the above-described control chip are electrically connected with each other in a fly-by topology (for example, see Figures 7 to 9 of Patent Literature 1). Furthermore, there is a semiconductor device in which a termination resistor is provided, for example, at an end of a signal transmission path through which a data signal is transmitted. SUMMARY

[0008] In the case of a configuration in which two memory chips each serving as a load are controlled by one control chip (hereinafter referred to as a "branch case"), such as a semiconductor device employing a "T-branch topology" or a semiconductor device employing a "fly-by topology", the driving capability of the control chip that controls the memory chips is insufficient compared to a configuration in which one memory chip is controlled by one control chip (hereinafter referred to as a "reference case"). Therefore, through the research of the present inventor, it was found that there is a possibility that a signal cannot be transmitted in the "branch case" due to the following reasons: 1) a configuration of a signal transmission path through which signal transmission between the control chip and each of the memory chips is performed, and; 2) a transmission speed (i.e., a data rate) of a signal to be transmitted on the signal transmission path.

[0009] Other objects and novel features will become apparent from the description and drawings.

[0010] Typical embodiments disclosed in the present application will be described briefly below.

[0011] A semiconductor device according to one embodiment includes a first memory chip, a second memory chip, a control chip that controls each of the memory chips, and a first signal transmission path through which signal transmission between the control chip and each of the memory chips is performed. Further, signal transmission between the control chip and the first memory chip is performed via the first signal transmission path. On the other hand, signal transmission between the control chip and the second memory chip is performed via a portion of the first signal transmission path and a second signal transmission path that branches from the first signal transmission path at a first branch point of the first signal transmission path, the first branch point being located between the control chip and the first memory chip. Further, a capacitance larger than each of parasitic capacitances parasitic on each of the chips is coupled to a third signal transmission path that branches from the first signal transmission path at a second branch point of the first signal transmission path, the second branch point being located between the control chip and the first branch point of the first signal transmission path.

[0012] In addition, a semiconductor device according to another embodiment includes a wiring substrate, a memory device mounted on the wiring substrate, a control chip mounted on the wiring substrate, and a capacitor element mounted on the wiring substrate. Here, the wiring substrate includes a first wiring that is a transmission path for a signal. In addition, the memory device includes an interposer, a first memory chip mounted on the interposer, a second memory chip mounted on the interposer, a first conductive material electrically connected to a first electrode pad of the first memory chip, a second conductive material electrically connected to a second electrode pad of the second memory chip, and an external connection terminal electrically connected to each of a first input / output circuit of the first memory chip and a second input / output circuit of the second memory chip. Further, the control chip controls each of the memory chips. Further, the capacitor element includes a first electrode electrically connected to the first wiring of the wiring substrate. Further, the first wiring has a first terminal electrically connected to an external connection terminal of the control chip and a second terminal electrically connected to the external connection terminal of the memory device. Further, the first input / output circuit of the first memory chip is electrically connected to the control chip via the first electrode pad of the first memory chip, the first conductive material, the external connection terminal of the memory device, and the first wiring of the wiring substrate. Further, the second input / output circuit of the second memory chip is electrically connected to the control chip via the second electrode pad of the second memory chip, the second conductive material, the external connection terminal of the memory device, and the first wiring of the wiring substrate. Further, the first electrode of the capacitor element is coupled to a path of the first wiring between the first terminal and the second terminal. Further, a capacitance of the capacitor element is greater than each of parasitic capacitances parasitic on each of the chips.

[0013] Further, a semiconductor device according to another embodiment includes: a wiring substrate; a first memory device mounted on the wiring substrate; a second memory device mounted on the wiring substrate; a control chip mounted on the wiring substrate; and a capacitor element mounted on the wiring substrate. Here, the wiring substrate includes a first wiring that is a transmission path for a signal. Further, the first memory device includes: a first interposer; a first memory chip mounted on the first interposer; a first conductive material electrically connected to a first electrode pad of the first memory chip; and a first external connection terminal electrically connected to a first input / output circuit of the first memory chip. Further, the second memory device includes: a second interposer; a second memory chip mounted on the second interposer; a second conductive material electrically connected to a second electrode pad of the second memory chip; and a second external connection terminal electrically connected to a second input / output circuit of the second memory chip. Further, the control chip controls each memory chip. Further, the capacitor element includes a first electrode electrically connected to the first wiring of the wiring substrate. Further, the first wiring has: a first terminal electrically connected to an external connection terminal of the control chip; a second terminal electrically connected to the first external connection terminal of the first memory device; and a third terminal electrically connected to the second external connection terminal of the second memory device. Further, the first input / output circuit of the first memory chip is electrically connected to the control chip via: the first electrode pad of the first memory chip, the first conductive material, the first external connection terminal of the first memory device, and the first wiring of the wiring substrate. Further, the second input / output circuit of the second memory chip is electrically connected to the control chip via: the second electrode pad of the second memory chip, the second conductive material, the second external connection terminal of the second memory device, a portion of the first wiring of the wiring substrate, and a second wiring of the wiring substrate. Here, the second wiring is a wiring branched from the first wiring at a first branch point of the first wiring, the first branch point being between the first terminal and the second terminal. Further, the first electrode of the capacitor element is coupled to a path of the first wiring between the first terminal, the second terminal, and the third terminal. Further, a capacitance of the capacitor element is greater than each parasitic capacitance parasitically present on each chip.

[0014] According to the semiconductor device described above in one embodiment, it is possible to provide a semiconductor device capable of transmitting a signal at high speed.

[0015] Further, according to the semiconductor device described above in another embodiment, it is possible to provide a semiconductor device capable of transmitting a signal at high speed.

[0016] Further, according to the semiconductor device in another embodiment, a semiconductor device capable of transmitting a signal at high speed can be provided. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a diagram (circuit diagram) illustrating a configuration of a semiconductor device researched by the present inventors;

[0018] Figure 2 is a diagram showing an eye pattern of a reference case researched by the present inventors;

[0019] Figure 3 is a diagram showing an eye pattern of a branch case 1 researched by the present inventors;

[0020] Figure 4 is a diagram showing an eye pattern of a branch case 2 researched by the present inventors;

[0021] Figure 5 is a diagram showing charge exchange occurring when a signal voltage is raised in the above branch case 2;

[0022] Figure 6 is a diagram showing charge exchange occurring when a signal voltage is lowered in the above branch case 2;

[0023] Figure 7 is a diagram (circuit diagram) illustrating a configuration of a semiconductor device found by the present inventors;

[0024] Figure 8 is a diagram showing charge exchange occurring when a signal voltage is raised in the above branch case 2;

[0025] Figure 9 is a diagram showing charge exchange occurring when a signal voltage is lowered in the above branch case 2;

[0026] Figure 10 is a diagram (circuit diagram) illustrating a configuration of a semiconductor device according to Embodiment 1;

[0027] Figure 11 is a diagram (plan view) schematically illustrating a planar layout of each electronic component constituting the semiconductor device according to Embodiment 1;

[0028] Figure 12 is a diagram (partly enlarged cross-sectional view) schematically illustrating a longitudinal cross-sectional structure of the above semiconductor device along an A-A cross-sectional line of Figure 11

[0029] Figure 13 is a diagram illustrating usage examples of each input / output circuit, each termination resistor, and the like, in which Embodiment 1 and a modified example of Embodiment 1 are compared; ​

[0030] Figure 14 is a diagram (circuit diagram) illustrating a configuration of a semiconductor device according to Embodiment 2;

[0031] Figure 15 is a diagram (plan view) schematically illustrating a planar layout of each electronic component constituting the semiconductor device according to Embodiment 2;

[0032] Figure 16 is a diagram (partly enlarged cross-sectional view) schematically illustrating a longitudinal cross-sectional structure of the semiconductor device shown in Figure 15

[0033] Figure 17 is a diagram showing usage examples of each input / output circuit, each termination resistor, and the like, in which Embodiment 2 is compared with each of Embodiment 1 and the modified example of Embodiment 1; and

[0034] Figure 18 is a diagram illustrating a modified example of the above-described capacitor element in each of Embodiment 1 and Embodiment 2. DETAILED DESCRIPTION

[0035] (Research Example)

[0036] First, before explaining the "DETAILED DESCRIPTION", the configuration of a semiconductor device researched by the present inventors and a problem clarified through the research of the present inventors will be explained in detail.

[0037] <Research Example Semiconductor Device SDR1r>

[0038] Figure 1 is a diagram (circuit diagram) illustrating a configuration of a semiconductor device SMD1r researched by the present inventors. As Figure 1 indicated, the semiconductor device SMD1r includes two memory chips MC1, MC2 and a control chip CC that controls the two memory chips MC1, MC2.

[0039] As Figure 1 indicated, each of the memory chips MC1, MC2 has electrode pads PD1, PD2, input / output circuits IO1, IO2 electrically connected to the electrode pads PD1, PD2, and termination resistors TR1, TR2 electrically connected to the electrode pads PD1, PD2. Incidentally, as Figure 1 indicated, one end portion of each of the termination resistors TR1, TR2 is electrically connected to each of the electrode pads PD1, PD2 of each of the memory chips MC1, MC2, and the other end portion opposite to the end portion is connected to a reference potential (i.e., "R=∞"). As Figure 1 ​As shown, for example, a parasitic capacitance PCT1, PCT2 of approximately 0.8 pF is parasitic on the respective electrode pad PD1, PD2. In other words, each parasitic capacitance PCT1, PCT2 is connected to each signal transmission path STP1, STP2 to which each input / output circuit IO1, IO2 is connected. Furthermore, the two memory chips MC1, MC2 are of the same type as each other, for example, LPDDR5-SDRAM (Low Power Double Data Rate 5 - Synchronous Dynamic Random Access Memory in accordance with JEDEC standards).

[0040] On the other hand, as Figure 1 shown, the control chip CC has an electrode pad PD and a control circuit SCC electrically connected to the electrode pad PD. As Figure 1 shown, as with the memory chips MC1, MC2, the electrode pad PD has a parasitic capacitance PCT0 of approximately 0.8 pF parasitic on the electrode pad PD. In other words, the parasitic capacitance PCT0 is connected to the signal transmission path STP1 to which the control circuit SCC is connected.

[0041] As described above, the semiconductor device SMD1r includes the signal transmission paths STP1, STP2, and signal transmission between the control chip CC and the memory chips MC1, MC2 is performed via the signal transmission paths STP1, STP2. Specifically, as Figure 1 shown, signal transmission between the control chip CC and the first memory chip MC1 is performed via the signal transmission path STP1. On the other hand, as Figure 1 shown, signal transmission between the control chip CC and the second memory chip MC2 is performed via a portion of the signal transmission path STP1 and the signal transmission path STP2 branched from the signal transmission path STP1 at a branching point N1 between the control chip CC and the first memory chip MC1. The signal transmission path STP1 from the branching point N1 to the first memory chip MC1 is the main path for the first memory chip MC1. Similarly, the signal transmission path STP2 from the branching point N1 to the second memory chip MC2 is the main path for the second memory chip MC2. However, in the present study example (including the underlying idea described later), the signal transmission path STP2 from the branching point N1 to the second memory chip MC2 is described as a path (branch line) branched from the signal transmission path STP1 connecting the control chip CC and the first memory chip MC1.

[0042] Furthermore, the distance of the signal transmission path STPl from the branch point Nl to the electrode pad PDl of the memory chip MC 1 and the distance of the signal transmission path STP2 from the branch point Nl to the electrode pad PD2 of the memory chip MC2 are substantially the same as each other. That is, the connection form between the first control chip CC and each of the memory chips MC 1, MC2 adopts a so-called "T-branch topology". It should be noted that "substantially the same" here means that although the products of actual design are the same, the products are not necessarily the same as each other due to manufacturing differences of the products actually manufactured. In addition, a so-called fly-by topology in which the above-mentioned distances are different from each other can be used as the connection mode of the control chip CC and each of the memory chips MC 1, MC2.

[0043] Next, the signal transmission operation of the above-mentioned semiconductor device SMDIr will be described.

[0044] For example, when the first memory chip MC1 is accessed, the input / output circuit IO1 of the first memory chip MC1 is activated, while the input / output circuit IO2 of the second memory chip MC2 is deactivated. When the first memory chip MC1 is accessed, the resistance value (R) of the termination resistor TR1 is reduced to turn on the termination resistor TR1 of the first memory chip MC1 to be accessed (i.e., to make it closer to the state where the first memory chip MC1 exists), while the resistance value (R) of the termination resistor TR2 is increased to turn off the termination resistor TR2 of the second memory chip MC2 not to be accessed (i.e., to make it closer to the state where the termination resistor TR2 does not exist). The term "access" used herein refers to, for example, an operation for writing data into a memory chip (write operation), an operation for reading data stored in a memory chip (read operation), or an operation for erasing data stored in a memory chip (erase operation). In addition, the control circuit SCC of the control chip CC performs the above-mentioned controls such as "active state", "inactive state", "on", and "off" based on a signal (hereinafter referred to as "excitation signal") transmitted from the control circuit SCC of the control chip CC via the electrode pad PD of the control chip CC, the signal transmission path STPl, STP2, and the electrode pad PD1, PD2 of the memory chips MC1, MC2. In addition, the input / output circuit IO1, IO2 of each memory chip MC1, MC2 is activated by charging each parasitic capacitor PCT1, PCT2 parasitic on each memory chip MC1, MC2, and is deactivated by discharging each parasitic capacitor PCT1, PCT2 parasitic on each memory chip MC1, MC2. Furthermore, in the present research example, although the timing of switching the value of the respective termination resistors TR1, TR2 is performed after switching the state of the respective input / output circuits IO1, IO2, the timing of switching the value of the respective termination resistors TR1, TR2 can be the same as the timing of switching the state of the respective input / output circuits IO1, IO2.

[0045] <Details of the problems found through research>

[0046] Next, details of the problems clarified through the research by the present inventor will be described.

[0047] First, as described above, the semiconductor device SDR1r researched by the present inventor is a configuration (branch case) in which two memory chips MC1, MC2 are controlled by one control chip CC. That is, in the semiconductor device SDR1r researched by the present inventor, two loads (input / output circuits of memory chips) are connected for one control chip CC. Therefore, the driving capability of the control chip CC is insufficient compared to the configuration in which one load is connected to one control chip CC.

[0048] Next, the inventors confirmed an eye pattern of a branching case (branching case 1) in which the total length of the signal transmission path (strictly speaking, the signal transmission path from the branching point N1 to each of the input / output circuits IO1, IO2) from the branching point N1 to each of the memory chips MC1, MC2 is, for example, 1.0 mm (= 0.5 mm x 2), and an eye pattern of a branching case (branching case 2) in which the total length of the signal transmission path is, for example, 12.0 mm (= 6.0 mm x 2), and an eye pattern of a reference case. As a result, as shown in Figures 2 to 4 FIG. 6, it was found that the eye pattern of each branching case in which the driving capability of the control chip was insufficient was more susceptible to interference than the eye pattern of the reference case, and when the length of the signal transmission path from the branching point N1 to each of the memory chips MC1, MC2 (i.e., the total length of the signal transmission path) was a certain length, the interference of the eye pattern became significant. Incidentally, the "eye pattern" is a waveform diagram that is graphically shown by superimposing transitions of a plurality of signal waveforms, as shown in Figures 2 to 4 Further, in a case where the eye pattern is interfered, it is difficult to accurately identify whether the signal voltage exceeds the desired voltage value (rise) or the signal voltage falls below the desired voltage value (fall).

[0049] Further, through the research of the inventors, it was found that the above-described eye pattern interference became more significant as the transmission speed (data rate) of the signal to be transmitted from the control chip CC to the corresponding memory chip MC1, MC2 became larger. The reason for this will be described later.

[0050] Next, the reason (mechanism) for the interference of the eye pattern will be described with reference to Figures 5 to 6 FIG. 7.

[0051] Figure 5 is a diagram illustrating charge exchange that occurs when the signal voltage rises under the above-described branching case 2. More specifically, for example, when one memory chip MC1 is accessed, first, an excitation signal (not shown) is supplied from the control chip CC to the corresponding memory chip MC1, MC2, the input / output circuit IO1 of the memory chip MC1 to be accessed (referred to as an "active element") is activated, and the input / output circuit IO2 of the memory chip MC2 that is not accessed (referred to as an "inactive element") is deactivated. Here, the parasitic capacitance PCT1 parasitic on the memory chip MC1 to be accessed is charged based on the excitation signal supplied from the control chip CC, thereby activating the input / output circuit IO1 of the memory chip MC1. On the other hand, the parasitic capacitance PCT2 parasitic on the memory chip MC2 that is not accessed is discharged based on the excitation signal, thereby deactivating the input / output circuit IO2 of the memory chip MC2.

[0052] However, when the above-described excitation signal is supplied to each of the memory chips MC1, MC2, the two memory chips MC1, MC2 resonate with each other, and as a result, the electric charge is exchanged between the two parasitic capacitances PCT1, PCT2 parasitic on the two memory chips MC1, MC2. As shown in FIG. 6, the electric charge ETR stored in the parasitic capacitance PCT1 parasitic on the memory chip MC1 as the active element moves to the parasitic capacitance PCT2 parasitic on the memory chip MC2 as the inactive element, and as a result, the parasitic capacitance of the active element is not immediately charged. Figure 5

[0053] Figure 6 is a diagram illustrating the exchange of electric charge occurring when the signal voltage drops under the above-described branch case 2. More specifically, for example, when one memory chip MC1 is accessed, first, an excitation signal (not shown) is supplied from the control chip CC to each of the memory chips MC1, MC2 to disable each of the input / output circuits IO1, IO2 of each of the memory chips MC1, MC2. Here, the parasitic capacitance PCT1 parasitic on the memory chip MC1 ("active device") to be accessed is discharged based on the excitation signal supplied from the control chip CC, thereby disabling the input / output circuit IO1 of the memory chip MC1. Similarly, the parasitic capacitance PCT2 parasitic on the memory chip MC2 ("inactive device") not to be accessed is discharged based on the above-described excitation signal, thereby disabling the input / output circuit IO2 of the memory chip MC2.

[0054] However, when the above-described excitation signal is supplied to each of the memory chips MC1, MC2, the two memory chips MC1, MC2 resonate with each other, and as a result, the electric charge is exchanged between the two parasitic capacitances PCT1, PCT2 parasitic on the two memory chips MC1, MC2. As shown in FIG. 6, the electric charge ETR stored in the parasitic capacitance PCT1 parasitic on the memory chip MC1 as the active element moves to the parasitic capacitance PCT2 parasitic on the memory chip MC2 as the inactive element, and as a result, the parasitic capacitance of the active element is not immediately charged. Figure 6

[0055] Note that the cycle of the above-described exchange of electric charge varies depending on the total length of the signal transmission path from the branch point N1 to the memory chips MC1, MC2.

[0056] ​​On the other hand, the excitation signal supplied (transmitted) to the active element from the control chip has a certain period. Here, the faster the transmission speed (data rate) of the signal, that is, the higher the frequency of the signal, the more frequencies it contains. For example, a signal with a data transmission rate of 8 Gbps contains many frequency spectra, such as 4 GHz, 2 GHz, 1 GHz, and nearby current frequency spectra. That is, increasing the data rate in the above branching case to perform high-speed access to the memory chip means that the probability that the period of the charge exchange and the period of the signal coincide with each other is higher.

[0057] Then, through the inventors' research, it has been clarified that the coincidence of the above two types of cycles with each other is the cause of the above eye diagram disturbance. Incidentally, through the inventors' further research, it has become clear that, as shown in Figures 3 to 4 the total length of the signal transmission path from the branching point N1 to the respective memory chips MC1, MC2 becomes longer, the period of the charge exchange approaches the period of the signal (i.e., becomes easier to match).

[0058] If the eye diagram is disturbed, the parasitic capacitances PCT1, PCT2 parasitic on each memory chip MC1, MC2 are prevented from being sufficiently charged and discharged, as a result, the signal can not be transmitted between the control chip CC and each memory chip MC1, MC2.

[0059] <Method of solving the problem (basic idea)>

[0060] Next, the method (basic idea) discovered by the inventors of the present invention and capable of suppressing the eye diagram disturbance will be described.

[0061] Figure 7 is a diagram (circuit diagram) illustrating the configuration of the semiconductor device SMD1ft discovered by the inventors of the present invention. As Figure 7 shown, like the semiconductor device SMD1r, the semiconductor device SMD1ft mainly includes two memory chips MC1, MC2, and a control chip CC that controls the two memory chips MC1, MC2. Unlike the semiconductor device SMD1r researched by the inventors, the semiconductor device SMD1ft discovered by the inventors further has a new capacitance CT between the control chip CC and the branching point N1 of the signal transmission path STP1. Specifically, as Figure 7 shown, the above new capacitance CT is coupled to (provided on) the signal transmission path STP3 that branches from the signal transmission path STP1 at the branching point N2 of the signal transmission path STP1, the branching point N2 being located between the control chip CC and the branching point N1 of the signal transmission path STP1.

[0062] The capacitance CT coupled to the signal transmission path STP3 is larger than each of the parasitic capacitance PCT0 parasitic to the control chip CC, the parasitic capacitance PCT1 parasitic to the first memory chip MC1, and the parasitic capacitance PCT2 parasitic to the second memory chip MC2. Specifically, the capacitance CT is larger than 1.0 times each of the parasitic capacitance PCT0 parasitic to the control chip CC, the parasitic capacitance PCT1 parasitic to the first memory chip MC1, and the parasitic capacitance PCT2 parasitic to the second memory chip MC2, and is smaller than or equal to 2.0 times each of the parasitic capacitance PCT0 parasitic to the control chip CC, the parasitic capacitance PCT1 parasitic to the first memory chip MC1, and the parasitic capacitance PCT2 parasitic to the second memory chip MC2. That is, the capacitance CT is a value satisfying the relational expression "0.8 pF < capacitance CT < 1.6 pF". The reason for this will be described later.

[0063] <Effects of the basic idea>

[0064] Next, the effects of the semiconductor device SMD1ft discovered by the inventors of the present application will be described with reference to Figures 8 to 9

[0065] Figure 8 is a diagram illustrating the charge exchange occurring when the signal voltage rises under the above branching case 2. More specifically, for example, when one memory chip MC1 is accessed, first, the control chip CC supplies an excitation signal (not shown) to the memory chips MC1, MC2, activates the input / output circuit IO1 of the memory chip MC1 to be accessed ("active element"), and deactivates the input / output circuit IO2 of the memory chip MC2 not to be accessed ("inactive element"). Here, the parasitic capacitance PCT1 parasitic to the memory chip MC1 to be accessed is charged based on the excitation signal supplied from the control chip CC, thereby activating the input / output circuit IO1 of the memory chip MC1. On the other hand, the parasitic capacitance PCT2 parasitic to the memory chip MC2 not to be accessed is discharged based on the above excitation signal, thereby deactivating the input / output circuit IO2 of the memory chip MC2.

[0066] Here, unlike the semiconductor device SMD1ft discovered by the inventors of the present application, the capacitance CT of the semiconductor device SMD1r studied by the inventors of the present application is not larger than the parasitic capacitances PCT1, PCT2. Therefore, when the above excitation signal is supplied to the memory chips MC1, MC2, charges are exchanged between the two parasitic capacitances PCT1, PCT2. In contrast, in the semiconductor device SMD1ft, it is found that in addition to the above two parasitic capacitances PCT1, PCT2, it has a capacitance CT larger than the two parasitic capacitances PCT1, PCT2. Therefore, as Figure 8 ​As shown, the electric charge ETR accumulated in the capacitor CT preferentially moves to the parasitic capacitor PCT2 parasitic on the memory chip MC2 that is the inactive element, compared to the parasitic capacitor PCT1 parasitic on the memory chip MC1 that is the active element. That is, the discharge timing of the parasitic capacitor parasitic on the active element changes. Therefore, the electric charge ETR stored in the parasitic capacitor of the active element becomes difficult to be extracted by the parasitic capacitor parasitic on the inactive element during the charging of the parasitic capacitor of the active element, and as a result, the parasitic capacitor of the active element is charged.

[0067] Figure 9 is a view showing the exchange of electric charges that occurs when the signal voltage drops under the above-described branch case 2. More specifically, for example, when one memory chip MC1 is accessed, first, an excitation signal (not shown) is supplied from the control chip CC to each memory chip MC1, MC2 to disable each input / output circuit IO1, IO2 of each memory chip MC1, MC2. Here, the parasitic capacitor PCT1 parasitic on the memory chip MC1 to be accessed is discharged based on the excitation signal supplied from the control chip CC, thereby disabling the input / output circuit IO1 of the memory chip MC1. Similarly, the parasitic capacitor PCT2 parasitic on the memory chip MC2 that is not accessed is discharged based on the above-described excitation signal, thereby disabling the input / output circuit IO2 of the memory chip MC2.

[0068] Here, in the semiconductor device SMD1r that the present inventors have studied, unlike the semiconductor device SMD1ft that the present inventors have found, the capacitor CT is not larger than each parasitic capacitor PCT1, PCT2, and therefore, when the above-described excitation signal is supplied to each memory chip MC1, MC2, the electric charges are exchanged between the two parasitic capacitors PCT1, PCT2. In contrast, in the semiconductor device SMD1ft, it is found that in addition to the above-described two parasitic capacitors PCT1, PCT2, it has a capacitor CT that is larger than the two parasitic capacitors PCT1, PCT2. Therefore, as shown in Figure 9 as shown, when the parasitic capacitor PCT1 parasitic on the memory chip MC1 that is the active element starts to discharge, the electric charge ETR stored in the parasitic capacitor PCT2 parasitic on the memory chip MC2 that is the inactive element preferentially moves to the capacitor CT that is larger than the parasitic capacitor PCT1 parasitic on the memory chip MC1. That is, the charging timing of the parasitic capacitor parasitic on the active element changes. This makes it difficult for the electric charge ETR stored in the parasitic capacitor of the inactive element to move to the parasitic capacitor parasitic on the active element when the parasitic capacitor of the active element discharges, and as a result, the parasitic capacitor of the active element is discharged.

[0069] When the newly provided capacitance CT is smaller than or equal to each of the parasitic capacitance PCT0 parasitic on the control chip CC, the parasitic capacitance PCT1 parasitic on the first memory chip MC1, and the parasitic capacitance PCT2 parasitic on the second memory chip MC2, the charge exchange between the capacitance CT and the parasitic capacitance parasitic on the inactive element is not preferentially performed compared to the charge exchange between the parasitic capacitance parasitic on the inactive element and the parasitic capacitance parasitic on the inactive element. Further, when the newly provided capacitance CT is larger than each of the parasitic capacitance PCT0 parasitic on the control chip CC, the parasitic capacitance PCT1 parasitic on the first memory chip MC1, and the parasitic capacitance PCT2 parasitic on the second memory chip MC2 (i.e., when the capacitance CT satisfies the relational expression "1.6 pF < capacitance CT"), there is a possibility that the capacitance CT cannot be sufficiently charged and discharged. Therefore, the wiring is a signal transmission path (here, the signal transmission path STP1) to which the capacitance CT (specifically, an electrode of the capacitance CT) is connected, and there is a possibility that current does not flow through the signal transmission path.

[0070] On the other hand, the semiconductor device SMD1ft discovered by the present inventors has a capacitance CT that is larger than 1.0 times each of the parasitic capacitance PCT0 parasitic on the control chip CC, the parasitic capacitance PCT1 parasitic on the first memory chip MC1, and the parasitic capacitance PCT2 parasitic on the second memory chip MC2, and is smaller than or equal to 2.0 times each of the parasitic capacitance PCT0 parasitic on the control chip CC, the parasitic capacitance PCT1 parasitic on the first memory chip MC1, and the parasitic capacitance PCT2 parasitic on the second memory chip MC2. Therefore, without interfering with the current, sufficient charging and discharging can be achieved for the parasitic capacitance of the active element.

[0071] (Embodiments)

[0072] Next, specific aspects related to the above-described basic idea will be described.

[0073] In the following embodiments, when necessary for convenience, the following embodiments are described by dividing them into a plurality of chapters or embodiments, but they are not independent of each other unless specifically described, and one chapter or embodiment refers to a modified example, details, supplementary description, etc. of part or all of the other chapters or embodiments. In the following embodiments, the number of elements, etc. (including the number of elements, numerical values, quantities, ranges, etc.) is not limited to a specific number, but can be not less than or equal to the specific number unless specifically indicated and fundamentally limited to the specific number. Furthermore, in the following embodiments, it goes without saying that constituent elements (including element steps, etc.) are not essential unless specifically indicated and fundamentally considered to be obviously necessary. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of an assembly, etc., it is assumed that the shape, etc. is substantially approximate or similar to the shape, etc. unless specifically indicated and fundamentally considered to be very clear. The same applies to the above-mentioned numerical values and ranges.

[0074] The following embodiments will be described in detail based on the drawings. In all the drawings for explaining the embodiments, members having the same function are denoted by the same reference numerals and hatching, and repetitive description thereof is omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless specifically necessary. In the drawings used in the embodiments, even in the case of a sectional view, the section line can be omitted to make the drawing easier to see. Furthermore, even in the case of a plan view, the section line can be used to make the figure easier to see.

[0075] (Embodiment 1)

[0076] <Configuration of semiconductor device SMD1 of Embodiment 1>

[0077] Figure 10 is a diagram (circuit diagram) illustrating a configuration of a semiconductor device SMD1 according to the present Embodiment 1. As Figure 10 indicated, similarly to the semiconductor device SMD1r according to the above-described basic idea, the semiconductor device SMD1 mainly includes two memory chips MC1, MC2, a control chip CC that controls the two memory chips MC1, MC2, and a capacitor CT.

[0078] In the present Embodiment 1, as Figure 10 indicated, the two memory chips MC1, MC2 are configured as one memory device MD. Then, as Figure 10 indicated, respective electrode pads PD1, PD2 electrically connected to respective input / output circuits IO1, IO2 of the respective memory chips MC1, MC2 are connected to external connection terminals ET that are commonly used with each other of the memory device MD via respective conductive members CDM1, CDM2 serving as a part of a signal transmission path. That is, as Figure 10As shown, branch point N1 is set in memory device MD.

[0079] Next, we will refer to Figures 10 to 12 Describe in detail the corresponding components that constitute the semiconductor device SMD1.

[0080] like Figures 11 to 12 As shown, the semiconductor device SMD1 includes a wiring substrate WB1, a memory device MD mounted on the wiring substrate WB1, a control chip CC mounted on the wiring substrate WB1, and a capacitor CT mounted on the wiring substrate WB1. Incidentally, the capacitor CT in this embodiment 1 is a capacitor element. Specifically, it is a chip capacitor (also called a "chip capacitor"). In this embodiment 1, the same reference numerals as those used for "capacitor CT" described in the above basic concept will be used to describe this capacitor element (i.e., it will be referred to as "capacitor element CT"). Figures 11 to 12 As shown, the capacitor element CT is positioned between the control chip CC and the memory device MD.

[0081] <Wire Wiring Substrate WB1>

[0082] Next, the configuration of the wiring substrate WB1 will be described. For example... Figures 11 to 12 As shown, the wiring substrate WB1 has multiple wirings WL1 and WL3 as signal transmission paths. Wiring WL1 includes a terminal TM1 electrically connected to the electrode pad PD of the control chip CC and a terminal TM2 electrically connected to the external connection terminal ET of the memory device MD. Incidentally, as... Figure 10 As shown, wiring WL1 is part of the signal transmission path STP1. Signal transmission between the control chip CC and memory chips MC1 and MC2 is performed through the signal transmission path STP1. On the other hand, as... Figure 10 and 12 As shown, routing WL3 is a branch of signal transmission path STP1 at branch point N2, where branch point N2 is located between the control chip CC and branch point N1 of signal transmission path STP1 (i.e., routing WL1). Then, as... Figures 11 to 12 As shown, wiring WL3 has terminals TM4 and TM5. One electrode ED1 of capacitor element CT is electrically connected to terminal TM4, and the other electrode ED2 of capacitor element CT is electrically connected to terminal TM5.

[0083] Furthermore, in this embodiment 1, the signal flowing through the wiring WL1, which serves as the signal transmission path STP1, is, for example, a data signal, but could also be another signal such as a command address signal. Additionally, as... Figure 11 As shown, the wiring substrate WB1 also includes wirings other than the aforementioned wirings WL1 and WL3, but their descriptions are omitted.

[0084] <Memory Device MD>

[0085] Next, the configuration of the memory device MD will be described. For example... Figures 11 to 12 As shown, the memory device MD includes an interposer IP, a memory chip IO1 mounted on the interposer IP and having an input / output circuit MC1, a memory chip IO2 mounted on the interposer IP and having an input / output circuit MC2, a conductive component CDM1 connected to an electrode pad PD1 of the memory chip MC1, a conductive component CDM2 connected to an electrode pad PD2 of the memory chip MC2, and an external connection terminal ET electrically connected to the input / output circuits IO1 and IO2.

[0086] Note that the interposer IP in this embodiment 1 is a glass epoxy resin-based substrate, which is the same as the wiring substrate WB1 described above. Furthermore, the memory chips MC1 and MC2 in this embodiment 1 are of the same type, for example, LPDDR5-SDRAM (JEDEC-compliant Low Power Double Data Rate 5 Synchronous Dynamic Random Access Memory). That is, in this embodiment 1, the aforementioned data signal is transmitted at a data rate of 5.0 Gbps or higher. Furthermore, the conductive components CDM1 and CDM2 in this embodiment 1 are, for example, bonding wires made of copper (Cu) or gold (Au). Figure 12 As shown, each memory chip MC1, MC2 and each conductive component CDM1, CDM2 are sealed with sealing material SR. The packaging structure of the memory device MD in this embodiment 1 is a so-called wire-bonded BGA (ball grid array) packaging structure.

[0087] like Figure 10 and 12 As shown, the input / output circuit IO1 of the memory chip MC1 is electrically connected to the control chip CC via the following: the electrode pad PD1 of the memory chip MC1, the conductive component CDM1, the external connection terminal ET of the memory device MD, and the wiring WL1 of the wiring substrate WB1. For example... Figure 10 and 12 As shown, the input / output circuit IO2 of memory chip MC2 is electrically connected to the control chip CC via the following: the electrode pad PD2 of memory chip MC2, the conductive component CDM2, the external connection terminal ET of memory device MD, and the wiring WL1 of wiring board WB1.

[0088] Incidentally, such as Figure 10 As shown, the conductive component CDM1 is part of the signal transmission path STP1, in which signals are transmitted between the control chip CC and a memory chip MC1. On the other hand, as... Figure 10As shown, the conductive component CDM2 is the signal transmission path STP2. Signal transmission between the control chip CC and another memory chip MC2 is performed through the signal transmission path STP2. Figure 12 As shown, conductive components CDM1 and CDM2 are connected to bonding leads BL formed on the upper surface of the interposer layer IP. That is, bonding leads BL correspond to... Figure 10 The branch point N1 is shown. Incidentally, as... Figure 12 As shown, the bonding lead BL is electrically connected to the external connection terminal ET via a via VAip formed in the interposer layer IP.

[0089] In this embodiment 1, the lengths of the two conductive components CDM1 and CDM2 are substantially the same. In other words, the distance from the external connection terminal ET of the memory device MD to the electrode pad PD1 of a memory chip MC1 is substantially the same as the distance from the external connection terminal ET of the memory device MD to the electrode pad PD2 of another memory chip MC2. That is, the interconnection topology of the memory device MD in this embodiment 1 is the aforementioned "T-branch topology".

[0090] In addition, such as Figure 10 As shown, in addition to the input / output circuit IO1 connected to the wiring WL1 and signal transmission path STP1 on the wiring substrate WB1, the memory chip MC1 also has a terminating resistor TR1 (i.e., "die-top termination") connected to the end of the signal transmission path STP1, which includes the conductive component CDM1 of the memory device MD. Similarly, as Figure 10 As shown, in addition to the input / output circuits IO2 connected to the signal transmission path STP2, the memory chip MC2 also has a terminating resistor TR2 (i.e., "die-top termination") connected to the end of the signal transmission path STP2, which includes the conductive component CDM2 of the memory device MD. Incidentally, the corresponding terminating resistors TR1 and TR2 are connected to a reference potential with a fixed potential of 0V (i.e., "R = ∞"). Therefore, the reflection of signals transmitted from the control circuit SCC of the control chip CC to the input / output circuits IO1 and IO2 of each memory chip MC1 and MC2 can be reduced, thus suppressing eye diagram interference.

[0091] As an example of using corresponding terminating resistors TR1 and TR2, as described above, when the first memory chip MC1 is accessed, the terminating resistor TR1 of the memory chip MC1 to be accessed is turned on, and the terminating resistor TR2 of the memory chip MC2 not being accessed is turned off.

[0092] <Control Chip CC>

[0093] Next, the configuration of the control chip CC will be described. For example...Figures 10 to 12 As shown, the control chip CC of this embodiment 1 has a control circuit SCC and an electrode pad PD electrically connected to the control circuit SCC. Incidentally, the control circuit SCC is formed on the main surface of a semiconductor substrate, for example, made of silicon. In addition, the electrode pad PD is composed of a portion of the uppermost wiring in a multilayer wiring layer formed on the main surface of the semiconductor substrate. Figure 10 The parasitic capacitance PCT0 shown is, for example, a capacitance parasitic on the electrode pad PD. In this embodiment 1, the two memory chips MC1 and MC2 are controlled by a control chip CC.

[0094] The configuration of memory chips MC1 and MC2 is basically the same as that of the control chip CC. That is, the input / output circuits IO1 and IO2 are formed on the main surface of a semiconductor substrate, for example, made of silicon. Furthermore, each electrode pad PD1 and PD2 is constituted by a portion of the uppermost wiring layer in a multilayer wiring layer formed on the main surface of the semiconductor substrate. In addition, Figure 10 Each parasitic capacitance PCT1, PCT2 shown is, for example, a capacitance parasitic on each electrode pad PD1, PD2.

[0095] <Capacitor Components CT>

[0096] Next, the configuration of the capacitor CT will be described. The capacitor element CT in this embodiment 1 is a "chip capacitor" as described above, specifically, as follows... Figures 11 to 12 As shown, it consists of two electrodes ED1 and ED2 connected by a dielectric (insulator). Then, as... Figures 10 to 12 As shown, one electrode ED1 of the capacitor CT is electrically connected to wiring WL1 of the wiring substrate WB1. More specifically, one electrode of the capacitor CT is connected to the path (here, “signal transmission path STP1”) in wiring WL1 of the wiring substrate WB1 located between terminal TM1 and terminal TM2 of wiring WL1.

[0097] In this embodiment 1, the capacitance of the capacitor device CT is greater than each of the following: the parasitic capacitance PCT0 on the control chip CC (see...). Figure 10 Parasitic capacitance PCT1 on the first memory chip MC1 (see...) Figure 10 ), and the parasitic capacitance PCT2 parasitic on the second memory chip MC2 (see Figure 10Specifically, each parasitic capacitance PCT0, PCT1, and PCT2 parasitized on each chip is, for example, 0.8 pF. On the other hand, the capacitance of the capacitor device CT is greater than 1.0 times and less than 2.0 times the corresponding parasitic capacitance PCT0, PCT1, and PCT2 parasitized on the corresponding chip. Specifically, the capacitance of the capacitor device CT in this embodiment 1 is, for example, 1.6 pF. The external dimensions of the capacitor element CT in the top view are, for example, "width × length = 0.2 mm × 0.4 mm".

[0098] <Effect of the semiconductor device SMD1 in Example 1>

[0099] Next, the effect of the semiconductor device SMD1 in this embodiment 1 will be described. First, the semiconductor device SMD1 in this embodiment 1 is a "branching case," where two memory chips MC1 and MC2 are controlled by a control chip CC. In the semiconductor device SMD1 constructed in the branching case, as described above, a capacitor CT larger than the parasitic capacitances PCT0, PCT1, and PCT2 is provided between the control chip CC and the branch point N1 of the signal transmission path STP1. As a result, a connection is achieved between the newly provided capacitor (capacitor element) CT and the parasitic capacitance on the unaccessed memory chip. Figures 8 to 9 The charge exchange is shown. Therefore, even if the signal transmission path becomes faster, eye diagram interference can be suppressed, and signals can be transmitted between the control chip CC and the memory chips MC1 and MC2.

[0100] <Modification Example of Example 1>

[0101] The following is a description of the modifications to Embodiment 1 described above.

[0102] (Example 1 of the modification of Example 1)

[0103] First, in Embodiment 1 above, as an example of using corresponding terminating resistors TR1 and TR2, when the first memory chip MC1 is accessed, the terminating resistor TR1 of the memory chip MC1 to be accessed is turned on, and the resistor TR2 of the memory chip MC1 not being accessed is turned off. However, in a semiconductor device employing a T-branch topology, when the total length of the signal transmission path (strictly speaking, the signal transmission path from branch point N1 to the corresponding input / output circuits IO1 and IO2) from branch point N1 to the corresponding memory chip MC1 or MCR2 is very long (e.g., when the total length is 13.0 mm or more), such as Figure 13As shown, corresponding terminating resistors TR1 and TR2 can be used. That is, the terminating resistor of the memory chip to be accessed is open, and the terminating resistor of the memory chip not being accessed is closed. As a result, the interference of the eye diagram can be further improved.

[0104] (Modified Example 2 of Example 1)

[0105] Furthermore, the routing topology of the memory device MD in this embodiment 1 is called the "T-branch topology," but the "flyover topology" described above can also be used. That is, the lengths of the two conductive components CDM1 and CDM2 can be different from each other. For example, when the distance from the external connection terminal ET of the memory device MD to the electrode pad PD2 of another memory chip MC2 (strictly speaking, the distance from the branch point N1 to the electrode pad PD2) is greater than the distance from the external connection terminal ET of the memory device MD to the electrode pad PD1 of a memory chip MC1 (strictly speaking, the distance from the branch point N1 to the electrode pad PD1), the interference of the eye diagram can be further improved by making the resistance value of the terminal resistor TR2 of the other memory chip MC2 (i.e., the resistance value of the one with the longer branch line) greater than the resistance value of the terminal resistor of one memory chip MC1 (i.e., the resistance value of the one with the shorter branch line).

[0106] (Example 2)

[0107] <Structure of the semiconductor device SMD2 in Example 2>

[0108] Next, we will refer to Figures 14 to 16 This describes the semiconductor device SMD2 according to Embodiment 2. The main difference from Embodiment 1 above is that the two memory chips MC1 and MC2 are configured as a single memory device MD. However, in Embodiment 2, the two memory chips MC1 and MC2 are configured as separate memory devices MD1 and MD2. Note that the following descriptions are omitted: contents that are the same as the above basic idea (configuration, components, etc.) and contents (configuration, components, etc.) described in Embodiment 1 above.

[0109] More specifically, such as Figure 14 As shown, one of the two memory chips MC1 and MC2 (here, memory chip MC1) is configured as memory device MD1. Furthermore, as... Figure 14 As shown, the other of the two memory chips MC1 and MC2 (here, memory chip MC2) is configured as memory device MD2. Figure 14 As shown, the external connection terminal ET1 of the electrode pad PD1 connected to the memory chip MC1 is different from the external connection terminal ET2 of the electrode pad PD2 connected to the memory chip MC2. That is, as Figures 14 to 16As shown, branch point N1 is located outside the corresponding memory devices MD1 and MD2. In other words, branch point N1 is on wiring WL1 of wiring substrate WB2, as shown... Figures 14 to 16 As shown.

[0110] Next, we will refer to Figures 14 to 16 Provide a detailed description of the corresponding components that constitute the semiconductor device SMD2.

[0111] like Figures 15 to 16 As shown, the semiconductor device SMD2 includes a wiring substrate WB2, a memory device MD1, a memory device MD2, a control chip CC, and a capacitor CT mounted on the wiring substrate WB2.

[0112] <Wire Wiring Board WB2>

[0113] Next, the configuration of the wiring substrate WB2 will be described. For example... Figures 15 to 16 As shown, the wiring substrate WB2 has multiple wirings WL1, WL2, and WL3 as signal transmission paths. Wiring WL1 includes a terminal TM1 electrically connected to the electrode pad PD of the control chip CC, an external connection terminal ET1 and an electrical connection terminal TM2 for the memory device MD1, and an external connection terminal ET2 and an electrical connection terminal TM3 for the memory device MD2. Incidentally, as... Figure 14 As shown, wiring WL1 is part of the signal transmission path STP1 that transmits signals between the control chip CC and the memory chip MC1. Furthermore, as... Figure 14 As shown, routing WL2 is a branch of signal transmission path STP1 (i.e., routing WL1) at branch point N1. Signal transmission between control chip CC and memory chip MC2 is performed via signal transmission path STP2. Furthermore, as... Figure 14 and Figure 16 As shown, wiring WL3 is a branch of signal transmission path STP1, located at branch point N2 of signal transmission path STP1 between the control chip CC and the branch point N1 of signal transmission path STP1 (i.e., wiring WL1). Then, as... Figures 15 to 16 As shown, wiring WL3 has terminals TM4 and TM5. Terminal TM4 is connected to one electrode ED1 of capacitor element CT, and terminal TM5 is connected to the other electrode ED2 of capacitor element CT.

[0114] <Each memory device MD1, MD2>

[0115] Next, the configuration of each memory device MD1, MD2 will be described. Since the two memory devices MD1, MD2 have the same configuration, a single memory device (here, memory device MD1) will be used to describe the configuration of each memory device MD1, MD2. For example... Figures 15 to 16 As shown, the memory device MD1 (MD2) includes an interposer IP1 (IP2), a memory chip MC1 (MC2) mounted on the interposer IP1 and having an input / output circuit IO1 (IO2), a conductive component CDM1 (CDM2) connected to the electrode pads PD1 (PD2) of the memory chip MC1, and an external connection terminal ET1 (ET2) electrically connected to the input / output circuit IO1.

[0116] Then, as Figure 14 and Figure 16 As shown in each figure, the I / O circuit IO1 of the memory chip MC1 is electrically connected to the control chip CC through the electrode pads PD1 of the memory chip MC1, the conductive component CDM1, the external connection terminal ET of the memory device MD1, and the wiring WL1 of the wiring substrate WB. Furthermore, as... Figure 14 and Figure 16 As shown in each figure, the input / output circuit IO2 of the memory chip MC2 includes the electrode pad PD2 of the memory chip MC2, the conductive component CDM2, the external connection terminal ET2 of the memory device MD2, a portion of the wiring WL1 of the wiring substrate WB, and is electrically connected to the control chip CC via the wiring WL2. The wiring WL2 branches off from the wiring WL1 at the branch point N1 located between the terminal TM1 of the wiring WL1 and the terminal TM2 of the wiring TM2.

[0117] In this embodiment 2, the lengths of the two conductive components CDM1 and CDM2 are different. In this embodiment 2, the distance from the external connection terminal ET2 of the memory device MD2 to the electrode pad PD2 of the memory chip MC2 (strictly speaking, the distance from the branch point N1 to the electrode pad PD2) is longer than the distance from the external connection terminal ET1 of the memory device MD1 to the electrode pad PD1 of the memory chip MC1 (strictly speaking, the distance from the branch point N1 to the electrode pad PD1). That is, the interconnection topology of the memory chips MC1 and MC2 in this embodiment 2 is the aforementioned "flyover topology".

[0118] In addition, as in Embodiment 1 above, as Figure 14As shown, each memory chip MC1, MC2 has terminating resistors TR1, TR2 connected to the ends of each signal transmission path STP1, STP2 (i.e., "die-top termination"), but the use of each terminating resistor TR1, TR2 differs from that in Embodiment 1. Specifically, as described above, Embodiment 2 employs a "flyover topology" as the interconnect topology for the memory chips MC1, MC2. Therefore, as Figure 17 As shown, the terminating resistor with the longer branch routing (here, "terminating resistor TR2") has a larger resistance value than the terminating resistor with the shorter branch routing (here, "terminating resistor TR1"). In other words, the terminating resistor TR1 for the memory chip MC1 with the short branch routing is open, while the terminating resistor TR2 for the memory chip MC2 with the longer branch routing is closed. This helps to improve eye diagram interference.

[0119] <Capacitor Components CT>

[0120] Next, the configuration of the capacitor CT will be described. Similar to Embodiment 1 above, the capacitor element CT in this Embodiment 2 is a "chip capacitor," specifically, as follows... Figures 15 to 16 As shown, it consists of two electrodes ED1 and ED2 connected by a dielectric (insulator). Then, as... Figures 14 to 16 As shown, one electrode ED1 of the capacitor element CT is electrically connected to the wiring WL1 of the wiring substrate WB. More specifically, one electrode ED1 of the capacitor element CT is coupled to the path (here, “signal transmission path STP1”) of the wiring WL1 of the wiring substrate WB located between terminals TN1, TM2 and TM3.

[0121] <Effect of the SMD2 semiconductor device in Example 2>

[0122] Next, the effect of the semiconductor device SMD2 in Embodiment 2 will be described. First, similar to Embodiment 1 above, the semiconductor device SMD2 in Embodiment 2 uses a control chip CC to control the "branching" of two memory chips MC1 and MC2. In the semiconductor device SMD2 constructed from branching, as with the basic idea described above, a capacitor CT larger than the parasitic capacitances PCT0, PCT1, and PCT2 is provided between the control chip CC and the branch point N1 of the signal transmission path. As a result, a connection is achieved between the newly provided capacitor (capacitor element) CT and the parasitic capacitance on the unaccessed memory chip. Figures 8 to 9 The charge exchange is shown. Therefore, even if the signal transmission path becomes faster, eye diagram interference can be suppressed, and signals can be transmitted between the control chip CC and the memory chips MC1 and MC2.

[0123] <Modified Example of Example 2>

[0124] Next, the modifications to Example 2 will be described.

[0125] (Modification Example 1 of Example 2)

[0126] First, the routing topology of the memory device MD in this embodiment 2 has been described as a "flyover topology," but the aforementioned "T-branch topology" can also be used. When using the T-branch topology as the interconnection topology of the memory device MD, it can also be used... Figure 13 The terminating resistors TR1 and TR2 shown are modifications of Example 1. As a result, interference in the eye diagram can be further improved.

[0127] The invention made by the inventors has been described in detail above based on the embodiments. However, the invention is not limited to the above embodiments, and needless to say, various modifications can be made without departing from its spirit. As specific examples, the modifications common to embodiments 1 and 2 above will be described below.

[0128] (Modified Example 1)

[0129] First, in embodiments 1 and 2 above, a new capacitor (capacitor element) CT is provided on the CC side of the control chip relative to the branch point N1 of the signal transmission path STP1 (line WL1). However, a new capacitor (capacitor element) CT can also be provided on the MC1 and MC2 sides of the memory chips relative to the branch point N1. However, as... Figure 12 and 16 As shown, when memory chips MC1 and MC2 are configured as a package (here, "BGA"), a capacitor element CT needs to be placed within the package during the package manufacturing process. Therefore, after package manufacturing, it is difficult to change the capacitor element within the package to a capacitor element with a different capacitance. Therefore, from the perspective of improving the combination flexibility of memory chips MC1 and MC2 and capacitor element CT, it is preferable not to mix capacitor element CT within the package containing the memory chips as in Embodiment 1 above.

[0130] In embodiments 1 and 2 above, capacitor CT can be used as a terminating resistor for control chip CC. In this case, the signal transmission path coupled to capacitor CT (signal transmission path STP3 in embodiments 1 and 2 above) also becomes part of the terminating resistor. Therefore, when capacitor CT is placed on the memory chip MC1 or MC2 side at branch point N1 of signal transmission path STP1, the signal transmission path from branch point N1 to capacitor CT must also be considered. Furthermore, the fact that capacitor CT is mixed in the package containing memory chips indicates that the load on control chip CC increases. Therefore, as described in embodiments 1 and 2 above, when using the newly placed capacitor CT as a terminating resistor for control chip CC, it is preferable to place it on the control chip CC side compared to branch point N1 of signal transmission path STP1 (wiring WL1).

[0131] (Modified Example 2)

[0132] Furthermore, in embodiments 1 and 2 above, the memory device MD was described as being composed of a wire-bonded BGA, a so-called flip-chip BGA that does not use bonding wires as conductive components, or a package that uses a lead frame as an interposer. Incidentally, if a configuration that does not use bonding wires as conductive components (e.g., a flip-chip BGA) is used, the distance from the external connection terminal ET of the memory device MD to the corresponding electrode pads PD1 and PD2 of the memory chips MC1 and MC2 is shorter compared to a wire-bonded BGA. That is, a flip-chip BGA can shorten the length of each branch wiring compared to a wire-bonded BGA. Therefore, eye diagram interference is more easily improved compared to a wire-bonded BGA.

[0133] (Modified Example 3)

[0134] In embodiments 1 and 2 described above, the control chip CC has been described as having a configuration in each memory chip MC1, MC2 that is not covered by the sealing member SR (so-called bare chip form). However, the control chip CC may also have a package structure in each memory chip MC1, MC2. On the other hand, in embodiments 1 and 2 described above, since the control chip CC is used as a bare chip, the control chip CC and the electrode pads PD of the control chip CC can be seen from the external connection terminal ET0 of the control device CD and the control device CD.

[0135] (Modified Example 4)

[0136] Furthermore, in embodiments 1 and 2 above, it was described that each of the control chip CC and memory chips MC1 and MC2 is a semiconductor device SMD1 and SMD2 mounted on a wiring substrate WBs. However, each of the chips CC and MC1 and MC2 (or each of the devices CD and MD) can be configured as an electronic device directly mounted on a motherboard (not shown) without using the aforementioned interconnect substrate WBs.

[0137] (Modified Example 5)

[0138] In embodiments 1 and 2 above, the use of a chip capacitor as a capacitive CT has been described. However, for example, as... Figure 18 As shown, pattern PTA1 consists of a portion of wiring WL1, a wiring layer in which wiring WL1 is formed, and another wiring layer (here, a single wiring layer) adjacent via an insulating layer (not shown). The capacitor CTm can be constructed using pattern PTA3, which is a portion of the formed wiring WL3. However, according to the inventors' research, to obtain a 0.8pF capacitor, the external dimensions of each of the above-described patterns PTA1 and PTA3 must be set to approximately 590 μm Ф, and to obtain a 1.45pF capacitor, the external dimensions of each of the above-described patterns PTA1 and PTA3 need to be set to approximately 870 μm Ф. Therefore, from the viewpoint of reducing the capacitor mounting area, it is preferable to use chip capacitors such as those described in Examples 1 and 2 above.

[0139] (Modified Example 6)

[0140] Furthermore, within the scope consistent with the main idea described in each of the above modification examples, some or all of the above modification examples may be combined with each other.

Claims

1. A semiconductor device, comprising: First memory chip; Second memory chip; A control chip that controls each of the first and second memory chips; as well as The first signal transmission path is used for signal transmission between the control chip and each of the first and second memory chips. The signal transmission between the control chip and the first memory chip is performed via the first signal transmission path. The signal transmission between the control chip and the second memory chip is performed via a portion of the first signal transmission path and a second signal transmission path branching off from the first signal transmission path at a first branch point located between the control chip and the first memory chip. A capacitance greater than each of the parasitic capacitances located on the control chip, the first parasitic capacitance on the first memory chip, and the second parasitic capacitance on the second memory chip is coupled to a third signal transmission path. This third signal transmission path branches off from the first signal transmission path at a second branch point located between the control chip and the first branch point of the first signal transmission path. The capacitance coupled to the third signal transmission path is greater than 1.0 times the first parasitic capacitance and less than or equal to 2.0 times the first parasitic capacitance.

2. The semiconductor device according to claim 1, The connection between the control chip and each of the first and second memory chips is a T-branch topology. The first memory chip includes a first terminating resistor, which is coupled to each of the first input / output circuits coupled to the first signal transmission path and to each end of the first signal transmission path. The second memory chip includes a second terminating resistor, which is coupled to each of the second input / output circuits coupled to the second signal transmission path and to each end of the second signal transmission path. In the case of accessing the first memory chip, the control chip: Activate the first input / output circuit of the first memory chip; Disable the second input / output circuit of the second memory chip; Increase the resistance value of the first terminating resistor; and Reduce the resistance value of the second terminating resistor, and In the case of accessing the second memory chip, the control chip: The first input / output circuit of the first memory chip is disabled; Activate the second input / output circuit of the second memory chip; Reduce the resistance value of the first terminating resistor; and Increase the resistance value of the second terminating resistor.

3. The semiconductor device according to claim 2, The data rate of each of the first and second memory chips is greater than or equal to 5.0 Gbps.

4. The semiconductor device according to claim 2, Each of the first and second memory chips is an LPDDR5-SDRAM (Low Power Double Data Rate 5 Synchronous Dynamic Random Access Memory).

5. The semiconductor device according to claim 1, The connection between the control chip and each of the first and second memory chips is a fly-through topology. The first memory chip includes a first input / output circuit and a first terminating resistor. The second memory chip includes a second input / output circuit and a second terminating resistor. The distance from the first branch point to the second input / output circuit is longer than the distance from the first branch point to the first input / output circuit. The resistance value of the second terminating resistor is greater than the resistance value of the first terminating resistor.

6. The semiconductor device according to claim 5, The data rate of each of the first and second memory chips is greater than or equal to 5.0 Gbps.

7. The semiconductor device according to claim 5, Each of the first and second memory chips is an LPDDR5-SDRAM (Low Power Double Data Rate 5 Synchronous Dynamic Random Access Memory).

8. A semiconductor device, comprising: A wiring substrate includes a first wiring, which is a signal transmission path; A memory device, mounted on the wiring substrate and comprising: Intermediate layer; A first memory chip is mounted on the interposer layer and has a first input / output circuit. A second memory chip is mounted on the interposer layer and has a second input / output circuit. A first conductive material is electrically connected to the first electrode pad of the first memory chip; A second conductive material is electrically connected to the second electrode pads of the second memory chip; and External connection terminals are electrically connected to each of the first input / output circuits of the first memory chip and the second input / output circuits of the second memory chip. A control chip, mounted on the wiring substrate, controls each of the first and second memory chips; and A capacitor element, mounted on the wiring substrate, includes a first electrode that is electrically connected to a first wiring on the wiring substrate. The first wiring has: The first terminal is electrically connected to the external connection terminal of the control chip; and The second terminal is electrically connected to the external connection terminal of the memory device. The first input / output circuit of the first memory chip is electrically connected to the control chip via the following: the first electrode pad of the first memory chip, the first conductive material, the external connection terminal of the memory device, and the first wiring of the wiring substrate. The second input / output circuit of the second memory chip is electrically connected to the control chip via the following: the second electrode pad of the second memory chip, the second conductive material, the external connection terminal of the memory device, and the first wiring of the wiring substrate. The first electrode of the capacitor element is coupled to the path of the first wiring located between the first terminal and the second terminal, and The capacitance of the capacitor element is greater than each of the following: the parasitic capacitance on the control chip, the first parasitic capacitance on the first memory chip, and the second parasitic capacitance on the second memory chip. The capacitance of the capacitor element is greater than 1.0 times the first parasitic capacitance and less than or equal to 2.0 times the first parasitic capacitance.

9. The semiconductor device according to claim 8, The wiring substrate includes a second wiring, which is a transmission path for a reference potential. The capacitor element is a chip capacitor, which includes a first electrode and a second electrode. The first electrode of the chip capacitor is electrically connected to the first wiring of the wiring substrate, and The second electrode of the chip capacitor is electrically connected to the second wiring of the wiring substrate.

10. The semiconductor device according to claim 9, The distance from the external connection terminal of the memory device to the first electrode pad of the first memory chip and the distance from the external connection terminal of the memory device to the second electrode pad of the second memory chip are the same as each other. The first memory chip includes: A first input / output circuit is coupled to a first signal transmission path, the first signal transmission path including the first wiring of the wiring substrate and the first conductive material of the memory device; as well as The first terminal resistor is coupled to the end of the first signal transmission path. The second memory chip includes: A second input / output circuit is coupled to a second signal transmission path, the second signal transmission path including the second conductive material of the memory device; and The second terminal resistor is coupled to the end of the second signal transmission path. In the case of accessing the first memory chip, the control chip: Activate the first input / output circuit of the first memory chip; Disable the second input / output circuit of the second memory chip; Increase the resistance value of the first terminating resistor; and Reduce the resistance value of the second terminating resistor, and In the case of accessing the second memory chip, the control chip: The first input / output circuit of the first memory chip is disabled; Activate the second input / output circuit of the second memory chip; Reduce the resistance value of the first terminating resistor; and Increase the resistance value of the second terminating resistor.

11. The semiconductor device according to claim 10, The data rate of each of the first and second memory chips is greater than or equal to 5.0 Gbps.

12. The semiconductor device according to claim 10, Each of the first and second memory chips is an LPDDR5-SDRAM (Low Power Double Data Rate 5 Synchronous Dynamic Random Access Memory).

13. The semiconductor device according to claim 9, The distance from the external connection terminal of the memory device to the second electrode pad of the second memory chip is longer than the distance from the external connection terminal of the memory device to the first electrode pad of the first memory chip. The first memory chip includes: A first input / output circuit is coupled to a first signal transmission path, the first signal transmission path including the first wiring of the wiring substrate and the first conductive material of the memory device; as well as The first terminal resistor is coupled to the end of the first signal transmission path. The second memory chip includes: A second input / output circuit is coupled to a second signal transmission path, the second signal transmission path including the second conductive material of the memory device; as well as The second terminating resistor is coupled to the end of the second signal transmission path, and The resistance value of the second terminating resistor is greater than the resistance value of the first terminating resistor.

14. The semiconductor device according to claim 13, The data rate of each of the first and second memory chips is greater than or equal to 5.0 Gbps.

15. The semiconductor device according to claim 13, Each of the first and second memory chips is an LPDDR5-SDRAM (Low Power Double Data Rate 5 Synchronous Dynamic Random Access Memory).

16. A semiconductor device, comprising: A wiring substrate includes a first wiring, which is a signal transmission path; A first memory device, mounted on the wiring substrate, includes: First intermediary layer; A first memory chip is mounted on the first interposer layer and has a first input / output circuit. A first conductive material is electrically connected to the first electrode pad of the first memory chip; and The first external connection terminal is electrically connected to the first input / output circuit of the first memory chip. A second memory device, mounted on the wiring substrate and comprising: Second intermediary layer; A second memory chip is mounted on the second interposer layer and has a second input / output circuit. A second conductive material is electrically connected to the second electrode pads of the second memory chip; and The second external connection terminal is electrically connected to the second input / output circuit of the second memory chip. A control chip, mounted on the wiring substrate, controls each of the first and second memory chips; and A capacitor element, mounted on the wiring substrate, includes a first electrode that is electrically connected to a first wiring on the wiring substrate. The first wiring has: The first terminal is electrically connected to the external connection terminal of the control chip; The second terminal is electrically connected to the first external connection terminal of the first memory device; and The third terminal is electrically connected to the second external connection terminal of the second memory device. The first input / output circuit of the first memory chip is electrically connected to the control chip via the following: the first electrode pad of the first memory chip, the first conductive material, the first external connection terminal of the first memory device, and the first wiring of the wiring substrate. The second input / output circuit of the second memory chip is electrically connected to the control chip via: the second electrode pad of the second memory chip, the second conductive material, the second external connection terminal of the second memory device, a portion of the first wiring on the wiring substrate, and a second wiring branching from the first wiring at a first branch point located between the first terminal and the second terminal. The first electrode of the capacitor element is coupled to the path of the first wiring located between the first terminal, the second terminal, and the third terminal. The capacitance of the capacitor element is greater than each of the following: the parasitic capacitance on the control chip, the first parasitic capacitance on the first memory chip, and the second parasitic capacitance on the second memory chip. The capacitance of the capacitor element is greater than 1.0 times the first parasitic capacitance and less than or equal to 2.0 times the first parasitic capacitance.

17. The semiconductor device according to claim 16, The wiring substrate includes a second wiring, which is a transmission path for a reference potential. The capacitor element is a chip capacitor, which includes a first electrode and a second electrode. The first electrode of the chip capacitor is electrically connected to the first wiring of the wiring substrate, and The second electrode of the chip capacitor is electrically connected to the second wiring of the wiring substrate.

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