Semiconductor device and method

Abstract

The present disclosure relates to semiconductor devices and methods. In one embodiment, a structure includes: a nanostructure; an epitaxial source / drain region adjacent to the nanostructure; a gate dielectric surrounding the nanostructure; a gate electrode located on the gate dielectric, the gate electrode having an upper portion and a lower portion, the upper portion having a first width that continuously increases in a first direction extending away from a top surface of the nanostructure, and the lower portion having a second width that is constant along the first direction; and a gate spacer located between the gate dielectric and the epitaxial source / drain region.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices and methods. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed. Summary of the invention

[0004] According to one embodiment of the present disclosure, a method for forming a semiconductor structure is provided, comprising: forming a dummy dielectric over a plurality of semiconductor layers; forming a dummy gate over the dummy dielectric; depositing a gate spacer adjacent to the dummy gate and the dummy dielectric; recessing the dummy gate to form a groove exposing the gate spacer; injecting impurities into a first region of the gate spacer to increase an etching rate of the first region of the gate spacer, with a second region of the gate spacer remaining unmodified by the injection; removing the dummy dielectric, the first region of the gate spacer, and a remaining portion of the dummy gate to expose a semiconductor layer in the groove; patterning the semiconductor layer to form a nanostructure; and forming a gate structure in the groove, the gate structure surrounding the nanostructure, the gate structure contacting the second region of the gate spacer.

[0005] According to another embodiment of the present disclosure, a semiconductor structure is provided, comprising: a nanostructure; an epitaxial source / drain region adjacent to the nanostructure; a gate dielectric surrounding the nanostructure; a gate electrode located above the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion continuously increasing in a first direction extending away from a top surface of the nanostructure, and a second width of the lower portion being constant along the first direction; and a gate spacer located between the gate dielectric and the epitaxial source / drain region.

[0006] According to another embodiment of the present disclosure, a semiconductor structure is provided, including: a nanostructure; a gate structure surrounding the nanostructure; and a first pair of gate spacers adjacent to the gate structure, wherein the first pair of gate spacers are separated by a first distance at a lower portion of the gate structure, and the first pair of gate spacers are separated by a second distance at an upper portion of the gate structure, and the second distance is greater than the first distance. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 An example of a nanostructured field effect transistor (nano-FET) in a three-dimensional view is shown in accordance with some embodiments.

[0009] Figures 2 to 17B are various views of other intermediate stages of fabrication of a nanoFET according to some embodiments.

[0010] Fig.18 A nanoFET is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0013] According to some embodiments, a funnel-shaped gate electrode is formed in a gate replacement process for a nanoFET. During the gate replacement process, a groove of a replacement gate may be widened to have a funnel shape. The groove may be widened by implanting impurities in an upper region of a gate spacer of the nanoFET and then removing the upper region of the gate spacer by etching selective to the impurities. Widening the groove to have a funnel shape may help avoid formation of a seam (or gap) when filling the replacement gate.

[0014] Figure 1 An example of a simplified nanoFET in a three-dimensional view according to some embodiments is shown. For illustration clarity, some features of the nanoFET are omitted (discussed below). The nanoFET can be a nanosheet field effect transistor (NSFET), a nanowire field effect transistor (NWFET), a gate-all-around field effect transistor (GAAFET), etc.

[0015] The nanoFET includes a nanostructure 55 located above a fin 66 extending from a substrate 50, wherein the nanostructure 55 serves as a channel region of the nanoFET. A shallow trench isolation (STI) region 68 is disposed above the substrate 50 and between adjacent fins 66, and the fins 66 may protrude from between adjacent STI regions 68 to be higher than these STI regions. Although the STI regions 68 are described / illustrated as being separated from the substrate 50, as used herein, the term "substrate" may refer to a separate semiconductor substrate, or a combination of a semiconductor substrate and an isolation region. In addition, although the bottom portion of the fin 66 is shown as a single material continuous with the substrate 50, the bottom portion of the fin 66 and / or the substrate 50 may include a single material or multiple materials. In this context, the fin 66 refers to the portion extending between adjacent STI regions 68.

[0016] The gate structure 85 surrounds the nanostructure 55 (e.g., the channel region of a nanoFET). The gate structure 85 includes a gate dielectric 112 and a gate electrode 114. The gate dielectric 112 is along the top surface, sidewalls, and bottom surface of the nanostructure 55, and may extend along the sidewalls of the fin 66 and above the top surface of the fin 66. The gate electrode 114 is above the gate dielectric 112. The epitaxial source / drain region 92 is disposed on the opposite side of the nanostructure 55 relative to the gate structure 85. In embodiments in which multiple transistors are formed, the epitaxial source / drain region 92 may be shared between the respective transistors. In embodiments in which a transistor is formed from multiple nanostructures 55, adjacent epitaxial source / drain regions 92 may be electrically coupled, for example, by merging the epitaxial source / drain regions 92 via epitaxial growth, or by coupling the epitaxial source / drain regions 92 to the same source / drain contact. One or more interlayer dielectric (ILD) layers (discussed below) are located over the epitaxial source / drain regions 92 and / or the gate electrode 114, through which contacts (discussed below) are formed to the epitaxial source / drain regions 92 and the gate electrode 114.

[0017] Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments contemplate aspects used in planar devices such as planar FETs, or fin field effect transistors (FinFETs).

[0018] Figure 1 Reference cross sections used in subsequent figures are further illustrated. Cross section AA is along the longitudinal axis of gate electrode 114 and in a direction perpendicular to the direction of current flow, e.g., between epitaxial source / drain regions 92 of the nanoFET. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of fin 66 and in the direction of current flow, e.g., between epitaxial source / drain regions 92 of the nanoFET. Cross section CC is parallel to cross section AA and extends through epitaxial source / drain regions 92 of the nanoFET. For clarity, subsequent figures refer to these reference cross sections.

[0019] Figures 2 to 6 is a three-dimensional view of an intermediate stage in fabricating a nanoFET according to some embodiments. Figures 2 to 6 Shown with Figure 1 Similar 3D view.

[0020] exist Figure 2In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, for example, a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (for example, with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, for example, a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, which is typically a silicon or glass substrate. Other substrates may also be used, for example, a multilayer or gradient substrate. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide; or combinations thereof.

[0021] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device such as an NMOS transistor, for example, an n-type nano FET, and the p-type region 50P can be used to form a p-type device such as a PMOS transistor, for example, a p-type nano FET. The n-type region 50N and the p-type region 50P can be physically separated (not shown separately), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be set between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0022] The substrate 50 may be lightly doped with p-type or n-type impurities. An anti-punch-through (APT) implant may be performed on the upper portion of the substrate 50 to form an APT region. During the APT implant, dopants may be implanted into the n-type region 50N and the p-type region 50P. The dopants may have a conductivity type opposite to the conductivity type of the source / drain region to be formed in each of the n-type region 50N and the p-type region 50P. The APT region may extend below the source / drain region to be subsequently formed in the nanoFET, and the source / drain region will be formed in a subsequent process. The APT region may be used to reduce leakage from the source / drain region to the substrate 50. In some embodiments, the doping concentration in the APT region may be about 10 18 cm -3 to about 10 19 cm -3 within the range.

[0023] A multilayer stack 64 is formed over the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 52 and second semiconductor layers 54. As discussed further below, in the p-type region 50P, the second semiconductor layer 54 will be removed and the first semiconductor layer 52 will be patterned to form a channel region of a nanoFET, and in the n-type region 50N, the first semiconductor layer 52 will be removed and the second semiconductor layer 54 will be patterned to form a channel region of a nanoFET. In another embodiment, the first semiconductor layer 52 may be removed and the second semiconductor layer 54 may be patterned to form a channel region of a nanoFET in the p-type region 50P, and the second semiconductor layer 54 may be removed and the first semiconductor layer 52 may be patterned to form a channel region of a nanoFET in the n-type region 50N.

[0024] For illustrative purposes, the multilayer stack 64 is shown as including three layers each of the first semiconductor layer 52 and the second semiconductor layer 54. It should be understood that the multilayer stack 64 may include any number of the first semiconductor layer 52 and the second semiconductor layer 54. Each layer of the multilayer stack 64 may be epitaxially grown using a process such as vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc., and may be epitaxially grown to a thickness in a range of about 8 nm to about 10 nm. In various embodiments, the first semiconductor layer 52 may be formed of a first semiconductor material suitable for a p-type nanoFET, such as silicon germanium (e.g., Si x Ge 1-x , where x can be in the range of 0 to 1), pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc., and second semiconductor layer 54 can be formed of a second semiconductor material suitable for n-type nanoFETs, for example, silicon, silicon carbide, III-V compound semiconductors, II-VI compound semiconductors, etc. For illustrative purposes, multilayer stack 64 is shown as having a bottommost semiconductor layer suitable for p-type nanoFETs. In some embodiments, multilayer stack 64 can be formed such that the bottommost layer is a semiconductor layer suitable for n-type nanoFETs.

[0025] The first semiconductor material and the second semiconductor material may be materials having high etching selectivity with respect to the same etching process. Thus, in the n-type region 50N, the first semiconductor layer 52 of the first semiconductor material may be removed without removing the second semiconductor layer 54 of the second semiconductor material, and in the p-type region 50P, the second semiconductor layer 54 of the second semiconductor material may be removed without removing the first semiconductor layer 52 of the first semiconductor material.

[0026] exist Figure 3In the embodiment, fins 66 are formed in the multilayer stack 64 and the substrate 50. The fins 66 are semiconductor strips. In some embodiments, the fins 66 can be formed in the multilayer stack 64 and the substrate 50 by etching trenches in the multilayer stack 64 and the substrate 50. The etching can be any acceptable etching process, for example, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching can be anisotropic.

[0027] The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Typically, double patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing for the creation of patterns having, for example, a smaller pitch than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.

[0028] The width of the fin 66 may be in the range of about 8 nm to about 40 nm. For illustrative purposes, the fins 66 in the n-type region 50N and the p-type region 50P are shown as having substantially equal widths. In some embodiments, the fins 66 in one region (e.g., the n-type region 50N) may be wider or narrower than the fins 66 in another region (e.g., the p-type region 50P).

[0029] exist Figure 4 In the embodiment shown, an STI region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material over the substrate 50 and the fin 66 and between adjacent fins 66. The insulating material can be an oxide such as silicon oxide, a nitride such as silicon nitride, or the like, or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In an embodiment, the insulating material is formed so that an excess of insulating material covers the fin 66. Although the insulating material is shown as a single layer, some embodiments may employ multiple layers. For example, in some embodiments, a liner can first be formed along the surface of the substrate 50 and the fin 66. Thereafter, a filling material such as discussed above can be formed over the liner.

[0030] Then, a removal process is applied to the insulating material to remove excess insulating material over the fins 66. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. may be employed. The planarization process exposes the fins 66 so that the top surfaces of the fins 66 and the insulating material are coplanar after the planarization process is completed.

[0031] The insulating material is then recessed to form STI regions 68. The insulating material is recessed so that the upper portions of the fins 66 in the n-type region 50N and the p-type region 50P protrude from between adjacent STI regions 68. In the illustrated embodiment, the top surface of the STI region 68 is coplanar with the top surface of the substrate 50. In some embodiments, the top surface of the STI region 68 is above or below the top surface of the substrate 50. In addition, the top surface of the STI region 68 can have a flat surface (as shown), a convex surface, a concave surface (e.g., a dish), or a combination thereof. The top surface of the STI region 68 can be formed to be flat, convex, and / or concave by appropriate etching. The STI region 68 can be recessed using an acceptable etching process, for example, an etching process that is selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the fin 66). For example, oxide removal using, for example, dilute hydrofluoric acid (dHF) acid can be used.

[0032] The above process is only one example of how to form fin 66. In some embodiments, fin 66 can be formed by an epitaxial growth process. For example, a dielectric layer can be formed above the top surface of substrate 50, and a groove can be etched through the dielectric layer to expose the substrate 50 below. An epitaxial structure can be epitaxially grown in the trench, and the dielectric layer can be recessed so that the epitaxial structure protrudes from the dielectric layer to form fin 66. The epitaxial structure may include alternating semiconductor materials as described above, for example, a first semiconductor material and a second semiconductor material. In embodiments in which the epitaxial structure is epitaxially grown, the epitaxially grown material can be doped in situ during growth, which can eliminate previous and / or subsequent implants, but in situ doping and implant doping can be used together.

[0033] In addition, appropriate wells may be formed in the fin 66 and / or the substrate 50. In some embodiments, a p-type well may be formed in the n-type region 50N, and an n-type well may be formed in the p-type region 50P. In another embodiment, a p-type well or an n-type well may be formed in both the n-type region 50N and the p-type region 50P.

[0034] In embodiments with different well types, photoresists or other masks may be used to implement different implantation steps for the n-type region 50N and the p-type region 50P. For example, a photoresist may be formed over the fins 66 and STI regions 68 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P of the substrate 50. The photoresist may be formed using a spin coating technique and may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in the p-type region 50P, and the photoresist may be used as a mask to substantially prevent the n-type impurity from being implanted into the n-type region 50N. The n-type impurity may be phosphorus, arsenic, antimony, etc., implanted into the region at a concentration of about 10 13 cm -3 to about 10 14 cm -3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0035] After the implantation of the p-type region 50P, a photoresist is formed over the fin 66 and the STI region 68 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N of the substrate 50. The photoresist may be formed using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation may be performed in the n-type region 50N and the photoresist may be used as a mask to substantially prevent the p-type impurity from being implanted into the p-type region 50P. The p-type impurity may be boron, boron fluoride, indium, etc., implanted into the region at a concentration of about 10 13 cm -3 to about 10 14 cm -3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0036] After implantation of n-type region 50N and p-type region 50P, annealing may be performed to repair implant damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fin may be in-situ doped during growth, which may eliminate implantation, but in-situ doping and implantation doping may be used together.

[0037] exist Figure 5In the embodiment of the present invention, a dummy dielectric layer 70 is formed on the fin 66. The dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and may be deposited or thermally grown according to an acceptable technique. A dummy gate layer 72 is formed on the dummy dielectric layer 70, and a mask layer 74 is formed on the dummy gate layer 72. The dummy gate layer 72 may be deposited on the dummy dielectric layer 70, and then planarized, for example, by CMP. The mask layer 74 may be deposited on the dummy gate layer 72. The dummy gate layer 72 may be a conductive material or a non-conductive material, and may be selected from the group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. The dummy gate layer 72 may be made of other materials with high etch selectivity relative to the etching of the isolation region (e.g., STI region 68 and / or dummy dielectric layer 70). The mask layer 74 may include one or more layers such as silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. Although the dummy dielectric layer 70 is shown as covering the STI region 68, it should be understood that the dummy dielectric layer 70 may be formed in other ways. In some embodiments, for example, when the dummy dielectric layer 70 is thermally grown, the dummy dielectric layer 70 is formed to cover only the fin 66.

[0038] exist Figure 6 , the mask layer 74 is patterned using acceptable photolithography and etching techniques to form a mask 78. Then, the pattern of the mask 78 is transferred to the dummy gate layer 72 by an acceptable etching technique to form a dummy gate 76. The pattern of the mask 78 can optionally be further transferred to the dummy dielectric layer 70 by an acceptable etching technique to form a dummy dielectric 60. The dummy gate 76 covers the portion of the fin 66 that will be patterned in a subsequent process to form a nanostructure, which will be used as a channel region of the nano FET. The pattern of the mask 78 can be used to physically separate adjacent dummy gates 76. The dummy gate 76 can also have a length direction that is substantially perpendicular (within process variations) to the length direction of the fin 66. The mask 78 can optionally be removed after patterning, for example by an acceptable etching technique.

[0039] 7A to 17B is a cross-sectional view of other intermediate stages in the fabrication of a nanoFET according to some embodiments. Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.16A and Fig.17A along Figure 1 , and shows features 50P in both the n-type region 50N and the p-type region. Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 16B and Fig. 17B Along Figure 1 , and illustrates features in both the n-type region 50N and the p-type region 50P. Fig. 11C and Fig.11D Along Figure 1 , and illustrates features of both the n-type region 50N and the p-type region 50P.

[0040] exist Fig. 7A and Figure 7B , a first spacer layer 80 and a second spacer layer 82 are formed. The first spacer layer 80 is formed on the top surface of the STI region 68, the top surface and sidewalls of the fin 66 and the mask 78 (if present), and the sidewalls of the dummy gate 76 and the dummy dielectric 60. The second spacer layer 82 is deposited on the first spacer layer 80. The first spacer layer 80 can be formed of silicon oxide, silicon nitride, silicon oxynitride, carbon silicon oxynitride, etc. The first spacer layer 80 can be formed by thermal oxidation, or can be deposited by CVD, ALD, etc. The second spacer layer 82 can be formed of silicon oxide, silicon nitride, silicon oxynitride, carbon silicon oxynitride, etc. The second spacer layer 82 can be deposited by CVD, ALD, etc.

[0041] In some embodiments, the first spacer layer 80 and the second spacer layer 82 are each made of silicon oxycarbon nitride (eg, SiO x N y C 1-x-y, where x and y are in the range of 0 to 1) and have different compositions of silicon oxycarbon nitride. Specifically, the first spacer layer 80 can be composed of more nitrogen (atomic percentage) than the second spacer layer 82, and the second spacer layer 82 can be composed of more oxygen (atomic percentage) than the first spacer layer 80. For the etching process (discussed further below) to be used to remove the dummy dielectric 60, forming the first spacer layer 80 of nitrogen-rich silicon oxycarbon nitride increases its etching selectivity relative to the dummy dielectric 60. Forming the second spacer layer 82 of oxygen-rich silicon oxycarbon nitride reduces the relative dielectric constant of the second spacer layer 82, thereby enabling the subsequently formed spacer to have greater electrical insulation.

[0042] In embodiments where the first spacer layer 80 and the second spacer layer 82 are each formed of silicon oxycarbonitride, the silicon oxycarbonitride layer may be deposited using a dielectric material precursor, including a silicon source precursor (e.g., hexachlorodisilane (Si2Cl6, HCD)), an oxygen source precursor (e.g., oxygen (O2)), a carbon source precursor (e.g., propylene (C3H6)), and a nitrogen source precursor (e.g., ammonia (NH3)). In embodiments where deposition is performed by CVD, the component(s) of the silicon oxycarbonitride layer may be controlled by controlling the flow rate of the source precursors during CVD. For example, the silicon source precursor may be dispensed at a rate in the range of about 100 sccm to about 1000 sccm, the oxygen source precursor may be dispensed at a rate in the range of about 1000 sccm to about 20,000 sccm, the carbon source precursor may be dispensed at a rate in the range of about 1000 sccm to about 10,000 sccm, and the nitrogen source precursor may be dispensed at a rate in the range of about 5,000 sccm to about 30,000 sccm.

[0043] Implantation for lightly doped source / drain (LDD) regions may be performed after forming the first spacer layer 80, or after forming both the first spacer layer 80 and the second spacer layer 82. In embodiments having different device types, similar to the implantation discussed above, a mask (e.g., photoresist) may be formed over the n-type region 50N while exposing the p-type region 50P, and impurities of an appropriate type (e.g., p-type) may be implanted into the fins 66 in the p-type region 50P. The mask may then be removed. Subsequently, a mask (e.g., photoresist) may be formed over the p-type region 50P while exposing the n-type region 50N, and impurities of an appropriate type (e.g., n-type) may be implanted into the fins 66 in the n-type region 50N. The mask may then be removed. The n-type impurity may be any of the previously discussed n-type impurities, and the p-type impurity may be any of the previously discussed p-type impurities. The impurity concentration of the lightly doped source / drain regions may be between about 10 15 cm -3 to about 1019 cm -3 Annealing can be used to repair implant damage and activate the implanted impurities.

[0044] exist Fig. 8A and Figure 8B , the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacer 81 and the second spacer 83, respectively. The first spacer layer 80 and the second spacer layer 82 can each be etched using a suitable etching process, for example, an isotropic etching process (for example, a wet etching process), an anisotropic etching process (for example, a dry etching process), etc. In some embodiments, the materials of the first spacer layer 80 and the second spacer layer 82 have a high etching selectivity to each other with respect to the same etching process, so that the first spacer layer 80 can be used as an etching stop layer when patterning the second spacer layer 82, and the second spacer layer 82 can be used as a mask when patterning the first spacer layer 80. For example, the second spacer layer 82 can be etched using an anisotropic etching process, wherein the first spacer layer 80 is used as an etching stop layer, and the remaining portion of the second spacer layer 82 forms the second spacer 83. Thereafter, the first spacer layer 80 may be etched using an isotropic etching process, wherein the second spacers 83 are used as an etching mask and the remaining portions of the first spacer layer 80 form the first spacers 81 .

[0045] In the illustrated embodiment, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66, the dummy gate 76, and the mask 78 (if present). In another embodiment, the second spacer layer 82 can be removed from above the first spacer layer 80 adjacent to the mask 78 (if present), the dummy gate 76, and / or the dummy dielectric 60.

[0046] Note that the above disclosure generally describes the process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used (e.g., the first spacer 81 may be formed before the second spacer 83 is formed, additional spacers may be formed and removed, etc.), etc. In addition, different structures and steps may be used to form n-type devices and p-type devices.

[0047] exist Fig. 9A and Fig. 9B, a first recess 86 is formed in the fin 66. The first recess 86 extends through the first semiconductor layer 52 and the second semiconductor layer 54, and may also extend into the substrate 50. In various embodiments, the first recess 86 may extend to the top surface of the substrate 50 without etching the substrate 50; the substrate 50 may be etched so that the bottom surface of the first recess 86 is disposed below the top surface of the STI region 68; etc. The first recess 86 may be formed by etching the fin 66 using an anisotropic etching process such as RIE, NBE, etc. During the etching process for forming the first recess 86, the first spacer 81, the second spacer 83, and the mask 78 mask portions of the first semiconductor layer 52, the second semiconductor layer 54, and the substrate 50. A single etching process may be used to etch each layer of the fin 66. In other embodiments, multiple etching processes may be used to etch the layers of the fin 66. A timed etching process may be used to stop etching the first recess 86 after the first recess 86 reaches a desired depth.

[0048] exist Fig. 10A and Fig. 10B , the first groove 86 is optionally extended. Specifically, the portion of the sidewall of the first semiconductor layer 52 exposed by the first groove 86 in the n-type region 50N can be etched in the n-type region 50N to form a sidewall groove 88, and the portion of the sidewall of the second semiconductor layer 54 exposed by the first groove 86 in the p-type region 50P can be etched in the p-type region 50P to form a sidewall groove 88. Although the sidewalls of the first semiconductor layer 52 and the second semiconductor layer 54 in the sidewall groove 88 are shown as straight, the sidewalls can be concave or convex. The sidewalls can be etched using an isotropic etching process, such as wet etching, etc. A mask can be used to protect the p-type region 50P, while an etchant selective to the first semiconductor material is used to etch the first semiconductor layer 52, so that in the n-type region 50N, the second semiconductor layer 54 and the substrate 50 remain relatively unetched compared to the first semiconductor layer 52. Similarly, a mask may be used to protect the n-type region 50N while an etchant selective to the second semiconductor material is used to etch the second semiconductor layer 54 and the substrate 50, such that in the p-type region 50P, the first semiconductor layer 52 and the substrate 50 remain relatively unetched compared to the second semiconductor layer 54. In embodiments where the first semiconductor layer 52 is formed of silicon germanium and the second semiconductor layer 54 is formed of silicon or silicon carbide, a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to etch the sidewalls of the first semiconductor layer 52 in the n-type region 50N, and a wet etching process using a hydroxide-hydrogen peroxide mixture (APM), a sulfuric acid-hydrogen peroxide mixture (SPM), or the like may be used to etch the sidewalls of the second semiconductor layer 54 in the p-type region 50P.

[0049] The internal spacer 90 is formed in the sidewall recess 88. As will be discussed in more detail below, source / drain regions will be subsequently formed in the first recess 86, and the first semiconductor layer 52 in the n-type region 50N and the second semiconductor layer 54 in the p-type region 50P will be subsequently replaced by corresponding gate structures. The internal spacer 90 serves as an isolation feature between the subsequently formed source / drain regions and the subsequently formed gate structure. In addition, the internal spacer 90 can be used to prevent damage to the subsequently formed source / drain regions by subsequent etching processes (e.g., etching processes for subsequently forming gate structures).

[0050] The inner spacer 90 can be formed by depositing an inner spacer layer in the first groove 86 and the sidewall groove 88. The inner spacer layer can be deposited by a conformal deposition process such as CVD, ALD, etc. The inner spacer layer can be formed of a material such as silicon nitride or silicon oxynitride, but any suitable material can be used, for example, a low dielectric constant (low-k) material with a k value of less than about 3.5. The inner spacer layer can then be etched to form the inner spacer 90. The etching can be an anisotropic etching process, such as RIE, NBE, etc. Although the outer sidewalls of the inner spacer 90 are shown as being recessed relative to the sidewalls of the second semiconductor layer 54 in the n-type region 50N and recessed relative to the sidewalls of the first semiconductor layer 52 in the p-type region 50P, the outer sidewalls of the inner spacer 90 can extend beyond or be flush with the sidewalls of the second semiconductor layer 54 and / or the first semiconductor layer 52, respectively. In other words, the inner spacer 90 can partially fill, completely fill, or overfill the sidewall groove 88. Furthermore, although the sidewalls of the inner spacer 90 are shown as being straight, the sidewalls of the inner spacer 90 may be concave or convex.

[0051] exist Fig.11A and Fig. 11B, an epitaxial source / drain region 92 is formed in the first recess 86. The epitaxial source / drain region 92 is formed in the first recess 86 so that each dummy gate 76 is disposed between a corresponding adjacent pair of the epitaxial source / drain regions 92. In some embodiments, the first spacer 81 and the second spacer 83 are used to separate the epitaxial source / drain region 92 from the dummy gate 76 by an appropriate lateral distance so that the epitaxial source / drain region 92 does not short-circuit the gate of a subsequently formed nanoFET. In addition, the internal spacer 90 can also be used to separate the epitaxial source / drain region 92 from the first semiconductor layer 52 in the n-type region 50N and the second semiconductor layer 54 in the p-type region 50P by an appropriate lateral distance so that the epitaxial source / drain region 92 does not short-circuit the gate of a subsequently formed nanoFET. The epitaxial source / drain regions 92 may be formed to contact the inner spacer 90 (if present), and may extend beyond the sidewalls of the second semiconductor layer 54 in the n-type region 50N and beyond the sidewalls of the first semiconductor layer 52 in the p-type region 50P (if the sidewall recess 88 is present). The epitaxial source / drain regions 92 may apply stress on the second semiconductor layer 54 in the n-type region 50N and on the first semiconductor layer 52 in the p-type region 50P, thereby improving performance.

[0052] The epitaxial source / drain region 92 in the n-type region 50N can be formed by masking the p-type region 50P. Then, the epitaxial source / drain region 92 is epitaxially grown in the first groove 86 in the n-type region 50N. The epitaxial source / drain region 92 may include any acceptable material suitable for an n-type nano FET. For example, if the second semiconductor layer 54 is silicon, the epitaxial source / drain region 92 in the n-type region 50N may include a material that applies tensile strain on the second semiconductor layer 54, such as silicon, silicon carbide, phosphorus-doped carbon silicon, silicon phosphide, etc. The epitaxial source / drain region 92 in the n-type region 50N may have a surface that is elevated relative to the corresponding surface of the fin 66, and may have a facet.

[0053] The epitaxial source / drain region 92 in the p-type region 50P can be formed by masking the n-type region 50N. Then, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 in the p-type region 50P. The epitaxial source / drain region 92 may include any acceptable material suitable for a p-type nano FET. For example, if the first semiconductor layer 52 is silicon germanium, the epitaxial source / drain region 92 in the p-type region 50P may include a material that applies compressive strain on the first semiconductor layer 52, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain region 92 in the p-type region 50P may also have a surface that is elevated relative to the corresponding surface of the fin 66 and may have a small facet.

[0054] The epitaxial source / drain regions 92 and / or the fins 66 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions followed by annealing. The impurity concentration of the source / drain regions may be between about 10 19 cm -3 to about 10 21 cm -3 The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 may be doped in situ during growth.

[0055] As a result of the epitaxial process used to form epitaxial source / drain regions 92, the upper surfaces of epitaxial source / drain regions 92 have facets that extend laterally outward beyond the sidewalls of fins 66. In some embodiments, these facets merge adjacent epitaxial source / drain regions 92 of the same nanoFET, such as Fig. 11C In other embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed, such as Fig.11D As shown. Fig.11A and Fig. 11B In the illustrated embodiment, the first spacer 81 and the second spacer 83 can be formed to cover the portion of the sidewall of the fin 66 that extends over the STI region 68, thereby preventing epitaxial growth. In some other embodiments, the spacer etch used to form the first spacer 81 and the second spacer 83 can be adjusted to remove the spacer material to allow the epitaxial growth area to extend to the top surface of the STI region 68.

[0056] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of a different semiconductor material and / or may be doped to a different dopant concentration. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration that is less than the second semiconductor material layer 92B and greater than the third semiconductor material layer 92C. In an embodiment in which the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be grown from the fin 66, the second semiconductor material layer 92B may be grown from the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be grown from the second semiconductor material layer 92B.

[0057] exist Fig. 12A and Fig. 12B In the embodiment of the present invention, a first interlayer dielectric (ILD) layer 96 is deposited over the epitaxial source / drain regions 92, the first spacer 81, the second spacer 83, the mask 78 (if present) or the dummy gate 76, and the STI region 68. The first ILD layer 96 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include: oxides, such as silicon oxide), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.; nitrides, such as silicon nitride; etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD layer 96 and the epitaxial source / drain regions 92, the first spacer 81, the second spacer 83, the mask 78 (if present) or the dummy gate 76, and the STI region 68. The CESL 94 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which has a different etch rate than the material of the first ILD layer 96 .

[0058] exist Fig.13A and Fig. 13B In the process, a planarization process such as CMP may be performed to make the top surface of the first ILD layer 96 flush with the top surface of the mask 78 (if present) or the dummy gate 76. The planarization process may also remove the mask 78 on the dummy gate 76, and portions of the first spacer 81 and the second spacer 83 along the sidewalls of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, the second spacer 83, and the first ILD layer 96 are coplanar (within the range of process variation). Therefore, the top surface of the dummy gate 76 is exposed through the first ILD layer 96. In some embodiments, the mask 78 may remain, in which case the planarization process makes the top surface of the first ILD layer 96 flush with the top surfaces of the mask 78, the first spacer 81, and the second spacer 83.

[0059] exist Fig.14A and Fig. 14B , the first semiconductor layer 52 in the n-type region 50N and the second semiconductor layer 54 in the p-type region 50P are removed. The remaining semiconductor layers form nanostructures 55N, 55P, which are disposed between adjacent pairs of epitaxial source / drain regions 92. Specifically, the remaining second semiconductor layer 54 in the n-type region 50N forms a nanostructure 55N, which will serve as a channel region of an n-type nanoFET, and the remaining first semiconductor layer 52 in the p-type region 50P forms a nanostructure 55P, which will serve as a channel region of a p-type nanoFET. The formation of the nanostructures 55N, 55P is described below with reference to FIG. 15A to FIG. 15G Discuss in more detail.

[0060] The dummy gate 76 and optional dummy dielectric 60 are removed and replaced with a gate structure 85 surrounding the nanostructure 55. The gate structure 85 includes a gate dielectric 112 and a gate electrode 114. The formation of the gate structure 85 is described below with reference to FIG. 15A to FIG. 15G As discussed further below, the gate electrode 114 is formed to have a funnel shape, wherein a lower portion of the gate electrode 114 has parallel opposing sidewalls, and an upper portion of the gate electrode 114 has inclined opposing sidewalls. Forming the gate electrode 114 to have a funnel shape may help avoid forming a seam (or void) in the gate electrode 114, which may improve the work function of the gate electrode 114 and reduce the internal gate resistance (R g ). Therefore, the performance and yield of the obtained nano FET can be improved.

[0061] FIG. 15A to FIG. 15G is a method for forming nanostructures 55 according to some embodiments (see Fig.15D ) and replacement gate structure 85 (see Figure 15G ) is a cross-sectional view of an intermediate stage of the process.

[0062] FIG. 15A to FIG. 15G along Figure 1 The reference cross section BB is shown in FIG. Fig. 14B n-type region 15N (a portion of n-type region 50N) and Fig. 14B 15P (a portion of the p-type region 50P) in is shown in more detail. In the process shown, the dummy dielectric 60 and the dummy gate 76 are removed and replaced with the gate dielectric 112 and the gate electrode 114, respectively. In some embodiments, the dummy dielectric 60 is removed in a first area of ​​the die (e.g., the core logic area) and retained in a second area of ​​the chip (e.g., the input / output area). In other words, the illustrated gate replacement process can be performed in the first area of ​​the die (e.g., the core logic area), and the gate replacement process without removing the dummy dielectric 60 can be performed in the second area of ​​the die (e.g., the input / output area).

[0063] exist Fig.15AIn the embodiment of the present invention, the dummy gate 76 and the mask 78 (if present) are etched in one or more etching steps to form the grooves 100. Each groove 100 exposes the sidewalls of the first spacer 81. The grooves 100 can be very small. For example, the grooves 100 can have a width W1 in the range of about 4 nm to about 24 nm, and can have a depth D1 in the range of about 50 nm to about 120 nm. The width W1 of the grooves 100 can have a standard deviation of about 1 nm. The width W1 of the grooves 100 corresponds to the length of the channel region of the nanoFET. Forming the channel region of the nanoFET to a shorter length can improve the performance of the resulting nanoFET. However, forming the channel region to a shorter length causes the grooves 100 to have a high aspect ratio (e.g., a large ratio of depth D1 to width W1). When the grooves 100 have a high aspect ratio, seams (or gaps) may be formed in the material deposited in the grooves 100, especially when the grooves 100 are further enlarged, as discussed further below. As discussed further below, an upper portion of the groove 100 will be widened to have a funnel shape, which may help avoid the formation of such a seam.

[0064] The dummy gate 76 may be recessed by wet etching or dry etching. For example, the etching process may include a dry etching process using (one or more) reactive gases that selectively etches the dummy gate 76 at a faster rate than the first ILD layer 96, the first spacer 81, or the second spacer 83. A timed etching process may be used to stop etching the dummy gate 76 after the groove 100 reaches a desired depth. Specifically, the depth of the groove 100 is controlled so that the fin 66 and the dummy dielectric 60 remain covered after the groove 100 is formed. In some embodiments, the dummy gate 76 is recessed by an anisotropic dry etching process performed using methane (CH4), fluorine (F), ammonia (NH3), etc., which may be performed for a duration in the range of about 30 seconds to 180 seconds, which may allow the remaining portion of the dummy gate 76 to have a height H1 (measured from the top surface of the fin 66) less than about 5 nm. Performing the anisotropic dry etching process with parameters within these ranges allows the recess 100 to be formed to a sufficient depth to both protect the fin 66 and the dummy dielectric 60 and ensure that the recess 100 can be sufficiently widened in subsequent processes. Performing the anisotropic dry etching process with parameters outside these ranges may not allow the recess 100 to be formed to a sufficient depth to both protect the fin 66 and the dummy dielectric 60 and ensure that the recess 100 can be sufficiently widened in subsequent processes.

[0065] exist Fig. 15BIn the embodiment, impurities are implanted into the first region of the spacers 81, 83 to modify the etching rate of the first region of the spacers 81, 83 compared to the second region of the gate spacer into which the impurities are not implanted. As discussed in more detail below, the first region of the spacers 81, 83 will be etched to widen the groove 100 to reduce or prevent the formation of gaps or seams when the replacement gate structure is subsequently formed. The second region of the spacers 81, 83 remains unmodified or less modified during / after the impurity implantation. In an embodiment in which the spacers 81, 83 are formed of silicon oxycarbonitride as described above, the impurities may be oxygen and may be implanted by a plasma oxidation process. In another embodiment in which the spacers 81, 83 are formed of silicon oxycarbonitride as described above, the impurities may be nitrogen and may be implanted by a plasma nitridation process. The impurity implantation modifies the region 81M of the first spacer 81 and the region 83M of the second spacer 83, while the unmodified region 81N of the first spacer 81 and the unmodified region 83N of the second spacer 83 are not affected by the impurity implantation (or at least less affected than the modified regions 81M, 83M). In some embodiments, the impurity implantation also modifies region 96M of first ILD layer 96, while unmodified region 96N of first ILD layer 96 is not affected by the impurity implantation. In some embodiments, the impurity implantation also modifies region 76M of dummy gate 76, while unmodified region 76N of dummy gate 76 is not affected by the impurity implantation. The exposed portion of CESL 94 is thin, so CESL 94 remains substantially unaffected by the impurity implantation.

[0066] The modified region 81M and the modified region 83M are rich in impurities. For example, the modified regions 81M and 83M may include oxycarbon nitride silicon with oxygen or nitrogen having a higher concentration (atomic percentage) than the unmodified region 81N and the unmodified region 83N, respectively. In some embodiments, the unmodified regions 81N and 83N maintain their initial composition. In other words, the final composition of the unmodified regions 81N and 83N is the same as the initial composition of the unmodified regions 81N and 83N. In some embodiments, the unmodified regions 81N and 83N are slightly modified, but less modified than the modified regions 81M and 83M. In other words, the final composition of the unmodified regions 81N and 83N is closer to their initial composition than the final composition of the modified regions 81M and 83M. As discussed further below, an etching selective to the modified (e.g., impurity-rich) regions will be subsequently performed to remove the modified regions 81M and the modified regions 83M, thereby widening the groove 100.

[0067] In some embodiments, the impurity implantation is performed by a plasma implantation process. The plasma implantation process can be performed in a chamber in which a chuck supports the substrate 50. A precursor gas is provided to the chamber, and a plasma generator can be used to generate plasma from the precursor gas. The plasma generator can be an inductively coupled plasma (ICP) generator, a transformer coupled plasma (TCP) generator, a remote plasma generator, etc.

[0068] During the plasma implantation process, a gas source is provided (e.g., flows) on the substrate 50. The gas source includes an impurity source precursor gas and a carrier gas. Suitable impurity source precursor gases include oxygen (O2) when oxygen is implanted and nitrogen (N2) when nitrogen is implanted. Suitable carrier gases include xenon, helium, argon, neon, krypton, radon, etc., or a combination thereof. For example, in an embodiment in which oxidation is performed, the gas source includes oxygen as an impurity source precursor gas and includes argon, oxygen, helium, neon or xenon as a carrier gas, wherein the impurity source precursor gas can be provided at a flow rate in the range of about 0 sccm to about 500 sccm, and the carrier gas can be provided at a flow rate in the range of about 10 sccm to about 1000 sccm. Similarly, in an embodiment where nitridation is performed, the gas source includes nitrogen as an impurity source precursor gas and includes argon, ammonia, nitrogen, helium, neon or xenon as a carrier gas, wherein the impurity source precursor gas can be provided at a flow rate in a range of about 0 sccm to about 500 sccm, and the carrier gas can be provided at a flow rate in a range of about 10 sccm to about 1000 sccm.

[0069] The plasma generator generates radio frequency (RF) power to generate plasma from a gas source. The plasma includes impurity ions 102 (e.g., oxygen ions, nitrogen ions, etc.) and impurity radicals 104 (e.g., oxygen radicals, nitrogen radicals, etc.). A bias is generated between the plasma generator and the chuck supporting the substrate 50. In some embodiments, the applied RF bias is pulsed between low power and high power. In some embodiments, the applied direct current (DC) bias is pulsed between low voltage and high voltage. During the bias application, the impurity ions 102 in the plasma are accelerated and injected into the spacers 81, 83 to form the modified regions 81M, 83M. The impurity ions 102 are also injected into the first ILD layer 96 to form the modified region 96M. The plasma generation power can be in the range of about 30 watts to about 4000 watts. In such an embodiment, when no bias is applied, the total energy of the impurity ions 102 is in the range of about 0.5 eV to about 25 eV, and the total energy of the impurity radicals 104 is in the range of about 0.5 eV to about 10 eV. The plasma implantation process may be performed using an RF bias having a low power of about zero and a high power of up to about 100 watts. The plasma implantation process may be performed using a DC bias having a low voltage of about zero and a high voltage of up to about 100 V. In such an embodiment, applying the bias increases the total energy of the impurity ions 102 by an amount in the range of about 3 eV to about 10 eV, and does not increase the total energy of the impurity radicals 104.

[0070] During the plasma implantation process, the impurity ions 102 collide with the impurity radicals 104, which may result in low directivity of the implantation and generate shadows during the implantation. In other words, the implantation is performed in a non-directional manner. According to some embodiments, the generated plasma includes very few impurity ions 102 and many impurity radicals 104. For example, the plasma density of the generated plasma may be about 10 9 to about 10 12 Generating a plasma having many impurity radicals 104 causes the impurity ions 102 to collide with more impurity radicals 104 during implantation, thereby increasing the amount of shadowing and causing fewer impurity ions 102 to be directed toward the remaining portion of the dummy gate 76. As a result, most of the impurity ions 102 are implanted at an acute angle of incidence relative to a major surface of the structure (e.g., the topmost surface of the first ILD layer 96 or the major surface of the substrate 50). The angle of incidence may be small, for example, in a range of about 3 degrees to about 50 degrees.

[0071] The amount of shadows during the plasma implantation process can be increased by controlling the environment when the plasma is generated. Specifically, the temperature, pressure, and plasma generation power, as well as the bias amount, can affect the amount of impurity ions 102 and impurity radicals 104 generated. According to some embodiments, the plasma is generated at a low temperature, low pressure, low plasma generation power, and low bias amount. For example, the plasma can be generated at a temperature in the range of about room temperature (e.g., about 20°C) to about 650°C, a pressure in the range of about 5mTorr to about 500mTorr, the plasma generation power discussed above, and the bias amount discussed above. Such a plasma generation environment produces a large amount of shadows during implantation. The plasma implantation process can be performed for a duration in the range of about 3 seconds to about 300 seconds, producing about 10 12 cm -3 to about 10 19 cm -3 . Performing the plasma implantation process with parameters within these ranges allows the modified regions 81M, 83M to have sufficient etch selectivity relative to the unmodified regions 81N, 83N, thereby protecting the unmodified regions 81N, 83N from etching during subsequent removal of the modified regions 81M, 83M. Performing the plasma implantation process with parameters outside these ranges may not allow the modified regions 81M, 83M to have sufficient etch selectivity relative to the unmodified regions 81N, 83N, and thus the unmodified regions 81N, 83N may not be protected from etching during subsequent removal of the modified regions 81M, 83M.

[0072] When the groove 100 has a high aspect ratio, implanting the impurity ions 102 with a large amount of shadows results in fewer impurity ions 102 being implanted into the lower portion of the groove 100 than in the upper portion of the groove 100. In addition, due to the large amount of shadows, the modified regions 81M, 83M are formed by implanting the top surfaces and exposed sidewalls of the spacers 81, 83, so that the modified regions 81M, 83M have a right triangle shape. The shape of the spacers 81, 83 resulting from the triangular modified regions 81M, 83M is discussed further below.

[0073] exist Fig. 15CIn one or more etching steps, the remaining portion of the dummy gate 76 is removed, thereby expanding the recess 100 to expose the dummy dielectric 60. The dummy gate 76 may be removed by a wet or dry etch process that etches both the modified region 76M and the unmodified region 76N of the dummy gate 76. For example, the etching process may include a dry etching process using (one or more) reactive gases that selectively etches the dummy gate 76 at a faster rate than the first ILD layer 96, the first spacer 81, or the second spacer 83. In some embodiments, by utilizing the same method as the reference Fig.15A The dummy gate 76 is removed by an anisotropic dry etching process performed with the same etchant discussed above (e.g., the anisotropic dry etching process for initially recessing the dummy gate 76), but the parameters of the anisotropic dry etching process are modified to increase the etching selectivity to the material of the dummy gate 76. During the dry etching, a bias is generated between the plasma generator and the chuck supporting the substrate 50. In some embodiments, the anisotropic dry etching for initially recessing the dummy gate 76 and the anisotropic dry etching for removing the remaining portion of the dummy gate 76 are performed using different biases, for example, different DC biases and / or different RF biases. In some embodiments, the dry etching for removing the remaining portion of the dummy gate 76 can be performed using a DC bias having a low voltage of about zero and a high voltage of up to about 300V. In some embodiments, the dry etching for removing the remaining portion of the dummy gate 76 can be performed using an RF bias having a low power of about zero and a high power of up to about 1000 watts. Performing the dry etch using the bias(es) within these ranges may increase the anisotropy of the dry etch, which may increase the etch selectivity to the material of the dummy gate 76 .

[0074] Then, the modified regions 81M, 83M of the spacers 81, 83 are removed in one or more etching steps to widen the upper portion of the groove 100. The (one or more) etching steps are selective to the impurities injected into the spacers 81, 83. For example, when the spacers 81, 83 include silicon oxycarbonitride and the modified regions 81M, 83M are oxygen-rich or nitrogen-rich, the etching process may include dry etching using (one or more) reactive gases that are selective to oxides or nitrides, respectively. Since the modified regions 81M, 83M have a greater impurity concentration than the unmodified regions 81N, 83N, the etching process etches the modified regions 81M, 83M at a greater rate than the unmodified regions 81N, 83N. For example, relative to the etching process, the etching rate of the modified regions 81M, 83M can be about 1.1 to about 10 times the etching rate of the unmodified regions 81N, 83N. In some embodiments, the dummy dielectric 60 may be formed of a material having a large impurity component, so the dummy dielectric 60 may also be etched at a high rate by an etching process. For example, when the dummy dielectric 60 is an oxide and the impurity injected into the modified regions 81M, 83M is oxygen, the etching selective to the oxygen-rich region may also etch the dummy dielectric 60. Specifically, during the removal of the modified regions 81M, 83M, the dummy dielectric 60 may be removed to deepen the recess 100. Finally, as described above, the modified region 96M of the first ILD layer 96 may also be formed. The modified region 96M of the first ILD layer 96 may also be etched at a high rate by an etching process to form a recess 106.

[0075] In some embodiments, the etching process is anisotropic dry etching performed using nitrogen trifluoride (NF3), ammonia (NH3), hydrogen fluoride (HF), etc. The etching gas solution can flow on the substrate 50, for example, in the groove 100, without generating plasma. The dry etching can be performed for a duration in the range of about 1 second to about 250 seconds, and at a temperature of about room temperature (e.g., about 20°C) to about 350°C. The dry etching converts the materials of the modified regions 81M, 83M, the modified regions 96M, and the dummy dielectric 60 into byproducts that can be discharged from the groove 100 by, for example, vacuum means. For example, when the impurity is oxygen, anisotropic dry etching can be performed with HF, NH3, NF3, or a combination thereof to produce byproducts, for example, ammonium fluorosilicate, silicon tetrafluoride, water, or a combination thereof. Similarly, when the impurity is nitrogen, anisotropic dry etching can be performed with HF, NH3, NF3, or a combination thereof to produce byproducts, for example, ammonium fluorosilicate, silicon tetrafluoride, water, or a combination thereof. Similarly, when the impurity is nitrogen, anisotropic dry etching can be performed with HF, NH3, NF3, or a combination thereof to produce byproducts, for example, ammonium fluorosilicate, silicon tetrafluoride, or a combination thereof.

[0076] In another embodiment in which the dummy dielectric 60 is not formed of a material having a large impurity content, the modified regions 81M, 83M of the spacers 81, 83 and the modified region 96M of the first ILD layer 96 may be removed in the first etching process, and the dummy dielectric 60 may be removed in the second etching process.

[0077] After the etching process, the unmodified regions 81N, 83N of the spacers 81, 83 and the unmodified region 96N of the first ILD layer 96 remain. The remaining portion of the first spacer 81 has an upper portion 81U and a lower portion 81L. The remaining portion of the second spacer 83 has an upper portion 83U and a lower portion 83L. The upper portions 81U, 83U and the lower portions 81L, 83L together form a funnel shape of the groove 100. The upper portions 81U, 83U have angled opposite sidewalls that intersect at the vertex. The opposite sidewalls of the upper portions 81U, 83U form an inner angle θ1. The angle θ1 can be in the range of about 3 degrees to about 50 degrees. The width of the upper portions 81U, 83U continuously decreases in a direction extending away from the top surface of the fin 66. The width of the lower portions 81L, 83L is constant along a direction extending away from the top surface of the fin 66. The lower portion 81 , 83L has parallel opposing side walls.

[0078] As described above, in some embodiments, regions 81N, 83N of spacers 81, 83 are not completely modified, but are modified less than regions 81M, 83M. Specifically, regions 81N, 83N may be implanted with less impurities than regions 81M, 83M. As a result, in such embodiments, upper portions 81U, 83U of spacers 81, 83 may contain some impurities, while lower portions 81L, 83L of spacers 81, 83 do not contain impurities. For example, when oxygen is implanted, upper portions 81U, 83U may include SiO x N y C 1-x-y , wherein x and y are in the range of 0 to 1 and x is greater than y, and the lower portions 81L, 83L of the spacers 81, 83 may include SiO x N y C 1-x-y , where x and y are in the range of 0 to 1 and x is less than, equal to, or greater than y.

[0079] The groove 100 is enlarged by removing the modified regions 81, 83M and the dummy dielectric 60. For example, the groove 100 may have a depth D2 in the range of about 55 nm to about 125 nm, may have a lower width W2 in the range of about 4 nm to about 24 nm, and may have an upper width W3 in the range of about 6 nm to about 40 nm. By removing the dummy gate 76 and the dummy dielectric 60, the depth D2 is greater than the depth D1 (see FIG. 2 ). Fig.15A The lower width W2 is located at the bottom of the groove 100 and is greater than the width W1 (see Fig.15A ), because the unmodified regions 81N, 83N of the spacers 81, 83 do receive some etching, albeit less than the modified regions 81M, 83M of the spacers 81, 83. The lower width W2 of the groove 100 may have a standard deviation of about 2 nm. The standard deviation of the lower width W2 may be greater than the standard deviation of the width W1. The lower width W2 of the groove 100 corresponds to the length of the channel region of the nanoFET. Forming the channel region of the nanoFET to a shorter length may improve the performance of the resulting nanoFET. The upper width W3 is located at the top of the groove 100 and is greater than the lower width W2.

[0080] The spacers 81, 83 have inner angles 81C, 83C at the interface of the upper portions 81U, 83U and the lower portions 81L, 83L, respectively. In the illustrated embodiment, the inner angles 81C, 83C have a well-defined profile. In some embodiments (discussed further below), the inner angles 81C, 83C do not have a well-defined profile, but rather have a rounded profile. The inner angle 81C is set at a height H2 from the top surface of the fin 66, which may be in the range of about 4 nm to about 38 nm.

[0081] Widening the groove 100 to have a funnel shape can help avoid a pinch-off effect when filling the groove 100, thereby avoiding the formation of a seam. The ratio of the upper width W3 to the lower width W2 can be in the range of about 1.1 to about 11, and the ratio of the depth D2 to the height H2 can be in the range of about 1.2 to about 32. Widening the groove 100 to have a dimension ratio within these ranges helps to form a funnel shape that can be used to avoid a pinch-off effect during subsequent filling. Forming the groove 100 to have a dimension ratio outside these ranges may not help to form a funnel shape that can be used to avoid a pinch-off effect during subsequent filling. For example, when the ratio of the upper width W3 to the lower width W2 is greater than a given range, parasitic capacitance may be caused between the resulting gate structures, for example, due to excessive loss of dielectric material between the gate structures. Similarly, when the ratio of the upper width W3 to the lower width W2 is less than a given range, a pinch-off effect may occur.

[0082] exist Fig.15D In the embodiment, the first semiconductor layer 52 in the n-type region 50N and the second semiconductor layer 54 in the p-type region 50P are removed to expand the groove 100. Therefore, the nanostructure 55N is formed in the n-type region 50N, and the nanostructure 55P is formed in the p-type region 50P.

[0083] The first semiconductor layer 52 in the n-type region 50N may be removed by masking the p-type region 50P and performing an etching process in the n-type region 50N. In some embodiments, the etching process is an isotropic etching process, for example, wet etching using an etchant that selectively etches the first semiconductor layer 52 at a faster rate than the second semiconductor layer 54 or the substrate 50. In an embodiment where the first semiconductor layer 52 is formed of silicon germanium, the first semiconductor layer 52 in the n-type region 50N may be removed by a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like.

[0084] The second semiconductor layer 54 in the p-type region 50P may be removed by masking the n-type region 50N and performing an etching process in the p-type region 50P. In some embodiments, the etching process is an isotropic etching process, for example, wet etching using an etchant that selectively etches the second semiconductor layer 54 at a faster rate than the first semiconductor layer 52 or the substrate 50. In embodiments where the second semiconductor layer 54 is formed of silicon or silicon carbide, the second semiconductor layer 54 in the p-type region 50P may be removed by a wet etching process using a diluted ammonium hydroxide-hydrogen peroxide mixture (APM), a sulfuric acid-hydrogen peroxide mixture (SPM), or the like.

[0085] exist Fig.15E , a gate dielectric layer 108 is formed. The gate dielectric layer 108 is conformally deposited in the recesses 100, 106. In the n-type region 50N, the gate dielectric layer 108 is formed on the top surface, sidewalls, and bottom surface of the nanostructure 55N. In the p-type region 50P, the gate dielectric layer 108 is formed on the top surface, sidewalls, and bottom surface of the nanostructure 55P. The gate dielectric layer 108 is also deposited on the top surface of the first ILD layer 96, the CESL 94, the first spacer 81, the second spacer 83, and the STI region 68.

[0086] Fig.15H yes Fig.15EDetailed view of region 15H in FIG. 15A shows gate dielectric layer 108 in more detail. Gate dielectric layer 108 includes one or more dielectric layers, such as oxides, metal oxides, metal silicates, etc., or combinations thereof. For example, in some embodiments, gate dielectric layer 108 may include an interfacial layer 108A of silicon oxide formed by thermal oxidation or chemical oxidation, and a metal oxide layer 108B on interfacial layer 108A. In some embodiments, gate dielectric layer 108 includes a high-k dielectric material, and in these embodiments, gate dielectric layer 108 may have a k value greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods of forming gate dielectric layer 108 may include molecular beam deposition (MBD), ALD, PECVD, etc. In some embodiments, the same gate dielectric layer 108 is deposited in n-type region 50N and p-type region 50P. In some embodiments, different gate dielectric layers 108 are deposited in the n-type region 50N and the p-type region 50P.

[0087] exist Fig.15F In the embodiment, a gate electrode layer 110 is deposited over the gate dielectric layer 108 , filling the remaining portion of the recess 100 . Fig.15H yes Fig.15F Detailed view of region 15H in FIG. 1 shows gate electrode layer 110 in more detail. Gate electrode layer 110 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although in Fig.15F A single gate electrode layer 110 is shown in FIG. 1 , but the gate electrode layer 110 may include any number of liner layers 110A, any number of work function adjustment layers 110B, and a filling material 110C, such as Fig.15H Any combination of layers constituting the gate electrode layer 110 may be deposited between adjacent nanostructures 55N in the n-type region 50N, and may be deposited between adjacent nanostructures 55P in the p-type region 50P.

[0088] exist Figure 15GIn the process, a planarization process such as CMP can be performed to remove excess portions of the material of the gate dielectric layer 108 and the material of the gate electrode layer 110, which are outside the recess 100, for example, above the top surface of the first ILD layer 96. The remaining portions of the gate dielectric layer 108 and the gate electrode layer 110 form the gate dielectric 112 and the gate electrode 114, respectively. The gate dielectric 112 and the gate electrode 114 form the gate structure 85 of the resulting nanoFET. The gate structure 85 is in physical contact with the remaining portions of the spacers 81, 83. After the planarization process, the gate structure 85 can have a height H3 (measured from the top surface of the nanostructure 55) in the range of about 4nm to about 30nm. Due to the planarization process, the final height H3 of the gate structure 85 is less than the depth D2 of the recess 100 (see Fig. 15C As discussed further below, the gate structure 85 has a funnel shape. In some embodiments, a ratio of an upper width of the gate structure 85 to a lower width of the gate structure 85 may be in a range of about 1.1 to about 11.

[0089] In some embodiments, the upper portions 81U, 83U of the spacers 81, 83 remain after the planarization process. The gate electrode 114 therefore has an upper portion 114U and a lower portion 114L, which together form a funnel shape. The width of the upper portion 114U increases continuously in a direction extending away from the top surface of the nanostructure 55. The width of the lower portion 114L is constant along a direction extending away from the top surface of the nanostructure 55. The width of the gate dielectric 112 is constant along the sidewall of the gate electrode 114. The gate electrode 114 has an inner angle 114C at the interface of the upper portion 114U and the lower portion 114L. The sidewall of the gate electrode 114 forms an inner angle θ2 at the inner angle 114C of the gate electrode 114, and the difference between the inner angle θ2 and the inner angle θ1 (see Fig. 15C ) is equal to 180 degrees. In other words, the interior angle θ2 can be in the range of about 183 degrees to about 230 degrees. In the illustrated embodiment, the interior angle 114C has a well-defined profile. In some embodiments (discussed further below), the interior angle 114C does not have a well-defined profile, but rather has a rounded profile.

[0090] The formation of the gate dielectric 112 in the n-type region 50N and the p-type region 50P may occur simultaneously, such that the gate dielectric 112 in each region is formed of the same material, and the formation of the gate electrode 114 may occur simultaneously, such that the gate electrode 114 in each region is formed of the same material. In some embodiments, the gate dielectric 112 in each region may be formed by a different process, such that the gate dielectric 112 may be a different material and / or have a different number of layers, and / or the gate electrode 114 in each region may be formed by a different process, such that the gate electrode 114 may be a different material and / or have a different number of layers. When different processes are used, various masking steps may be used to mask and expose the appropriate regions.

[0091] The invention is discussed in the context of a plasma oxidation process or a plasma nitridation process. FIG. 15A to FIG. 15G However, it should be understood that any impurity can be implanted (see Fig. 15B ) into the spacers 81, 83 to modify the etch rate of portions of the spacers 81, 83. Any etch selective to the implanted impurities (see Fig. 15C ) to remove the modified portions of the spacers 81 , 83 and widen the groove 100 .

[0092] exist Fig.16A and Fig. 16B In the embodiment of the present invention, the second ILD layer 118 is deposited on the first ILD layer 96. The second ILD layer 118 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include: an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.; a nitride, such as silicon nitride; etc. After formation, the second ILD layer 118 may be planarized, for example, by CMP. In some embodiments, an etch stop layer is formed between the first ILD layer 96 and the second ILD layer 118. The etch stop layer may include a dielectric material having an etch rate different from that of the material of the second ILD layer 118, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0093] In some embodiments, before forming the second ILD layer 118, a gate mask 116 may be formed over the gate dielectric 112 and the gate electrode 114. The gate mask 116 may protect the gate dielectric 112 and the gate electrode 114 during subsequent contact formation, and the subsequently formed gate contact may penetrate the gate mask 116. As an example of forming the gate mask 116, the gate dielectric 112 and the gate electrode 114 may be recessed to form a recess directly between opposing portions of the second spacer 83. One or more layers of dielectric material are filled in the recess, for example, silicon nitride, silicon oxynitride, etc. A planarization process is performed to remove excess portions of the dielectric material extending over the first ILD layer 96. The remaining portion of the dielectric material in the recess forms the gate mask 116.

[0094] exist Fig.17A and Fig. 17B In the embodiment of the present invention, a gate contact 120 extending through the second ILD layer 118 and the gate mask 116 (if present) is formed, and a source / drain contact 122 extending through the second ILD layer 118, the first ILD layer 96, and the CESL 94 is formed. An opening for the gate contact 120 is formed through the second ILD layer 118 and the gate mask 116, and an opening for the source / drain contact 122 is formed through the second ILD layer 118, the first ILD layer 96, and the CESL 94. The opening can be formed using acceptable photolithography and etching techniques. A liner (e.g., a diffusion barrier layer, an adhesion layer, etc.) and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD layer 118. The remaining liner and conductive material form a gate contact 120 and a source / drain contact 122 in the opening. The gate contact 120 is connected (e.g., physically and electrically coupled) to the gate electrode 114, and the source / drain contact 122 is connected to the epitaxial source / drain region 92. The gate contact 120 and the source / drain contact 122 can be formed in different processes, or can be formed in the same process. Although the gate contact 120 and the source / drain contact 122 are shown in the same cross-section, the contacts can be formed in different cross-sections, which can avoid shorting of the contacts.

[0095] In some embodiments, a silicide region is formed between the epitaxial source / drain region 92 and the source / drain contact 122. In some embodiments, the silicide region is formed by depositing a metal in an opening for the source / drain contact 122 (e.g., on the epitaxial source / drain region 92) and then performing a thermal annealing process. The metal can be a metal that can react with the semiconductor material (e.g., silicon, silicon germanium, germanium, etc.) of the epitaxial source / drain region 92 to form a silicide region, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof, etc. After the thermal annealing process, any unreacted portions of the deposited metal can then be removed, for example, by an etching process. Although they are referred to as silicide regions, the regions formed on the epitaxial source / drain region 92 can also be germanide regions, silicon germanide regions (e.g., regions including silicide and germanide), etc.

[0096] Fig.18 A cross-sectional view of a nanoFET according to some embodiments is shown. Fig. 17B The n-type region 15N (a portion of the n-type region 50N) and Fig. 17B The p-type region 15P in FIG. 114 (a portion of the p-type region 50P) is shown in FIG. 115. As shown in the figure, the gate mask 116 may have an inclined sidewall.

[0097] Embodiments can achieve advantages. Performing impurity implantation allows the first region (e.g., region 81M, 83M) of the spacers 81, 83 to be modified more than the second region (e.g., region 81N, 83N) of the spacers 81, 83. Therefore, etching that is selective to impurities can be performed to remove the first region (e.g., region 81M, 83M) of the spacers 81, 83 without substantially etching the second region (e.g., region 81N, 83N) of the spacers 81, 83. In this way, the groove 100 has an upper portion whose width continuously increases in a direction extending away from the fin 66. Forming the groove 100 having such a shape can help avoid a pinch-off effect when filling the groove 100 with the gate electrode layer 110. Therefore, the gap filling window for the gate electrode layer 110 can be improved. Improving the gap filling window for the gate electrode layer 110 can avoid or reduce the formation of a seam (or gap) in the gate electrode 114. Therefore, the work function and internal gate resistance (R g ), thereby improving the performance and yield of the resulting FinFET.

[0098] In one embodiment, a method includes: forming a dummy dielectric over a plurality of semiconductor layers; forming a dummy gate over the dummy dielectric; depositing a gate spacer adjacent to the dummy gate and the dummy dielectric; recessing the dummy gate to form a groove exposing the gate spacer; implanting impurities in a first region of the gate spacer to increase an etch rate of the first region of the gate spacer, with a second region of the gate spacer remaining unmodified by the implantation; removing the dummy dielectric, the first region of the gate spacer, and a remaining portion of the dummy gate to expose a semiconductor layer in the groove; patterning the semiconductor layer to form a nanostructure; and forming a gate structure in the groove, the gate structure surrounding the nanostructure, the gate structure contacting the second region of the gate spacer.

[0099] In some embodiments of the method, implanting an impurity in the first region of the gate spacer includes: flowing a gas source including an impurity source precursor gas and a carrier gas through the semiconductor layer; generating a plasma from the gas source, the plasma including impurity ions and impurity radicals; and accelerating the impurity ions in the plasma toward the gate spacer in a non-directional manner. In some embodiments of the method, the impurity is oxygen and the impurity source precursor gas includes oxygen. In some embodiments of the method, the impurity is nitrogen and the impurity source precursor gas includes nitrogen. In some embodiments of the method, the plasma is generated at a temperature in a range of 20°C to 650°C, a pressure in a range of 5mTorr to 500mTorr, and a radio frequency (RF) power in a range of 30 watts to 4000 watts, and accelerating the impurity ions includes applying a direct current (DC) bias having a low voltage of zero and a high voltage of up to 100V. In some embodiments of the method, the plasma is generated at a temperature in a range of 20° C. to 650° C., a pressure in a range of 5 mTorr to 500 mTorr, and a radio frequency (RF) power in a range of 30 watts to 4000 watts, and accelerating the impurity ions includes applying an RF bias having a low power of zero and a high power of up to 100 watts. In some embodiments of the method, the plasma has a plasma density of 10 9 Up to 10 12In some embodiments of the method, removing the dummy dielectric and the first region of the gate spacer includes: performing an anisotropic dry etch in the groove, the anisotropic dry etch etching the dummy dielectric and the first region of the gate spacer at a greater rate than etching the second region of the gate spacer. In some embodiments of the method, the impurity is oxygen, the gate spacer includes silicon oxynitride, the anisotropic dry etch is performed using nitrogen trifluoride, ammonia, or hydrogen fluoride, and the anisotropic dry etch converts the first region of the gate spacer into ammonium fluorosilicate, silicon tetrafluoride, or water byproducts. In some embodiments of the method, the impurity is nitrogen, the gate spacer includes silicon oxynitride, the anisotropic dry etch is performed using nitrogen trifluoride, ammonia, or hydrogen fluoride, and the anisotropic dry etch converts the first region of the gate spacer into ammonium fluorosilicate or silicon tetrafluoride byproducts. In some embodiments of the method, after removing the dummy dielectric, the first region of the gate spacer, and the remaining portion of the dummy gate, the recess has an upper width and a lower width, the upper width is greater than the lower width, and a ratio of the upper width to the lower width is in a range of 1.1 to 11. In some embodiments of the method, recessing the dummy gate includes performing a first anisotropic dry etching process using methane at a first bias, and removing the remaining portion of the dummy gate includes performing a second anisotropic dry etching process using methane at a second bias, the second bias being different from the first bias.

[0100] In one embodiment, a structure includes: a nanostructure; an epitaxial source / drain region adjacent to the nanostructure; a gate dielectric surrounding the nanostructure; a gate electrode located above the gate dielectric, the gate electrode having an upper portion and a lower portion, the upper portion having a first width that continuously increases in a first direction extending away from a top surface of the nanostructure, and the lower portion having a second width that is constant along the first direction; and a gate spacer located between the gate dielectric and the epitaxial source / drain region.

[0101] In some embodiments of the structure, the gate electrode includes an inner corner at the interface of the upper portion and the lower portion, and the sidewall of the gate electrode forms an angle at the inner corner, the angle being in the range of 183 degrees to 230 degrees. In some embodiments of the structure, the gate spacer has an upper portion and a lower portion, the third width of the upper portion continuously decreases in the first direction, and the fourth width of the lower portion is constant along the first direction. In some embodiments, the structure also includes: a gate mask, above the gate electrode and the gate dielectric, the gate mask having an inclined sidewall; and a gate contact, extending through the gate mask and contacting the gate electrode. In some embodiments of the structure, the gate spacer includes a silicon oxycarbonitride, the silicon oxycarbonitride having a first concentration of oxygen in the upper portion of the gate spacer, and a second concentration of oxygen in the lower portion of the gate spacer, the second concentration being less than the first concentration. In some embodiments of the structure, the gate spacer includes silicon oxycarbon nitride having a first concentration of nitrogen in an upper portion of the gate spacer and a second concentration of nitrogen in a lower portion of the gate spacer, the second concentration being less than the first concentration.

[0102] In one embodiment, a structure includes: a nanostructure; a gate structure surrounding the nanostructure; and a first pair of gate spacers adjacent to the gate structure, the first pair of gate spacers being separated by a first distance at a lower portion of the gate structure, the first pair of gate spacers being separated by a second distance at an upper portion of the gate structure, the second distance being greater than the first distance.

[0103] In some embodiments of the structure, a ratio of the second distance to the first distance is in a range of 1.1 to 11.

[0104] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0105] Example 1 is a method for forming a semiconductor structure, comprising: forming a dummy dielectric above multiple semiconductor layers; forming a dummy gate above the dummy dielectric; depositing a gate spacer adjacent to the dummy gate and the dummy dielectric; recessing the dummy gate to form a groove exposing the gate spacer; injecting impurities into a first region of the gate spacer to increase an etching rate of the first region of the gate spacer, with a second region of the gate spacer remaining unmodified by the injection; removing the dummy dielectric, the first region of the gate spacer, and a remaining portion of the dummy gate to expose a semiconductor layer in the groove; patterning the semiconductor layer to form a nanostructure; and forming a gate structure in the groove, the gate structure surrounding the nanostructure, the gate structure contacting the second region of the gate spacer.

[0106] Example 2 is the method described in Example 1, wherein injecting impurities into the first region of the gate spacer includes: flowing a gas source including an impurity source precursor gas and a carrier gas through the semiconductor layer; generating a plasma from the gas source, the plasma including impurity ions and impurity radicals; and accelerating the impurity ions in the plasma toward the gate spacer in a non-directional manner.

[0107] Example 3 is the method of Example 2, wherein the impurity is oxygen and the impurity source precursor gas includes oxygen gas.

[0108] Example 4 is the method of Example 2, wherein the impurity is nitrogen and the impurity source precursor gas includes nitrogen.

[0109] Example 5 is the method described in Example 2, wherein the plasma is generated at a temperature in the range of 20°C to 650°C, a pressure in the range of 5mTorr to 500mTorr, and a radio frequency (RF) power in the range of 30W to 4000W, and wherein accelerating the impurity ions includes applying a direct current (DC) bias having a low voltage of zero and a high voltage of up to 100V.

[0110] Example 6 is the method described in Example 2, wherein the plasma is generated at a temperature in the range of 20°C to 650°C, a pressure in the range of 5mTorr to 500mTorr, and a radio frequency (RF) power in the range of 30W to 4000W, and wherein accelerating the impurity ions includes applying an RF bias having a low power of zero and a high power of up to 100W.

[0111] Example 7 is the method of Example 2, wherein the plasma density of the plasma is 10 9 Up to 10 12within the range.

[0112] Example 8 is the method described in Example 1, wherein removing the dummy dielectric and the first region of the gate spacer includes: performing anisotropic dry etching in the groove, and the anisotropic dry etching etches the dummy dielectric and the first region of the gate spacer at a greater rate than etching the second region of the gate spacer.

[0113] Example 9 is the method described in Example 8, wherein the impurity is oxygen, the gate spacer includes silicon oxycarbonitride, the anisotropic dry etching is performed using nitrogen trifluoride, ammonia, or hydrogen fluoride, and the anisotropic dry etching converts the first region of the gate spacer into ammonium fluorosilicate, silicon tetrafluoride, or water byproducts.

[0114] Example 10 is the method described in Example 8, wherein the impurity is nitrogen, the gate spacer includes silicon oxycarbonitride, the anisotropic dry etching is performed using nitrogen trifluoride, ammonia, or hydrogen fluoride, and the anisotropic dry etching converts the first region of the gate spacer into ammonium fluorosilicate or silicon tetrafluoride byproducts.

[0115] Example 11 is the method described in Example 1, wherein, after removing the dummy dielectric, the first region of the gate spacer, and the remaining portion of the dummy gate, the groove has an upper width and a lower width, the upper width is greater than the lower width, and the ratio of the upper width to the lower width is in the range of 1.1 to 11.

[0116] Example 12 is the method described in Example 1, wherein recessing the dummy gate includes performing a first anisotropic dry etching process using methane under a first bias, and wherein removing the remaining portion of the dummy gate includes performing a second anisotropic dry etching process using methane under a second bias, the second bias being different from the first bias.

[0117] Example 13 is a semiconductor structure comprising: a nanostructure; an epitaxial source / drain region adjacent to the nanostructure; a gate dielectric surrounding the nanostructure; a gate electrode located above the gate dielectric, the gate electrode having an upper portion and a lower portion, the first width of the upper portion continuously increasing in a first direction extending away from a top surface of the nanostructure, and the second width of the lower portion being constant along the first direction; and a gate spacer located between the gate dielectric and the epitaxial source / drain region.

[0118] Example 14 is the structure described in Example 13, wherein the gate electrode includes an inner angle at the interface between the upper portion and the lower portion, and the side wall of the gate electrode forms an angle at the inner angle, and the angle is in the range of 183 degrees to 230 degrees.

[0119] Example 15 is the structure of Example 13, wherein the gate spacer has an upper portion and a lower portion, the third width of the upper portion continuously decreases in the first direction, and the fourth width of the lower portion is constant along the first direction.

[0120] Example 16 is the structure described in Example 13, further comprising: a gate mask located above the gate electrode and the gate dielectric, the gate mask having an inclined sidewall; and a gate contact extending through the gate mask and contacting the gate electrode.

[0121] Example 17 is the structure described in Example 13, wherein the gate spacer includes carbon oxynitride silicon having a first concentration of oxygen in an upper portion of the gate spacer and a second concentration of oxygen in a lower portion of the gate spacer, the second concentration being less than the first concentration.

[0122] Example 18 is the structure described in Example 13, wherein the gate spacer includes carbon oxynitride silicon having a first concentration of nitrogen in an upper portion of the gate spacer and a second concentration of nitrogen in a lower portion of the gate spacer, the second concentration being less than the first concentration.

[0123] Example 19 is a semiconductor structure comprising: a nanostructure; a gate structure surrounding the nanostructure; and a first pair of gate spacers adjacent to the gate structure, the first pair of gate spacers being separated by a first distance at a lower portion of the gate structure, the first pair of gate spacers being separated by a second distance at an upper portion of the gate structure, the second distance being greater than the first distance.

[0124] Example 20 is the structure of Example 19, wherein a ratio of the second distance to the first distance is in the range of 1.1 to 11.

Claims

1. A method for forming a semiconductor structure, comprising: forming a dummy dielectric over the plurality of semiconductor layers; forming a dummy gate on the dummy dielectric; depositing a gate spacer adjacent to the dummy gate and the dummy dielectric; recessing the dummy gate to form a groove exposing the gate spacer; implanting an impurity in a first region of the gate spacer to increase an etch rate of the first region of the gate spacer, with a second region of the gate spacer remaining unmodified by the implant; removing the dummy dielectric, the first region of the gate spacer, and a remaining portion of the dummy gate to expose a semiconductor layer in the recess; patterning the semiconductor layer to form a nanostructure; as well as A gate structure is formed in the groove, the gate structure surrounds the nanostructure, and the gate structure contacts the second region of the gate spacer.

2. The method according to claim 1, wherein: Implanting impurities in the first region of the gate spacer includes: flowing a source gas including an impurity source precursor gas and a carrier gas through the semiconductor layer; generating a plasma from the gas source, the plasma comprising impurity ions and impurity radicals; and The impurity ions in the plasma are accelerated toward the gate spacers in a non-directional manner.

3. The method according to claim 2, wherein: The impurity is oxygen, and the impurity source precursor gas includes oxygen gas.

4. The method according to claim 2, wherein: The impurity is nitrogen, and the impurity source precursor gas includes nitrogen.

5. The method according to claim 2, wherein: The plasma is generated at a temperature in the range of 20°C to 650°C, a pressure in the range of 5mTorr to 500mTorr, and a radio frequency (RF) power in the range of 30W to 4000W, and wherein accelerating the impurity ions includes applying a direct current (DC) bias having a low voltage of zero and a high voltage of up to 100V.

6. The method according to claim 2, wherein: The plasma is generated at a temperature in the range of 20°C to 650°C, a pressure in the range of 5mTorr to 500mTorr, and a radio frequency (RF) power in the range of 30W to 4000W, and wherein accelerating the impurity ions includes applying an RF bias having a low power of zero and a high power of up to 100W.

7. The method according to claim 2, wherein: The plasma density of the plasma is 10 9 Up to 10 12 within the range.

8. The method according to claim 1, wherein: Removing the dummy dielectric and the first region of the gate spacer includes: An anisotropic dry etch is performed in the recess, the anisotropic dry etch etching the dummy dielectric and the first region of the gate spacer at a greater rate than etching the second region of the gate spacer.

9. The method according to claim 8, wherein: The impurity is oxygen, the gate spacer includes silicon oxycarbonitride, the anisotropic dry etching is performed using nitrogen trifluoride, ammonia, or hydrogen fluoride, and the anisotropic dry etching converts the first region of the gate spacer into ammonium fluorosilicate, silicon tetrafluoride, or water byproduct.

10. The method according to claim 8, wherein: The impurity is nitrogen, the gate spacer includes silicon oxycarbonitride, the anisotropic dry etching is performed using nitrogen trifluoride, ammonia, or hydrogen fluoride, and the anisotropic dry etching converts the first region of the gate spacer into ammonium fluorosilicate or silicon tetrafluoride byproducts.

11. The method according to claim 1, wherein: After removing the dummy dielectric, the first region of the gate spacer, and the remaining portion of the dummy gate, the groove has an upper width and a lower width, the upper width is greater than the lower width, and a ratio of the upper width to the lower width is in a range of 1.1 to 11.

12. The method according to claim 1, wherein: Recessing the dummy gate includes performing a first anisotropic dry etching process using methane at a first bias, and wherein removing the remaining portion of the dummy gate includes performing a second anisotropic dry etching process using methane at a second bias different from the first bias.

13. A semiconductor structure comprising: Nanostructures; an epitaxial source / drain region adjacent to the nanostructure; a gate dielectric surrounding the nanostructure; a gate electrode disposed on the gate dielectric, the gate electrode having an upper portion and a lower portion, the upper portion having a first width that continuously increases in a first direction extending away from a top surface of the nanostructure, and the lower portion having a second width that is constant along the first direction; as well as a gate spacer between the gate dielectric and the epitaxial source / drain regions, The gate spacer includes silicon oxycarbonitride having a first concentration of an element in an upper portion of the gate spacer and a second concentration of the element in a lower portion of the gate spacer, the second concentration being less than the first concentration, wherein the element is oxygen or nitrogen.

14. The structure according to claim 13, wherein: The gate electrode includes an inner corner at an interface of the upper portion and the lower portion, and a sidewall of the gate electrode forms an angle at the inner corner, the angle being in a range of 183 degrees to 230 degrees.

15. The structure according to claim 13, wherein: The gate spacer has an upper portion and a lower portion, a third width of the upper portion continuously decreases in the first direction, and a fourth width of the lower portion is constant along the first direction.

16. The structure of claim 13, further comprising: A gate mask, located on the gate electrode and the gate dielectric, the gate mask having an inclined sidewall; as well as A gate contact extends through the gate mask to contact the gate electrode.

17. A semiconductor structure comprising: Nanostructures; a gate structure surrounding the nanostructure; as well as a first pair of gate spacers adjacent to the gate structure, the first pair of gate spacers being separated by a first distance at a lower portion of the gate structure, the first pair of gate spacers being separated by a second distance at an upper portion of the gate structure, the second distance being greater than the first distance, Wherein, the first pair of gate spacers includes carbon oxynitride silicon, which has a first concentration of an element in the upper portion of the first pair of gate spacers and a second concentration of the element in the lower portion of the first pair of gate spacers, and the second concentration is less than the first concentration, wherein the element is oxygen or nitrogen.

18. The structure according to claim 17, wherein: A ratio of the second distance to the first distance is in a range of 1.1 to 11.

Images