High-efficiency dual-band power amplifier based on low-pass matching network and its design method

Abstract

The present invention discloses a high-efficiency dual-frequency power amplifier based on a low-pass matching network and a design method thereof, wherein the power amplifier comprises an input matching network, a gate bias circuit, a transistor, a drain bias circuit and an output matching circuit based on a low-pass matching network, wherein the input matching network adopts a stepped impedance matching circuit for matching; the output matching circuit comprises a drain bias circuit, a harmonic matching network and a fundamental matching circuit, the harmonic matching network is used to achieve harmonic control and low-pass filtering to suppress harmonics, and the fundamental matching circuit is used to achieve dual-frequency matching within a required frequency band. The present invention can achieve control and suppression of harmonics, thereby achieving high-efficiency output at two frequencies.

Description

Technical Field

[0001] The invention belongs to the field of radio frequency technology and relates to a high-efficiency dual-frequency power amplifier based on a low-pass matching network and a design method thereof. Background Art

[0002] The rapid development of wireless communication technology and mobile Internet has greatly promoted the changes in people's production and lifestyle, and at the same time has created a huge demand for RF front-ends, requiring them to meet the standards of different industrial applications. As the most important part of the RF front-end, the power amplifier plays the role of signal amplification, and its performance determines the performance of the entire communication system. Especially with the advent of the 5G era, the increase in mobile terminals has led to the growth of information data, which in turn has expanded the channel capacity, making high peak-to-average power ratio signals the mainstream, thus putting forward higher requirements for power amplifiers, especially in terms of bandwidth, efficiency, and output power.

[0003] At present, due to the coexistence of multiple communication standards and formats, modern communication systems are required to have higher flexibility and compatibility. As the communication frequency becomes higher and higher, the working bandwidth is also widened. In order to meet the needs, scientific researchers have proposed a variety of solutions. Ultra-wideband power amplifier is a more common design method. It meets the needs by covering multiple communication systems with the working bandwidth of the power amplifier. However, in actual design, ultra-wideband, especially cross-octave design, is difficult. At the same time, efficiency is sacrificed to meet the bandwidth, resulting in waste of resources. Therefore, in order to reduce the cost of communication equipment, designers turned their attention to multi-band power amplifiers, which only guarantee the performance of the power amplifier within the required frequency band, which not only reduces the design difficulty, but also saves resources. Compared with traditional single-frequency power amplifiers, the demand for RF power amplifiers that can work in multiple frequency bands at the same time will continue to increase in the future.

[0004] Therefore, in view of the above application requirements, it is necessary to study a design scheme for realizing the design of dual-band / multi-band power amplifier. Summary of the invention

[0005] To solve the above problems, the technical solution of the present invention is: a high-efficiency dual-band power amplifier based on a low-pass matching network, comprising an input matching network, a gate bias circuit, a transistor, a drain bias circuit, a harmonic control network and a fundamental matching circuit, wherein:

[0006] The input end of the input matching network serves as a power input end, and the output end thereof is connected to the gate of the transistor;

[0007] The gate bias circuit is connected in parallel to the input matching network, and the end is connected in parallel to the ground through a decoupling capacitor Cg;

[0008] The transistor drain is connected to the input end of the harmonic control network, the harmonic control network is connected to the fundamental matching circuit, the output end of the fundamental matching circuit serves as the power output end, the drain bias circuit is connected in parallel to the harmonic control network, and the end is connected in parallel to the ground through a decoupling capacitor Cd.

[0009] Preferably, the input matching network includes microstrip lines T1, T2, T3, T4, T6, T7 and a DC blocking capacitor C1; one end of the microstrip line T1 is connected to the input end, and the other end of the microstrip line T1 is connected to one end of the DC blocking capacitor C1; the other end of the DC blocking capacitor C1 is connected to one end of the microstrip line T2, and the microstrip line T2 is connected in series with the microstrip lines T3, T4, T6 and T7 in sequence; and the microstrip line T7 is connected to the gate terminal of the transistor.

[0010] Preferably, the gate bias circuit includes a microstrip line TL5 and a decoupling capacitor Cg, wherein one end of the microstrip line TL5 is connected in parallel to the connection between the microstrip lines T4 and T6, the other end of the microstrip line TL5 is connected to one end of the decoupling capacitor Cg, and the other end of the decoupling capacitor Cg is grounded.

[0011] Preferably, the bias voltage of the gate bias circuit is -2.8V.

[0012] Preferably, the harmonic control network includes microstrip lines T8, T9, T10, T14, module TS1 and module TS2, microstrip line T8 is connected to the drain of the transistor, microstrip line T8 is connected in series with microstrip lines T9, T10 and T14 in sequence, module TS1 includes microstrip line T11, one end of microstrip line T11 is connected between microstrip lines T9 and T10, and the other end of microstrip line T11 is open; microstrip line T14 is connected to module TS2 and the fundamental wave matching circuit; module TS2 includes microstrip lines T15, T16 and T17 connected in series.

[0013] Preferably, the microstrip line T9 and the microstrip line T10 have the same typical parameters, and the microstrip line T9 and the microstrip line T10 form a T-shaped line.

[0014] Preferably, the drain bias circuit includes microstrip lines T12, T13 and a decoupling capacitor Cd, wherein one end of the microstrip line T13 is connected to the microstrip lines T10 and T14 in the harmonic control network and is connected in parallel in the harmonic control network, the other end of the microstrip line T13 is connected to one end of the microstrip line T12, and the other end of the microstrip line T12 is connected to the decoupling capacitor Cd.

[0015] Preferably, the bias voltage of the drain bias circuit is 28V.

[0016] Preferably, the fundamental wave matching circuit includes microstrip lines T18, T19, T20 and a DC blocking capacitor C2, wherein one end of the microstrip line T18 is connected to the harmonic control network, and the other end is connected to one end of the microstrip line T19; the other end of the microstrip line T19 is connected to one end of the DC blocking capacitor C2; the other end of the DC blocking capacitor C2 is connected to one end of the microstrip line T20, and the other end of the microstrip line T20 is connected to the load impedance.

[0017] Based on the above purpose, the present invention also provides a design method of a high-efficiency dual-band power amplifier based on a low-pass matching network, using the above-mentioned high-efficiency dual-band power amplifier based on a low-pass matching network, comprising the following steps:

[0018] S10, source pull and load pull are performed on the transistor at the low frequency band f1 and the high frequency band f2, and it is iterated three times. At the same time, the midpoint of the line connecting the maximum efficiency point and the maximum power point is selected as the load impedance value Z to be matched later. Dopt1,2 and source impedance Z Sopt1,2 ;

[0019] S20, according to the above optimal source impedance value Z Sopt1,2 , using the stepped impedance resonant network to complete the design of the input matching network;

[0020] S30, determining the parameters of two parallel modules TS1 and TS2 and the drain bias circuit of the harmonic control network according to the harmonic range of the selected frequency, wherein module TS1 includes a microstrip line T11, and module TS2 includes serially connected microstrip lines T15, T16 and T17, wherein the electrical parameters of the microstrip lines T15 and T17 are the same, and the electrical length of the two is θ S2 , the electrical length of microstrip line T16 is 2θ S2 , module TS2 generates transmission zeros within the harmonic range to achieve harmonic suppression;

[0021] S40, after determining the harmonic control network, use microstrip lines T18 and T19 to complete fundamental impedance matching, that is, transform the real impedance value after harmonic transformation to 50 ohms;

[0022] S50, simulate and fine-tune the overall circuit.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] The present invention can achieve control and suppression at the harmonics of the required frequency band, so that the drain voltage and current have a relatively small overlap, thereby improving the efficiency of the power amplifier. At the same time, a harmonic control network is used to create multiple transmission zeros near the passband to filter out harmonic components and achieve dual-frequency matching. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1It is a structural block diagram of a high-efficiency dual-frequency power amplifier based on a low-pass matching network of the present invention;

[0026] Figure 2 It is a schematic diagram of the overall circuit structure of a high-efficiency dual-frequency power amplifier based on a low-pass matching network of the present invention;

[0027] Figure 3 It is a circuit schematic diagram of the output matching part of the high-efficiency dual-frequency power amplifier based on the low-pass matching network of the present invention;

[0028] Figure 4 It is an S parameter diagram of the output matching circuit of the high-efficiency dual-frequency power amplifier based on the low-pass matching network of the present invention;

[0029] Figure 5 It is an S parameter diagram of a high-efficiency dual-frequency power amplifier based on a low-pass matching network of the present invention;

[0030] Figure 6 It is a curve diagram showing the power added efficiency of the high-efficiency dual-frequency power amplifier based on the low-pass matching network of the present invention changing with frequency. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0032] On the contrary, the present invention covers any substitution, modification, equivalent method and scheme made on the essence and scope of the present invention as defined by the claims. Further, in order to make the public have a better understanding of the present invention, some specific details are described in detail in the detailed description of the present invention below. Those skilled in the art can fully understand the present invention without the description of these details.

[0033] In view of the defects of the prior art, the applicant has conducted an in-depth study on the structure of the traditional broadband high-efficiency power amplifier in the prior art. During the study, the applicant found that the traditional broadband high-efficiency power amplifier in the prior art has a relatively single mode, a relatively complex structure, is difficult to implement, has a large overall circuit size, and is relatively costly.

[0034] In order to overcome the defects of the prior art, see Figure 1 , which is a block diagram of a hybrid mode broadband high-efficiency power amplifier based on harmonic control according to the present invention, includes an input matching network 10, a gate bias circuit 21, a transistor 30, a drain bias circuit 22, a harmonic control network 41 and a fundamental matching circuit 42, wherein:

[0035] The input end of the input matching network 10 serves as a power input end, and its output end is connected to the gate of the transistor 30;

[0036] The gate bias circuit 21 is connected in parallel to the input matching network 10, and the end is connected in parallel to the ground through the decoupling capacitor Cg;

[0037] The drain of transistor 30 is connected to the input end of harmonic control network 41, harmonic control network 41 is connected to fundamental matching circuit 42, the output end of fundamental matching circuit 42 serves as the power output end, drain bias circuit 22 is connected in parallel to harmonic control network 41, and the end is connected in parallel to ground through decoupling capacitor Cd.

[0038] See also Figure 2 , is an overall circuit schematic diagram, the input matching network 10 includes microstrip lines T1, T2, T3, T4, T6, T7 and a DC blocking capacitor C1; one end of the microstrip line T1 is connected to the input end, and the other end of the microstrip line T1 is connected to one end of the DC blocking capacitor C1; the other end of the DC blocking capacitor C1 is connected to one end of the microstrip line T2, and the microstrip line T2 is connected in series with the microstrip lines T3, T4, T6 and T7 in sequence; the microstrip line T7 is connected to the gate terminal of the transistor 30.

[0039] The gate bias circuit 21 includes a microstrip line TL5 and a decoupling capacitor Cg, wherein one end of the microstrip line TL5 is connected in parallel to the connection point of the microstrip lines T4 and T6, the other end of the microstrip line TL5 is connected to one end of the decoupling capacitor Cg, and the other end of the decoupling capacitor Cg is grounded. The bias voltage of the gate bias circuit 21 is -2.8V.

[0040] For transistor 30, Cree's CGH40010F is selected, which has a small signal gain of 14-16 dB, a saturation gain of 10 dB, and a saturated output power of more than 10 W. According to the operating manual, it is operated in a class AB state, with a gate bias set to -2.7 V and a drain bias of 28 V. This example aims to achieve high-efficiency output at 1.6 GHz and 2.4 GHz frequencies.

[0041] See also Figure 3The schematic diagram of the output matching circuit includes a harmonic control network 41, a drain bias circuit 22 and a fundamental matching circuit 42. The harmonic control network 41 includes microstrip lines T8, T9, T10 and T14, and modules TS1 and TS2. The microstrip line T8 is connected to the drain of the transistor 30. The microstrip line T8 is connected in series with the microstrip lines T9, T10 and T14 in sequence. The module TS1 includes a microstrip line T11. One end of the microstrip line T11 is connected between the microstrip lines T9 and T10, and the other end of the microstrip line T11 is open. The microstrip line T14 is connected to the module TS2 and the fundamental matching circuit 42. The module TS2 includes microstrip lines T15, T16 and T17 connected in series. Among them, the typical parameters of the microstrip line T9 and the microstrip line T10 are the same, and the two form a T-shaped line with the microstrip line T11.

[0042] The drain bias circuit 22 includes microstrip lines T12, T13 and a decoupling capacitor Cd, wherein one end of the microstrip line T13 is connected to the microstrip lines T10 and T14 in the harmonic control network 41, and is connected in parallel to the harmonic control network 41, and the other end of the microstrip line T13 is connected to one end of the microstrip line T12, and the other end of the microstrip line T12 is connected to the decoupling capacitor Cd. The bias voltage of the drain bias circuit 22 is 28V.

[0043] The fundamental wave matching circuit 42 includes microstrip lines T18, T19, T20 and a DC blocking capacitor C2, wherein one end of the microstrip line T18 is connected to the harmonic control network 41, and the other end is connected to one end of the microstrip line T19; the other end of the microstrip line T19 is connected to one end of the DC blocking capacitor C2; the other end of the DC blocking capacitor C2 is connected to one end of the microstrip line T20, and the other end of the microstrip line T20 is connected to the load impedance.

[0044] A design method of a high-efficiency dual-band power amplifier based on a low-pass matching network of the present invention adopts the above-mentioned high-efficiency dual-band power amplifier based on a low-pass matching network, and comprises the following steps:

[0045] S10, in the Advanced Design System (ADS), the transistor 30 is source-pulled and load-pulled at the low frequency band f1 and the high frequency band f2, and iterated three times, and the midpoint of the line connecting the maximum efficiency point and the maximum power point is selected as the load impedance value Z to be matched later. Dopt1,2 and source impedance Z Sopt1,2 ;

[0046] S20, according to the above optimal source impedance value Z Sopt1,2 , using a stepped impedance resonant network to complete the design of the input matching network 10;

[0047] S30, determining the parameters of the two parallel modules TS1 and TS2 of the harmonic control network 41 and the drain bias circuit 22 according to the harmonic range of the selected frequency, wherein the module TS1 includes a microstrip line T11, and the module TS2 includes serially connected microstrip lines T15, T16 and T17, wherein the electrical parameters of the microstrip lines T15 and T17 are the same, and the electrical length of the two is θ S2 , the electrical length of microstrip line T16 is 2θ S2 , module TS2 generates transmission zeros within the harmonic range to achieve harmonic suppression;

[0048] See also Figure 3 , TB includes microstrip lines T12 and T13 connected in series. TB is a low-frequency quarter-wavelength line to achieve drain bias and generate transmission zero TZ0. Module TS2 is used to generate transmission zeros TZ1 and TZ3 and transmission pole RZ. According to the harmonic range of the selected frequency band, the frequency of the transmission zero TZ1 is set to 2f2. At the same time, according to formulas (1)-(3), θ can be obtained S2 Value

[0049]

[0050]

[0051]

[0052] in, R Z =Z S1 / Z S2 , Z S1 and Z S2 are the impedance values ​​of microstrip lines T15 and T16 respectively, is the frequency f of the transmission zero point tz The electrical length at is the frequency f of the transmission pole rz TS1 is used to generate another transmission zero point TZ2, whose electrical length is close to the transmission pole f rz So far, the design of the parallel transmission line part for suppressing harmonics has been completed, and the next step is to achieve dual-frequency matching.

[0053] After obtaining the load-pull results, the eighth microstrip line is used to convert the complex impedance Z at the two frequencies into Dopt1,2 Converted into conjugate impedance value R1±jX, its parameters can be determined by calculating formulas (4) and (5);

[0054]

[0055]

[0056] Where Z Dopt,1 =R a +jX a , Z Dopt,2 =R b +jX b , R a , R b and X a , X b are the real and imaginary parts of the optimal impedance values ​​at two frequencies obtained by load pulling, β1 and β2 are the propagation coefficients at two frequencies, and n is an arbitrary integer.

[0057] Then, the conjugate impedance is converted into real impedance R2 by using microstrip lines T9, T10 and T11 to form a T-shaped line. The electrical parameters of microstrip lines T9 and T10 are exactly the same. Microstrip line T11 also plays the role of generating the transmission zero point TZ2, and its electrical length is approximately the same as the transmission pole f. rz The microstrip line T14 is responsible for connecting the open circuit point generated by the module TB of the drain bias circuit 22 to the transmission pole of the module TS2, and its electrical length is the transmission pole frequency f RZ The quarter-wavelength line below;

[0058] S40, after determining the harmonic control network 41, the fundamental impedance matching is completed using the microstrip lines T18 and T19, that is, the real impedance value after the harmonic transformation is transformed to 50 ohms, and its parameters can be determined using formulas (4)-(6):

[0059]

[0060]

[0061]

[0062] Among them, R f =f2 / f1, Z in is the real impedance value after harmonic transformation, Z5, Z6 and θ5, θ6 are the impedance value and electrical length of microstrip lines T18 and T19 respectively, Z L The load is 50 ohms.

[0063] S50, simulate and fine-tune the overall circuit.

[0064] The module TS2 in the above S30 is used to generate two transmission zeros to suppress harmonics. It is composed of microstrip lines T15, T16 and T17, wherein the microstrip lines T15 and T17 have the same electrical parameters and their electrical length is θ S2 , the electrical length of microstrip line T16 is 2θ S2 By performing open circuit and short circuit operations and calculating the corresponding Y in,TS2 =0 and Yin,TS2 =∞, we can get the transmission zero point f TZ With the pole f RZ , their corresponding electrical length θ S2 It can be calculated by equations (1)-(3). From (1) and (2), we can see that the position of the transmission zero and pole is mainly determined by R Z Decide, when R Z When R is small, the transmission zeros can be separated by a larger interval and the frequency of the transmission poles is higher, so that a larger transmission stopband can be obtained. Z When R is larger, better roll-off characteristics can be obtained to filter out harmonic components. Z Taking all factors into consideration, R Z Set to 1.6, transmission zeros are generated at 4.8GHz and 14GHz, and transmission poles are generated at 10GHz. After module TS2 is determined, a wider stopband cannot be formed due to the presence of a transmission pole at 10GHz, so it is necessary to add another transmission zero between the two transmission zeros. At this time, module TS1 can be used to add another transmission zero. Considering that there is not much room for efficiency improvement after controlling the third harmonic in actual circuit design, the designed module TS1 generates a transmission zero at 8GHz, so that a larger stopband can be generated within the third harmonic range of the two frequencies. At this point, modules TS1 and TS2 used to generate transmission zeros to achieve low-pass filtering and harmonic suppression have been determined.

[0065] The next step is to realize the dual-frequency matching function. Microstrip line T8 has parasitic compensation and impedance transformation functions, that is, matching the optimal impedance values ​​at two frequencies obtained by load pulling to a pair of conjugate impedances. The specific parameters are calculated based on the values ​​obtained by load pulling and equations (4)-(5). Microstrip lines T9, T10 and T11 together constitute another T-shaped line, which is used to transform the conjugate complex impedance obtained after the transformation of microstrip line T8 to the same real impedance. However, it should be noted that microstrip line T11 is involved in generating the transmission zero point, so its value is fixed. In actual design, only the values ​​of microstrip lines T9 and T10 are required, where the electrical parameters of microstrip lines T9 and T10 are completely consistent. Microstrip line T14 is responsible for connecting the open point generated by module TB of the drain bias circuit 22 to the transmission pole of module TS2. Its electrical length is the transmission pole frequency f RZ The quarter-wavelength line below.

[0066] Microstrip lines T18 and T19 are the fundamental wave matching circuit 42 in this design. It is necessary to match the 50 ohms at the load end to the fundamental wave impedance value after the impedance transformation of the harmonic control network 41. After determining the specific parameters of the above harmonic control network 41, the values ​​of microstrip lines T18 and T19 can be calculated using formulas (6)-(8), and the overall S parameters of the output matching part circuit are as follows: Figure 4 The S parameter simulation results of the overall circuit are shown in Figure 5 .

[0067] According to the power amplifier designed as described above, the circuit simulation is carried out through ADS, and the results are shown in Figure 6 , it can achieve high-efficiency output at frequencies of 1.6 and 2.4 GHz, with a bandwidth of more than 100 MHz and a PAE of more than 69%.

[0068] No matter how detailed the above description is, there are many ways to implement the present invention, and what is described in the specification are only some specific implementation examples of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

[0069] The above detailed description of the embodiments of the present invention is not intended to be exhaustive or to limit the present invention to the above explicit forms. While the above specific embodiments and embodiments of the present invention are described for illustrative purposes, those skilled in the art will recognize that various equivalent modifications may be made within the scope of the present invention.

[0070] While the above description describes specific embodiments of the present invention and describes the expected best mode, no matter how detailed the description appears above, the present invention can also be implemented in many ways. The details of the above circuit structure and its control method can be varied considerably in its implementation details, but it is still included in the present invention disclosed herein.

[0071] As mentioned above, it should be noted that the specific terms used in describing certain features or schemes of the present invention should not be used to indicate that the term is redefined here to limit certain specific features, characteristics or schemes of the present invention associated with the term. In general, the terms used in the appended claims should not be interpreted as limiting the present invention to the specific embodiments disclosed in the specification unless the above detailed description section explicitly defines these terms. Therefore, the actual scope of the present invention includes not only the disclosed embodiments, but also all equivalent schemes for implementing or performing the present invention under the claims.

[0072] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A design method for a high-efficiency dual-band power amplifier based on a low-pass matching network, characterized in that: The following steps are involved: S10, for transistors in the low frequency band With high frequency The source pull and load pull are performed at the point, and iterated three times. At the same time, the midpoint of the line connecting the maximum efficiency point and the maximum power point is selected as the load impedance value Z to be matched later. Dopt1,2 and source impedance Z Sopt1,2 ; S20, according to the source impedance value Z Sopt1,2 , using the stepped impedance resonant network to complete the design of the input matching network; S30, determining the parameters of two parallel modules TS1 and TS2 and the drain bias circuit of the harmonic control network according to the harmonic range of the selected frequency, wherein module TS1 includes a microstrip line T11, and module TS2 includes serially connected microstrip lines T15, T16 and T17, wherein the electrical parameters of the microstrip lines T15 and T17 are the same, and the electrical lengths of the two are θ S2 , the electrical length of microstrip line T16 is 2 θ S2 , module TS2 generates transmission zeros within the harmonic range to achieve harmonic suppression; S40, after determining the harmonic control network, use microstrip lines T18 and T19 to complete fundamental impedance matching, that is, transform the real impedance value after harmonic transformation to 50 ohms; S50, simulate and fine-tune the overall circuit.

2. A high-efficiency dual-band power amplifier based on a low-pass matching network, implemented by the design method according to claim 1, characterized in that: It includes an input matching network, a gate bias circuit, a transistor, a drain bias circuit, a harmonic control network and a fundamental matching circuit, wherein: The input end of the input matching network serves as a power input end, and the output end thereof is connected to the gate of the transistor; The gate bias circuit is connected in parallel to the input matching network, and the end is connected in parallel to the ground through a decoupling capacitor Cg; The transistor drain is connected to the input end of the harmonic control network, the harmonic control network is connected to the fundamental matching circuit, the output end of the fundamental matching circuit serves as the power output end, the drain bias circuit is connected in parallel to the harmonic control network, and the end is connected in parallel to the ground through a decoupling capacitor Cd; The input matching network includes microstrip lines T1, T2, T3, T4, T6, T7 and a DC blocking capacitor C1; one end of the microstrip line T1 is connected to the input end, and the other end of the microstrip line T1 is connected to one end of the DC blocking capacitor C1; the other end of the DC blocking capacitor C1 is connected to one end of the microstrip line T2, and the microstrip line T2 is connected in series with the microstrip lines T3, T4, T6 and T7 in sequence; the microstrip line T7 is connected to the gate end of the transistor; The harmonic control network includes microstrip lines T8, T9, T10, and T14, module TS1 and module TS2, microstrip line T8 is connected to the drain of the transistor, microstrip line T8 is connected in series with microstrip lines T9, T10, and T14 in sequence, module TS1 includes microstrip line T11, one end of microstrip line T11 is connected between microstrip lines T9 and T10, and the other end of microstrip line T11 is open; microstrip line T14 is connected to module TS2 and a fundamental wave matching circuit; module TS2 includes microstrip lines T15, T16, and T17 connected in series.

3. The high-efficiency dual-band power amplifier based on a low-pass matching network according to claim 2, characterized in that: The gate bias circuit includes a microstrip line TL5 and a decoupling capacitor Cg, wherein one end of the microstrip line TL5 is connected in parallel to the connection between the microstrip lines T4 and T6, the other end of the microstrip line TL5 is connected to one end of the decoupling capacitor Cg, and the other end of the decoupling capacitor Cg is grounded.

4. The high-efficiency dual-band power amplifier based on a low-pass matching network according to claim 3, characterized in that: The bias voltage of the gate bias circuit is -2.8V.

5. The high-efficiency dual-band power amplifier based on a low-pass matching network according to claim 2, characterized in that: The microstrip line T9 and the microstrip line T10 have the same typical parameters, and the microstrip line T9 and the microstrip line T10 form a T-shaped line.

6. The high-efficiency dual-band power amplifier based on a low-pass matching network according to claim 2, characterized in that: The drain bias circuit includes microstrip lines T12, T13 and a decoupling capacitor Cd, wherein one end of the microstrip line T13 is connected to the microstrip lines T10 and T14 in the harmonic control network and is connected in parallel in the harmonic control network, the other end of the microstrip line T13 is connected to one end of the microstrip line T12, and the other end of the microstrip line T12 is connected to the decoupling capacitor Cd.

7. The high-efficiency dual-band power amplifier based on a low-pass matching network according to claim 6, characterized in that: The bias voltage of the drain bias circuit is 28V.

8. The high-efficiency dual-band power amplifier based on a low-pass matching network according to claim 2, characterized in that: The fundamental wave matching circuit includes microstrip lines T18, T19, T20 and a DC blocking capacitor C2, wherein one end of the microstrip line T18 is connected to the harmonic control network, and the other end is connected to one end of the microstrip line T19; the other end of the microstrip line T19 is connected to one end of the DC blocking capacitor C2; the other end of the DC blocking capacitor C2 is connected to one end of the microstrip line T20, and the other end of the microstrip line T20 is connected to the load impedance.

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