Three-dimensional ferroelectric memory device including backside gate electrode and method of manufacturing the same

Abstract

The present invention discloses a ferroelectric memory device, the ferroelectric memory device comprising: an alternating stack of insulator layers and conductive layers, the alternating stack being positioned above the top surface of a substrate; a memory stack structure, the memory stack structure vertically extending through the alternating stack and comprising a ferroelectric material layer, a front gate dielectric contacting the ferroelectric material layer, and a vertical semiconductor channel contacting the front gate dielectric; a back gate dielectric, the back gate dielectric contacting the vertical semiconductor channel; and a back gate electrode, the back gate electrode contacting the back gate dielectric. The portion of the ferroelectric material layer adjacent to the conductive material layer can be programmed with a polarization state to store data.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. non-provisional patent application serial number 16 / 249,300, filed on January 16, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to the field of semiconductor devices, and in particular, to a three-dimensional ferroelectric memory device including a backside gate electrode and a method for manufacturing the same. Background Art

[0004] A ferroelectric memory device refers to a memory device in which information is stored in the ferroelectric state of a ferroelectric material. The ferroelectric state can affect the conductivity of adjacent material portions through the influence of charge accumulated at the interface with the adjacent material portion. The different conductivity states of adjacent material portions can be used to encode data in a non-volatile manner. Summary of the invention

[0005] According to one aspect of the present disclosure, a three-dimensional memory device is provided, comprising: an alternating stack of insulating strips and conductive strips, the alternating stack being located above a substrate and being laterally spaced apart from each other by line grooves, wherein the line grooves extend laterally along a first horizontal direction and are spaced apart along a second horizontal direction; and a line groove filling structure, the line groove filling structure being located in the line grooves, wherein each of the line groove filling structures comprises a corresponding group of memory stacking structures, a back gate dielectric contacting each memory stacking structure within the corresponding group of the memory stacking structures, and a back gate electrode contacting the back gate dielectric, wherein each memory stacking structure comprises a ferroelectric material layer, a front gate dielectric contacting the ferroelectric material layer, and a vertical semiconductor channel contacting the front gate dielectric and the back gate dielectric.

[0006] According to another aspect of the present disclosure, a three-dimensional memory device is provided, comprising: an alternating stack of insulator layers and conductive layers, the alternating stack being positioned above a top surface of a substrate; a memory stack structure extending vertically through the alternating stack and comprising a ferroelectric material layer, a front gate dielectric contacting the ferroelectric material layer, and a vertical semiconductor channel contacting the front gate dielectric; a back gate dielectric contacting the vertical semiconductor channel; and a back gate electrode contacting the back gate dielectric.

[0007] According to another aspect of the present disclosure, a method for forming a three-dimensional memory device is provided, the method comprising: forming a vertical alternating sequence of insulating layers and spacer material layers above a substrate; dividing the vertical alternating sequence into an alternating stack of insulating strips and spacer material strips and a line trench filling structure by forming line trenches extending laterally through the vertical alternating sequence along a first horizontal direction; forming a memory stack structure in the line trenches, wherein each memory stack structure comprises a ferroelectric material layer, a front gate dielectric contacting the ferroelectric material layer, and a vertical semiconductor channel contacting the front gate dielectric; and forming a back gate dielectric and a back gate electrode in each of the line trenches above a corresponding subset of the vertical semiconductor channels.

[0008] According to another aspect of the present disclosure, a method for manufacturing a three-dimensional memory device is provided, the method comprising: forming an alternating stack of insulating layers and spacer material layers above a substrate; forming a memory opening extending vertically through the alternating stack; and sequentially forming a ferroelectric material layer, a front gate dielectric contacting the ferroelectric material layer, a vertical semiconductor channel, a back gate dielectric, and a back gate electrode within the memory opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A is a schematic vertical cross-sectional view of a first exemplary structure after forming at least one peripheral device, an insulating spacer layer, a buried conductive layer, and an in-process source level layer according to the first embodiment of the present disclosure.

[0010] Figure 1B yes Figure 1A A vertical cross-sectional view of a stack of insulating spacer layers, buried conductive layers, and source level layers in a first exemplary structure of FIG.

[0011] Figure 2 is a schematic vertical cross-sectional view of a first exemplary structure after forming a vertically alternating sequence of insulating layers and spacer material layers according to the first embodiment of the present disclosure.

[0012] Figure 3 is a schematic vertical cross-sectional view of a first exemplary structure after forming a stepped terrace and a backward stepped dielectric material portion according to the first embodiment of the present disclosure.

[0013] Figure 4A is a schematic vertical cross-sectional view of a first exemplary structure after forming a linear trench according to the first embodiment of the present disclosure.

[0014] Figure 4B yes Figure 4A A top view of the first exemplary structure. The vertical plane A-A' is Figure 4A The plane of the section.

[0015] Figure 5A yes Figure 4A and Figure 4B A vertical cross-sectional view of a line trench in a first exemplary structure.

[0016] Figure 5B It is along Figure 5A Horizontal section view of plane B-B'.

[0017] Fig. 6A is a vertical cross-sectional view of a linear trench after forming a continuous ferroelectric material layer, a continuous front-side gate dielectric layer, and a semiconductor channel material layer according to the first embodiment of the present disclosure.

[0018] Figure 6B It is along Fig. 6A Horizontal section view of plane B-B'.

[0019] Fig. 7A is a vertical cross-sectional view of a line trench after forming a sacrificial line trench filling material layer according to the first embodiment of the present disclosure.

[0020] Figure 7B It is along Fig. 7A Horizontal section view of plane B-B'.

[0021] Fig. 8A is a vertical cross-sectional view of the first exemplary structure after forming a patterned photoresist layer according to the first embodiment of the present disclosure.

[0022] Figure 8B It is along Fig. 8A Horizontal cross-sectional view of the first exemplary structure along plane BB'.

[0023] Figure 8C yes Fig. 8A and Figure 8B A top view of a first exemplary structure.

[0024] Fig.9A is a vertical cross-sectional view of the first exemplary structure after anisotropically etching unmasked portions of the sacrificial line trench fill material layer and forming a pillar cavity according to the first embodiment of the present disclosure.

[0025] Fig. 9B It is along Fig.9A Horizontal cross-sectional view of the first exemplary structure along plane BB'.

[0026] Fig. 9C yes Fig.9A and Fig. 9B A top view of a first exemplary structure.

[0027] Fig. 10Ais a vertical cross-sectional view of a region of the first exemplary structure after removal of the patterned photoresist layer according to the first embodiment of the present disclosure.

[0028] Fig. 10B It is along Fig. 10A Horizontal cross-sectional view of a region of the first exemplary structure in plane BB'.

[0029] Fig.11A is a vertical cross-sectional view of a region of the first exemplary structure after removing portions of the semiconductor channel material layer, the continuous front side gate dielectric layer, and the continuous ferroelectric material layer surrounding each vertical cavity according to the first embodiment of the present disclosure.

[0030] Fig. 11B It is along Fig.11A Horizontal cross-sectional view of a region of the first exemplary structure in plane BB'.

[0031] Fig. 12A is a vertical cross-sectional view of a region of the first exemplary structure after forming a line cavity by removing remaining portions of the sacrificial line trench fill material layer according to the first embodiment of the present disclosure.

[0032] Fig. 12B It is along Fig. 12A Horizontal cross-sectional view of a region of the first exemplary structure in plane BB'.

[0033] Fig.13A is a vertical cross-sectional view of the first exemplary structure after forming a backside gate dielectric layer, a backside gate electrode, and laterally undulating dielectric rails within each line cavity according to the first embodiment of the present disclosure.

[0034] Fig. 13B yes Fig.13A A top view of the first exemplary structure. The vertical plane A-A' is Fig.13A The plane of the section.

[0035] Fig. 13C yes Fig.13A A vertical cross-sectional view of a region of a first exemplary structure.

[0036] Fig.13D It is along Fig. 13C The horizontal section of plane D-D'. The vertical plane C-C' is Fig. 13C The plane of the section.

[0037] Fig.14A is a vertical cross-sectional view of the first exemplary structure after forming a backside via cavity according to the first embodiment of the present disclosure.

[0038] Fig. 14B yes Fig.14AA top view of the first exemplary structure. The vertical plane A-A' is Fig.14A The plane of the section.

[0039] Fig. 14C is along Fig. 14B A vertical cross-sectional view of a region of the first exemplary structure along a vertical plane CC'.

[0040] FIG. 15A to FIG. 15C are sequential vertical cross-sectional views of regions of a first exemplary structure during replacement of a source level material layer with a source level material layer according to the first embodiment of the present disclosure.

[0041] Fig.16 is a vertical cross-sectional view of a region of a first exemplary structure after forming a backside recess according to the first embodiment of the present disclosure.

[0042] Fig.17 is a vertical cross-sectional view of a region of a first exemplary structure after forming conductive strips according to an embodiment of the present disclosure.

[0043] Fig.18 is a vertical cross-sectional view of a region of the first exemplary structure after removal of deposited metallic material from within a backside via cavity according to the first embodiment of the present disclosure.

[0044] Fig.19A is a vertical cross-sectional view of the first exemplary structure after forming a dielectric post structure in a backside via cavity according to the first embodiment of the present disclosure.

[0045] Fig.19B yes Fig.19A A top view of the first exemplary structure. The vertical plane A-A' is Fig.19A The plane of the section.

[0046] Fig.19C is along Fig.19B A vertical cross-sectional view of a region of the first exemplary structure along a vertical plane CC'.

[0047] Fig. 20 is a vertical cross-sectional view of the first exemplary structure after forming a drain region according to the first embodiment of the present disclosure.

[0048] Fig.21A is a schematic vertical cross-sectional view of the first exemplary structure after forming a word line contact via structure according to the first embodiment of the present disclosure.

[0049] Fig. 21B yes Fig.21A A top view of the first exemplary structure. The vertical plane A-A' is Fig.21A The plane of the section.

[0050] Fig. 22 is a vertical cross-sectional view of a second exemplary structure after forming a stack including alternating multiple material layers according to the second embodiment of the present disclosure.

[0051] Fig.23 is a vertical cross-sectional view of a second exemplary structure after forming a memory opening through a stack according to the second embodiment of the present disclosure.

[0052] Fig.24 is a vertical cross-sectional view of the second exemplary structure after forming a ferroelectric material layer and a front side gate dielectric and a vertical semiconductor channel within each memory opening according to the second embodiment of the present disclosure.

[0053] Fig.25 is a vertical cross-sectional view of a second exemplary structure after forming a backside gate dielectric according to the second embodiment of the present disclosure.

[0054] Fig.26 is a vertical cross-sectional view of a second exemplary structure after forming a backside gate electrode and a dielectric capping layer according to the second embodiment of the present disclosure.

[0055] Fig. 27 is a vertical cross-sectional view of a second exemplary structure after forming a backside cavity according to the second embodiment of the present disclosure.

[0056] Fig.28 is a vertical cross-sectional view of a second exemplary structure after replacing the sacrificial material layer with a conductive layer according to the second embodiment of the present disclosure.

[0057] Fig.29 is a vertical cross-sectional view of a second exemplary structure after forming a backside via spacer according to the second embodiment of the present disclosure.

[0058] Fig.30 is a vertical cross-sectional view of a second exemplary structure after forming a source level cavity according to the second embodiment of the present disclosure.

[0059] Fig.31 is a vertical cross-sectional view of a second exemplary structure after forming a source region according to the second embodiment of the present disclosure.

[0060] Fig.32A is a vertical cross-sectional view of a second exemplary structure after forming a source electrode and a backside contact via structure according to the second embodiment of the present disclosure.

[0061] Fig.32B yes Fig.32A A horizontal cross-sectional view of the second exemplary structure along plane BB'. The vertical plane AA' corresponds to Fig.32AThe vertical plane of the vertical section view.

[0062] Fig.33A is a vertical cross-sectional view of a second exemplary structure after forming a contact via structure and a conductive line structure according to the second embodiment of the present disclosure.

[0063] Fig.33B is along the perpendicular Fig.33A The vertical section plane of the vertical plane Fig.33A Another vertical cross-sectional view of a second exemplary structure of FIG.

[0064] Fig.34 is a vertical cross-sectional view of an alternative embodiment of a second exemplary structure according to the second embodiment of the present disclosure.

[0065] Fig.35 Definitions of various parameters used during operation of the ferroelectric memory device of various embodiments of the present disclosure are shown.

[0066] Fig.36A Shown is the configuration of an inversion layer within a vertical semiconductor channel during sensing of a selected ferroelectric memory cell in an “erased” state, according to an embodiment of the present disclosure.

[0067] Fig.36B Shown is the configuration of an inversion layer within a vertical semiconductor channel during sensing of a selected ferroelectric memory cell in a “programmed” state, in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0068] The present disclosure relates to a three-dimensional ferroelectric memory device including a backside gate electrode, a method for manufacturing the same and an operating method thereof, and various aspects thereof are described below. Embodiments of the present disclosure may be used to form various structures, including a multi-level metal interconnect structure, and non-limiting examples thereof include semiconductor devices, such as a three-dimensional monomer memory array device including a plurality of NAND memory strings. The accompanying drawings are not drawn to scale. Multiple instances of an element may be repeated in the case of a single instance of an element shown therein, unless explicitly described or otherwise clearly indicated that there is no repetition of the element. Serial numbers such as "first", "second" and "third" are used only to identify similar elements, and different serial numbers may be used throughout the specification and claims of the present disclosure. As used herein, a first element positioned "on" a second element may be positioned on the outer side of a surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element.

[0069] A monomeric three-dimensional memory array is a memory array in which multiple memory levels are formed above a single substrate (such as a semiconductor wafer) without an intermediate substrate. The term "monomeric" refers to the layers of each level of the array being deposited directly on the layers of each lower level of the array. In contrast, a two-dimensional array can be formed separately and then packaged together to form a non-monomeric memory device. For example, a non-monomeric stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels, as described in U.S. Patent No. 5,915,167 entitled "Three Dimensional Structure Memory". The substrate may be thinned or removed from the memory level before bonding, but since the memory level is initially formed above a separate substrate, such memory is not a true monomeric three-dimensional memory array. The three-dimensional memory devices of various embodiments include monomeric three-dimensional NAND string memory devices and can be manufactured using the methods of various embodiments described herein.

[0070] As used herein, "ferroelectric material" refers to any material that exhibits a spontaneous electric polarization that can be reversed by the application of an external electric field.

[0071] refer to Figure 1A and Figure 1B , shows a first exemplary structure according to a first embodiment of the present disclosure, which can be used, for example, to manufacture a ferroelectric memory device structure including a vertical NAND string. The first exemplary structure includes a substrate 8, such as a silicon wafer or silicon on an insulator substrate. The substrate 8 may include a substrate semiconductor layer 9 in an upper portion thereof. The substrate semiconductor layer 9 may be an upper portion of the silicon wafer 8, a doped well in an upper portion of the silicon wafer 8, or a semiconductor (e.g., silicon) layer located above the top surface of the substrate. The substrate 8 may have a main surface 7, which may be, for example, the topmost surface of the substrate semiconductor layer 9. The main surface 7 may be a semiconductor surface. In one embodiment, the main surface 7 may be a single crystal semiconductor surface, such as a single crystal silicon surface.

[0072] As used herein, "semiconductor material" refers to a semiconductor material having a -6 S / cm to 1.0×10 5 S / cm. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0×10 -6 S / cm to 1.0×10 5 S / cm, and can produce materials with electrical conductivity in the range of 1.0 S / cm to 1.0×10 5S / cm. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material having an electrical conductivity greater than 1.0×10 5 S / cm. As used herein, "insulator material" or "dielectric material" refers to a material having an electrical conductivity of less than 1.0×10 -6 As used herein, "heavily doped semiconductor material" refers to a material doped with electrical dopants at a sufficiently high atomic concentration to become a conductive material when formed into a crystalline material or when converted to a crystalline material by an annealing process (e.g., starting from an initially amorphous state) (i.e., having a conductivity greater than 1.0×10 5 S / cm). A "doped semiconductor material" may be a heavily doped semiconductor material, or may include a semiconductor material that provides a conductivity of 1.0×10 -6 S / cm to 1.0×10 5 S / cm) in the range of 1000 Å / s. A semiconductor material having an electrical dopant (i.e., a p-type dopant and / or an n-type dopant) with a conductivity in the range of 1000 Å / s. An "intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, a semiconductor material can be semiconducting or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, a "metallic material" refers to a conductive material that includes at least one metal element therein. All conductivity measurements are performed under standard conditions.

[0073] At least one semiconductor device 700 of the peripheral circuit may be formed on a portion of the substrate semiconductor layer 9. The at least one semiconductor device may include, for example, a field effect transistor. For example, at least one shallow trench isolation structure 720 may be formed by etching a portion of the substrate semiconductor layer 9 and depositing a dielectric material therein. A gate dielectric layer, at least one gate conductor layer, and a gate cap dielectric layer may be formed over the substrate semiconductor layer 9, and may then be patterned to form at least one gate structure (750, 752, 754, 758), each of which may include a gate dielectric 750, a gate electrode (752, 754), and a gate cap dielectric 758. The gate electrode (752, 754) may include a stack of a first gate electrode portion 752 and a second gate electrode portion 754. At least one gate spacer 756 may be formed around the at least one gate structure (750, 752, 754, 758) by depositing and anisotropically etching a dielectric liner. An active region 730 may be formed in the upper portion of the substrate semiconductor layer 9, for example, by using the at least one gate structure (750, 752, 754, 758) as a mask structure to introduce electrical dopants. Additional masks may be used as needed. The active region 730 may include a source region and a drain region of a field effect transistor. A first dielectric liner 761 and a second dielectric liner 762 may be optionally formed. Each of the first dielectric liner and the second dielectric liner (761, 762) may include a silicon oxide layer, a silicon nitride layer, and / or a dielectric metal oxide layer. As used herein, silicon oxide includes silicon dioxide and non-stoichiometric silicon oxide having more or less than two oxygen atoms for each silicon atom. Silicon dioxide is preferred. In an illustrative example, the first dielectric liner 761 may be a silicon oxide layer, and the second dielectric liner 762 may be a silicon nitride layer. At least one semiconductor device of the peripheral circuit may include a driver circuit of a subsequently formed memory device, which may include at least one NAND device. A dielectric material such as silicon oxide may be deposited over the at least one semiconductor device and may subsequently be planarized to form a planarized dielectric layer 770 . The region including the at least one semiconductor device 700 is referred to herein as a peripheral device region 200 .

[0074] A dielectric material layer 768 may be formed over the substrate semiconductor layer 9. The second dielectric material layer 768 may include a single dielectric material layer or a plurality of dielectric material layers. The dielectric material layer 768 may include any one or more of doped silicate glass, undoped silicate glass, and organic silicate glass. In one embodiment, at least one dielectric material layer 768 may include or be substantially composed of a dielectric material layer having a dielectric constant not exceeding 3.9 of the dielectric constant of undoped silicate glass (silicon oxide).

[0075] Optional layers of metal material and semiconductor material may be deposited above or inside the patterned recesses of the dielectric material layer 768 and patterned by photolithography to provide an optional conductive plate layer 6 and a source level material layer 10' in the process. The optional conductive plate layer 6 (if present) provides a high conductivity conduction path for current flowing into or out of the source level material layer 10' in the process. The optional conductive plate layer 6 includes a conductive material such as a metal, a metal silicide, or a heavily doped semiconductor material. For example, the optional conductive plate layer 6 may include a tungsten or tungsten silicide layer having a thickness in the range of 3nm to 100nm, but smaller and larger thicknesses may also be used. A metal nitride layer (not shown) may be provided on top of the conductive plate layer 6 as a diffusion barrier. The conductive plate layer 6 may be used as a special source line in the completed device. In addition, the conductive plate layer 6 may include an etch stop layer and may include any suitable conductive, semiconductor or insulating layer. The optional conductive plate layer 6 may include a metal compound material such as a conductive metal silicide or nitride (e.g., TiN) and / or a metal (e.g., W). The thickness of the optional conductive plate layer 6 may be in the range of 5 nm to 100 nm, although lesser and greater thicknesses may also be used.

[0076] The source level material layer 10' in the process may include various layers that are subsequently modified to form the source level material layer. The source level material layer includes a source contact layer when formed, which is used as a common source region of the vertical field effect transistor of the three-dimensional memory device. In one embodiment, the source level material layer 10' in the process may include a lower source level material layer 112, a lower sacrificial liner 103, a source level sacrificial layer 104, a higher sacrificial liner 105, a higher source level material layer 116, a source level insulating layer 117, and an optional source selection level conductive layer 118 from bottom to top.

[0077] The lower source level material layer 112 and the higher source level material layer 116 may include doped semiconductor materials, such as doped polysilicon or doped amorphous silicon. The conductivity type of the lower source level material layer 112 and the higher source level material layer 116 may be opposite to the conductivity of the vertical semiconductor channel to be formed subsequently. For example, if the vertical semiconductor channel to be formed subsequently has a doping of a first conductivity type, the lower source level material layer 112 and the higher source level material layer 116 have a doping of a second conductivity type opposite to the first conductivity type. The thickness of each of the lower source level material layer 112 and the higher source level material layer 116 may be in the range of 10nm to 300nm, such as 20nm to 150nm, but smaller and larger thicknesses may also be used.

[0078] The source level sacrificial layer 104 comprises a sacrificial material that can be selectively removed for the lower sacrificial pad 103 and the upper sacrificial pad 105. In one embodiment, the source level sacrificial layer 104 can comprise a semiconductor material, such as undoped amorphous silicon, polycrystalline silicon, or a silicon-germanium alloy with an atomic concentration of germanium greater than 20%. The thickness of the source level sacrificial layer 104 can be in the range of 30nm to 400nm, such as 60nm to 200nm, but smaller and larger thicknesses can also be used.

[0079] The lower sacrificial liner 103 and the upper sacrificial liner 105 include materials that can be used as etch stop materials during the removal of the source level sacrificial layer 104. For example, the lower sacrificial liner 103 and the upper sacrificial liner 105 can include silicon oxide, silicon nitride, and / or dielectric metal oxide. In one embodiment, each of the lower sacrificial liner 103 and the upper sacrificial liner 105 can include a silicon oxide layer having a thickness in the range of 2nm to 30nm, although smaller and larger thicknesses can also be used.

[0080] The source level insulating layer 117 may include a dielectric material, such as silicon oxide. The thickness of the source level insulating layer 117 may be in the range of 20 nm to 400 nm, such as 40 nm to 200 nm, but smaller and larger thicknesses may also be used. The optional source select level conductive layer 118 may include a conductive material that may be used as a source select level gate electrode. For example, the optional source select level conductive layer 118 may include a heavily doped semiconductor material, such as heavily doped polysilicon or doped amorphous silicon, which may subsequently be converted into doped polysilicon by an annealing process. The thickness of the optional source level conductive layer 118 may be in the range of 30 nm to 200 nm, such as 60 nm to 100 nm, but smaller and larger thicknesses may also be used.

[0081] The source level material layer 10' can be formed directly above a subset of semiconductor devices on a semiconductor substrate 8 (e.g., a silicon wafer) during the process. As used herein, a first element is positioned "directly above" a second element if the first element is positioned above a horizontal plane that includes the topmost surface of the second element and an area of ​​the first element and an area of ​​the second element have an area overlap in a plan view (i.e., along a vertical plane or direction perpendicular to the top surface 7 of the substrate 8).

[0082] The optional conductive plate layer 6 and the in-process source level material layer 10' may be patterned to provide openings in areas where through memory level contact via structures and through dielectric contact via structures are subsequently to be formed. Patterned portions of the stack of conductive plate layer 6 and in-process source level material layer 10' are present in each memory array region 100 where a three-dimensional memory stacked structure will subsequently be formed. Thus, the areas where the in-process source level material layer 10' is present include the memory array region 100 where memory devices will subsequently be formed, and the contact region 300 where the stepped surface and contact via structures for contacting various conductive strips will subsequently be formed.

[0083] refer to Figure 2 , a vertical alternating sequence of a first material layer (which may be an insulating layer 32) and a second material layer (which may be a sacrificial material layer 42) is formed above the top surface of the substrate 8. As used herein, "material layer" refers to a layer including a material throughout its entirety. As used herein, a "vertical alternating sequence" or "vertical alternating multiple" first and second elements of a first element and a second element refers to a structure in which an instance of the first element and an instance of the second element are alternating in a vertical direction. Each instance of a first element that is not an end element of an alternating multiple element is adjacent to two instances of the second element on both sides, and each instance of a second element that is not an end element of an alternating multiple element is adjacent to two instances of the first element on both ends. The first element may have the same thickness therebetween, or may have different thicknesses. The second element may have the same thickness therebetween, or may have different thicknesses. The alternating multiple first and second material layers may start with an instance of the first material layer or an instance of the second material layer, and may end with an instance of the first material layer or an instance of the second material layer. In one embodiment, an instance of the first element and an instance of the second element may form a unit that is periodically repeated within an alternating multiple element.

[0084] Each first material layer includes a first material, and each second material layer includes a second material different from the first material. In one embodiment, each first material layer may be an insulating layer 32, and each second material layer may be a sacrificial material layer. In this case, the stack may include alternating multiple insulating layers 32 and sacrificial material layers 42, and constitute a prototype stack including alternating layers of insulating layers 32 and sacrificial material layers 42. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component thereof.

[0085] The alternating plurality of stacks are referred to herein as alternating sequences (32, 42). In one embodiment, the alternating sequence (32, 42) may include an insulating layer 32 composed of a first material and a sacrificial material layer 42 composed of a second material, wherein the second material is different from the material of the insulating layer 32. The first material of the insulating layer 32 may be at least one insulating material. Therefore, each insulating layer 32 may be an insulating material layer. Insulating materials that can be used for the insulating layer 32 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, etc.) and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the insulating layer 32 may be silicon oxide.

[0086] The second material of sacrificial material layer 42 is a sacrificial material that is selectively removable with respect to the first material of insulating layer 32. As used herein, removal of a first material is "selective with respect to" a second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0087] The sacrificial material layer 42 may include an insulating material, a semiconductor material, or a conductive material. The second material of the sacrificial material layer 42 may then be replaced with a conductive electrode, which may be used, for example, as a control gate electrode of a vertical NAND device. Non-limiting examples of the second material include silicon nitride, an amorphous semiconductor material (such as amorphous silicon), and a polycrystalline semiconductor material (such as polycrystalline silicon). In one embodiment, the sacrificial material layer 42 may be a spacer material layer including silicon nitride or a semiconductor material including at least one of silicon and germanium.

[0088] In one embodiment, insulating layer 32 may include silicon oxide, and the sacrificial material layer may include a silicon nitride sacrificial material layer. The first material of insulating layer 32 may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for insulating layer 32, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of sacrificial material layer 42 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0089] The sacrificial material layer 42 may be appropriately patterned so that a conductive material portion subsequently formed by replacing the sacrificial material layer 42 may be used as a conductive electrode, such as a control gate electrode of a subsequently formed single three-dimensional NAND string memory device. The sacrificial material layer 42 may include a portion having a stripe shape extending substantially parallel to the main surface 7 of the substrate.

[0090] The thickness of the insulating layer 32 and the sacrificial material layer 42 can be in the range of 20nm to 50nm, but smaller and larger thicknesses can be used for each insulating layer 32 and each sacrificial material layer 42. The number of repetitions of the pair of insulating layers 32 and sacrificial material layers (e.g., control gate electrodes or sacrificial material layers) 42 can be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions can also be used. The top gate electrode and the bottom gate electrode in the stack can be used as select gate electrodes. In one embodiment, each sacrificial material layer 42 in the alternating sequence (32, 42) can have a uniform thickness that is substantially constant within each corresponding sacrificial material layer 42.

[0091] Although the present disclosure is described using an embodiment in which the spacer material layer is a sacrificial material layer 42 that is subsequently replaced with a conductive strip, embodiments in which the sacrificial material layer is formed as a conductive strip are explicitly contemplated herein. In this case, the step of replacing the spacer material layer with a conductive strip may be omitted.

[0092] An insulating capping layer 70 may be formed over the alternating sequence (32, 42). The insulating capping layer 70 includes a sacrificial material different from the material of the sacrificial material layer 42. In one embodiment, the insulating capping layer 70 may include a silicate glass material, such as undoped silicate glass or doped silicate glass. Examples of doped silicate glass include borosilicate glass, phosphosilicate glass, borophosphosilicate glass, and organosilicate glass. The insulating capping layer 70 may be formed by a chemical vapor deposition process. For example, tetraethyl orthosilicate (TEOS) may be thermally decomposed in the presence or absence of a dopant gas to form a doped silicate glass or an undoped silicate glass. The thickness of the insulating capping layer 70 may be in the range of 50 nm to 300 nm, but smaller and larger thicknesses may also be used.

[0093] refer to Figure 3, the vertically alternating sequence of the insulating layer 32 and the spacer material layer (i.e., the sacrificial material layer 42) can be patterned to form a stepped surface extending continuously from the bottommost layer of the vertically alternating sequence (32, 42) to the topmost layer of the alternating sequence (32, 42) in the contact area 300. A stepped cavity can be formed in the contact area 300 positioned between the memory array area 100 and the peripheral device area 200, the peripheral device area containing at least one semiconductor device for peripheral circuits. The stepped cavity can have various stepped surfaces so that the horizontal cross-sectional shape of the stepped cavity changes stepwise according to the vertical distance from the top surface of the substrate (9, 10). In one embodiment, the stepped cavity can be formed by repeatedly performing a set of processing steps. The set of processing steps can include, for example, a first type of etching process and a second type of etching process, the first type of etching process vertically increasing the cavity depth by one or more steps, the second type of etching process laterally expanding the area to be vertically etched in a subsequent etching process of the first type. As used herein, a "level" of a structure comprising an alternating plurality is defined as the relative position of a pair of first and second material layers within the structure.

[0094] By forming a stepped cavity, a stepped surface is formed at the peripheral portion of the vertical alternating sequence (32, 42). As used herein, "stepped surface" refers to a set of surfaces including at least two horizontal surfaces and at least two vertical surfaces, such that each horizontal surface is adjacent to a first vertical surface extending upward from a first edge of the horizontal surface, and adjacent to a second vertical surface extending downward from a second edge of the horizontal surface. "Stepped cavity" refers to a cavity having a stepped surface.

[0095] The terrace region is formed by patterning the vertical alternating sequence (32, 42). Each sacrificial material layer 42 except the topmost sacrificial material layer 42 in the vertical alternating sequence (32, 42) extends laterally further than any overlying sacrificial material layer 42 in the vertical alternating sequence (32, 42). The terrace region includes a stepped surface of the vertical alternating sequence (32, 42) that extends continuously from the bottommost layer in the vertical alternating sequence (32, 42) to the topmost layer in the vertical alternating sequence (32, 42).

[0096] A backward stepped dielectric material portion 65 (i.e., an insulating filling material portion) may be formed in the stepped cavity by depositing a dielectric material therein. For example, a dielectric material such as silicon oxide may be deposited in the stepped cavity. Excess portions of the deposited dielectric material may be removed from above the top surface of the insulating cap layer 70, for example, by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the backward stepped dielectric material portion 65. As used herein, a "backward stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that increases monotonically according to the vertical distance from the top surface of the substrate on which the element is present. If silicon oxide is used for the backward stepped dielectric material portion 65, the silicon oxide of the backward stepped dielectric material portion 65 may be doped with a dopant or may not be doped with a dopant, such as B, P, and / or F.

[0097] refer to Figure 4A , Figure 4B , Figure 5A and Figure 5B A photolithographic material stack (not shown) including at least a photoresist layer may be formed over the insulating cap layer 70 and the backward stepped dielectric material portion 65, and may be photolithographically patterned to form a linear opening therein. The linear opening extends laterally along a first horizontal direction hd1, and has a uniform width along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The pattern in the photolithographic material stack may be transferred through the insulating cap layer 70 or the backward stepped dielectric material portion 65, and through the vertical alternating sequence (32, 42) by at least one anisotropic etching using the patterned photolithographic material stack as an etching mask. A portion of the vertical alternating sequence (32, 42) below the linear opening in the patterned photolithographic material stack is etched to form a linear groove 149. As used herein, a "linear groove" refers to a groove having a straight extension laterally along a horizontal direction.

[0098] The line grooves 149 extend laterally through the vertical alternating sequence (32, 42) along the first horizontal direction hd1. In one embodiment, the line grooves 149 have a corresponding uniform width that does not change when translated along the first horizontal direction hd1. In one embodiment, the line grooves 149 may always have the same width, and the spacing between pairs of adjacent line grooves 149 may be the same. In this case, the line grooves 149 may constitute a one-dimensional periodic array of line grooves 149, which has a spacing along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The width of the line grooves 149 along the second horizontal direction hd2 may be in the range of 30nm to 500nm, such as 60nm to 250nm, but smaller and larger widths may also be used.

[0099] The line trench 149 extends through each layer of the vertical alternating sequence (32, 42) and the rear stepped dielectric material portion 65. The chemistry of the anisotropic etching process used to etch the material through the vertical alternating sequence (32, 42) can be alternating to optimize the etching of the first material and the second material in the vertical alternating sequence (32, 42). The anisotropic etching can be, for example, a series of reactive ion etching. The sidewalls of the line trench 149 can be substantially vertical, or can be tapered. The patterned photolithographic material stack can then be removed, for example, by ashing.

[0100] The line groove 149 extends laterally through the entire memory array area 100 and may extend laterally into the contact area 300. The line groove 149 may extend laterally through the entire contact area 300 along the first horizontal direction hd1, or may extend laterally only through a portion of the width of the contact area 300 rather than the entire width along the first horizontal direction hd1 of the contact area. The line grooves 149 may be laterally spaced apart from each other along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. In one embodiment, after the top surface of the semiconductor material layer 10 is physically exposed at the bottom of each line groove 149, overetching of the semiconductor material layer 10 may be optionally performed. Overetching may be performed before or after removing the photolithographic material stack. In other words, the recessed surface of the semiconductor material layer 10 may be vertically offset from the non-recessed top surface of the semiconductor material layer 10 by a recessed depth. The recessed depth may be in the range of, for example, 1 nm to 50 nm, but smaller and larger depths may also be used. Overetching is optional and may be omitted. If over-etching is not performed, the bottom surface of the line trench 149 may be coplanar with the topmost surface of the semiconductor material layer 10 .

[0101] Each of the line grooves 149 may include a sidewall (or multiple sidewalls) extending substantially perpendicular to the topmost surface of the substrate. The substrate semiconductor layer 9 and the semiconductor material layer 10 together constitute the substrate (9, 10), which may be a semiconductor substrate. Alternatively, the semiconductor material layer 10 may be omitted, and the line grooves 149 may extend to the top surface of the substrate semiconductor layer 9. In one embodiment, the vertical alternating sequence of the insulating layer 32 and the spacer material layer (such as the sacrificial material layer 42) may be divided by the line grooves 149 into discrete alternating stacks of insulating strips 32 (i.e., divided portions of the insulating layer 32) and spacer material strips (i.e., divided portions of the spacer material layer). Alternatively, the line grooves 149 may not divide the vertical alternating sequence of the insulating layer 32 and the spacer material layer (such as the sacrificial material layer 42) into discrete alternating stacks of insulating strips and spacer material strips. In this case, the insulating layer 32 and the spacer material layer (such as the sacrificial material layer 42) may remain as a continuous material layer with the openings formed by the linear trenches 149 therethrough.

[0102] refer to Fig. 6A and Figure 6B , a continuous ferroelectric material layer 154L, a continuous front side gate dielectric layer 152L, and a semiconductor channel material layer 160L are sequentially formed in the line trench 149 and over the insulating cap layer 70. The continuous ferroelectric material layer 154L may be formed on the sidewalls of the insulating layer 32 and the sacrificial material layer 42. The continuous ferroelectric material layer 154L includes a ferroelectric material.

[0103] In one embodiment, the continuous ferroelectric material layer 154L includes at least one ferroelectric material and / or is essentially composed of at least one ferroelectric material, such as hafnium oxide, barium titanate (BaTiO3; BT), colemanite (Ca2B6O11-5H2O), bismuth titanate (Bi12TiO20, Bi 4Ti3O12 or Bi2Ti2O7), europium barium titanate, ferroelectric polymer, germanium telluride, anhydrous potassium magnesium sulfate (M2M'2(SO4)3, where M is a monovalent metal and M' is a divalent metal), lead tantalate (Pb(ScxTa1-x)03), lead titanate (PbTiO3; PT), lead zirconate titanate (Pb(Zr,Ti)O3; PZT), lithium niobate (LiNbO3; LN), (LaAlO3), polyvinylidene fluoride (CH2CF 2)n, potassium niobate (KNbO3), potassium sodium tartrate (KNaC4H406·4H2O), potassium titanyl phosphate (KO5PTi), sodium bismuth titanate (Na0.5Bi0.5TiO3 or Bi0.5Na0.5TiO3), NH4H2PO4 (ADP), KH2PO4 (KDP), LiTaO3 (LT), (Pb,La)TiO3 (PLT) and (Pb,La)(Zr,Ti)O3 (PLZT). In one embodiment, the continuous ferroelectric material layer 154L includes a ferroelectric dielectric material and / or is essentially composed of a ferroelectric dielectric material.

[0104] The continuous ferroelectric material layer 154L may be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique. The thickness of the continuous ferroelectric material layer 154L may be in the range of 1 nm to 10 nm, such as 2 nm to 5 nm, although smaller and larger thicknesses may also be used.

[0105] The continuous front gate dielectric layer 152L may include a single dielectric material layer, or a stack of multiple dielectric material layers. In one embodiment, the continuous front gate dielectric layer 152L may include a silicon oxide layer. Optionally, the continuous front gate dielectric layer 152L may additionally include a dielectric metal oxide layer, such as an aluminum oxide layer. The thickness of the continuous front gate dielectric layer 152L may be in the range of 1 nm to 10 nm, such as 2 nm to 6 nm, but smaller and larger thicknesses may also be used. The continuous front gate dielectric layer 152L may be formed by a conformal deposition process such as low pressure chemical vapor deposition or atomic layer deposition.

[0106] The semiconductor channel material layer 160L may be deposited on the continuous front side gate dielectric layer 152L. The semiconductor channel material layer 160L includes a semiconductor material, such as at least one element semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 160L includes amorphous silicon or polycrystalline silicon. The semiconductor channel material layer 160L may be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer 160L may be in the range of 2nm to 10nm, but smaller and larger thicknesses may also be used. In one embodiment, the semiconductor channel material layer 160L may have a doping of a first conductivity type, which is a conductivity type identical to the doped conductivity type of the semiconductor material layer 10. In one embodiment, the semiconductor channel material layer 160L may include a semiconductor material including electrical dopants at an atomic concentration in a range of 1.0×10 14 / cm 3 to 1.0×10 18 / cm 3 .

[0107] refer to Fig. 7A and Figure 7B , the sacrificial line trench fill material layer 59L can be formed by filling the remaining volume of the line trench 149 with a sacrificial line trench fill material. The sacrificial line trench fill material includes a material that can be selectively removed with respect to the material of the semiconductor channel material layer 160L. In one embodiment, the sacrificial line trench fill material layer 59L may include a spin-on sacrificial material, such as spin-on carbon (SOC). In one embodiment, the spin-on carbon material may include amorphous carbon in a volatile solvent that is removed after curing.

[0108] refer to FIG. 8A to FIG. 8C, a photoresist layer 67 may be applied over the sacrificial line trench filling material layer 59L and may be photolithographically patterned to form openings in the memory array region 100 and the contact region 300. The pattern of the openings in the memory array region 100 includes a two-dimensional array of discrete openings, each discrete opening corresponding to an area in which a dielectric isolation column will be subsequently formed. In one embodiment, the two-dimensional array of discrete openings may be a periodic two-dimensional array of discrete openings. The openings in the contact region 300 may be elongated along a first horizontal direction hd1 and may extend along the first horizontal direction hd1 along the entire length of the staircase region (i.e., the stepped surface of the vertical alternating sequence (32, 42)). Each opening in the photoresist layer 67 may cover a corresponding area in which the sacrificial line trench filling material layer 59L vertically extends through the vertical alternating sequence (32, 42).

[0109] refer to 9A to 9C , the unmasked portion of the sacrificial line trench fill material layer 59L can be etched under each opening in the photoresist layer 67 by an anisotropic etching process. The anisotropic etching process can use the chemical properties of the sacrificial line trench fill material to selectively etch the material of the semiconductor channel material layer 160L. In one embodiment, a gas mixture for selectively etching amorphous carbon for silicon can be used as an etchant gas during the anisotropic etching process. For example, a combination of carbonyl sulfide (COS) and O2 or other reactive ion etching gases for etching carbon can be used. The array of column cavities 69 is formed in a volume within the memory array area 100, and the sacrificial line trench fill material is removed from the memory array area. Line cavities 69' are formed in a volume within the contact area 300, and the sacrificial line trench fill material is removed from the contact area. Thus, a plurality of vertical cavities ( 69 , 69 ′) extend through the sacrificial line trench fill material layer 59L, which extends continuously over the insulating capping layer 70 within the plurality of cavities ( 69 , 69 ′) therethrough.

[0110] refer to Fig. 10A and Fig. 10B , the patterned photoresist layer 67 may be removed selectively to the semiconductor channel material layer 160L, for example, by dissolving in an organic solvent.

[0111] refer to Fig.11A and Fig. 11B, removing portions of the semiconductor channel material layer 160L, the continuous front side gate dielectric layer 152L, and the continuous ferroelectric material layer 154L from each vertical cavity (69, 69'). In one embodiment, portions of the semiconductor channel material layer 160L, the continuous front side gate dielectric layer 152L, and the continuous ferroelectric material layer 154L can be sequentially etched around each vertical cavity (69, 69') by a series of etching processes. The duration of each etching process can be selected so that the etching distance is in the range of the thickness of each etching material layer to twice the thickness of the etching material layer. The sequence of etching processes may include a first wet etching process for etching the material of the semiconductor channel material layer 160L, a second wet etching process for etching the material of the continuous front side gate dielectric layer 152L, and a third wet etching process for etching the material of the continuous ferroelectric material layer 154L. In an exemplary example, the semiconductor channel material layer 160L may include amorphous silicon or polycrystalline silicon, and the first wet etching process may use hot trimethyl-2-hydroxyethylammonium hydroxide ("hot TMY") or tetramethylammonium hydroxide (TMAH). The continuous front side gate dielectric layer 152L may include aluminum oxide and / or silicon oxide, and the second wet etching process may use a mixture of at least two of ammonium hydroxide, phosphoric acid, methyl hydroxide, bromine, hydrogen peroxide, and deionized water for aluminum oxide and / or dilute hydrofluoric acid for silicon oxide. The chemical properties of the third wet etching process may be selected based on the composition of the continuous ferroelectric material layer 154L.

[0112] refer to Fig. 12A and Fig. 12B, the sacrificial line trench filling material layer 59L can be selectively removed for the semiconductor channel material layer 160L, the continuous front side gate dielectric layer 152L, the continuous ferroelectric material layer 154L and the vertical alternating sequence (32, 42). For example, the sacrificial line trench filling material layer 59L can be removed by ashing or by dissolving in an organic solvent. When the sacrificial line trench filling material layer 59L is removed, a neck cavity 169 is formed from each volume within the line trench 149, from which a portion of the sacrificial line trench filling material layer 59L is removed. Each neck cavity 169 is adjacent to at least one adjacent pillar cavity 69. Lateral undulation cavities (69, 169) are formed within the unfilled volume of the line trench 149. Each lateral undulation cavity (69, 169) has a lateral undulation width and is formed within a corresponding one of the line trenches 149. The volume of the laterally undulating cavities (69, 169) includes all the volume of the pillar cavities 69 from which the sacrificial line trench filling material layer 59L is removed and all the volume within the line trench 149. Each laterally undulating cavity (69, 169) may extend laterally along the first horizontal direction hd1 and may have a periodically undulating width along the second horizontal direction hd2 within the memory array region 100. Each laterally undulating cavity (69, 169) includes a laterally alternating sequence of pillar cavities 69 (corresponding to the ball region) and neck cavities 169 (corresponding to the neck region). Each laterally undulating cavity (69, 169) may extend laterally through the memory array region 100 and the contact region 300 along the first horizontal direction hd1.

[0113] refer to FIG. 13A to FIG. 13D , at least one dielectric material may be conformally deposited in each continuous line cavity 269 by a conformal deposition process to form a backside gate dielectric layer. The backside gate dielectric layer may include a silicon oxide layer, and may optionally include a dielectric metal oxide layer, such as an aluminum oxide layer. The thickness of the backside gate dielectric layer may be within 1 nm to 10 nm, such as 2 nm to 6 nm, but smaller and larger thicknesses may also be used.

[0114] The conductive material is conformally deposited to form a gate electrode material layer. The gate electrode material layer may include a heavily doped semiconductor material layer and / or a metal material that can be used as a gate electrode material. For example, the gate electrode material layer may include doped polysilicon. For example, the gate electrode material layer may have a thickness in the range of 4 nm to 100 nm, such as 6 nm to 40 nm, but smaller and larger thicknesses may also be used.

[0115] The dielectric fill material may be deposited by a conformal deposition process or a self-planarization process. For example, low pressure chemical vapor deposition (LPCVD) may be used to conformally deposit the silicate glass material, or spin coating may be used to deposit spin-on glass. Optionally, an annealing process may be performed to densify or reflow the silicate glass material.

[0116] Excessive portions of the semiconductor channel material layer 160L, the continuous front side gate dielectric layer 152L, the continuous ferroelectric material layer 154L, the back side gate dielectric layer, the gate electrode material layer, and the dielectric filling material can be removed from above the horizontal plane including the top surface of the insulating cap layer 70 by a planarization process, which can include recess etching or chemical mechanical planarization. Each of the semiconductor channel material layer 160L, the continuous front side gate dielectric layer 152L, the continuous ferroelectric material layer 154L, the back side gate dielectric layer, the gate electrode material layer, and the dielectric filling material is divided into a plurality of discrete portions by a planarization process. Each divided material portion can be located within the volume of a corresponding one of the line grooves 149.

[0117] Each remaining portion of the dielectric filling material constitutes a laterally undulating dielectric guide 166, which includes a corresponding laterally alternating sequence of bulbous regions and neck regions. Each remaining portion of the gate electrode material layer constitutes a backside gate electrode 164, which may have a U-shaped vertical cross-sectional profile and extend laterally along the first horizontal direction hd1. Each remaining portion of the backside gate dielectric layer constitutes a backside gate dielectric 162, which may have a U-shaped vertical cross-sectional profile and extend laterally along the first horizontal direction hd1. Each remaining portion of the semiconductor channel material layer 160L constitutes a vertical semiconductor channel 160, which may have a U-shaped vertical cross-sectional profile. Each line groove 149 includes a one-dimensional array of vertical semiconductor channels 160. Each remaining portion of the continuous front side gate dielectric layer 152L constitutes a front side gate dielectric 152, which may have a U-shaped vertical cross-sectional profile. Each line groove 149 includes a one-dimensional array of front side gate dielectrics 152. Each remaining portion of the continuous ferroelectric material layer 154L constitutes a ferroelectric material layer 154 , which may have a U-shaped vertical cross-sectional profile. Each linear trench 149 includes a one-dimensional array of ferroelectric material layers 154 .

[0118] Each group of the front side gate dielectric 152 and the ferroelectric material layer 154 constitutes a memory film 150. Each group of the vertical semiconductor channel 160 and the memory film 150 constitutes a memory stack structure 155, which is subsequently modified to form a completed memory stack structure. The continuous ferroelectric material layer 154L, the continuous front side gate dielectric layer 152L, and the semiconductor channel material layer 160L are patterned into a memory stack structure 155. Therefore, each group of the semiconductor channel material layer 160L, the continuous front side gate dielectric layer 152L, and the remaining portion of the continuous ferroelectric material layer 154L constitutes a memory stack structure 155. Each memory stack structure 155 includes a ferroelectric material layer 154, a front side gate dielectric 152 contacting the ferroelectric material layer 154, and a vertical semiconductor channel 160 contacting the front side gate dielectric 152.

[0119] A back gate dielectric 162 and a back gate electrode 164 are formed in each line groove 149 above a corresponding subset of the vertical semiconductor channels 160. Each back gate dielectric 162 may include a conformal dielectric material layer. Each back gate electrode 164 may include a laterally alternating sequence of neck regions and spherical regions. Each of the spherical regions of the back gate electrode 164 has a larger lateral extent than the neck region of the back gate electrode 164 along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. Each line groove 149 is filled with a corresponding line groove filling structure (154, 152, 160, 162, 164, 166), which includes two rows of ferroelectric material layers 154, two rows of front gate dielectrics 152, a one-dimensional array of vertical semiconductor channels 160, a back gate dielectric 162, a back gate electrode 164, and a laterally undulating dielectric guide rail 166.

[0120] refer to FIG. 14A to FIG. 14C , backside via cavities 179 may be formed by discrete regions of the laterally undulating dielectric rails 166 and by regions of the vertically alternating sequence (32, 42) located near the end regions of the laterally undulating dielectric rails 166. In one embodiment, a first subset of backside via cavities 179 may be formed within a region of the lateral extension of the line trenches 149 along the first horizontal direction hd1 within the memory array region 100. Additionally, a second subset of backside via cavities 179 may be formed within a region overlapping the laterally undulating dielectric rails 166 and / or within a region of the lateral extension of the line trenches 149 along the first horizontal direction hd1 within the contact region 300. Thus, the combination of the line trenches 149 and the first subset of backside via cavities 179 may divide the vertically alternating sequence of the insulating layer 32 and the sacrificial material layer 42 into a plurality of alternating stacks of insulating strips and sacrificial material strips. Each patterned portion of the insulating layer 32 constitutes an insulating strip, and each patterned portion of the sacrificial material layer 42 constitutes a sacrificial material strip. Therefore, each insulating strip is hereinafter referred to using the same reference numerals as insulating layer 32 , and each sacrificial material strip is hereinafter referred to using the same reference numerals as sacrificial material layer 42 .

[0121] The positions of the backside via cavities 179 may be selected so that each point within the sacrificial material strip 42 is laterally spaced apart from the nearest backside via cavity in the backside via cavities 179 by no more than a lateral etch distance during a subsequent etching process that selectively etches the material of the sacrificial material strip 42 to the material of the insulating strip 32 and the ferroelectric material layer 154. The width of each backside via cavity 179 along the second horizontal direction hd2 may be the same as or greater than the width of the line trench 149 along the second horizontal direction hd2 and less than the pitch of the line trench 149 along the second horizontal direction hd2. The length of each backside via cavity 179 along the first horizontal direction hd1 may be the same as, less than, or greater than the length of the spherical region of the laterally undulating dielectric rail 166.

[0122] The insulating strips 32 and the sacrificial material strips 42 (i.e., the remaining portion of the vertical alternating sequence) include alternating stacks of the insulating strips 32 and the sacrificial material strips 42. Within each alternating stack of the insulating strips 32 and the sacrificial material strips 42, the insulating strips 32 and the sacrificial material strips 42 are vertically alternating and extend laterally along a first horizontal direction hd1. The alternating stacks of the insulating strips 32 and the sacrificial material strips 42 and the line trench filling structures (154, 152, 160, 162, 164, 166) are formed above the substrate 8. The alternating stacks (32, 42) extend laterally along the first horizontal direction hd1 and are laterally spaced apart from each other along a second horizontal direction hd2 by the line trench filling structures (154, 152, 160, 162, 164, 166). The alternating stacks (32, 42) and line trench filling structures (154, 152, 160, 162, 164, 166) are laterally alternating along a second horizontal direction hd2.

[0123] FIG. 15A to FIG. 15C are sequential vertical cross-sectional views of regions of a first exemplary structure during replacement of a source level material layer 10 ′ with a source level material layer according to an embodiment of the present disclosure.

[0124] refer to Fig.15A, an etchant can be introduced into the backside trench in an isotropic etching process, which selectively etches the material of the source level sacrificial layer 104 with respect to the materials of the lower source layer 112, the upper source layer 116, the optional source select level conductive layer 118, the alternating stack (32, 42), the insulating cap layer 70 and the source level insulating strip 117. For example, if source level sacrificial layer 104 comprises undoped amorphous silicon or undoped amorphous silicon germanium alloy, lower source layer 112, upper source layer 116, and optional source select level conductive layer 118 comprise heavily n-doped silicon, and upper and lower sacrificial liners (105, 103) comprise silicon oxide, a wet etching process using hot trimethyl-2-hydroxyethylammonium hydroxide (“hot TMY”) or tetramethylammonium hydroxide (TMAH) may be used to selectively remove source level sacrificial layer 104 with respect to lower source layer 112, upper source layer 116, optional source select level conductive layer 118, alternating stacks (32, 42), insulating capping layer 70, and source level insulating strips 117, and upper and lower sacrificial liners (105, 103). A source cavity 109 is formed in the volume from which source level sacrificial layer 104 is removed.

[0125] refer to Fig. 15B , a sequence of isotropic etchants (such as wet etchants) may be applied to the physically exposed portions of the memory film 150. The component layers of the memory film 150 are etched from the outside to the inside. The cylindrical surface of the vertical semiconductor channel 60 is physically exposed at the level of the source cavity 109. The upper and lower sacrificial liners (105, 103) may be incidentally etched during the removal of the portion of the memory film 150 positioned at the level of the source cavity 109. The volume of the source cavity 109 may be expanded by removing portions of the memory film 150 at the level of the source cavity 109 and the upper and lower sacrificial liners (105, 103). The top surface of the lower source layer 112 and the bottom surface of the upper source layer 116 may be physically exposed to the source cavity 109.

[0126] Each one-dimensional array of U-shaped ferroelectric material layers 154 in the line grooves 149 is divided into two rows of ferroelectric material layers 154. Each one-dimensional array of U-shaped front side gate dielectrics 152 is divided into two rows of front side gate dielectrics 152. A stacked cap including a first material portion of the same material as the ferroelectric material layer 154 and a second material portion of the same material as the front side gate dielectric 152 is formed under each U-shaped vertical semiconductor channel 160 below the level of the source cavity 109.

[0127] refer to Fig. 15C, a doped semiconductor material having a second conductivity type can be deposited by a selective semiconductor deposition process. During the selective semiconductor deposition process, a semiconductor precursor gas, an etchant, and a dopant precursor gas can flow simultaneously into a processing chamber including the first exemplary structure. For example, if the second conductivity type is n-type, a semiconductor precursor gas (such as silane, disilane, or dichlorosilane), an etchant gas (such as hydrogen chloride), and a dopant precursor gas (such as phosphine, arsine, or antimonide) can be used. The deposited doped semiconductor material forms a source contact layer 114, which can contact the sidewalls of the vertical semiconductor channel 60. The duration of the selective semiconductor deposition process can be selected so that the source cavity 109 is filled with the source contact layer 114. Therefore, the source contact layer 114 can be formed by selectively depositing the doped semiconductor material from the semiconductor surface surrounding the source cavity 109. In one embodiment, the doped semiconductor material can include doped polysilicon.

[0128] The layer stack including the lower source layer 112, the source contact layer 114 and the upper source layer 116 constitutes a buried source layer (112, 114, 116) which serves as a common source region connecting each of the vertical semiconductor channels 60 and having a doping of the second conductivity type. The average dopant concentration of the buried source layer (112, 114, 116) can be in the range of 5.0×1019 / cm3 to 2.0×1021 / cm3, but smaller and larger dopant concentrations can also be used. The layer group including the buried source layer (112, 114, 116), the source level insulating strip 117 and the optional source select level conductive layer 118 constitutes the source level material layer 10, which replaces the source level material layer 10' during the process. Optionally, an oxidation process may be performed to convert a surface portion of the source contact layer 114 into a semiconductor oxide portion (not shown) beneath each backside via cavity 179. The surface portion of each semiconductor layer (114, 116, 118) exposed in each backside via cavity 179 may optionally be oxidized to form a semiconductor oxide (e.g., silicon oxide) capping portion.

[0129] refer to Fig.16 , an etchant may be introduced into backside via cavity 179, for example, using an isotropic etching process, which etchant selectively etches the second material of sacrificial material strip 42 relative to the first material of insulating strip 32 and source level material layer 10. Backside recess 43 is formed in the volume from which sacrificial material strip 42 is removed. The second material of sacrificial material strip 42 may be removed selectively to the first material of insulating strip 32, the ferroelectric material of ferroelectric material layer 154, the material of rear stepped dielectric material portion 65, and the material of source level material layer 10.

[0130] The isotropic etching process that selectively removes the second material to the first material and the outermost layer of the memory film 150 can be a wet etching process using a wet etching solution, or can be a vapor phase (dry) etching process in which the etchant is introduced into the backside via cavity 179 in the vapor phase. For example, if the sacrificial material strip 42 includes silicon nitride, and if the insulating strip 32 and the rear stepped dielectric material portion 65 include silicon oxide / oxynitride materials, such as undoped silicate glass and / or doped silicate glass and / or thermal silicon oxide or oxynitride, the etching process can be a wet etching process in which the first exemplary structure is immersed in a wet etching bath including phosphoric acid, which selectively etches silicon nitride to silicon oxide. The duration of the isotropic etching process can be selected so that the sacrificial material strip 42 is completely removed from each alternating stack (32, 42) of the insulating strip 32 and the sacrificial material strip 42. Each backside recess 43 can be a laterally extending cavity having a lateral dimension greater than the vertical extent of the cavity. In other words, the lateral dimension of each back-side recessed portion 43 may be greater than the height of the back-side recessed portion 43 .

[0131] In one embodiment, the memory array area 100 includes a single three-dimensional NAND string array having multiple device levels disposed above the substrate (9, 10). In this case, each backside recess 43 may define a space for receiving a corresponding word line of the single three-dimensional NAND string array. Each backside recess in the plurality of backside recesses 43 may extend substantially parallel to the top surface 7 of the substrate 8. The backside recess 43 may be vertically bounded by the top surface of the underlying insulating strip 32 and the bottom surface of the covering insulating strip 32. In one embodiment, each backside recess 43 may have a uniform height throughout.

[0132] refer to Fig.17 , the metal barrier layer 46A can be deposited directly on the physically exposed outer sidewalls of the ferroelectric material layer 154 in the back side recess 43. The metal barrier layer 46A includes a conductive metal material, which can be used as a diffusion barrier and / or adhesion promoting layer for a subsequently deposited metal fill material. The metal barrier layer 46A may include a conductive metal nitride material such as TiN, TaN, WN or a stack thereof, or may include a conductive metal carbide material such as TiC, TaC, WC or a stack thereof. In one embodiment, the metal barrier layer 46A may be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal barrier layer 46A may be in the range of 2nm to 8nm, such as 3nm to 6nm, but smaller and larger thicknesses may also be used. In one embodiment, the metal barrier layer 46A may be substantially composed of a conductive metal nitride such as TiN.

[0133] The metal filling material is deposited in the remaining volume of the backside recess 43, on the sidewalls of at least one backside through-hole cavity 179, and on the top surface of the insulating cap layer 70 to form a metal filling material portion 46B. The metal filling material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), chemical plating, electroplating, or a combination thereof. In one embodiment, the metal filling material portion 46B can be substantially composed of at least one elemental metal. At least one elemental metal of the metal filling material portion 46B can be selected from, for example, tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metal filling material portion 46B can be substantially composed of a single elemental metal. In one embodiment, a fluorine-containing precursor gas such as WF6 can be used to deposit the metal filling material portion 46B. In one embodiment, the metal filling material portion 46B can be a tungsten layer including residual fluorine atoms as impurities.

[0134] A plurality of conductive strips 46 (i.e., conductive strips having a strip shape) may be formed in the plurality of backside recesses 43, and a continuous metal material layer may be formed on the sidewalls of each backside via cavity 179 and over insulating cap layer 70. Each conductive strip 46 includes a portion of a metal barrier layer 46A and a metal filling material portion 46B located between a pair of vertically adjacent dielectric material strips, such as a pair of insulating strips 32.

[0135] refer to Fig.18 , for example, by etching back the deposited metal material of the continuous conductive material layer from the sidewalls of each backside via cavity 179 and from above the insulating cap layer by isotropic wet etching, anisotropic dry etching, or a combination thereof. Each remaining portion of the deposited metal material in the backside recess 43 constitutes a conductive strip 46. Each conductive strip 46 can be a conductive line structure. Thus, the sacrificial material strip 42 is replaced with a conductive strip 46.

[0136] Each conductive strip 46 may be used as a combination of a plurality of control gate electrodes at the same level and a word line electrically interconnected (i.e., electrically connected) with the plurality of control gate electrodes at the same level. The plurality of control gate electrodes within each conductive strip 46 are control gate electrodes for vertical memory devices including the memory stack structure 155. In other words, each conductive strip 46 may be a word line used as a common control gate electrode for a plurality of vertical memory devices.

[0137] Although the present disclosure is described using an embodiment in which the vertical alternating sequence is divided into multiple alternating stacks of insulating strips 32 and sacrificial material strips 42 when forming the backside via cavity 179, embodiments are expressly contemplated herein in which the vertical alternating sequence is divided into multiple alternating stacks of insulating strips 32 and sacrificial material strips 42 at different processing steps. In one embodiment, the vertical alternating sequence may be divided into multiple alternating stacks of insulating strips 32 and sacrificial material strips 42 when forming the backside via cavity 179 (i.e., at Figure 4A and Figure 4B At the processing step of , the vertical alternating sequence is divided into a plurality of alternating stacks of insulating strips 32 and spacer material strips 42 , with the linear trenches 149 extending along the first horizontal direction hd1 through the entire length of the contact area 300 .

[0138] Generally, the conductive strips 46 of various embodiments may be formed directly on the sidewalls of the ferroelectric material layer 154. The conductive strips 46 may include at least one conductive material selected from a metal (such as a conductive metal nitride material, tungsten, cobalt, molybdenum, and / or copper) and a doped semiconductor material (including an electrical dopant having an atomic concentration of at least 1.0×1020 / cm3). The vertical semiconductor channel 60 may include a semiconductor material including an electrical dopant having an atomic concentration in the range of 1.0×1014 / cm3 to 1.0×1018 / cm3.

[0139] refer to FIG. 19A to FIG. 19C , an insulating material may be formed in the back side through hole cavity 179 and above the insulating cap layer 70 by a conformal deposition process or a self-planarization process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. An exemplary self-planarization process is spin coating. The insulating material may include silicon oxide, silicon nitride, a dielectric metal oxide, an organosilicate glass, or a combination thereof. In one embodiment, the insulating material may include silicon oxide. Optionally, excess portions of the insulating material may be removed from above a horizontal plane including the top surface of the insulating cap layer 70 by recess etching or chemical mechanical planarization. Each remaining portion of the insulating material constitutes a dielectric pillar structure 76.

[0140] refer to Fig. 20, a drain region 63 including a doped semiconductor material having a doping of the second conductivity type may be formed to contact each of the vertical semiconductor channels 60. The drain region 63 may be formed by implanting a dopant of the second conductivity type into a top portion of each of the vertical semiconductor channels 60. Alternatively, each of the vertical semiconductor channels 60 may be recessed by selective recess etching, and then a doped semiconductor material having a doping of the second conductivity type is deposited into the recess above the vertical semiconductor channel 60 to form the drain region 63. Optionally, a dopant of the second conductivity type may be implanted into the drain region 63 to increase the dopant concentration therein. The atomic concentration of the dopant of the second conductivity type in the drain region 63 may be in the range of 5.0×1019 / cm3 to 2.0×1021 / cm3, but smaller and larger atomic concentrations may also be used. Each set of the memory stack structure 55 and the drain region 63 constitutes a memory stack assembly 58.

[0141] refer to Fig.21A and Fig. 21B , contact via structures 86 (which are referred to herein as word line contact via structures) may be formed on the conductive strips 46 through the backward stepped dielectric material portion 65. A two-dimensional array of contact via structures 86 may be formed on the top surface of a respective one of the conductive strips 46 in the contact region 300.

[0142] Additional contact via structures and additional dielectric material layers may be formed over the insulating cap layer 70. For example, a drain contact via structure (not explicitly shown) may be formed on the top surface of each drain region 63. The bit line 98 may be formed to electrically contact every other drain region 63 along the second horizontal direction hd2, i.e., a set of corresponding drain regions 63 located within every other line trench 149 along the second horizontal direction hd2. Fig. 21B An exemplary layout of the bit lines 98 is shown in FIG. In this configuration, each conductive strip 46 used as a word line activates only a single portion of a memory cell (e.g., a single portion of a memory film 50) for each bit line 98, and a uniquely selected memory cell corresponding to a single activated portion of one of the memory films 50 can be programmed or read.

[0143] Referring to all drawings of the first exemplary structure and according to various embodiments of the present disclosure, there is provided a three-dimensional memory device, the three-dimensional memory device comprising: an alternating stack of insulating strips 32 and conductive strips 46, which are located above a substrate 8 and are laterally spaced apart from each other by line trenches 149, wherein the line trenches 149 extend laterally along a first horizontal direction hd1 and are spaced apart along a second horizontal direction hd2; and line trench filling structures (155, 162, 164, 166, 63) which are located in the line trenches 149, wherein the line trench filling structures (155, 162, 164, 166, 63) 55, 162, 164, 166, 63) each includes a corresponding group of memory stack structures 155, a back gate dielectric 162 contacting each memory stack structure 155 within the corresponding group of memory stack structures 155, and a back gate electrode 164 contacting the back gate dielectric 162, wherein each memory stack structure 155 includes a ferroelectric material layer 154, a front gate dielectric 152 contacting the ferroelectric material layer 154, and a vertical semiconductor channel 160 contacting the front gate dielectric 152 and the back gate dielectric 162.

[0144] In one embodiment, each group of memory stack structures 155 includes a respective row of discrete memory stack structures arranged along a first horizontal direction hd1.

[0145] In one embodiment, each of the ferroelectric material layer 154, the front side gate dielectric 152, and the vertical semiconductor channel 160 extends from a first horizontal plane including a bottom surface of a bottommost conductive strip in the alternating stack (32, 46) of conductive strips 46 to a second horizontal plane including a top surface of a topmost conductive strip in the alternating stack (32, 46) of conductive strips 46.

[0146] In one embodiment, each of the back gate electrodes 164 extends laterally along a first horizontal direction hd1 and is configured to apply a back bias voltage to each of the vertical semiconductor channels 160 within a corresponding one of the line trench filling structures (155, 162, 164, 166, 63).

[0147] In one embodiment, each of the backside gate electrodes 164 has a laterally undulating profile, the ferroelectric material layer 154 includes hafnium oxide, and the conductive strips 46 contact sidewalls of the ferroelectric material layer 154 .

[0148] refer to Fig. 22, a second exemplary structure according to a second embodiment of the present disclosure is shown. The second exemplary structure includes a substrate 10, which includes a substrate semiconductor layer 9. The substrate semiconductor layer 9 is a semiconductor material layer located at least in the upper portion of the substrate, and may include at least one semiconductor material, which may include at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, and / or other semiconductor materials known in the art. The substrate may have a main surface 7, which may be, for example, the topmost surface of the substrate semiconductor layer 9. The main surface 7 may be a semiconductor surface. In one embodiment, the main surface 7 may be a single crystalline semiconductor surface.

[0149] The optional dielectric material portion 13 can be formed within the substrate semiconductor layer 9, for example, by forming a shallow trench in the upper portion of the substrate semiconductor layer 9, filling the shallow trench with a dielectric material, and removing excess portions of the dielectric material from above the top surface of the substrate semiconductor layer 9 using a planarization process such as a chemical mechanical planarization (CMP) process. The remaining portion of the dielectric material constitutes the dielectric material portion. The dielectric material portion includes a dielectric material such as silicon oxide, silicon nitride, a dielectric metal oxide, or a combination thereof.

[0150] The patterned conductive material layer 14 may be formed on the top surface of the dielectric material portion 13. The patterned conductive material layer 14 may be formed, for example, by depositing a conductive material layer over the substrate 10 and patterning the deposited conductive material by a combination of a photolithography method and an etching process. For example, a photoresist layer may be applied and patterned to mask a portion of the deposited conductive material, and the unmasked portion of the deposited conductive material may be removed by an etching process. The remaining portion of the conductive material constitutes the patterned conductive material layer 14. In one embodiment, the conductive material layer 14 may be a metal material layer. In one embodiment, the conductive material layer 14 may include a stack having a conductive metal nitride layer including a conductive metal nitride (such as TiN, TaN and WN) and a metal material layer including an elemental metal or its alloy (such as W, Al, Cu or its alloy) from bottom to top. The thickness of the conductive material layer 14 may be in the range of 2nm to 40nm, but smaller and larger thicknesses may also be used. In one embodiment, the entire periphery of the conductive material layer 14 may be completely within the area defined by the periphery of the dielectric material portion 13.

[0151] Alternatively, the conductive material layer 14 may be formed as a doped semiconductor layer within the upper portion of the substrate 10. In this case, the doped semiconductor layer may be electrically isolated from the substrate semiconductor layer 9 by a reverse biased pn junction between the doped semiconductor layer and the substrate semiconductor layer 9. The dielectric material portion 13 electrically isolates the conductive material layer 14 from the substrate semiconductor layer 9.

[0152] The bottommost insulator layer 132 may be formed over the substrate 10 and the conductive material layer 14. The bottommost insulator layer 132 includes an electrically insulating material. Electrically insulating materials that can be used for the bottommost insulator layer 132 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials, which are commonly referred to as high dielectric constant (high-k) dielectric oxides. In one embodiment, the bottommost insulator layer 132 may include the same material as the insulator layer to be formed subsequently. In one embodiment, the bottommost insulator layer 132 includes silicon oxide.

[0153] A temporary material layer 41 may be formed over the bottommost insulator layer 132. The temporary material layer 41 includes a material that is selectively removable for a first material of an insulator layer to be formed subsequently and a second material of a sacrificial material layer to be formed subsequently. As used herein, "temporary material" refers to a material that is present on a structure during at least one processing step and is removed from the structure prior to completion of the structure (i.e., prior to termination of the last processing step).

[0154] A stack of alternating multiple first material layers (which may be insulator layers 32) and second material layers (which may be sacrificial material layers 42) is formed above the top surface of the substrate, which may be, for example, on the top surface of the temporary material layer 41. The alternating multiple first material layers and second material layers may start with an instance of the first material layer and end with another instance of the first material layer. In one embodiment, the instance of the first element and the instance of the second element may form a unit that is periodically repeated within the alternating multiple layers.

[0155] Each first material layer includes a first material, and each second material layer includes a second material different from the first material. In one embodiment, each first material layer 32 can be an insulating layer, and each second material layer 142 can be a spacer material layer providing a vertical spacing between vertical pairs of adjacent first material layers 32. In one embodiment, the spacer material layer can be a sacrificial material layer. In this case, the stack can include alternating multiple insulator layers 32 and sacrificial material layers 42.

[0156] Although the present disclosure is described using an exemplary embodiment in which the spacer material layer is formed as the sacrificial material layer 42, in other embodiments, the spacer material layer is formed as a conductive layer. In such embodiments, the processing step of replacing the sacrificial material layer with a conductive layer can be omitted.

[0157] The alternating multiple stacks are referred to herein as alternating stacks (32, 42). In one embodiment, the alternating stacks (32, 42) may include an insulator layer 32 composed of a first material and a sacrificial material layer 42 composed of a second material, wherein the second material is different from the material of the insulator layer 32. The first material of the insulator layer 32 may be at least one electrically insulating material. Therefore, each insulator layer 32 may be an electrically insulating material layer. Electrically insulating materials that can be used for the insulator layer 32 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the insulator layer 32 is silicon oxide.

[0158] The second material of the sacrificial material layer 42 is a sacrificial material that can be selectively removed from the first material of the insulator layer 32. The sacrificial material layer 42 may include an electrically insulating material, a semiconductor material, or a conductive material. The second material of the sacrificial material layer 42 may then be replaced with a conductive electrode that can be used, for example, as a control gate electrode for a vertical NAND device. Non-limiting examples of the second material include silicon nitride, an amorphous semiconductor material (such as amorphous silicon), and a polycrystalline semiconductor material (such as polycrystalline silicon). In one embodiment, the sacrificial material layer 42 may be a material layer including silicon nitride or a semiconductor material including germanium or a silicon-germanium alloy.

[0159] In one embodiment, insulator layer 32 may include silicon oxide and sacrificial material layer may include silicon nitride. The first material of insulator layer 32 may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for insulator layer 32, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of sacrificial material layer 42 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0160] The sacrificial material layer 42 may be appropriately patterned so that a conductive material portion subsequently formed by replacing the sacrificial material layer 42 may be used as a conductive electrode, such as a control gate electrode of a subsequently formed single three-dimensional NAND string memory device. The sacrificial material layer 42 may include a portion having a stripe shape extending substantially parallel to the main surface 7 of the substrate.

[0161] The thickness of the bottommost insulator layer 132, the temporary material layer 41, the insulator layer 32, and the sacrificial material layer 42 may be in the range of 20nm to 50nm, but smaller and larger thicknesses may be used for each layer. The number of repetitions of the paired insulator layer 32 and the sacrificial material layer (e.g., the control gate electrode or the sacrificial material layer) 42 may be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions may also be used. The top gate electrode and the bottom gate electrode in the stack may be used as select gate electrodes. In one embodiment, each sacrificial material layer 42 in the alternating stack (32, 42) may have a uniform thickness that is substantially constant within each corresponding sacrificial material layer 42.

[0162] In one embodiment, the bottommost insulator layer 132 and the insulator layer 32 may include silicon oxide, the sacrificial material layer 42 may include silicon nitride, and the temporary material layer 41 may include a semiconductor material. The semiconductor material of the temporary material layer 41 may be, for example, a Group IV semiconductor material, a Group III-V compound semiconductor material, a Group II-VI semiconductor material, an organic semiconductor material. In an exemplary example, the semiconductor material may be amorphous silicon or polycrystalline silicon.

[0163] In another embodiment, the bottommost insulator layer 132 and the insulator layer 32 may include silicon oxide, the sacrificial material layer 42 may include a semiconductor material that can be selectively etched with respect to the semiconductor material of the semiconductor material layer 10, and the temporary material layer 41 may include silicon nitride. The semiconductor material of the sacrificial material layer 42 may be, for example, germanium, a silicon-germanium alloy, a III-V compound semiconductor material, a II-VI semiconductor material, or an organic semiconductor material.

[0164] refer to Fig.23A photolithographic material stack (not shown) including at least a photoresist layer may be formed above the alternating stack (32, 42) and may be photolithographically patterned to form an opening therein. The pattern in the photolithographic material stack may be transferred through the entire alternating stack (32, 42) by at least one anisotropic etch using the patterned photolithographic material stack as an etch mask. The portion of the alternating stack (32, 42) below the opening in the patterned photolithographic material stack is etched to form a memory opening 49. In other words, the pattern in the patterned photolithographic material stack is transferred through the alternating stack (32, 42) to form a memory opening 49 extending through the alternating stack (32, 42). The chemical properties of the anisotropic etching process for etching the material through the alternating stack (32, 42) may be alternating to optimize the etching of the first material and the second material in the alternating stack (32, 42). The anisotropic etching may be, for example, a series of reactive ion etchings. Optionally, the conductive material layer 14 may be used as an etch stop layer between the alternating stack (32, 42) and the substrate. The sidewalls of the reservoir opening 49 may be substantially vertical, or may be tapered.The patterned photolithographic material stack may subsequently be removed, for example, by ashing.

[0165] The memory opening 49 is formed by the alternating stack (32, 42), the temporary material layer 41, and the bottommost insulator layer 132, so that the memory opening 49 extends from the top surface of the alternating stack (32, 42) to the top surface of the conductive material layer 14 above the substrate 10. The area in which the array of memory openings 49 is formed is referred to as the device area herein. In one embodiment, each memory opening 49 may have a cylindrical shape, and the horizontal cross-sectional shape of each memory opening may be a closed shape of a circle, an ellipse, a polygon, or a substantially curved line.

[0166] refer to Fig.24 , a continuous ferroelectric material layer, a continuous front side gate dielectric layer and a continuous vertical semiconductor channel material layer are sequentially deposited into the array of memory openings 49 and above the alternating stack (32, 42). The continuous ferroelectric material layer may have the same composition and the same thickness as the continuous ferroelectric material layer 154L of the first embodiment. The continuous ferroelectric material layer may be formed directly on the top surface of the conductive material layer 14. The continuous front side gate dielectric layer may have the same composition and the same thickness as the front side gate dielectric layer 152L. The continuous vertical semiconductor channel material layer may have the same material composition and thickness as the continuous vertical semiconductor channel material layer 160L according to the first embodiment.

[0167] Horizontal portions of the continuous vertical semiconductor channel material layer, the continuous front gate dielectric layer, and the continuous ferroelectric material layer may be anisotropically etched from above the alternating stack (32, 42) and at the bottom of each memory opening 49. Each remaining discrete portion of the continuous vertical semiconductor channel material layer constitutes a vertical semiconductor channel 60. Each remaining discrete portion of the continuous front gate dielectric layer constitutes a front gate dielectric 152. Each remaining discrete portion of the continuous ferroelectric material layer constitutes a ferroelectric material layer 154. Each ferroelectric material layer 154 may be formed directly on the top surface of the conductive material layer 154. Each combination of the ferroelectric material layer 154 and the front gate dielectric 152 constitutes a memory film 50. Each vertical semiconductor channel 60 includes a semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

[0168] A cavity 49' may exist within the volume of each memory opening 49 that is not filled with the memory film 50 and the vertical semiconductor channel 60. The annular horizontal portion of the memory film 50 may be located below the vertical semiconductor channel 60 within each memory opening. The top surface of the conductive material layer 14 may be physically exposed at the bottom of each cavity 49'. The vertical semiconductor channel 60 is electrically isolated from the substrate 10 by the memory film 50 within each memory opening 49. Each memory film 50 may be topologically homeomorphic to a torus. Each memory film 50 may be topologically homeomorphic to a torus. As used herein, an element is topologically homeomorphic to a geometric shape if its shape can be mapped to the geometric shape by continuous deformation without creating or destroying any holes.

[0169] refer to Fig.25 , a back gate dielectric 62 can be formed on the inner sidewalls of the vertical semiconductor channel 60 within each memory opening. In one embodiment, the back gate dielectric 62 can be formed by depositing a back gate dielectric layer in the memory opening and above the alternating stack (32, 42), and by anisotropically etching the back gate dielectric layer. An opening is formed through each horizontal portion of the back gate dielectric layer at the bottom portion of each memory opening. Each remaining vertical portion of the back gate dielectric layer constitutes the back gate dielectric 62.

[0170] The back gate dielectric 62 includes at least one dielectric material. The dielectric materials that may be included in the back gate dielectric 62 include, but are not limited to, silicon oxide, silicon nitride, dielectric metal oxide, organic silicate glass, or a combination thereof. In one embodiment, the back gate dielectric 62 may include a stack of silicon oxide layers and dielectric metal oxide layers. The thickness of each back gate dielectric 62 may be in the range of 3nm to 30nm, but smaller and larger thicknesses may also be used. The bottom surface of each back gate dielectric 62 may contact the top surface of the conductive material layer 14. The outer sidewall of each back gate dielectric 62 may contact the inner sidewall of the vertical semiconductor channel 60 and the inner sidewall of the memory film 50. Each back gate dielectric 62 may be homeomorphic to the ring topology.

[0171] refer to Fig.26 , a backside gate electrode 64 may be formed in each cavity 49' laterally surrounded by the backside gate dielectric 62. At least one conductive material may be deposited in each cavity 49' laterally enclosed by the backside gate dielectric 62 and above the alternating stack (32, 42). The at least one conductive material may include, for example, a conductive metal nitride liner material (such as TiN, TaN and / or WN) and a conductive fill material (such as an elemental metal (e.g., W), an intermetallic alloy, a doped semiconductor material, a metal semiconductor alloy material, or a combination thereof). The deposited conductive material may be removed from above the topmost surface of the alternating stack (32, 42) by a planarization process. Chemical mechanical planarization (CMP) and / or a recess etching process may be used for the planarization process.

[0172] The remaining portion of the deposited conductive material may be vertically recessed below a horizontal plane including the top surface of the alternating stack (32, 42), for example, by recess etching. The recess depth below the horizontal plane including the top surface of the alternating stack (32, 42) may be in the range of 3 nm to 300 nm, but smaller and larger recess depths may also be used. Each remaining portion of the deposited conductive material constitutes a backside gate electrode 64. Each backside gate electrode 64 may be in contact with the conductive material layer 14.

[0173] In one embodiment, the top surface of each back gate electrode 64 may be formed above a horizontal plane including the top surface of the topmost sacrificial material layer 42 within the alternating stack (32, 42). In one embodiment, during the vertical recessing of the deposited conductive material, the top portion of each back gate dielectric 62 may be vertically recessed in parallel to form the back gate electrode 64. In another embodiment, the recessing of the deposited conductive material to form the back gate electrode 64 may be performed selectively to the dielectric material of the back gate dielectric 62, i.e., without substantially etching the dielectric material of the back gate dielectric 62. In this case, the top surface of each back gate electrode 64 may be recessed below a horizontal plane including the topmost surface of the alternating stack (32, 42).

[0174] In one embodiment, an electrical dopant, which may be a p-type dopant or an n-type dopant, may be introduced into the top portion of each vertical semiconductor channel 60 to convert each implanted portion into a drain region 63. The drain region 63 may be formed on top of the remaining portion of the vertical semiconductor channel 60. Each drain region 63 may be an annular structure, i.e., may be homeomorphic to a torus topology. Each drain region 63 may contact the inner sidewall of the memory film 50 and may contact the topmost portion of the outer sidewall of the back gate dielectric 62.

[0175] A dielectric capping layer 67 may be deposited into the recesses within the memory openings and over the alternating stacks (32, 42). The dielectric capping layer 67 includes a dielectric material that may be the same as or different from the dielectric material contained within the back gate dielectric 62. The dielectric capping layer 67 may include a material different from that of the sacrificial material layer 42. For example, the dielectric capping layer 67 may include silicon oxide or a dielectric metal oxide such as aluminum oxide. Optionally, the top surface of the dielectric capping layer 67 may be planarized. The dielectric capping layer 67 may contact the inner sidewalls and top surface of each drain region 63, the top surface of each back gate dielectric 62, and the top surface of each back gate electrode 64.

[0176] Each group of memory film 50 and vertical semiconductor channel 60 in the memory opening constitutes a memory stack structure 55. The backside gate electrode 64 and a group of nested layers laterally surrounding the backside gate electrode 64 in the memory opening together constitute a pillar structure (64, 62, 60, 63, 50). The group of nested layers includes the backside gate dielectric 62, the vertical semiconductor channel 60 and the memory film 50 from the inside to the outside.

[0177] refer to Fig. 27, a photoresist layer (not shown) may be applied over the dielectric capping layer 67 and the alternating stack (32, 42) and may be photolithographically patterned to form openings therein. The pattern in the photoresist layer may be transferred through the dielectric capping layer 67 and the alternating stack (32, 42) using anisotropic etching to form at least one backside contact groove 79. Each backside contact groove 79 may extend through the entirety of the alternating stack (32, 42) and may have a horizontal surface of the temporary material layer 41 as a bottom surface. In one embodiment, the anisotropic etching may be selective to the material of the temporary material layer 41, and the bottom surface of each backside contact groove 79 may coincide with the top surface of the temporary material layer 41. In another embodiment, the bottom surface of the backside contact groove 79 may be located between a first horizontal plane including the topmost surface of the temporary material layer 41 and the bottom surface of the temporary material layer 41. The sidewalls of each backside contact groove 79 may be substantially vertical or tapered. The photoresist layer may then be removed, for example, by ashing.

[0178] refer to Fig.28 , an etchant may be introduced into at least one backside contact trench 79, for example, using an etching process, the etchant selectively etching the second material of the sacrificial material layer 42 relative to the first material of the insulator layer 32 and the temporary material layer 41. A backside recess is formed in the volume from which the sacrificial material layer 42 is removed. The second material of the sacrificial material layer 42 may be removed selectively to the first material of the insulator layer 32, the material of the temporary material layer 41, and the outermost material of the memory film 50. In an illustrative example, the sacrificial material layer 42 may include silicon nitride, the material of the insulator layer 32 may be silicon oxide, and the material of the temporary material layer 41 may be germanium, a silicon-germanium alloy, amorphous silicon, or polycrystalline silicon. In another embodiment, the sacrificial material layer 42 may include a semiconductor material such as germanium, a silicon-germanium alloy, or silicon, the material of the insulator layer 32 may include silicon oxide, and the material of the temporary material layer 41 may include silicon nitride.

[0179] The etching process that selectively removes the second material with respect to the first material and the outermost layer of the memory film 50 may be a wet etching process using a wet etching solution, or may be a vapor phase (dry) etching process that introduces an etchant in a vapor phase into the at least one backside contact trench 79. For example, if the sacrificial material layer 42 includes silicon nitride, the etching process may be a wet etching process that immerses the exemplary structure in a wet etching bath including phosphoric acid, which selectively etches silicon nitride with respect to silicon oxide, silicon, and various other materials used in the art.

[0180] Each back side recess may be a laterally extending cavity, the lateral dimension of which is greater than the vertical extent of the cavity. In other words, the lateral dimension of each back side recess may be greater than the height of the back side recess. Multiple back side recesses may be formed in the volume of the second material from which the sacrificial material layer 42 is removed. The memory opening in which the memory stack structure 55 is formed is referred to herein as the front side opening or the front side cavity, in contrast to the back side recess. In one embodiment, the device area includes a monomer three-dimensional NAND string array having a plurality of device levels disposed above the substrate 10. In this case, each back side recess may define a space for receiving a corresponding word line of the monomer three-dimensional NAND string array.

[0181] Each of the plurality of backside recesses may extend substantially parallel to the top surface of the substrate 10. The backside recess may be vertically defined by the top surface of the underlying insulator layer 32 and the bottom surface of the covering insulator layer 32. In one embodiment, each backside recess may have a uniform height throughout.

[0182] Conductive material may be deposited in multiple backside recesses, on the sidewalls of at least one backside contact trench 79, and above the top surface of the dielectric cap layer 67. As used herein, conductive material refers to an electrically conductive material. The conductive material may be deposited by a conformal deposition method, which may be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), chemical plating, electroplating, or a combination thereof. The conductive material may be an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal semiconductor alloy such as a metal silicide, an alloy thereof, and a combination or stack thereof. Non-limiting exemplary conductive materials that may be deposited in multiple backside recesses include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, and tantalum nitride. In one embodiment, the conductive material may include a metal such as tungsten and / or a metal nitride. In one embodiment, the conductive material for filling multiple backside recesses may be selected from tungsten and a combination of titanium nitride and tungsten. In one embodiment, the conductive material may be deposited by chemical vapor deposition.

[0183] A plurality of conductive layers 46 may be formed in the plurality of backside recesses, and a conductive material layer (not shown) may be formed on the sidewalls of each backside contact trench 79 and over the dielectric capping layer 67. Thus, at least a portion of each sacrificial material layer 42 may be replaced with a conductive layer 46, which is a conductive material portion. In one embodiment, the conductive layer 46 may be formed in the shape of conductive strips extending laterally in a first horizontal direction and laterally spaced apart in a second horizontal direction perpendicular to the first horizontal direction.

[0184] Subsequently, the deposited conductive material of the conductive material layer may be etched back, for example by isotropic etching, from each backside contacting the sidewalls of trench 79 and from above dielectric cap layer 67. Each remaining portion of the deposited conductive material in the backside recess constitutes conductive layer 46. Each conductive layer 46 may be a conductive line structure.

[0185] Each conductive layer 46 may function as a combination of a plurality of control gate electrodes and a word line electrically connected (i.e., electrically connected) to the plurality of control gate electrodes. The plurality of control gate electrodes within each conductive layer 46 may include control gate electrodes located at the same level as the vertical memory device including the memory stack structure 55. In other words, each conductive layer 46 may be a word line functioning as a common control gate electrode for a plurality of vertical memory devices.

[0186] Each memory stack structure 55 includes a memory film 50 and a vertical semiconductor channel 60 located within a memory opening 49. If each control gate electrode 46 laterally surrounds the entire perimeter of the memory stack structure 55, the total number of ferroelectric memory elements within the memory stack structure 55 may be the same as the total number of levels of the control gate electrode, which may be an end portion of the conductive layer 46. Alternatively, if more than one control gate electrode is formed near the memory stack structure 55 at the same level, the total number of ferroelectric memory elements at the corresponding level of the memory stack structure 55 may be the same as the total number of control gate electrodes 46 located near the memory stack structure 55 at the corresponding level. If a total of N control gate electrodes are located near the memory film 50 at each level of the conductive layer 46, the total number of ferroelectric memory elements of each memory film 50 may be the product of the total number of levels of the conductive layer 46 and the integer N.

[0187] refer to Fig.29 , an insulating spacer 74 can be formed on the sidewalls of the back contact groove 79 by depositing a dielectric material layer and anisotropically etching a horizontal portion of the dielectric material layer. The insulating spacer 74 includes a dielectric material, which may include, for example, silicon oxide, silicon nitride, dielectric metal oxide, dielectric metal oxynitride, or a combination thereof. The thickness of the insulating spacer 74 (as measured at its bottom portion) can be in the range of 1nm to 50nm, but smaller and larger thicknesses can also be used. In one embodiment, the thickness of the insulating spacer 74 can be in the range of 3nm to 10nm. The cavity 79' is formed in the volume of each back contact groove 79 that is not filled with the insulating spacer 74.

[0188] refer to Fig.30, an etchant can be introduced into at least one back contact trench 79, for example, using an etching process, which etchant selectively etches the material of the temporary material layer 41 relative to the first material of the insulator layer 32. A bottommost backside cavity is formed in the volume from which the temporary material layer 41 is removed. The bottommost backside cavity is referred to herein as the source level backside recess 29. The source level backside recess 29 is a backside cavity located at the source level (i.e., the level at which the source region will be subsequently formed). In one embodiment, the material of the temporary material layer 41 can be selectively removed with respect to the first material of the insulator layer 32 and the material of the insulating spacer 74.

[0189] The etching process for selectively removing the material of the temporary material layer 41 for the first material may be a wet etching process using a wet etching solution, or may be a vapor phase (dry) etching process in which an etchant is introduced into the backside trench 79 in a vapor phase. For example, if the temporary material layer 41 includes silicon nitride, the etching process may be a wet etching process in which the exemplary structure is immersed in a wet etching bath including phosphoric acid, which selectively etches silicon nitride for silicon oxide, silicon, and various other materials used in the art. In another example, if the temporary material layer 41 includes germanium or a silicon-germanium alloy, the etchant may include a combination of hydrogen peroxide and dilute hydrofluoric acid.

[0190] refer to Fig.31 , a portion of each memory film 50 physically exposed to the source level backside recess 29 may be removed by at least one etching process, which may be a series of isotropic etching processes. The chemical properties of each isotropic etching process may be selected to sequentially remove the various materials of the memory film 50 from the outside to the inside. If each memory film 50 includes a ferroelectric material layer 154 and a front side gate dielectric 152, the first isotropic etching process may etch a portion of the ferroelectric material layer 154, and the second isotropic etching process may etch a portion of the front side gate dielectric 152. An annular dielectric material portion 50A including the remaining portion of the memory film 50 may be formed below each source region 30. The annular dielectric material portion 50A provides electrical isolation between the source region 30 and the underlying patterned conductive material layer 14.

[0191] Subsequently, electrical dopants may be introduced through cavity 79' and into the physically exposed portions of the sidewalls of each vertical semiconductor channel 60. The electrical dopants may be p-type dopants or n-type dopants. Exemplary p-type dopants include B, Ga, and In. Exemplary n-type dopants include P, As, and Sb. Each portion of the vertical semiconductor channel 60 into which the electrical dopants are introduced is converted into a source region 30.

[0192] The electrical dopants may be introduced into the physically exposed portions of the vertical semiconductor channels 60 by a plasma doping process and / or a vapor phase doping process. If a plasma doping process is used, the exemplary structure may be placed in a processing chamber in which a plasma of the electrical dopant is generated. Non-limiting examples of process gases from which the plasma may be generated include B2H6, PH3, AsH3, and SbH3. In the vapor phase doping process, the exemplary structure is placed in a processing chamber and subjected to a dopant gas at an elevated temperature, which may be, for example, in a range of 600 degrees Celsius to 1,000 degrees Celsius. The atomic concentration of the electrical dopant in each source region 30 may be in a range of 1.0×1019 / cm3 to 1.0×1021 / cm3, although smaller and larger atomic concentrations may also be used.

[0193] Within each memory opening, the source region 30 may have the same horizontal cross-sectional shape and area as the vertical semiconductor channel 60 overlying it. The source region 30 includes the same semiconductor material as the remainder of the vertical semiconductor channel 60, and also includes electrical dopants. In one embodiment, the composition of the source region 30 may differ from the composition of the vertical semiconductor channel 60 in that electrical dopant atoms are present in the source region 30, while the vertical semiconductor channel 60 is substantially free of electrical dopants or is doped with electrical dopants of opposite conductivity to the dopants of the source region 30. Additionally, the composition of the drain region 63 may differ from the composition of the vertical semiconductor channel 60 in that electrical dopant atoms are present in the drain region 63, while the vertical semiconductor channel 60 is substantially free of electrical dopants or is doped with electrical dopants of opposite conductivity to the dopants of the source region 30. In one embodiment, the source region 30 and the drain region 63 within the same memory opening may have the same lateral thickness, and may have substantially the same horizontal cross-sectional area. The source region 30 and the drain region 63 may have the same type of doping. For example, the source region 30 and the drain region 63 may be n-doped, or the source region 30 and the drain region 63 may be p-doped. The vertical semiconductor channel 60 may be p-doped, n-doped, or intrinsic.

[0194] refer to Fig.32A and Fig.32B, the conductive material may be deposited in the cavity 79' within the source level backside recess 29 and the backside contact groove 79, and deposited above the top surface of the dielectric cap layer 67. The conductive material may be deposited by a conformal deposition method, which may be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), chemical plating, electroplating, or a combination thereof. The conductive material may be an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal semiconductor alloy such as a metal silicide, an alloy thereof, and a combination or stack thereof. In one embodiment, the conductive material may include a metal such as tungsten and / or a metal nitride. In one embodiment, the conductive material for filling the cavity 79' within the source level backside recess 29 and the backside contact groove 79 may be selected from tungsten and a combination of titanium nitride and tungsten. In one embodiment, the conductive material may be deposited by chemical vapor deposition.

[0195] Excess portions of the conductive material deposited above the top surface of the dielectric cap layer 67 may be removed by a planarization process, which may be a chemical mechanical planarization (CMP) process and / or a recess etching process. A source electrode 26 may be formed in each source level backside recess 29 and backside contact via structure 176. Each source electrode 26 contacts the source region 30. Each source electrode 26 is formed directly on the source region 30 and the annular dielectric material portion 50A. The source electrode 26 may laterally surround the source region 30 and contact the entire outer perimeter of the source region 30.

[0196] The dielectric material portion including the annular unetched portion 50A of the memory film 50 may exist between the source region 30 and the underlying conductive material layer 14. A plurality of conductive material layers 14 may be provided. The conductive material layer 14 may be below a single memory stack structure 55, a plurality of memory stack structures 55 located between a pair of adjacent backside contact via structures 176, or a plurality of memory stack structures 55 located in an area including more than two backside contact via structures 176. The width of each portion of the conductive material layer 14 may correspond to the width of a word line finger F between a pair of adjacent backside contact via structures 176, or may correspond to the width of a block B including a plurality of backside contact via structures 176.

[0197] In one embodiment, the backside trench and the backside contact via structures 176 may extend laterally along the first horizontal direction hd1, and each of the insulating layers 32 may be divided into insulating strips 32 extending laterally along the first horizontal direction hd1 and laterally spaced apart along the second horizontal direction hd2. In addition, the conductive layer 46 may have the shape of conductive strips 46 extending laterally along the first horizontal direction hd1 and laterally spaced apart along the second horizontal direction hd2.

[0198] refer to Fig.33A and Fig.33B , a contact cavity including a set of stepped surfaces may be formed in the contact region 300 of the second exemplary structure, for example, by repeating a vertical anisotropic etching process and a horizontal opening expansion process (such as trimming). The contact region 300 is adjacent to the device region 100, which includes the memory stack structure and the backside contact through-hole structure 46 in the memory opening. The contact cavity may be filled with a backward stepped dielectric material portion 65, which is a dielectric material portion whose lateral extent is larger at a level away from the substrate 10 than at a level close to the substrate 10. The backward stepped dielectric material portion 65 may be formed by depositing a dielectric material such as silicon oxide, organic silicate glass, silicon nitride, or a combination thereof into the contact cavity, and removing excess portions of the deposited dielectric material from above a horizontal plane including the top surface of the dielectric cap layer 67 by a planarization process. The planarization process may use a chemical mechanical planarization process (CMP) or a recess etching process.

[0199] A via level dielectric layer 70 may be formed over the dielectric capping layer 67 and the backside contact via structure 176. The via level dielectric layer 70 includes an interlayer dielectric material such as silicon oxide, silicon nitride, and organosilicate glass. The via level dielectric layer 70 may have a thickness in the range of 30 nm to 1,000 nm, although lesser and greater thicknesses may also be used.

[0200] Various contact via structures may be formed by the via level dielectric layer 70 and the underlying material layers. The various contact via structures may include at least one source contact via structure 181 that contacts the top surface of the backside contact via structure 176, and a drain contact via structure 73 that contacts the top surface of the drain region 63. The depth of each via cavity for the drain contact via structure 73 may be controlled so that the bottom surface of the via cavity for the drain contact via structure 73 is formed above the topmost surface of the backside gate electrode 64. Each remaining portion of the dielectric capping layer 67 that remains above the gate electrode 64 is referred to herein as a dielectric capping portion 67C. Each dielectric capping portion 67C has the same composition as the remaining portion of the dielectric capping layer 67 that is present above the alternating stack (32, 46) of the insulator layer 32 and the conductive layer 46. The bottom surface of the drain contact via structure 73 may contact the top surface of the dielectric capping portion 67C and the annular top surface of the drain region 63. The top surface of the backside gate electrode 64 may contact the bottom surface of the dielectric capping portion 67C.

[0201] The additional contact via structures (8C, 14C) may be formed through one of the via level dielectric layer 70, the dielectric cap layer 67, and the backward stepped dielectric material portion 65, and reach the top surface of the conductive layer 46 or at least one conductive material layer 14. Each control electrode contact via structure 8C may contact or be electrically connected to the conductive layer 46, and is electrically isolated from the source electrode 26 and other conductive lines 46 located at different levels. Each back gate contact via structure 14C may contact or be electrically connected to at least one conductive material layer 14, and is electrically isolated from the source electrode 26 and the conductive line 46. The back gate contact via structure 14C and the conductive material layer 14 provide a conductive path to the backside gate electrode 64, so that a backside bias voltage can be applied during the operation of each memory stack structure. In one embodiment, the additional contact via structures (8C, 14C) may be formed in the same deposition step by depositing the same conductive material and removing excess portions of the deposited conductive material from the top surface of the via level dielectric layer 70.

[0202] A line-level dielectric layer 80 may be formed over the via-level dielectric layer 70. The line-level dielectric layer 80 includes an interlayer dielectric material such as silicon oxide, silicon nitride, and organosilicate glass. The thickness of the line-level dielectric layer 80 may be in the range of 30 nm to 1,000 nm, although smaller and larger thicknesses may also be used.

[0203] Various conductive line structures (83, 186, 88) may be formed by the line-level dielectric layer 80. The various conductive line structures (83, 186, 88) may include at least one source line 186 contacting a top surface of the source contact via structure 181, at least one drain line 83 (i.e., a bit line) contacting a top surface of the drain contact via structure 73, a gate control line 88 contacting a corresponding control electrode contact via structure 8C, and a back gate control line 89 contacting a back gate contact via structure 14C.

[0204] The second exemplary structure is a monolithic three-dimensional memory structure, which includes: a stack (32, 46) including a plurality of alternating insulator layers 32 and conductive layers 46, a memory opening 49 extending through the stack (32, 46), and a pillar structure (64, 62, 60, 63, 30, 50) located within the memory opening and including a back gate electrode 64 and a set of nested layers laterally surrounding the back gate electrode 64. The set of nested layers includes, from the inside to the outside, a back gate dielectric 62, a vertical semiconductor channel 60, and a memory film 50. The patterned conductive material layer 14 may contact the bottom surface of the back gate electrode 64. The patterned conductive material layer 14 may be electrically isolated from the vertical semiconductor channel 60.

[0205] The second exemplary structure may also include an annular dielectric material portion 50A having the same composition as the memory film 50 and contacting the outer sidewall of the back gate dielectric 62. The patterned conductive material layer 14 may contact the bottom surface of another back gate electrode 64 located within another memory opening through the stack (32, 46). The dielectric material portion 13 may be included within the upper portion of the substrate 10 and may contact the bottom surface of the patterned conductive material layer 14.

[0206] Dielectric capping portion 67C may contact a top surface of backside gate electrode 64, and drain region 63 may contact a top surface of vertical semiconductor channel 60 and a surface of dielectric capping portion 67C. Drain region 63 may have a ring shape and may contact a sidewall of dielectric capping portion 67C.

[0207] The source region 30 may be adjacent to a bottom portion of the vertical semiconductor channel 60 and may laterally surround a portion of the backside gate dielectric 62. The source electrode 26 may contact and laterally surround the source region 30. The source electrode 26 is located above the substrate 10. The source electrode 26 may be below the alternating stack (32, 46), and the backside contact via structure 176 may extend through the alternating stack (32, 46) and contact the source electrode 26. In one embodiment, the source region 30 may have the same horizontal cross-sectional shape as the vertical semiconductor channel 60 and may be laterally spaced apart from the backside gate electrode 64 by the backside gate dielectric 62.

[0208] refer to Fig.34 , shows an alternative embodiment of the second exemplary structure, which can be derived from the second exemplary structure by omitting the processing step for introducing Fig.26 The electrical dopant shown converts the top portion of the vertical semiconductor channel 60 into a drain region 63. Therefore, the drain region 63 does not exist. Figures 26 to 32B 60. After forming the via-level dielectric layer 70 and the via cavities therethrough, the top surface of each vertical semiconductor channel 60 is physically exposed at the bottom surfaces of the various via cavities. Doped semiconductor material may be deposited within the via cavities and above the via-level dielectric layer 70. The deposited doped semiconductor material may be patterned, for example, by a planarization process that may use chemical mechanical planarization (CMP) and / or recess etching. The remaining portion of the doped semiconductor material may form a drain region 163. Each drain region 163 contacts the top surface of the vertical semiconductor channel 60. The dielectric cap portion 67C may contact the bottom surface of the drain region 63 and the inner sidewall of the vertical semiconductor channel 60.

[0209] In an alternative embodiment of the second exemplary structure, each dielectric capping portion 67C may be formed over the backside gate electrode 64 and on the inner sidewalls of the vertical semiconductor channel 60. Each drain region 163 may be formed over the dielectric capping portion 67C and on the top surface of the dielectric capping portion and the top surface of the vertical semiconductor channel 60 by depositing and patterning a doped semiconductor material. Additional structures such as a line-level dielectric layer 80 and a conductive line structure (83, 186, 88) may be formed on the backside gate electrode 64 and on the inner sidewalls of the vertical semiconductor channel 60. Fig.33A and Fig.33B The second exemplary structure is shown.

[0210] With reference to all the accompanying drawings and in accordance with various embodiments of the present disclosure, a three-dimensional memory device is provided, comprising: an alternating stack of insulator layers 32 and conductive layers 46, the alternating stack being located above a top surface of a substrate (8 or 10); a memory stack structure (155 or 55), the memory stack structure vertically extending through the alternating stack (32, 46) and comprising a ferroelectric material layer 154, a front gate dielectric 152 contacting the ferroelectric material layer 154, and a vertical semiconductor channel (160 or 60) contacting the front gate dielectric 152; a back gate dielectric (162 or 62), the back gate dielectric contacting the vertical semiconductor channel (160 or 60); and a back gate electrode (164 or 64), the back gate electrode contacting the back gate dielectric (162 or 62).

[0211] In one embodiment, the memory stack structure 55 is located within an opening 49 that extends through the alternating stack (32, 46) and has a generally cylindrical shape; and each of the ferroelectric material layer 154, the front gate dielectric 152, the vertical semiconductor channel 60, and the back gate dielectric 62 has a corresponding generally annular cylindrical shape.

[0212] In some embodiments, each of the ferroelectric material layer 154, the front gate dielectric 152, the vertical semiconductor channel (160 or 60), and the back gate dielectric (162 or 62) extends vertically from a first horizontal plane including a bottom surface of a bottommost conductive layer in the conductive layer 46 to a second horizontal plane including a top surface of a topmost conductive layer in the conductive layer 46.

[0213] In one embodiment, the source region 30 may contact the bottom end of the vertical semiconductor channel 60 , and the drain region 63 may contact the top end of the vertical semiconductor channel 60 .

[0214] In one embodiment, the source region 30 has a first annular shape and laterally surrounds the back gate electrode 64 and is contacted by the source electrode 26 located below the alternating stack (32, 46); and the bottom surface of the back gate electrode 64 contacts the top surface of the patterned conductive material layer 14 located below the source electrode 26.

[0215] Reference Fig.35 , shows a hysteresis curve of the ferroelectric polarization P of a ferromagnetic material (e.g., hafnium oxide) as a function of the applied external voltage V. In a programming scheme utilizing the Fig.35 hysteresis characteristics shown, the ferroelectric state corresponding to the programming state "0" originates from the immediately preceding state having a positive ferroelectric saturation polarization Ps1 without subsequent exposure to a negative programming voltage. The ferroelectric state corresponding to the programming state "1" originates from the immediately preceding state having a negative ferroelectric saturation polarization Ps0 without subsequent exposure to a positive programming voltage. The positive ferroelectric remanent polarization Pr1 is the positive polarization retained after the positive voltage that caused the positive ferroelectric saturation polarization Ps1 is turned off. The negative ferroelectric remanent polarization Pr0 is the negative polarization retained after the negative voltage that caused the negative ferroelectric saturation polarization Ps1 is turned off. The negative coercive voltage Vc1 is the negative voltage that, when applied, results in zero ferroelectric polarization after the state of positive ferroelectric saturation polarization Ps1. The positive coercive voltage Vc0 is the positive voltage that, when applied, results in zero ferroelectric polarization after the state of negative ferroelectric saturation polarization Ps0.

[0216] During a read operation in a vertical ferromagnetic NAND string cell array used in devices of various embodiments, each portion of the vertical semiconductor channel (160 or 60) adjacent to the conductive layer 46 has a threshold voltage Vth. A pass voltage Vpass will be applied to each unselected conductive layer 46 to ensure that the portions of the vertical semiconductor channel (160 or 60) adjacent to the unselected conductive layer 46 are turned on. The vertical field effect transistor including the vertical semiconductor channel (160 or 60) should operate in the saturation state. In addition, the pass voltage should be applied in a manner that avoids inverting the ferroelectric polarization at the level of the unselected conductive layer 46. Keeping the pass voltage Vpass less than the coercive voltage Vc prevents an accidental flip of the ferroelectric polarization at the unselected level. In summary, various embodiments allow the following conditions to be met:

[0217] a) Vth << Vpass;

[0218] b) Vpass << Vth + VDS (source-drain voltage); and

[0219] c) Vpass << Vc.

[0220] Generally speaking, the pass voltage Vpass of the unselected level for switching on the vertical semiconductor channel is greater than the coercive voltage Vc of the ferroelectric material. Therefore, the ferroelectric memory device in the conventional vertical NAND configuration, in which the switching on the vertical semiconductor channel of the unselected level depends only on the pass voltage applied to the word line, is inoperable due to the incidental polarization switching. In other words, an attempt to read the polarization state of the selected level results in the switching of the polarization state of the unselected level in the ferroelectric memory device in the conventional vertical NAND configuration.

[0221] According to one aspect of the present disclosure, the back gate electrode (164 or 64) applies an additional bias voltage to enable the portion of the vertical semiconductor channel (160, 60) located at the unselected level to be turned on. Therefore, when the pass voltage Vpass applied at the conductive layer 46 is less than the threshold voltage Vth of the vertical semiconductor channel (160, 60), the back bias voltage VBG applied to the back gate electrode (164, 64) turns on the unselected portion of the vertical semiconductor channel (160, 60). The pass voltage Vpass applied at the conductive layer 46 is less than the coercive voltage Vc of the ferroelectric material of the ferroelectric material layer 154, so the reversal of the ferromagnetic state does not occur at the unselected level.

[0222] Fig.36A and Fig.36B An inversion layer is shown formed in a vertical semiconductor channel (160, 60) during sensing of a selected ferroelectric memory cell by applying a back bias voltage VBG to a back gate electrode (164, 64). A source side select gate (SGS) and a drain side select gate (SGD) are shown, which can be implemented as a bottommost conductive layer 46 and a topmost conductive layer, respectively. A suitable source side select voltage VSGS and a suitable drain side select voltage VSGD can be applied to activate a selected ferroelectric memory vertical NAND cell. Although more than four levels (such as 8-1,024 levels) of ferroelectric memory cells can exist in a ferroelectric memory vertical NAND cell, only three levels are shown for schematic illustration. Specifically, a selected level is shown, which corresponds to a selected ferroelectric memory element located in a portion of a ferroelectric material layer 154 adjacent to a conductive layer 46, which corresponds to a word line of the selected ferroelectric memory element. Fig.36A The case where a selected level is programmed in the "erased" state is shown. Fig.36B The selected level is shown being programmed in the "Programmed" state. The unselected levels are shown in the "Erassed" state, which indicates the state of each ferroelectric memory element in the "Erassed" state. The unselected levels are shown in the "Programmed" state, which indicates the state of each ferroelectric memory element in the "Programmed" state.

[0223] To sense the ferroelectric state of a selected ferroelectric memory element, a sensing voltage of about (Vc0+Vc1) / 2 is applied to the conductive layer 46 of the word line corresponding to the selected ferroelectric memory element. An unselected gate voltage or pass voltage of about Vc1 (or less) is applied to each conductive layer 46 of the word line corresponding to the unselected ferroelectric memory element. A backside bias voltage VBG significantly higher than the threshold voltage Vth is applied to the backside gate electrode (164, 64). If the selected ferroelectric memory element is in a state such as Fig.36A In the "erased" state shown, the polarization of the portion of the ferroelectric material layer 154 at the selected level is about Pr1. The vertical semiconductor channel (160, 60) is turned off at the selected level, and the state "0" is detected for the selected ferroelectric memory element. If the selected ferroelectric memory element is in the "erased" state Figure 3 In the "programmed" state shown in B6, the polarization of the portion of the ferroelectric material layer 154 at the selected level is about Pr0. The vertical semiconductor channel (160, 60) is turned on at all levels and state "1" is detected for the selected ferroelectric memory element.

[0224] Various embodiments of the present disclosure provide a three-dimensional memory device that utilizes ferroelectrics to provide advantages in scalability, exhibiting small coercive fields and voltages within thin dielectrics, thereby providing low voltage switches that are not prone to unexpected polarization reversals. Various embodiments enable unselected transistors to be turned on without causing the associated ferroelectric layer to undergo polarization reversals. Various embodiments also enable detection of the difference between the drain-source current IDS between an "erased" state and a "programmed" state.

[0225] The number of levels that can be stacked in a three-dimensional memory device depends on the thickness uniformity of the ferroelectric material layer 154 throughout the device. In some embodiments, the ferroelectric material layer 154 may include and / or consist essentially of hafnium oxide, which may be easily deposited using a conformal deposition process such as atomic layer deposition. Thus, a ferroelectric memory device in a three-dimensional NAND array configuration may be provided.

[0226] Although specific preferred embodiments are mentioned above, it will be understood that the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Embodiments using specific structures and / or configurations are shown in the present disclosure, and it should be understood that the claims may be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A three-dimensional memory device, comprising: an alternating stack of insulating strips and conductive strips, the alternating stack being located above the substrate and laterally spaced apart from one another by line trenches, wherein the line trenches extend laterally along a first horizontal direction and are spaced apart along a second horizontal direction; and a line trench filling structure located in the line trench, wherein each of the line trench filling structures comprises a respective group of memory stack structures, and each group of memory stack structures comprises a respective row of discrete memory stack structures arranged along the first horizontal direction, a backside gate dielectric contacting each memory stack structure within the respective group of memory stack structures, and a backside gate electrode contacting the backside gate dielectric, Each memory stack structure includes a ferroelectric material layer, a front gate dielectric contacting the ferroelectric material layer, and a vertical semiconductor channel contacting the front gate dielectric and the back gate dielectric, and Each of the line trench filling structures comprises a laterally undulating dielectric rail contacting the backside gate electrode, extending laterally along the first horizontal direction, and comprising a laterally alternating sequence of neck regions and ball-shaped regions, the neck regions having a smaller width than the ball-shaped regions along the second horizontal direction.

2. A three-dimensional memory device according to claim 1, wherein each of the ferroelectric material layer, the front side gate dielectric and the vertical semiconductor channel extends from a first horizontal plane to a second horizontal plane, the first horizontal plane includes the bottom surface of the bottommost conductive strip in the alternating stack of the conductive strips, and the second horizontal plane includes the top surface of the topmost conductive strip in the alternating stack of the conductive strips.

3. The three-dimensional memory device of claim 1 , wherein each of the backside gate electrodes extends laterally along the first horizontal direction and is configured to apply a backside bias voltage to each of the vertical semiconductor channels within a corresponding one of the line trench filling structures.

4. The three-dimensional memory device according to claim 1, wherein: Each of the backside gate electrodes has a laterally undulating profile; The ferroelectric material layer includes hafnium oxide; and The conductive strip contacts a sidewall of the ferroelectric material layer. 5 . The three-dimensional memory device of claim 1 , wherein the backside gate dielectric comprises a continuous layer that contacts each memory stack structure within a respective group of the memory stack structures.

6. The three-dimensional memory device of claim 1, wherein the backside gate electrode is laterally spaced apart from each memory stack structure within a corresponding group of the memory stack structures by a lateral spacing that is the same as a thickness of the backside gate dielectric.

7. The three-dimensional memory device of claim 1, wherein each of the ferroelectric material layers is in direct contact with a corresponding backside gate dielectric.

8. The three-dimensional memory device according to claim 1, wherein: Each of the front side gate dielectrics is in direct contact with a respective gate dielectric; and Each backside gate dielectric is in direct contact with a corresponding plurality of the ferroelectric material layers of the three-dimensional memory device. 9 . The three-dimensional memory device of claim 1 , wherein each backside gate dielectric is in direct contact with a corresponding plurality of the vertical semiconductor channels of the three-dimensional memory device.

10. A three-dimensional memory device, comprising: an alternating stack of insulator layers and conductive layers, the alternating stack positioned above a top surface of the substrate; a memory stack structure extending vertically through the alternating stack and comprising a ferroelectric material layer, a front side gate dielectric contacting the ferroelectric material layer, and a vertical semiconductor channel contacting the front side gate dielectric; a backside gate dielectric, the backside gate dielectric contacting the vertical semiconductor channel; a back gate electrode contacting the back gate dielectric; a source region, the source region contacting a bottom end of the vertical semiconductor channel; A source electrode surrounds the source region, includes a conductive material different from that of the source region, contacts the annular bottom surface of the ferroelectric material layer, and is located below the alternating stack.

11. The three-dimensional memory device according to claim 10, wherein: The memory stack structure is located within an opening extending through the alternating stack and having a cylindrical shape; and Each of the ferroelectric material layer, the front side gate dielectric, the vertical semiconductor channel, and the back side gate dielectric has a corresponding annular cylindrical shape.

12. A three-dimensional memory device according to claim 10, wherein each of the ferroelectric material layer, the front gate dielectric, the vertical semiconductor channel and the back gate dielectric extends vertically from a first horizontal plane to a second horizontal plane, the first horizontal plane includes the bottom surface of the bottommost conductive layer in the conductive layers, and the second horizontal plane includes the top surface of the topmost conductive layer in the conductive layers. 13 . The three-dimensional memory device according to claim 10 , further comprising a drain region contacting a top end of the vertical semiconductor channel.

14. The three-dimensional memory device according to claim 13, wherein: The source region has a first annular shape and laterally surrounds the back gate electrode; and A bottom surface of the backside gate electrode contacts a top surface of the patterned conductive material layer below the source electrode. 15 . The three-dimensional memory device of claim 10 , wherein a top surface of the source electrode contacts a bottom surface of an insulating layer within the alternating stack. 16 . The three-dimensional memory device of claim 10 , further comprising a conductive material layer contacting a bottom surface of the backside gate electrode. 17 . The three-dimensional memory device of claim 16 , wherein the conductive material layer is located below the source region and the source electrode and is vertically spaced apart from the source region by another insulating layer. 18 . The three-dimensional memory device of claim 10 , further comprising a backside contact via structure extending vertically through the alternating stacks and contacting the source electrode.

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