Electronic device with low refresh rate display pixels

Abstract

The invention is entitled "Electronic device with low refresh rate display pixels." A display is disclosed that can have an array of organic light emitting diode display pixels that operate at low refresh rates. Each display pixel can have six thin film transistors and a capacitor. One of the six transistors can be used as a drive transistor and the remaining five transistors and capacitor can be used for compensation. One or more bias stress operations can be applied prior to threshold voltage sampling to mitigate first frame dimming. Multiple anode reset and bias stress operations can be inserted during a vertical blanking period to reduce flicker and maintain balance and can also be inserted between successive data refreshes to improve first frame performance. Two different emission signals that control each pixel can be toggled back and forth using a pulse width modulation scheme to help provide a darker black level.

Description

[0001] This application is a divisional application of China Patent Application No. 201810937439.5, with an application date of August 17, 2018, and titled “Electronic Device with Low Refresh Rate Display Pixels.”

[0002] This application claims priority to U.S. Patent Application No. 15 / 996,366, filed June 1, 2018, and Provisional Patent Application No. 62 / 547,030, filed August 17, 2017, which are hereby incorporated by reference in their entirety. TECHNICAL FIELD

[0003] The present disclosure relates generally to electronic devices, and more particularly, to electronic devices with displays. BACKGROUND

[0004] Electronic devices often include displays. For example, cellular telephones and portable computers include displays for presenting information to a user.

[0005] Displays, such as organic light emitting diode displays, have an array of display pixels based on light emitting diodes. In this type of display, each display pixel includes a light emitting diode and a thin film transistor for controlling the application of a signal to the light emitting diode to produce light.

[0006] Variations in threshold voltage in thin film transistors can cause undesirable visible display artifacts. For example, threshold voltage hysteresis can cause white pixels to be displayed differently depending on context. A white pixel in a frame, for example, can be accurately displayed if it was a white pixel in the previous frame, but can be inaccurately displayed (i.e., it can have a gray appearance) if it was a black pixel in the previous frame. This type of history dependent behavior of the light output of display pixels in a display causes the display to exhibit low response times. To address problems associated with threshold voltage variations, displays such as organic light emitting diode displays are provided with threshold voltage compensation circuits. However, such circuits can not adequately address all threshold voltage variations, can not satisfactorily improve response times, and can have designs that are difficult to implement. SUMMARY

[0007] An electronic device can include a display having an array of display pixels. The display pixels can be organic light emitting diode display pixels. Each display pixel can include a light emitting diode, a power line, a data line, an initialization line, a first transistor having a source terminal and a drain terminal coupled to the data line, a second transistor having a drain terminal, a gate terminal, and a source terminal coupled to the source terminal of the first transistor, a third transistor coupled between the drain terminal and the gate terminal of the second transistor, a fourth transistor coupled between the power line and the second transistor, a fifth transistor coupled between the second transistor and the light emitting diode, a sixth transistor coupled between the initialization line and the light emitting diode, and a storage capacitor coupled in series between the third transistor and the sixth transistor.

[0008] The third transistor has a gate terminal that receives a first scan signal. The sixth transistor has a gate terminal that receives the first scan signal. The first transistor has a gate terminal that receives a second scan signal that is different than the first scan signal. The fifth transistor has a gate terminal that receives a first emission signal. The fourth transistor has a gate terminal that receives a second emission signal that is different than the first emission signal.

[0009] The display pixels can be refreshed using a four-phase refresh scheme that includes an initialization phase during which only the first scan signal and the second emission signal are asserted, a bias stress phase during which only the second scan signal is asserted, a threshold voltage sampling and data write phase during which only the first scan signal and the second scan signal are asserted, and an emission phase during which only the first emission signal and the second emission signal are asserted. Performing the bias stress phase prior to the threshold voltage sampling and data write phase can help mitigate threshold voltage hysteresis of the second transistor, which can prevent the first frame from dimming (e.g., preventing a significant dimming in brightness when the pixel is transitioning from displaying a black level to a white level).

[0010] This type of display pixel can also be suitable for operation at a low refresh rate (e.g., 1 Hz, 2 Hz, etc.) where the vertical blanking period is at least ten times longer than the data refresh period. Multiple anode reset operations can be inserted during the vertical blanking period to help reduce flicker. Additional bias stress operations can be performed during the vertical blanking period along with the anode reset operations to help balance transistor stress. When the display pixel is transitioning from black to white (or from one gray scale to another), multiple data refreshes and multiple anode resets (with bias stress) can be applied to help provide faster threshold voltage settling and improved first frame performance. Pulse width modulation (PWM) schemes can also be used to simultaneously toggle the first emission control signal and the second emission control signal back and forth to control the brightness of the display while reducing leakage. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1is a schematic diagram of an exemplary display such as an organic light emitting diode display having an array of organic light emitting diode display pixels according to one embodiment.

[0012] Figure 2 is a circuit diagram of an exemplary display driver circuit according to one embodiment.

[0013] Figure 3 is a schematic diagram of a low refresh rate display driving scheme according to one embodiment.

[0014] Figure 4 is a circuit diagram of an exemplary organic light emitting diode display pixel according to one embodiment.

[0015] Figure 5 is a timing diagram showing how bias stress is applied prior to threshold voltage sampling according to one embodiment.

[0016] Figures 6A-6D is a schematic diagram showing the configuration of a display pixel of Figure 4 during four different phases shown in Figure 5 .

[0017] Figure 7 is a schematic diagram showing the thin film transistor hysteresis effect that causes a first frame to dim according to one embodiment.

[0018] Figure 8A is a timing diagram showing how one or more anode reset operations are performed during an extended blanking period according to one embodiment.

[0019] Figure 8B is a timing diagram showing the behavior of relevant signals during an anode reset operation shown in Figure 8A according to one embodiment.

[0020] Figure 9A and Figure 9B is a schematic diagram showing the configuration of a display pixel of Figure 4 during two different phases shown in Figure 8B .

[0021] Figure 10 is a timing diagram showing how bias stress is applied prior to an anode reset during an extended blanking period according to one embodiment.

[0022] Figures 11A-11D is a schematic diagram showing the configuration of a display pixel of Figure 4 during different phases shown in Figure 10 .

[0023] Figure 12 This is a schematic diagram illustrating how, according to one implementation scheme, multiple anode reset and bias stress operations can be inserted during a multi-refresh-driven scheme to help reduce the darkening of the first frame.

[0024] Figure 13 This is a timing diagram illustrating how, according to one implementation, the first and second transmit signals are switched back and forth simultaneously to help mitigate the problem of bad smudges during the data refresh phase.

[0025] Figure 14 This is a timing diagram illustrating how, according to one embodiment, the first and second transmit signals can have different duty cycles only during the first PWM (pulse width modulation) cycle of the anode reset phase to help minimize leakage current. Detailed Implementation

[0026] Displays in electronic devices may be provided with driver circuitry for displaying images on the display pixel array. Figure 1 An example display is shown. For example... Figure 1 As shown, the display 14 may have one or more layers, such as a substrate 24. The layer, such as the substrate 24, may be formed from a planar rectangular layer of material, such as a planar glass layer. The display 14 may have an array of display pixels 22 for displaying images to a user. The array of display pixels 22 may be formed from rows and columns of display pixel structures on the substrate 24. These structures may include thin-film transistors, such as polysilicon thin-film transistors, semiconductor oxide thin-film transistors, etc. The array of display pixels 22 may have any suitable number of rows and columns (e.g., ten or more, one hundred or more, or one thousand or more).

[0027] Display driver circuits such as display driver integrated circuit 16 can be coupled to conductive paths such as metal traces on substrate 24 using solder or conductive adhesive. Display driver integrated circuit 16 (sometimes referred to as a timing controller chip) can include communication circuitry for communicating with system control circuitry over path 25. Path 25 can be formed by traces on a flexible printed circuit or other cable. System control circuitry can be located on a main logic board in an electronic device such as a cellular telephone, computer, television, set-top box, media player, portable electronic device, or other electronic device that is using display 14. During operation, system control circuitry can provide display driver integrated circuit 16 with information about an image to be displayed on display 14 via path 25. To display the image on display pixels 22, display driver integrated circuit 16 can provide clock signals and other control signals to display driver circuits such as row driver circuit 18 and column driver circuit 20. Row driver circuit 18 and / or column driver circuit 20 can be formed by one or more integrated circuits and / or one or more thin-film transistor circuits on substrate 24.

[0028] Row driver circuit 18 can be located on the left and right edges of display 14, on a single edge of display 14 only, or at other locations in display 14. During operation, row driver circuit 18 can provide row control signals on horizontal lines 28 (sometimes referred to as row lines or "scan" lines). Thus, row driver circuit 18 can sometimes be referred to as a scan line driver circuit. If desired, row driver circuit 18 can also be used to provide other row control signals.

[0029] Column driver circuit 20 can be used to provide data signals D from display driver integrated circuit 16 to a plurality of corresponding vertical lines 26. Column driver circuit 20 can sometimes be referred to as a data line driver circuit or a source driver circuit. Vertical lines 26 are sometimes referred to as data lines. During compensation operations, column driver circuit 20 can use paths such as vertical lines 26 to provide reference voltages. During programming operations, display data is loaded into display pixels 22 using lines 26.

[0030] Each data line 26 is associated with a respective column of display pixels 22. Multiple sets of horizontal signal lines 28 extend horizontally through display 14. Power paths and other lines can also provide signals to pixels 22. Each set of horizontal signal lines 28 is associated with a respective row of display pixels 22. The number of horizontal signal lines in each row can be determined by the number of transistors in display pixels 22 that are independently controlled by the horizontal signal lines. Different configurations of display pixels can be operated by different numbers of control lines, data lines, power lines, etc.

[0031] The row driver circuit 18 can assert control signals on the row lines 28 in the display 14. For example, the driver circuit 18 can receive clock and other control signals from the display driver integrated circuit 16 and can assert control signals in each row of display pixels 22 in response to the received signals. The rows of display pixels 22 can be processed sequentially, with processing for each frame of image data beginning at the top of the array of display pixels and ending at the bottom of the array (as one example). While a scan line in a row is being asserted, control signals and data signals provided to the column driver circuit 20 by the circuit 16 instruct the circuit 20 to demultiplex and drive the associated data signal D onto the data lines 26, so that the display pixels in the row will be programmed with the display data present on the data lines D. The display pixels are then able to display the loaded display data.

[0032] The column driver circuit 20 can output a data line signal containing gray scale information for multiple color channels such as red, green, and blue channels (see, e.g., FIG. 1). Figure 2 The column driver circuit 20 can output a data line signal containing gray scale information for multiple color channels such as red, green, and blue channels (see, e.g., FIG. 1). Figure 2 As shown in the example of FIG. 2, a display demultiplexer control circuit such as the display demultiplexer control circuit 58 in the column circuit 20 can be used to supply data line demultiplexer control signals R, G, and B (in this example corresponding to the red, green, and blue channels) to the gate terminals of the demultiplexing transistors 60. A data line driver 62 can generate data line output signals SOi, SO2... (sometimes referred to as source output signals) on data line paths 64. The source output signals contain analog pixel data for image pixels of all three colors (i.e., red, blue, and green). The control signals applied to the gates of the demultiplexing transistors 60 turn the transistors 60 on and off in a pattern that routes red channel information from the source output signals to the red data lines RDL, routes green channel information from the source output signals to the green data lines GDL, and routes blue channel information from the source output signals to the blue data lines BDL.

[0033] The optional loading circuit 66 can be implemented using one or more discrete components (e.g., capacitors, inductors, and resistors) inserted into the line 54, or can be implemented in a distributed manner using some or all of the structures that form the line 54. The optional loading circuit 66 and / or circuitry in the column driver circuit 20 (e.g., the circuit 58) can be used to control the shape of the demultiplexer control signals R, G, and B. Signal shaping techniques such as these can be used to smooth display control signal pulses (such as the demultiplexer control signal pulses) and thereby reduce harmonic signal generation and radio frequency interference.

[0034] In an organic light emitting diode display such as display 14, each display pixel includes a respective organic light emitting diode for emitting light. A drive transistor controls the amount of light output from the organic light emitting diode. Control circuitry in the display pixel is configured to perform threshold voltage compensation operations so that the intensity of the output signal from the organic light emitting diode is proportional to the size of a data signal loaded into the display pixel, independent of the threshold voltage of the drive transistor.

[0035] Display 14 can be configured to support low refresh rate operation. Operating display 14 using a relatively low refresh rate (e.g., a refresh rate of 1 Hz, 2 Hz, or other suitable low rate) can be suitable for applications that output content that is static or nearly static and / or applications that require minimal power consumption. Figure 3 is a schematic diagram of a low refresh rate display driving scheme in accordance with one embodiment. As shown in Figure 3 Display 14 can alternatively be between a short data refresh phase (as indicated by period T refresh) and an extended vertical blanking phase (as indicated by period T blank). As one example, in accordance with a 60 Hz data refresh operation, each data refresh period T refresh can be approximately 16.67 milliseconds (ms), while each vertical blanking period T blank can be approximately 1 second, such that the overall refresh rate of display 14 is reduced to 1 Hz. Configured in this manner, T blank can be adjusted to tune the overall refresh rate of display 14. For example, if the duration of T blank is tuned to half a second, the overall refresh rate will increase to approximately 2 Hz. In embodiments described herein, the duration of T blank can be at least two times, at least ten times, at least 30 times, or at least 60 times longer than the duration of T refresh (as an example).

[0036] Figure 4 A schematic diagram of an illustrative organic light emitting diode display pixel 22 that can be used in display 14 to support low refresh rate operation is shown in Figure 4 As shown in

[0037] In one suitable arrangement, transistor T3 can be implemented as a semiconductor oxide transistor, while the remaining transistors T1, T2, and T4-T6 are silicon transistors. Semiconductor oxide transistors exhibit lower leakage current relative to silicon transistors, so implementing transistor T3 as a semiconductor oxide transistor will help reduce flicker at low refresh rates (e.g., by T3 preventing current leakage).

[0038] In another suitable arrangement, transistors T3 and T6 can be implemented as semiconductor oxide transistors, while the remaining transistors T1, T2, T4, and T5 are silicon transistors. Since both transistors T3 and T6 are controlled by the signal Scanl, forming them as the same transistor type can help simplify manufacturing.

[0039] In another suitable arrangement, transistors T3, T6, and also T2 can be implemented as semiconductor oxide transistors, while the remaining transistors T1, T4, and T5 are silicon transistors. Transistor T2 functions as a drive transistor, and has a threshold voltage that is critical to the emission current of pixel 22. As discussed below in connection with at least Figure 7 threshold voltage of a drive transistor can occur. Thus, forming a drive transistor as a top-gate semiconductor oxide transistor can help reduce hysteresis (e.g., a top-gate IGZO transistor experiences less Vth hysteresis than a silicon transistor). If desired, all of the transistors T1 -T6 can be semiconductor oxide transistors. In addition, any one or more of the transistors T1 -T6 can be a p-type (i.e., p-channel) thin-film transistor.

[0040] Display pixel 22 can include a light-emitting diode 304. A positive supply voltage VDDEL can be supplied to positive supply terminal 300, and a ground supply voltage VSS EL (e.g., 0 volts or other suitable voltage) can be supplied to ground supply terminal 302. The state of drive transistor T2 controls the amount of current flowing from terminal 300 to terminal 302 through diode 304, and thus controls the amount of emitted light 306 from display pixel 22. Diode 304 can have an associated parasitic capacitance C OLED (not shown).

[0041] Terminal 308 is used to provide an initialization voltage Vini (e.g., a negative voltage such as -1 V or -2 V or other suitable voltage) to help turn off diode 304 when diode 304 is not in use. From time to time, a signal such as Figure 1The control signals for the display driver circuit of the line driver circuit 18 are provided to control terminals, such as terminals 312, 313, 314, and 315. Terminals 312 and 313 can be used as first scan control terminals and second scan control terminals, respectively, while terminals 314 and 315 can be used as first transmit control terminals and second transmit control terminals, respectively. Scan control signals Scan1 and Scan2 can be applied to scan terminals 312 and 313, respectively. Transmit control signals EM1 and EM2 can be supplied to terminals 314 and 315, respectively. Data input terminals, such as data signal terminal 310, are coupled to... Figure 1 The corresponding data line 26 shown is used to receive image data for display pixels 22.

[0042] exist Figure 4 In the example, transistors T4, T2, T5, and diode 304 may be connected in series between power supply terminals 300 and 302. Specifically, transistor T4 may have a drain terminal coupled to the positive power supply terminal 300, a gate terminal for receiving the transmit control signal EM2, and a source terminal (labeled Node1). The terms "source" and "drain" terminals of a transistor are sometimes used interchangeably and may therefore be referred to herein as "source-drain" terminals. Driver transistor T2 may have a gate terminal (labeled Node2), a source terminal (labeled Node3), and a drain terminal coupled to Node1. Transistor T5 may have a drain terminal coupled to Node3, a gate terminal for receiving the transmit control signal EM1, and a source terminal (labeled Node4) coupled to the ground power supply terminal 302 via diode 304.

[0043] Transistor T3, capacitor Cst, and transistor T6 can be connected in series between Node 1 and power supply terminal 308. Transistor T3 may have a drain terminal coupled to Node 1, a gate terminal for receiving scan control signal Scan 1, and a source terminal coupled to Node 2. Storage capacitor Cst may have a first terminal coupled to Node 2 and a second terminal coupled to Node 4. Transistor T6 may have a drain terminal coupled to Node 4, a gate terminal for receiving scan control signal Scan 1, and a source terminal for receiving voltage Vini through terminal 308. Transistor T1 may have a drain terminal for receiving data line signal DL through terminal 310, a gate terminal for receiving scan control signal Scan 2, and a source terminal coupled to Node 3. With this connection, signal EM2 can be asserted to enable transistor T4. Signal EM1 can be asserted to activate transistor T5; signal Scan 2 can be asserted to turn on transistor T1; and signal Scan 1 can be asserted to switch to using transistors T3 and T6.

[0044] During the data refresh cycle, the display pixel 22 can operate in at least four phases: (1) reset / initialization phase, (2) bias stress phase, (3) threshold voltage sampling and data writing phase, and (4) emission phase. Figure 5 It is a timing diagram showing the relevant signal waveforms that can be applied to display pixel 22 during the four stages of the data refresh operation.

[0045] At time t1 (at the start of the initialization phase), signal Scan1 can be pulsed high, and signal EM1 can be deasserted (e.g., pushed low) while signal Scan2 is low and signal EM2 is high. Figure 6A The configuration of pixel 22 during this time period is shown. (As shown) Figure 6A As shown, only transistors T3, T4, and T6 are turned on (because signals Scan1 and EM2 are asserted), so the first terminal of capacitor Cst is charged to VDDEL, and the second terminal of capacitor Cst is pulled low to Vini. During the initialization phase, the voltage across capacitor Cst is thus reset to a predetermined voltage difference (VDDEL - Vini). Node 3 can also be charged high to (VDDEL - Vth2), where Vth2 is the threshold voltage of transistor T2.

[0046] At time t2, signal Scan1 decreases, signal Scan2 is asserted (e.g., pushed up), and signal EM2 is deasserted (e.g., pushed down), which indicates the end of the initialization phase and the beginning of the bias stress phase. Figure 6B The configuration of pixel 22 during this time period is shown. (As shown) Figure 6B As shown, only transistors T1 and T2 are turned on (because during the initialization phase, signal Scan2 is high and Node2 is charged). With this configuration, Node2 is held at VDDEL, and Node3 will be biased to Vdata using transistor T1. In other words, the gate-to-source voltage Vgs of transistor T2 will be set to (VDDEL - Vdata). Vdata is at least partially applied to transistor T2 before any threshold voltage is sampled.

[0047] At time t3, the signal Scan1 is pulsed high, which indicates the end of the bias stress phase and the start of the threshold voltage Vth sampling and data writing phase. Figure 6C The configuration of pixel 22 during this time period is shown. (As shown) Figure 6CAs shown, only transistors T1, T2, and T6 are turned on (because signals Scan1 and Scan2 are asserted). With this configuration, Node1 and Node2 will be pulled low from VDDEL to (Vdata + Vth2), while Node3 is set to Vdata. In other words, the gate-to-source voltage Vgs of transistor T2 will be set to Vth2 (i.e., Vdata + Vth2 - Vdata, where Vdata is canceled out). The voltage across capacitor Cst is (Vdata + Vth2 - Vini). At time t4, Scan1 and Scan2 are deasserted, indicating the end of the threshold voltage and data write phase.

[0048] At time t5, signals EM1 and EM2 are asserted, indicating the start of the transmission phase. Figure 6D The configuration of pixel 22 during this time period is shown. (As shown) Figure 6D As shown, transistors T2, T4, and T5 are turned on to allow emitter current 650 to flow through diode 304. The gate-to-source voltage Vgs of transistor T2 will be set by the voltage across the storage capacitor Cst, which was previously set to (Vdata + Vth2 - Vini) during the data write phase. Since emitter current 650 is proportional to (Vgs - Vth2), it will be independent of Vth2, as Vth2 is canceled out when Vth2 is subtracted from (Vdata + Vth2 - Vini).

[0049] In certain situations, the threshold voltage Vth2 can be shifted, such as when the display 14 transitions from a black image to a white image or from one grayscale to another. This shift in Vth2 (sometimes referred to in this text as thin-film transistor "hysteresis") can cause a decrease in brightness, also known as "first-frame dimming." TFT hysteresis in... Figure 7 As shown in the image. Figure 7 As shown, curve 700 represents the saturation current Id waveform as a function of Vgs of transistor T2 for the black frame, while curve 704 represents the target Id waveform as a function of Vgs of transistor T2 for the white frame. Without bias stress, the sampled Vth' corresponds to the black frame and will therefore deviate considerably from the target curve 702. By applying bias stress, the sampled Vth' will correspond to Vdata and will therefore be much closer to the target curve 702 (see curve 702 achieved by applying bias stress). Performing a bias stress stage before sampling Vth2 to bias the Vgs of transistor T2 through Vdata can thus help mitigate hysteresis and prevent the first frame from darkening.

[0050] Another problem that may arise when operating the display 14 at a low refresh rate is that the transmit current is switched back and forth only during the data refresh cycle.Figure 8A The display brightness as a function of time is shown. As shown in Figure 8, during the data refresh cycle T_refresh, the brightness may suddenly drop by 800. This sudden drop of 800 is caused by the sequential shutdown and then activation of transistor T4, such as in... Figure 5 - The four phases are shown in Figure 6. A sudden drop in brightness of 800 at 1Hz can cause noticeable flickering to be perceived by the user.

[0051] To eliminate flicker, an additional brightness drop of 802 can be inserted during the vertical blanking period T_blank. Figure 8A In the example, three additional 802 drops are inserted, which is merely illustrative. Generally, at least 10, at least 100, or more than 100 drops can be generated during the extended blanking period T_blank. By artificially and intentionally generating brightness drops at a higher frequency, the flickering becomes less noticeable to the human eye.

[0052] The 802 drop during the blanking cycle can be generated alternately between the anode reset phase and the emission phase. Figure 8B This is a timing diagram illustrating the behavior of the relevant signals during the anode reset and emission phases. At time t1, signal Scan2 can be pulsed high, and signal EM2 can be deasserted while signal Scan1 remains low and signal EM1 remains high (e.g., EM2 can be pushed low). Figure 9A The configuration of pixel 22 during this time period is shown. (As shown) Figure 9A As shown, transistors T1 and T5 are turned on (because signals Scan2 and EM1 are asserted), so Node4 (which is the anode of diode 304) will be reset to voltage Vp via transistor 900. The data signal can remain at voltage Vp during the blanking gap. For example, voltage Vp can be at VSSEL, 2V, or any data voltage level between VSSEL and 2V. Source driver 62 (see also...) Figure 2 Transistor T4 will be deactivated during this period. Therefore, no emitter current can flow during the anode reset phase. At time t2, signal Scan2 is pushed low, marking the end of the anode reset phase.

[0053] At time t3, signal EM2 is asserted (e.g., EM2 is pushed high), which reactivates transistor T4. Figure 9B The configuration of pixel 22 during this time period is shown. (As shown) Figure 9B As shown, transistors T2, T4, and T5 are all turned on, so the emission current 950 will flow through diode 304. The emission current 950 will continue to flow until the next anode reset phase occurs at time t4. Therefore, the time period from t3 to t4 depicts the emission phase.Figure 8B The schematic diagram is not drawn to scale. Generally, the emission phase may be longer than the anode reset phase. The emission phase may also be shorter than the anode reset phase. The anode reset operation can be performed frequently as needed (e.g., to generate as much brightness drop as possible during the vertical blanking cycle as needed 802) to help reduce or minimize low refresh rate flicker.

[0054] Since bias stress is applied during the data refresh cycle, it can also be applied during the vertical blanking cycle to help maintain balance in terms of biasing the pixel transistors. Figure 10 This is a timing diagram illustrating how a bias stress stage can be inserted during the vertical blanking cycle before the anode reset stage (e.g., Figure 10 Figure 9 is extended by inserting a bias stress stage just before the anode reset stage begins. Figures 11A-11D Pixel 22 is shown in Figure 10 The configurations during each operational phase are shown. Specifically, Figure 11A and Figure 11D This shows that due to the combination Figure 6D and Figure 9B The described launch phase is the same as the launch phase without the need for iteration.

[0055] like Figure 10 As shown, signal EM1 can be deasserted before time t1, which prepares pixel 22 for bias stress. At time t1, signal Scan2 is asserted, marking the start of the bias stress phase. Figure 11B The configuration of pixel 22 during this time period is shown. (As shown) Figure 11B As shown, only transistors T1 and T2 are turned on. When configured in this way, Node3 will use transistor T1 to bias Vdata.

[0056] At time t2, signal EM1 is asserted (e.g., EM1 is pushed high) to turn on transistor T5, which marks the end of the bias stress phase and the beginning of the anode reset phase. Figure 11C The configuration of pixel 22 during this time period is shown. (As shown) Figure 11C As shown, both transistors T1 and T5 are turned on, thus resetting the diode anode terminal Node4 to Vdata. At time t3, signal Scan2 is deasserted to indicate the end of the anode reset phase. From time t4 to t5, transmit signals EM1 and EM2 are both pushed high to allow transmit current to flow. Generally, during the extended vertical blanking period, a bias stress phase can be performed concurrently with or just before any number of anode reset operations to help replicate and mirror the bias stress throughout the operation of display 14.

[0057] According to another suitable implementation, when the display 14 transitions from a black frame to a white frame (or typically, when the display 14 transitions from one grayscale to another), multiple data refresh operations and multiple anode reset operations can be performed. Figure 12 This is a schematic diagram illustrating how multiple anode resets and bias stress operations are inserted during a multi-refresh drive scheme to help reduce the dimming of the first frame. The top waveform shows how the threshold voltage of the drive transistor T2 changes when transitioning from a black frame to a white frame. The bottom waveform shows how the brightness of display 14 changes due to the execution of multiple data refreshes and / or anode resets when transitioning from a black frame to a white frame.

[0058] exist Figure 12 In the example, at least two data refreshes can be performed at 30Hz (e.g., at times t1 and t3). At each time between t1 and t3, Figure 5 - All four stages in Figure 6 are executable. Solid curves 1202 and 1206 show the threshold voltage tracking and luminance behavior when only two data refreshes are performed, respectively. Performing more than one data refresh enhances Vth tracking, resulting in a better luminance response that minimizes the dimming of the first frame.

[0059] In addition to multi-refresh operations, additional anode reset plus bias stress operations can be performed at 60Hz (e.g., at times t1, t2, t3, t4, and t5). The anode reset rate can be greater than the multi-refresh rate. At each of these times (e.g., ... Figure 12 During the period indicated by "X", it can be as follows: Figures 10-1 Figure 1 shows the application of bias stress and anode reset. Dashed curves 1204 and 1208 illustrate the threshold voltage tracking and luminance behavior when performing a 30Hz data refresh and a 60Hz anode reset with bias stress, respectively. As shown in curve 1204, Vth tracking is further improved by the applied additional bias stress, which contributes to faster Vth stabilization. As shown in curve 1208, the luminance at time t3 is closer to the target level, thus providing better first-frame performance.

[0060] Figure 12 The example of an anode reset rate being twice the multi-refresh rate is merely illustrative. In another suitable arrangement, the anode reset rate can be three times the multi-refresh rate. This configuration increases the frequency of bias stress between each successive data refresh phase, providing faster Vth stabilization and further improving first-frame performance. In other suitable arrangements, the anode reset can be any integer multiple of the data refresh rate (e.g., at least four times, at least eight times, greater than ten times, etc.).

[0061] Typically, during the transmission phase, the brightness of display 14 can be adjusted via pulse width modulation (PWM). In conventional display driving schemes, signal EM2 is repeatedly pulsed and has an adjustable duty cycle to control brightness, while signal EM1 remains high without switching back and forth. If signal EM1 remains high (turning on transistor T5), excessive current may leak through transistor T5, resulting in a poor black level. To mitigate this problem, signals EM1 and EM2 can be switched back and forth simultaneously and synchronized with each other.

[0062] Figure 13 This is a timing diagram illustrating how to make EM1 and EM2 pulses 1300 have the same duty cycle and synchronize with each other. EM1 is deasserted while EM2 turns off transistor T5, thus cutting off the leakage current path (e.g., when both EM1 and EM2 are low, there is no DC path from Node1 to the diode). The pulse number and pulse width can be tuned to output the desired brightness level of the display. Figure 5 besides Figure 12 Details for time period 1350 are shown in (if multiple refresh schemes are supported).

[0063] The behavior of transmitted signals EM1 and EM2 during the anode reset phase may also be similar. During the anode reset phase, signal EM1 must be asserted for a relatively long period of time (see, for example...). Figure 8B ).like Figure 13 As shown, signal EM1 may remain high for roughly a quarter of the entire anode reset cycle (e.g., during the first PWM cycle). For the remaining three-quarters of the anode reset cycle, signals EM1 and EM2 can be switched back and forth together.

[0064] Figure 14 Details of time period 1352 at the beginning of each anode reset cycle are shown. Figure 14 As shown, signals EM1 and EM2 are simultaneously asserted at time t1 (e.g., EM1 and EM2 are pushed high). At time t2, signals EM1 and EM2 are simultaneously deasserted and signal Scan2 is pulsed high. During the time interval from t2 to t3, Vdata is biased to a low voltage, and both Node1 and Node3 are subsequently discharged to a low voltage through transistor T1. This operation is similar to combining... Figure 5- The bias stress operation is illustrated in Figure 6. Nodes 1 and 3 are discharged via transistor T1, and even if signal EM1 subsequently rises (at time t3), there is no further charge leakage from Node 1 to the diode. Therefore, the time period between t2 and t3 is sometimes referred to as the discharge period T_discharge. As mentioned above, for the remainder of the anode reset cycle, signals EM1 and EM2 have the same duty cycle, so there is no DC path from Node 1 to the diode.

[0065] Combination Figures 5-14 The various methods described for operating the display 14 are not mutually exclusive and can be used in combination in a single implementation to help reduce flicker, improve first-frame performance, and improve black levels for low refresh rate displays.

[0066] According to one embodiment, a display pixel is provided, the display pixel including a light-emitting diode, a power line, a data line, an initialization line, a first transistor having a source terminal and a drain terminal coupled to the data line, a second transistor having a drain terminal, a gate terminal and a source terminal coupled to the source terminal of the first transistor, a third transistor coupled between the drain terminal and the gate terminal of the second transistor, a fourth transistor coupled between the power line and the second transistor, a fifth transistor coupled between the second transistor and the light-emitting diode, and a sixth transistor coupled between the initialization line and the light-emitting diode, wherein only the first transistor is turned on during a bias stress phase to mitigate the threshold voltage hysteresis of the second transistor.

[0067] According to another embodiment, the third transistor has a gate terminal for receiving a first scan signal, the sixth transistor has a gate terminal for receiving a first scan signal, the first transistor has a gate terminal for receiving a second scan signal different from the first scan signal, the fifth transistor has a gate terminal for receiving a first transmit signal, and the fourth transistor has a gate terminal for receiving a second transmit signal different from the first transmit signal.

[0068] According to another implementation, during the bias stress phase, only the second scan signal is asserted, while the first scan signal, the first transmit signal, and the second transmit signal are deasserted.

[0069] According to another implementation, the initialization phase precedes the bias stress phase, during which only the first scan signal and the second transmit signal are asserted.

[0070] According to another implementation, the threshold voltage sampling and data writing phase immediately follows the bias stress phase, and during the threshold voltage sampling and data writing phase, only the first scan signal and the second scan signal are asserted.

[0071] According to another implementation, the bias stress phase, initialization phase, and threshold voltage sampling and data writing phase are performed during the data refresh cycle. The blanking cycle follows the data refresh cycle and is at least ten times longer than the data refresh cycle. During the blanking cycle, multiple anode reset operations are performed to reduce flicker.

[0072] According to another implementation, during each of the multiple anode reset operations, only the second scan signal and the first transmission signal are asserted.

[0073] According to another implementation, an additional bias stress phase is applied before each of the multiple anode reset operations to provide balanced transistor stress, and during the additional bias stress phase, only the second scan signal is asserted.

[0074] According to one embodiment, a method for operating a display pixel is provided. The display pixel includes a light-emitting diode (LED), a power line, a data line, an initialization line, a first transistor having a source terminal and a drain terminal coupled to the data line, a second transistor having a drain terminal, a gate terminal, and a source terminal coupled to the source terminal of the first transistor, a third transistor coupled between the drain terminal and the gate terminal of the second transistor, a fourth transistor coupled between the power line and the second transistor, a fifth transistor coupled between the second transistor and the LED, and a sixth transistor coupled between the initialization line and the LED. This method of operating the display pixel includes operating the display pixel at an overall refresh rate below 30 Hz, and performing multi-bias stress operation to mitigate threshold voltage hysteresis of the second transistor when the display pixel transitions from displaying black to displaying white, wherein only the first transistor is turned on during the bias stress operation.

[0075] According to another embodiment, the method includes providing a first scan signal to the gate terminal of a third transistor and the gate terminal of a sixth transistor, providing a second scan signal to the gate terminal of a first transistor, providing a first transmit signal to the gate terminal of a fifth transistor, and providing a second transmit signal to the gate terminal of a fourth transistor.

[0076] According to another embodiment, the method includes performing an anode reset operation along with a bias stress operation when a display pixel changes from displaying black to displaying white, wherein only a second scan signal and a first transmit signal are pushed high during each of the anode reset operations.

[0077] According to another embodiment, the method includes performing multiple data refresh operations at a first rate when a display pixel changes from displaying black to displaying white, and forming an anode reset operation at a second rate greater than the first rate.

[0078] According to another implementation, performing the data refresh operation includes performing an initialization phase by only raising the first scan signal and the second transmit signal, performing a bias stress phase by only raising the second scan signal, performing a threshold voltage sampling and data writing phase by only raising the first scan signal and the second scan signal, and performing a transmission phase by only raising the first transmit signal and the second transmit signal.

[0079] According to another embodiment, the method includes performing multiple anode reset operations to reduce flicker during the vertical blanking cycle, wherein only the second scan signal and the first transmit signal are asserted during each of the multiple anode reset operations.

[0080] According to another embodiment, the method includes applying an additional bias stress operation before each of the multiple anode reset operations to provide balanced transistor stress, during which only the second scan signal is asserted.

[0081] According to one embodiment, a display pixel is provided, the display pixel including a light-emitting diode, a power line, a data line, an initialization line, a first transistor having a source terminal and a drain terminal coupled to the data line, a second transistor having a drain terminal, a gate terminal and a source terminal coupled to the source terminal of the first transistor, a third transistor coupled between the drain terminal and the gate terminal of the second transistor, a fourth transistor coupled between the power line and the second transistor, a fifth transistor coupled between the second transistor and the light-emitting diode, and a sixth transistor coupled between the initialization line and the light-emitting diode, the fifth transistor having a gate terminal for receiving a first transmitted signal, the fourth transistor having a gate terminal for receiving a second transmitted signal, and using a pulse width modulation (PWM) scheme to simultaneously switch the first transmitted signal and the second transmitted signal back and forth to control the brightness of the display pixel.

[0082] According to another implementation, during a pulse width modulation cycle, a first transmit signal is pushed high while a second transmit signal is pushed low to perform an anode reset, and only the first transmit signal is pushed high during the anode reset.

[0083] According to another embodiment, the third transistor and the sixth transistor have gate terminals for receiving a first scan signal, the first transistor has gate terminals for receiving a second scan signal, and a discharge phase follows an anode reset, during which only the second scan signal is pulsed high to discharge the display pixels and reduce leakage.

[0084] According to another implementation, only the second scan signal is pushed up during the bias stress phase to mitigate the threshold voltage hysteresis of the second transistor.

[0085] According to another implementation, multiple anode reset operations are performed during the blanking cycle to reduce flicker.

[0086] According to another embodiment, the third transistor is a semiconductor oxide transistor, and the first, second, fourth, fifth, and sixth transistors are silicon transistors.

[0087] According to another embodiment, the third and sixth transistors are semiconductor oxide transistors, and the first, second, fourth, and fifth transistors are silicon transistors.

[0088] According to another embodiment, the second, third, and sixth transistors are semiconductor oxide transistors, and the first, fourth, and fifth transistors are silicon transistors.

[0089] According to another embodiment, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are semiconductor oxide transistors.

[0090] The foregoing is merely illustrative and various modifications can be made to the described implementation scheme. The aforementioned implementation scheme can be implemented individually or in any combination.

Claims

1. A display pixel, comprising: First power supply line; Second power supply line; A light-emitting diode having a cathode coupled to a second power line and having an anode; A first emitter transistor, the first emitter transistor being coupled to the first power line; A second emitting transistor is coupled to the anode of the light-emitting diode; A silicon driving transistor having a gate terminal, a first source-drain terminal coupled to a first emitter transistor, and a second source-drain terminal coupled to a second emitter transistor; A semiconductor oxide transistor having a gate terminal, a first source-drain terminal coupled to an initialization line, and a second source-drain terminal; A capacitor coupled between the second source-drain terminal of the semiconductor oxide transistor and the gate terminal of the silicon drive transistor; as well as A switching transistor having a first source-drain terminal configured to receive a reset voltage or a data voltage and a second source-drain terminal having a second source-drain terminal coupled to the silicon driving transistor, and the switching transistor being configured to reset the anode of the light-emitting diode multiple times during a vertical blanking period.

2. The display pixel of claim 1, wherein the semiconductor oxide transistor comprises semiconductor oxide.

3. The display pixel according to claim 2, further comprising: An additional semiconductor oxide transistor having a first source-drain terminal coupled to the gate terminal of the silicon driving transistor and a second source-drain terminal coupled to the first source-drain terminal of the silicon driving transistor.

4. The display pixel of claim 1, wherein the switching transistor comprises a silicon anode reset transistor.

5. The display pixel of claim 1, wherein the first emitter transistor and the second emitter transistor comprise silicon channel material.

6. The display pixel of claim 1, wherein the silicon driving transistor comprises a p-type silicon transistor.

7. A display pixel, comprising: A light-emitting diode, wherein the light-emitting diode has a cathode and an anode; A silicon driving transistor configured to drive current through the light-emitting diode during light emission; The emitter transistor has a first source-drain terminal coupled to the silicon driving transistor and a second source-drain terminal coupled to the anode of the light-emitting diode; A first semiconductor oxide transistor, the first semiconductor oxide transistor having a first source-drain terminal and a second source-drain terminal coupled to an initialization line; The second semiconductor oxide transistor has a first source-drain terminal coupled to the gate terminal of the silicon driving transistor and a second source-drain terminal coupled to the source-drain terminal of the silicon driving transistor; A storage capacitor is coupled between the second source-drain terminal of the first semiconductor oxide transistor and the gate terminal of the silicon drive transistor; as well as A switching transistor having a first source-drain terminal configured to receive a reset voltage or a data voltage and a second source-drain terminal having another source-drain terminal coupled to the silicon driving transistor, and the switching transistor being activated multiple times during a vertical blanking cycle.

8. The display pixel of claim 7, wherein the first semiconductor oxide transistor and the second semiconductor oxide transistor comprise semiconductor oxide.

9. The display pixel of claim 8, wherein the silicon driving transistor comprises a p-type silicon transistor.

10. An apparatus comprising: A light-emitting diode, wherein the light-emitting diode has a cathode and an anode; A driving transistor configured to drive an emission current through the light-emitting diode; A semiconductor oxide transistor having a first source-drain terminal and a second source-drain terminal coupled to an initialization line, wherein an initialization voltage is provided on the initialization line; A capacitor coupled between the second source-drain terminal of the semiconductor oxide transistor and the gate terminal of the driving transistor; as well as A switching transistor having a first source-drain terminal configured to receive a reset voltage or data voltage separate from the initialization voltage and a second source-drain terminal having a source-drain terminal coupled to the driving transistor, wherein the switching transistor is configured to apply the reset voltage to the anode of the light-emitting diode multiple times during a vertical blanking cycle.

11. The apparatus of claim 10, wherein the semiconductor oxide transistor comprises a semiconductor oxide.

12. The apparatus of claim 11, wherein the driving transistor comprises a silicon driving transistor.

13. The apparatus of claim 11, wherein the switching transistor comprises a silicon transistor.

14. The apparatus of claim 11, further comprising: An additional semiconductor oxide transistor having a gate terminal, a first source-drain terminal coupled to the gate terminal of the driving transistor, and a second source-drain terminal coupled to another source-drain terminal of the driving transistor.

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