Semiconductor device and method

Abstract

The present application relates to semiconductor devices and methods. An improved internal spacer for a semiconductor device and a method for forming the same are disclosed. In one embodiment, a semiconductor device includes: a substrate; a plurality of semiconductor channel structures on the substrate; a gate structure on the plurality of semiconductor channel structures, the gate structure extending between adjacent semiconductor channel structures in the plurality of semiconductor channel structures; a source / drain region adjacent to the gate structure, the source / drain region contacting the semiconductor channel structure; and an internal spacer inserted between the source / drain region and the gate structure, the internal spacer including: a first internal spacer layer contacting the gate structure and the source / drain region, the first internal spacer layer including silicon and nitrogen; and a second internal spacer layer contacting the first internal spacer layer and the source / drain region, the second internal spacer layer including silicon, oxygen and nitrogen.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices and methods. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of materials on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed. Summary of the invention

[0004] According to a first aspect of the present disclosure, a semiconductor device is provided, comprising: a substrate; a plurality of semiconductor channel structures located on the substrate; a gate structure located on the plurality of semiconductor channel structures, wherein the gate structure extends between adjacent semiconductor channel structures among the plurality of semiconductor channel structures; a source / drain region adjacent to the gate structure, the source / drain region contacting the plurality of semiconductor channel structures; and an internal spacer inserted between the source / drain region and the gate structure, the internal spacer comprising: a first internal spacer layer contacting the gate structure and the source / drain region, the first internal spacer layer comprising silicon and nitrogen; and a second internal spacer layer contacting the first internal spacer layer and the source / drain region, the second internal spacer layer comprising silicon, oxygen and nitrogen, the second internal spacer layer having a lower dielectric constant than the first internal spacer layer.

[0005] According to a second aspect of the present disclosure, a semiconductor device is provided, comprising: a semiconductor substrate; a plurality of channel regions located on the semiconductor substrate; a gate structure located on the plurality of channel regions, wherein the gate structure extends between adjacent channel regions in the plurality of channel regions; an upper spacer along a sidewall of the gate structure; a source / drain region adjacent to the gate structure; and a plurality of internal spacers, each of the internal spacers being inserted between adjacent channel regions in the plurality of channel regions, each of the internal spacers being inserted between the source / drain region and the gate structure, and each of the internal spacers being inserted between the source / drain region and the gate structure. The device comprises: a first internal spacer layer, which is in contact with the gate structure and the source / drain region, and the first internal spacer layer includes silicon and nitrogen; a second internal spacer layer, which is in contact with the first internal spacer layer and the source / drain region, and the second internal spacer layer includes silicon, oxygen and nitrogen, and the second internal spacer layer has a lower dielectric constant than the first internal spacer layer; and a third internal spacer layer, which is in contact with the second internal spacer layer and the source / drain region, and the third internal spacer layer includes silicon and nitrogen, wherein the sidewall of the internal spacer adjacent to the source / drain region is W-shaped in a cross-sectional view.

[0006] According to a third aspect of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a multilayer stack on a semiconductor substrate, the multilayer stack comprising alternating layers of a first semiconductor material and a second semiconductor material, the second semiconductor material being different from the first semiconductor material; etching the sidewalls of the first semiconductor material to form sidewall grooves; depositing a first internal spacer layer on the multilayer stack and in the sidewall grooves; depositing a second internal spacer layer on the first internal spacer layer; depositing a third internal spacer layer to fill the sidewall grooves; performing a first etching process to etch the first internal spacer layer, the second internal spacer layer, and the third internal spacer layer, and forming an internal spacer in the sidewall groove comprising the first internal spacer layer, the second internal spacer layer, and the remaining portion of the third internal spacer layer, wherein the first etching process etches the second internal spacer layer at a greater etching rate than the etching rate of the third internal spacer layer; performing a second etching process to remove the first semiconductor material and form a first groove extending between the internal spacers, wherein the second etching process etches the first internal spacer layer at a smaller etching rate than the etching rate of the first semiconductor material; and forming a gate structure in the first groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 An example of a semiconductor device including a nanostructure field effect transistor (NSFET) in a three-dimensional view is shown in accordance with some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Fig. 6A , Figure 6B , Figure 6C , Fig. 7A , Figure 7B , Figure 7C , Fig. 8A , Figure 8B , Figure 8C , Fig. 9A , Fig. 9B , Fig. 9C , Fig. 10A , Fig. 10B , Fig. 10C , Fig.11A , Fig. 11B , Fig. 11C , Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.13A , Fig. 13B , Fig. 13C , Fig.13D , Fig.14A , Fig. 14B , Fig. 14C , Fig.15A , Fig. 15B , Fig. 15C , Fig.16A , Fig. 16B , Fig. 16C , Fig.17A , Fig. 17B , Fig. 17C , Fig.18A , Fig.18B , Fig. 18C , Fig.18D , Fig.19A , Fig.19B , Fig.19C , Fig. 20A , Fig. 20B and Fig. 20C is a cross-sectional view of an intermediate stage in the fabrication of a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which an additional feature is formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0011] Additionally, for ease of description, spatially relative terms, such as "under," "beneath," "below," "above," "above," etc., may be used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features) as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0012] Various embodiments provide methods for forming improved internal spacers in semiconductor devices, and semiconductor devices formed by the methods. Internal spacers can be used to isolate gate stacks from source / drain regions. The internal spacers can be formed by depositing multiple dielectric layers having different compositions. For example, in some embodiments, the internal spacers can be formed by three dielectric layers having different etching selectivities and different dielectric constants (k values). The internal spacers can be formed by depositing a first dielectric layer having a high etching selectivity, then depositing a second dielectric layer having a low k value on top of the first dielectric layer, and then depositing a third dielectric layer having a low k value on top of the second dielectric layer. In some embodiments, the first dielectric layer may include silicon carbon nitride (SiCN), and the second and third dielectric layers may include silicon oxycarbon nitride (SiOCN). Including the first dielectric layer having a high etching selectivity in the internal spacer improves the etching resistance of the internal spacer and improves the profile of the internal spacer. Including the second and third dielectric layers in the internal spacer reduces the effective capacitance (C eff ), and improve device performance.

[0013] Figure 1An example of a nanostructure (e.g., nanosheet, nanowire, gate-all-around, etc.) field effect transistor (NSFET) according to some embodiments is shown. The NSFET includes a nanostructure 55 on a substrate 50 (e.g., a semiconductor substrate). The nanostructure 55 includes a second semiconductor layer 54A-54C, which serves as a channel region of the nanostructure 55. A shallow trench isolation (STI) region 58 is disposed in the substrate 50, and the nanostructure 55 is disposed on and between adjacent STI regions 58. Although the STI region 58 is described / illustrated as being separate from the substrate 50, as used herein, the term "substrate" may refer to only the semiconductor substrate, or a combination of the semiconductor substrate and the STI region.

[0014] The gate dielectric layer 100 is along the top surface, sidewalls, and bottom surface of the nanostructure 55, for example, on the top surface, sidewalls, and bottom surface of each second semiconductor layer 54A-54C, and along the top surface and sidewalls of a portion of the substrate 50. The gate electrode 102 is located on the gate dielectric layer 100. The epitaxial source / drain region 92 is disposed on the opposite side of the nanostructure 55, the gate dielectric layer 100, and the gate electrode 102. Figure 1 Reference cross sections used in subsequent figures are further illustrated. Cross section AA' is along the longitudinal axis of gate electrode 102 and in a direction, for example, perpendicular to the direction of current flow between epitaxial source / drain regions 92 of the NSFET. Cross section BB' is perpendicular to cross section AA' and along the longitudinal axis of nanostructure 55 and in a direction of current flow, for example, between epitaxial source / drain regions 92 of the NSFET. Cross section CC' is parallel to cross section AA' and extends through epitaxial source / drain regions 92 of the NSFET. For clarity, subsequent figures refer to these reference cross sections.

[0015] Some embodiments discussed herein are discussed in the context of NSFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments contemplate aspects for use in fin field effect transistors (FinFETs), or planar devices such as planar FETs.

[0016] Figures 2 to 20C is a cross-sectional view of an intermediate stage in the fabrication of a NSFET according to some embodiments. Figures 2 to 5 , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A, Fig.18D , Fig.19A and Fig. 20A Shows Figure 1 Reference section AA' shown in . Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig.12D , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig. 18C , Fig.19B and Fig. 20B Shows Figure 1 Reference section BB' is shown. Figure 6C , Figure 7C , Figure 8C , Fig. 9C , Fig. 10C , Fig. 11C , Fig. 12C , Fig. 13C , Fig.13D , Fig. 14C , Fig. 15C , Fig. 16C , Fig. 17C , Fig. 18C , Fig.19C and Fig. 20C Shows Figure 1 Reference section CC' shown in .

[0017] exist Figure 2 In the invention, a substrate 50 for forming a NSFET is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, typically a silicon substrate or a glass substrate. Other substrates may also be used, such as a multilayer substrate or a gradient substrate. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide; or combinations thereof.

[0018] Substrate 50 has region 50N and region 50P. Region 50N can be used to form an n-type device, for example, an NMOS transistor, such as an n-type NSFET. Region 50P can be used to form a p-type device, for example, a PMOS transistor, such as a p-type NSFET. Region 50N can be physically separated from region 50P (as shown by separator 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be arranged between region 50N and region 50P.

[0019] Appropriate wells (not shown separately) may be formed in the regions 50N and 50P of the substrate 50. In some embodiments, a P-well may be formed in the region 50N, and an N-well may be formed in the region 50P. In some embodiments, a P-well or an N-well may be formed in each of the regions 50N and 50P.

[0020] In embodiments including different well types, a photoresist or other mask (not shown separately) may be used to implement different implantation steps for region 50N and region 50P. For example, a photoresist may be formed over substrate 50 in region 50N. The photoresist is patterned to expose region 50P of substrate 50. The photoresist may be formed using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, an n-type impurity implantation is performed in region 50P, and the photoresist may be used as a mask to substantially prevent n-type impurities from being implanted into region 50N. The n-type impurity may be phosphorus, arsenic, antimony, etc., implanted into the region at a concentration equal to or less than 1×10 18 Atom / cm 3 , for example, from about 1×10 16 Atom / cm 3 About 1×10 18 Atom / cm 3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0021] After implanting region 50P, a photoresist is formed over substrate 50 in region 50P. The photoresist is patterned to expose region 50N of substrate 50. The photoresist may be formed using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation may be performed in region 50N, and the photoresist may be used as a mask to substantially prevent the p-type impurity from being implanted into region 50P. The p-type impurity may be boron, boron fluoride, indium, etc., implanted into the region at a concentration equal to or less than 1×10 18 Atom / cm 3 , for example, from about 1×10 16 Atom / cm 3About 1×10 18 Atom / cm 3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0022] An anti-punch-through (APT) implant may be performed on the upper portion of substrate 50 to form APT region 53. During the APT implant, dopants may be implanted in region 50N and region 50P. The dopants may have a similar structure to the source / drain regions to be formed in each of region 50N and region 50P (e.g., as described below with respect to Figures 13A-13D The APT region 53 may be of a conductivity type opposite to the conductivity type of the epitaxial source / drain region 92 discussed above. The APT region 53 may extend below the subsequently formed source / drain region in the resulting NSFET, which will be formed in a subsequent process. The APT region 53 may be used to reduce leakage from the source / drain region to the substrate 50. In some embodiments, the doping concentration in the APT region 53 may be from about 1×10 18 Atom / cm 3 To about 1×10 19 Atom / cm 3 For simplicity and clarity, APT region 53 is not shown in subsequent figures. After the implantation of regions 50N and 50P (including the formation of wells and / or APT regions 53), annealing may be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities.

[0023] Further in Figure 2In the embodiment of the present invention, a multilayer stack 56 is formed on a substrate 50. The multilayer stack 56 includes alternating first semiconductor layers 52 and second semiconductor layers 54 of different semiconductor materials. The first semiconductor layer 52 may be formed of a first semiconductor material, which may include, for example, silicon germanium (SiGe), etc. The second semiconductor layer 54 may be formed of a second semiconductor material, which may include, for example, silicon (Si), silicon carbon (SiC), etc. In some embodiments, the first semiconductor layer 52 may be formed of a second semiconductor material, and the second semiconductor layer 54 may be formed of a first semiconductor material. For purposes of illustration, the multilayer stack 56 includes three first semiconductor layers 52 (e.g., first semiconductor layers 52A-52C) and three second semiconductor layers 54 (e.g., second semiconductor layers 54A-54C). In some embodiments, the multilayer stack may include between two and four pairs of first semiconductor layers 52 and second semiconductor layers 54. In some embodiments, the multilayer stack 56 may include any number of first semiconductor layers 52 and second semiconductor layers 54. Each layer of the multilayer stack 56 can be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. The thickness of each of the first semiconductor layers 52A-52C can be from about 8 nm to about 12 nm or from about 9.5 nm to about 10.5 nm. The thickness of each of the second semiconductor layers 54A-54C can be from about 5 nm to about 15 nm or from about 8 nm to about 12 nm.

[0024] For the purpose of illustration, the second semiconductor layer 54 will be described as forming a channel region in the region 50N and the region 50P. The first semiconductor layer 52 may be a sacrificial layer in the region 50N and the region 50P, which may be removed later. In some embodiments, the first semiconductor layer 52 may form a channel region, and the second semiconductor layer 54 may be a sacrificial layer in the region 50N and the region 50P. In some embodiments, the second semiconductor layer 54 may form a channel region in the region 50N and a sacrificial layer in the region 50P, and the first semiconductor layer 52 may form a sacrificial layer in the region 50N and a channel region in the region 50P, or the first semiconductor layer 52 may form a channel region in the region 50N and a sacrificial layer in the region 50P, and the second semiconductor layer 54 may form a sacrificial layer in the region 50N and a channel region in the region 50P.

[0025] exist Figure 3 In the embodiment of the present invention, nanostructures 55 are formed in multilayer stack 56, and substrate 50 is etched. In some embodiments, nanostructures 55 may be formed by etching trenches in multilayer stack 56 and substrate 50. Etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. Etching may be anisotropic.

[0026] The nanostructure 55 and the substrate 50 may be patterned by any suitable method. For example, one or more photolithography processes may be used to pattern the nanostructure 55 and the substrate 50, including a double patterning process or a multi-patterning process. Typically, a double patterning process or a multi-patterning process combines photolithography and self-alignment processes, allowing the creation of patterns having, for example, a spacing smaller than that obtainable using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over the substrate and patterned using a photolithography process. A spacer is formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the nanostructure 55 and the substrate 50. In some embodiments, a mask (or other layer) may remain on the nanostructure 55 after the nanostructure 55 and the substrate 50 are patterned.

[0027] exist Figure 4 In the embodiment of the present invention, a shallow trench isolation (STI) region 58 is formed adjacent to the patterned portion of the substrate 50 and the nanostructure 55. The STI region 58 can be formed by forming an insulating material (not shown separately) on the substrate 50 and between the adjacent patterned portions / nanostructures 55 of the substrate 50. The insulating material can be an oxide (e.g., silicon oxide), a nitride, etc., or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert the deposited material into another material, such as an oxide), etc., or a combination thereof. Other insulating materials formed by any acceptable process can be used. In some embodiments, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In some embodiments, the insulating material is formed so that an excess of the insulating material covers the nanostructure 55. The insulating material can include a single layer or multiple layers can be used. For example, in some embodiments, a liner (not shown separately) can be first formed along the surface of the substrate 50 and the nanostructure 55. Thereafter, a fill material such as described above may be formed over the liner.

[0028] A removal process is then applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, a planarization process may be employed, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. The planarization process may planarize the insulating material and the nanostructure 55. The planarization process exposes the nanostructure 55 so that the top surfaces of the nanostructure 55 and the insulating material are flush after the planarization process is completed.

[0029] The insulating material is then recessed to form a Figure 4The STI region 58 shown. The insulating material is recessed so that the upper portion of the nanostructure 55 and the substrate 50 protrudes from between adjacent STI regions 58. In addition, the top surface of the STI region 58 can have a flat surface (as shown), a convex surface, a concave surface (e.g., a dish), or a combination thereof. The top surface of the STI region 58 can be formed to be flat, convex, and / or concave by appropriate etching. The STI region 58 can be recessed using an acceptable etching process, for example, an etching process that is selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the nanostructure 55 and the substrate 50). For example, oxide removal using an acid such as dilute hydrofluoric acid (dHF) can be employed.

[0030] about Figure 2-4 The process described is only one example of how to form the nanostructure 55. In some embodiments, the nanostructure 55 can be formed by an epitaxial growth process. For example, a dielectric layer can be formed above the top surface of the substrate 50, and a groove can be etched through the dielectric layer to expose the substrate 50 below. The epitaxial structure can be epitaxially grown in the groove, and the dielectric layer can be recessed so that the epitaxial structure protrudes from the dielectric layer to form the nanostructure 55. In the nanostructure 55, the epitaxial structure can include alternating layers of a first semiconductor material and a second semiconductor material. The dielectric layer can then be recessed so that portions of the substrate 50 and the nanostructure 55 protrude from the dielectric layer. In embodiments in which portions of the substrate 50 and the nanostructure 55 are epitaxially grown, the epitaxially grown material can be in-situ doped during growth, which can eliminate previous and subsequent implants, but in-situ doping and implant doping can be used together.

[0031] exist Figure 5In the embodiment of the present invention, a dummy dielectric layer 60 is formed on the portion of the substrate 50 extending above the STI region 58 (if any) and the nanostructure 55. The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed on the dummy dielectric layer 60, and a mask layer 64 is formed on the dummy gate layer 62. The dummy gate layer 62 can be deposited on the dummy dielectric layer 60 and then planarized by a process such as implantation CMP. The mask layer 64 can be deposited on the dummy gate layer 62. The dummy gate layer 62 can be a conductive material or a non-conductive material, and can be selected from the group including the following items: amorphous silicon, polysilicon, polycrystalline silicon germanium (poly-SiGe), metal-containing nitride, metal-containing silicide, metal-containing oxide, and metal. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other known and in the art techniques for depositing selected materials. Dummy gate layer 62 may be made of other materials with high etching selectivity relative to the material of STI region 58. Mask layer 64 may include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across region 50N and region 50P. Note that dummy dielectric layer 60 is shown as covering only nanostructure 55 and substrate 50 for illustration purposes only. In some embodiments, dummy dielectric layer 60 may be deposited such that dummy dielectric layer 60 covers STI region 58 and extends between dummy gate layer 62 and STI region 58.

[0032] FIG. 6A to FIG. 20C Various additional steps in the fabrication of example devices are shown. FIG. 6A to FIG. 20C Features in either region 50N or region 50P are shown. For example, FIG. 6A to FIG. 20C The structure shown is applicable to both region 50N and region 50P. Differences in the structures of region 50N and region 50P, if any, are described in the text accompanying each figure.

[0033] exist FIG. 6A to FIG. 6C In the embodiment, the mask layer 64 (see Figure 5) is patterned to form a mask 74. The pattern of the mask 74 can be transferred to the dummy gate layer 62 using an acceptable etching technique to form the dummy gate 72. In some embodiments, the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60. The dummy gate 72 covers the corresponding channel region of the nanostructure 55. In some embodiments, in the region 50N, the channel region can be formed in the second semiconductor layer 54A-54C including the second semiconductor material, and in the region 50P, the channel region can be formed in the first semiconductor layer 52A-52C including the first semiconductor material. The pattern of the mask 74 can be used to physically separate each dummy gate 72 from the adjacent dummy gate 72. The dummy gate 72 can have a length direction that is substantially perpendicular to the length direction of the corresponding nanostructure 55. The dummy dielectric layer 60, the dummy gate 72 and the mask 74 can be collectively referred to as a "dummy gate stack". The dummy gate 72 may have a gate length of about 12 nm to about 20 nm, or about 14.5 nm to about 17 nm.

[0034] exist 7A to 7C in FIG. 6A to FIG. 6C A first spacer layer 80 and a second spacer layer 82 are formed over the structure shown. 7A to 7C In the embodiment of the present invention, a first spacer layer 80 is formed on the top surface of the STI region 58, the top surface and sidewalls of the nanostructure 55 and the mask 74, and the sidewalls of the substrate 50, the dummy gate 72, and the dummy dielectric layer 60. A second spacer layer 82 is deposited on the first spacer layer 80. The first spacer layer 80 can be formed by thermal oxidation, or deposited by CVD, ALD, etc. The first spacer layer 80 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. The second spacer layer 82 can be deposited by CVD, ALD, etc. The second spacer layer 82 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0035] exist FIG. 8A to FIG. 8C In the process, the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacer 81 and the second spacer 83. The first spacer layer 80 and the second spacer layer 82 may be etched using an appropriate etching process, for example, an anisotropic etching process (for example, a dry etching process), etc. The first spacer 81 and the second spacer 83 may be disposed on the sidewalls of the nanostructure 55, the dummy dielectric layer 60, the dummy gate 72, and the mask 74. Due to the etching process used to etch the first spacer layer 80 and the second spacer layer 82, and the different heights between the nanostructure 55 and the dummy gate stack, the first spacer 81 and the second spacer 83 may have different heights adjacent to the nanostructure 55 and the dummy gate stack. Specifically, as Figure 8B and Figure 8CAs shown, in some embodiments, the first spacer 81 and the second spacer 83 may extend partially upward along the sidewall of the nanostructure 55, and may extend to the top surface of the dummy gate stack. In some embodiments, the first spacer 81 and the second spacer 83 may extend partially upward along the sidewall of the dummy gate stack. For example, the top surface of the first spacer 81 and the second spacer 83 may be disposed above the top surface of the dummy gate 72 and below the top surface of the mask 74. The effective dielectric constant (k value) of the first spacer 81 and the second spacer 83 may be from about 4.1 to about 5.5, or from about 4.6 to about 5.0, and the thickness T5 may be from about 3.5nm to about 5.0nm, or from about 4.1nm to about 4.4nm.

[0036] exist 9A to 9C In the embodiment, a first groove 86 is formed in the nanostructure 55 and the substrate 50. The first groove 86 may extend through the first semiconductor layer 52A-52C and the second semiconductor layer 54A-54C. In some embodiments, the first groove 86 may also extend into the substrate 50. Fig. 9C As shown, the top surface of the STI region 58 can be flush with the top surface of the substrate 50. In some embodiments, the substrate 50 can be etched so that the bottom surface of the first recess 86 is disposed below the top surface of the STI region 58, etc. The first recess 86 can be formed by etching the nanostructure 55 and / or the substrate 50 using an anisotropic etching process (e.g., reactive ion etching (RIE), neutral beam etching (NBE), etc.). During the etching process for forming the first recess 86, the first spacer 81, the second spacer 83, and the mask 74 mask portions of the nanostructure 55 and the substrate 50. A single etching process can be used to etch each layer in the multilayer stack 56. In some embodiments, multiple etching processes can be used to etch the layers of the multilayer stack 56. A timed etching process can be used to stop etching the first recess 86 after the first recess 86 reaches a desired depth.

[0037] exist FIG. 10A to FIG. 10CIn the embodiment, the sidewalls of the layers of the multilayer stack 56 (e.g., the first semiconductor layers 52A-52C) formed of the first semiconductor material exposed by the first groove 86 are etched to form sidewall grooves 88. The sidewalls can be etched using an isotropic etching process such as wet etching or the like. The etchant used to etch the first semiconductor layers 52A-52C can be selective to the first semiconductor material so that the second semiconductor layers 54A-54C and the substrate 50 remain relatively unetched compared to the first semiconductor layers 52A-52C. In an embodiment in which the first semiconductor layers 52A-52C include, for example, SiGe and the second semiconductor layers 54A-54C include, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like can be used to etch the sidewalls of the multilayer stack 56. In other embodiments, a dry etching process can be used to etch the layers of the multilayer stack 56. The sidewalls of the multilayer stack 56 can be etched using hydrogen fluoride, another fluorine-based gas, or the like. The sidewall recess 88 may extend to a depth D1 from about 3 nm to about 6 nm, or from about 4.3 nm to about 4.7 nm, and may have a width W1 from about 8 nm to about 12 nm, or from about 9 nm to about 11 nm.

[0038] like Fig. 10B As shown, the sidewalls of the first semiconductor layers 52A-52C may be concave. In some embodiments, the central portion of the first semiconductor layers 52A-52C may be recessed from the peripheral portion of the first semiconductor layers 52A-52C by a distance of about 1 nm to about 2 nm, or about 1.4 nm to about 1.6 nm. In other embodiments, the sidewalls of the first semiconductor layers 52A-52C may be substantially vertical or convex.

[0039] exist FIG. 11A to FIG. 11C in FIG. 10A to FIG. 10C Internal spacer layers (e.g., first internal spacer layer 90A, second internal spacer layer 90B, and third internal spacer layer 90C) are deposited on the structure shown. The first internal spacer layer 90A may be deposited by a conformal deposition process such as CVD, ALD, etc. The first internal spacer layer 90A may be deposited by a thermal deposition process at a temperature of about 500° C. to about 850° C., or about 650° C. to about 700° C.

[0040] The first inner spacer layer 90A may be formed of a material that allows a high first etch selectivity, which is a ratio of an etch rate of the first semiconductor layers 52A-52C to an etch rate of the first inner spacer layer 90A. In this way, the subsequent removal of the first semiconductor layers 52A-52C (hereinafter, regarding FIG. 17A to FIG. 17CThe first etch selectivity may be greater than about 100, or may be in the range of about 50 to about 500, or about 150 to about 250. The material of the first inner spacer layer 90A may also be selected to have a higher second etch selectivity, which is the ratio of the etch rate of the second inner spacer layer 90B to the etch rate of the first inner spacer layer 90A. In this way, the subsequent patterning of the first inner spacer layer 90A, the second inner spacer layer 90B, and the third inner spacer layer 90C (discussed below) may also be reduced. FIG. 12A to FIG. 12D The first inner spacer layer 90A may be etched during the etching process (discussed in detail in the embodiment of the present invention). The second etch selectivity may be greater than about 1.5, or may be in the range of about 1.2 to about 3.0, or about 1.5 to about 2.5. In various embodiments, the first inner spacer layer 90A may include silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), etc. In embodiments where the first inner spacer layer 90A includes carbon, the carbon atomic concentration in the first inner spacer layer 90A may be less than about 10%.

[0041] In embodiments where the first inner spacer layer 90A includes silicon nitride, the atomic percentage of nitrogen in the first inner spacer layer 90A may be in a range of about 35% to about 50%, or about 40% to about 45%. In embodiments where the first inner spacer layer 90A includes silicon carbonitride, the atomic percentage of nitrogen in the first inner spacer layer 90A may be in a range of about 25% to about 45%, or about 32.5% to about 37.5%, and the atomic percentage of carbon in the first inner spacer layer 90A may be in a range of about 5% to about 20%, or about 10% to about 15%. The first inner spacer layer 90A may have a carbon content of about 2.5 g / cm 3 To about 2.9g / cm 3 The dielectric constant (k value) of the first inner spacer layer 90A may be about 6.0 to about 7.3, or about 6.5 to about 6.8. The first inner spacer layer 90A may be deposited to a thickness T1 of about 0.5 nm to about 1.5 nm, or about 0.8 nm to about 1.2 nm.

[0042] Then, the second inner spacer layer 90B may be deposited over the first inner spacer layer 90A. The second inner spacer layer 90B may be deposited by a conformal deposition process such as CVD, ALD, etc. The second inner spacer layer 90B may be deposited by a thermal deposition process at a temperature of about 500° C. to about 850° C., or about 650° C. to about 700° C.

[0043] The second inner spacer layer 90B may be formed of a low-k material to reduce the inner spacer formed by the first inner spacer layer 90A, the second inner spacer layer 90B, and the third inner spacer layer 90C (eg, as described below with respect to FIG. 12A to FIG. 12D The second inner spacer layer 90B may have an effective k value (k value) of about 4.2 to about 5.7, or about 4.8 to about 5.1. In some embodiments, the second inner spacer layer 90B may include silicon oxycarbon nitride (SiOCN), silicon oxynitride (SiON), etc.

[0044] The carbon atomic percentage in the second inner spacer layer 90B can be about 0% to about 5%, less than about 5%, or about 2.5%. The nitrogen atomic percentage in the second inner spacer layer 90B can be about 10% to about 35%, or about 20% to about 25%. The oxygen atomic percentage in the second inner spacer layer 90B can be in the range of about 30% to about 60%, or about 42.5% to about 47.5%. The second inner spacer layer 90B can be deposited to a thickness T2 of about 1 nm to about 3 nm, or about 1.8 nm to about 2.2 nm.

[0045] A third inner spacer layer 90C may then be deposited over the second inner spacer layer 90B. The third inner spacer layer 90C may be deposited by a conformal deposition process such as CVD, ALD, etc. The third inner spacer layer 90C may be deposited by a thermal deposition process at a temperature of about 500° C. to about 850° C., or about 650° C. to about 700° C.

[0046] The third inner spacer layer 90C may be formed of a low-k material to reduce the inner spacer formed by the first inner spacer layer 90A, the second inner spacer layer 90B, and the third inner spacer layer 90C (eg, as described below with respect to FIG. 12A to FIG. 12D The third inner spacer layer 90C may have an effective k value (k value) as discussed above). For example, the dielectric constant (k value) of the third inner spacer layer 90C may be about 4.5 to about 6.0, or about 5.1 to about 5.4. The material of the third inner spacer layer 90C may also be selected to have a higher third etch selectivity, which is the ratio of the etch rate of the second inner spacer layer 90B to the etch rate of the third inner spacer layer 90C. In this way, the subsequent patterning of the first inner spacer layer 90A, the second inner spacer layer 90B, and the third inner spacer layer 90C (described below) may be reduced. FIG. 12A to FIG. 12DThe third etch selectivity may be greater than about 1.5, or may be in the range of about 1.2 to about 3.0, or about 1.5 to about 2.5. In some embodiments, the third inner spacer layer 90C may include silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon oxynitride (SiON), etc.

[0047] In embodiments where the third inner spacer layer 90C includes silicon nitride, the nitrogen atomic percentage in the third inner spacer layer 90C may be in a range of about 35% to about 50%, or about 40% to about 45%. In embodiments where the third inner spacer layer 90C includes silicon oxycarbonitride or silicon oxynitride, the carbon atomic percentage in the third inner spacer layer 90C may be less than about 10%, may be in a range of about 3% to about 10%, or about 5% to 8%, or may be about 0%; the nitrogen atomic percentage in the third inner spacer layer 90C may be in a range of about 30% to about 50%, or about 37.5% to about 42.5%; and the oxygen atomic percentage in the third inner spacer layer 90C may be in a range of about 25% to about 55%, or about 37.5% to about 42.5%. The second inner spacer layer 90B may have a greater oxygen atomic percentage than the first inner spacer layer 90A and the third inner spacer layer 90C. The third inner spacer layer 90C can be deposited to a thickness T3 of about 1.5 nm to about 3.5 nm, or about 2.3 nm to about 2.7 nm. In some embodiments, the third inner spacer layer 90C and the second inner spacer layer 90B can have a combined thickness of about 3.5 nm to about 5.5 nm, or about 4.3 nm to about 4.7 nm.

[0048] Including a low-k material for the second inner spacer layer 90B and the third inner spacer layer 90C may be contrary to conventional wisdom because the low-k material may be resistant to the etchant used to remove the first semiconductor layers 52A-52C (described below with respect to FIG. 17A to FIG. 17C However, since the first inner spacer layer 90A can be formed of a material having a high etching selectivity to the etchant used to remove the first semiconductor layers 52A-52C, the second inner spacer layer 90B and the third inner spacer layer 90C can be protected from the etchant used to remove the first semiconductor layers 52A-52C, and a low-k material can be used for the second inner spacer layer 90B and the third inner spacer layer 90. This can reduce the internal spacer including the second inner spacer layer 90B and the third inner spacer layer 90C (for example, as described below with respect to FIG. 12A to FIG. 12D The effective k value of the internal spacer 90 discussed above reduces the effective capacitance (C eff ), and improve device performance.

[0049] A gradient region may be formed between the first inner spacer layer 90A and the second inner spacer layer 90B, and between the second inner spacer layer 90B and the third inner spacer layer 90C. The thickness of the gradient region between the first inner spacer layer 90A and the second inner spacer layer 90B may be about 0.5 nm to about 1.0 nm, or about 0.7 nm to about 0.8 nm, and the oxygen atomic concentration may be about 0% to about 60%, or about 27.5% to about 32.5%. The thickness of the gradient region between the second inner spacer layer 90B and the third inner spacer layer 90C may be about 0.5 nm to about 1.0 nm, or about 0.7 nm to about 0.8 nm, and the oxygen atomic concentration may be about 25% to about 60%, or about 40% to about 45%.

[0050] In some embodiments, the first inner spacer layer 90A, the second inner spacer layer 90B, and the third inner spacer layer 90C may be deposited in situ so that no native oxide is formed at the interface between the first inner spacer layer 90A and the second inner spacer layer 90B, or between the second inner spacer layer 90B and the third inner spacer layer 90C. The first inner spacer layer 90A, the second inner spacer layer 90B, and the third inner spacer layer 90C may be deposited by a process having a consistency greater than about 95%, and may be deposited in the sidewall recess 88 having an aspect ratio (the ratio of the depth D1 of the sidewall recess 88 to the width W1 of the sidewall recess 88) greater than about 20. The ratio of the thickness T1 of the first inner spacer layer 90A to the thickness T2 of the second inner spacer layer 90B may be about 0.3 to about 1.0, or about 0.4 to about 0.6. The ratio of the thickness T2 of the second inner spacer layer 90B to the thickness T3 of the third inner spacer layer 90C may be about 0.5 to about 1.5, or about 0.4 to about 0.6. The ratio of the thickness T1 of the first inner spacer layer 90A to the thickness T3 of the third inner spacer layer 90C may be about 0.3 to about 1.0, or about 0.4 to about 0.6.

[0051] Although three inner spacer layers are described, more or fewer inner spacer layers may be formed. For example, in some embodiments, FIG. 10A to FIG. 10C Fewer than three internal spacer layers (eg, two internal spacer layers) or more than three internal spacer layers (eg, four or more internal spacer layers) are formed over the structure shown. The same or similar processes as described above can be used for embodiments including different numbers of internal spacer layers.

[0052] In embodiments where two inner spacer layers are formed, the first inner spacer layer may be the same or similar to the first inner spacer layer 90A, and the second inner spacer layer may be the same or similar to any of the second inner spacer layer 90B or the third inner spacer layer 90C. Thus, the second inner spacer layer may include silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon oxynitride (SiON), etc. In embodiments where the second inner spacer layer includes silicon nitride, the atomic percentage of nitrogen in the second inner spacer layer may be in the range of about 35% to about 50%, or about 40% to about 45%. In embodiments where the second inner spacer layer comprises silicon oxycarbonitride or silicon oxynitride, the carbon atomic percentage in the second inner spacer layer may be less than about 10%, may be in the range of about 0% to about 10%, or about 2.5% to about 7.5%, or may be about 0%; the nitrogen atomic percentage in the second inner spacer layer may be in the range of about 10% to about 50%, or about 27.5% to about 32.5%; and the oxygen atomic percentage in the second inner spacer layer may be in the range of about 25% to about 60%, or about 40% to about 45%. The dielectric constant (k value) of the second inner spacer layer may be about 4.2 to about 6.0, or about 4.9 to about 5.3. The ratio of the thickness of the first inner spacer layer to the thickness of the second inner spacer layer may be about 0.3 to about 1.0, or about 0.4 to about 0.5. Including the first inner spacer layer and the second inner spacer layer having a specified thickness ratio can minimize the effective k value of the inner spacer formed by the first inner spacer layer and the second inner spacer layer, while preventing the first semiconductor layers 52A-52C from being removed (hereinafter referred to as FIG. 17A to FIG. 17C Discussion).

[0053] exist FIG. 12A to FIG. 12D In the process, the first inner spacer layer 90A, the second inner spacer layer 90B, and the third inner spacer layer 90C are etched to form the inner spacer layer 90 . Fig.12D Shows Fig. 12B Detailed view of region 91 of the first inner spacer layer 90A, the second inner spacer layer 90B, and the third inner spacer layer 90C. The etching process of the first inner spacer layer 90A, the second inner spacer layer 90B, and the third inner spacer layer 90C may be a dry etching process or a wet etching process, and may be isotropic. When a wet etching process is used, sulfuric acid (H2SO4), phosphoric acid (H3PO4), diluted hydrofluoric acid (dHF), a combination thereof, or the like may be used to etch the first inner spacer layer 90A, the second inner spacer layer 90B, and the third inner spacer layer 90C.

[0054] like Fig. 12B and 12DAs shown, each inner spacer 90 may be D-shaped in a cross-sectional view. The third inner spacer layer 90C may be the innermost layer and may be D-shaped in a cross-sectional view. The second inner spacer layer 90B may be C-shaped in a cross-sectional view and may surround the top surface, bottom surface, and side surfaces of the third inner spacer layer 90C. The first inner spacer layer 90A may be C-shaped in a cross-sectional view and may surround the top surface, bottom surface, and side surfaces of the second inner spacer layer 90B.

[0055] As previously discussed, the first inner spacer layer 90A, the second inner spacer layer 90B, and the third inner spacer layer 90C may be formed of materials that make the second etching selectivity and the third etching selectivity high. In this way, the second inner spacer layer 90B is etched at a higher rate than the first inner spacer layer 90A or the third inner spacer layer 90C. Fig.12D As shown, this allows the inner spacer 90 to have a W-shaped sidewall in a cross-sectional view. The first inner spacer layer 90A, the second inner spacer layer 90B, and the third inner spacer layer 90C may be etched such that the sidewall of the first inner spacer layer 90A is recessed from the sidewall of the second semiconductor layer 54A-54C by about 1 / 40 mm. to about The sidewalls of the second inner spacer layer 90B are recessed from the sidewalls of the second semiconductor layers 54A-54C by about 1.5 mm. to about The depth D3 is within the range of , and the sidewalls of the third inner spacer layer 90C are recessed from the sidewalls of the second semiconductor layers 54A-54C by about to about Thus, the depth of the sidewall of the inner spacer 90 from the sidewall of the second semiconductor layer 54A-54C may be less than about The depth of the sidewall of the inner spacer 90 from the sidewall of the second semiconductor layer 54A-54C is maintained at about The following may help reduce the effective k value of the inner spacer 90. The ratio of D2:D3 may be about 0.2 to about 1.0, and the ratio of D3:D4 may be about 0.2 to about 1.0. The inner spacer 90 may have a thickness T4 of about 3 nm to about 6 nm, about 4.3 nm to about 4.7 nm, or greater than about 3 nm, and a width W2 of about 8 nm to about 12 nm, or about 9.5 nm to about 10.5 nm. Keeping the thickness T4 of the inner spacer 90 above about 3 nm may help reduce the effective k value of the inner spacer 90. The ratio of the thickness T4 of the inner spacer 90 to the width W2 of the inner spacer 90 may be about 0.5 to about 1.0, or about 0.6 to about 0.8. The inner spacer 90 may have an effective k value of about 4.0 to about 6.0, or about 4.8 to about 5.2.

[0056] By using different materials with different dielectric constants and etching selectivities for the first inner spacer layer 90A, the second inner spacer layer 90B, and the third inner spacer layer 90C, the effective k value of the inner spacer layer 90 can be reduced, the profile of the inner spacer 90 can be improved, and over-etching of the first inner spacer layer 90A, the second inner spacer layer 90B, and the third inner spacer layer 90C can be avoided. This produces a NSFET including the inner spacer 90 with a reduced effective capacitance (C eff ), improved performance and reduced device defects.

[0057] exist FIG. 13A to FIG. 13D In the embodiment, an epitaxial source / drain region 92 is formed in the first recess 86 to apply stress to the second semiconductor layer 54A-54C of the nanostructure 55, thereby improving performance. Fig. 13B As shown, epitaxial source / drain regions 92 are formed in first recesses 86 such that each dummy gate 72 is disposed between a corresponding adjacent pair of epitaxial source / drain regions 92. In some embodiments, first spacers 81 are used to separate the epitaxial source / drain regions 92 from the dummy gates 72 by an appropriate lateral distance so that the epitaxial source / drain regions 92 do not short-circuit the gate of a subsequently formed resulting NSFET.

[0058] The epitaxial source / drain regions 92 in the region 50N (e.g., NMOS region) can be formed by masking the region 50P (e.g., PMOS region). The epitaxial source / drain regions 92 are then epitaxially grown in the first recess 86. The epitaxial source / drain regions 92 can include any acceptable material, such as a material suitable for an n-type NSFET. For example, if the second semiconductor layers 54A-54C are silicon, the epitaxial source / drain regions 92 can include a material that applies tensile strain to the second semiconductor layers 54A-54C, such as silicon, silicon carbide, silicon carbide doped with phosphorus, silicon phosphorus, etc. The epitaxial source / drain regions 92 can have surfaces that protrude from corresponding surfaces of the multilayer stack 56 and can have small facets.

[0059] The epitaxial source / drain regions 92 in the region 50P (e.g., a PMOS region) can be formed by masking the region 50N (e.g., an NMOS region). The epitaxial source / drain regions 92 are then epitaxially grown in the first recess 86. The epitaxial source / drain regions 92 can include any acceptable material, such as a material suitable for a p-type NSFET. For example, if the second semiconductor layers 54A-54C are silicon germanium, the epitaxial source / drain regions 92 can include a material that applies compressive strain on the second semiconductor layers 54A-54C, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain regions 92 can also have surfaces that protrude from corresponding surfaces of the multilayer stack 56 and can have small facets.

[0060] The epitaxial source / drain regions 92, the first semiconductor layers 52A-52C, the second semiconductor layers 54A-54C, and / or the substrate 50 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming source / drain regions, and then annealed. The impurity concentration of the source / drain regions may be about 1×10 19 Atom / cm 3 and about 1×10 21 Atom / cm 3 The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 may be doped in-situ during growth.

[0061] As a result of the epitaxial process used to form epitaxial source / drain regions 92 in regions 50N and 50P, the upper surfaces of epitaxial source / drain regions 92 have facets that extend laterally outward beyond the sidewalls of nanostructures 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same NSFET to merge, such as Fig. 13C In some embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed, as shown in FIG. Fig.13D As shown. Fig. 13C and Fig.13D In the illustrated embodiment, first spacers 81 can be formed to cover the sidewalls of nanostructures 55 and / or portions of substrate 50 extending over STI regions 58, thereby preventing epitaxial growth. In some embodiments, the spacer etch used to form first spacers 81 can be adjusted to remove spacer material to allow the region of epitaxial growth to extend to the surface of STI regions 58.

[0062] exist FIG. 14A to FIG. 14C In the embodiment, the first interlayer dielectric (ILD) 96 is deposited on FIG. 13A to FIG. 13C. The first ILD 96 may be formed of a dielectric material and may be deposited by any suitable method such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain regions 92, the mask 74, and the first spacer 81. The CESL 94 may include a dielectric material having an etch rate different from that of the material of the overlying first ILD 96, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0063] exist FIG. 15A to FIG. 15C In the process, a planarization process such as CMP may be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 72 or the mask 74. FIG. 15A to FIG. 15C In the illustrated embodiment, the planarization process may also remove the mask 74 on the dummy gate 72, and portions of the first spacer 81 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the first spacer 81, and the first ILD 96 are flush. Therefore, the top surface of the dummy gate 72 is exposed through the first ILD 96. In some embodiments, the mask 74 may remain, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 74 and the first spacer 81.

[0064] exist FIG. 16A to FIG. 16C In the embodiment of the present invention, the dummy gate 72 and the mask 74 (if present) are removed in (one or more) etching steps, thereby forming a second recess 98. The portion of the dummy dielectric layer 60 in the second recess 98 may also be removed. In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (one or more) reactive gases that selectively etches the dummy gate 72 at a faster rate than the first ILD 96 or the first spacer 81. Each second recess 98 exposes and / or overlies portions of the multilayer stack 56 that serve as channel regions in the subsequently completed NSFET. The portions of the multilayer stack 56 that serve as channel regions are disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy dielectric layer 60 may serve as an etch stop layer when etching the dummy gate 72. The dummy dielectric layer 60 may then be removed after the dummy gate 72 is removed.

[0065] exist FIG. 17A to FIG. 17CIn the embodiment, the first semiconductor layer 52A-52C is removed and the second groove 98 is extended. The first semiconductor layer 52A-52C can be removed by an isotropic etching process (e.g., wet etching, dry etching, etc.). The first semiconductor layer 52A-52C can be removed using an etchant that is selective to the material of the first semiconductor layer 52A-52C, while the second semiconductor layer 54A-54C, the substrate 50, the STI region 58, and the first internal spacer layer 90A remain relatively unetched compared to the first semiconductor layer 52A-52C. In an embodiment in which the first semiconductor layer 52A-52C includes, for example, SiGe and the second semiconductor layer 54A-54C includes, for example, Si, and the first semiconductor layer 52A-52C is removed by wet etching, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), ozone (O3), ammonia (NH3), a first chemical solution, a second chemical solution, a combination thereof, etc. can be used to remove the first semiconductor layer 52A-52C. The first chemical solution (sometimes referred to as a standard clean 1 (SC1) solution) may include ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O). The second chemical solution (sometimes referred to as a standard clean 2 (SC2) solution) may include hydrochloric acid (HCl), hydrogen peroxide (H2O2), and water (H2O). In embodiments where the first semiconductor layers 52A-52C are removed by dry etching, hydrogen fluoride (HF), fluorine (F2), other fluorine-based gases, chlorine-based gases, etc. may be used to remove the first semiconductor layers 52A-52C.

[0066] As previously discussed, the first inner spacer layer 90A can be formed of a material having a high first etch selectivity relative to the material of the first semiconductor layers 52A-52C. Removing the first semiconductor layers 52A-52C can cause some etching of the first inner spacer layer 90A. For example, the etching process for removing the first semiconductor layers 52A-52C can etch the exposed surface of the first inner spacer layer 90A to a depth of about 0.5nm to about 1.5nm, or about 0.8nm to about 1.2nm. The first inner spacer layer 90A can be deposited to such a thickness that after removing the first semiconductor layers 52A-52C, the second inner spacer layer 90B remains unexposed by the first inner spacer layer 90A. The first inner spacer layer 90A formed of a material having a high first etch selectivity prevents etching of the second inner spacer layer 90B and the third inner spacer layer 90C (formed of a low-k dielectric material), thereby reducing the effective k value of the inner spacer 90, improving the profile of the inner spacer 90, and avoiding over-etching of the first inner spacer layer 90A, the second inner spacer layer 90B, and the third inner spacer layer 90C. This produces a NSFET including the inner spacer 90 with a reduced effective capacitance (C eff), improved performance and reduced device defects.

[0067] exist 18A to 18D In the embodiment, a gate dielectric layer 100 and a gate electrode 102 are formed for replacing a gate. Fig.18D Shows Fig.18A Detailed view of region 101 of the gate dielectric layer 100. The gate dielectric layer 100 is conformally deposited in the second recess 98, for example, on the top surface and sidewalls of the substrate 50, and on the top surface, sidewalls, and bottom surface of the second semiconductor layers 54A-54C. The gate dielectric layer 100 may also be deposited on the top surfaces of the first ILD 96, CESL 94, and STI regions 58, and on the top surface and sidewalls of the first spacer 81.

[0068] According to some embodiments, the gate dielectric layer 100 includes silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a k value greater than about 7.0 and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The formation method of the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0069] The gate electrode 102 is deposited on the gate dielectric layer 100 and fills the remaining portion of the second recess 98. The gate electrode 102 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Fig.18A and Fig.18B A single-layer gate electrode 102 is shown in FIG. 1 , but the gate electrode 102 may include any number of liner layers 102A, any number of work function adjustment layers 102B, and a filling material 102C, such as Fig.18D As shown. After filling the second groove 98, a planarization process such as CMP may be performed to remove the material of the gate electrode 102 and the excess portion of the gate dielectric layer 100 that is above the top surface of the first ILD 96. The material of the gate electrode 102 and the remaining portion of the gate dielectric layer 100 thereby form a replacement gate of the resulting NSFET. The gate electrode 102 and the gate dielectric layer 100 may be collectively referred to as a "gate stack". The gate electrode 102 may have a gate length of about 13.0 nm to about 16.0 nm, or about 14.0 nm to about 15.0 nm.

[0070] The formation of the gate dielectric layer 100 in the region 50N and the region 50P may occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 may occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region may be formed by a different process, such that the gate dielectric layer 100 may be a different material, and / or the gate electrode 102 in each region may be formed by a different process, such that the gate electrode 102 may be a different material. When different processes are used, various masking steps may be used to mask and expose the appropriate regions.

[0071] exist FIG. 19A to FIG. 19C In some embodiments, a second ILD 106 is deposited over the first ILD 96. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and may be deposited by any suitable method such as CVD, PECVD, etc. In some embodiments, before forming the second ILD 106, the gate stack (including the gate dielectric layer 100 and the corresponding overlying gate electrode 102) is recessed to form a groove directly above the gate stack and between opposing portions of the first spacer 81. A gate mask 104 is filled in the groove, which includes one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.), and a planarization process is then performed to remove excess portions of the dielectric material extending over the first ILD 96. A gate contact (e.g., described below with respect to FIG. 20A to FIG. 20C A gate contact 112 is discussed to penetrate the gate mask 104 to contact the top surface of the recessed gate electrode 102 .

[0072] exist FIG. 20A to FIG. 20C, a gate contact 112 and a source / drain contact 114 are formed through the second ILD 106 and the first ILD 96. An opening for the source / drain contact 114 is formed through the first ILD 96 and the second ILD 106, and an opening for the gate contact 112 is formed through the second ILD 106 and the gate mask 104. The opening can be formed using acceptable photolithography and etching techniques. One or more liners, such as a diffusion barrier layer, an adhesion layer, a combination or multiple layers thereof, etc., can be formed in the opening, and a conductive material can be formed over the (one or more) liners. The (one or more) liners may include titanium, titanium nitride, tantalum, tantalum nitride, a combination or multiple layers thereof, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 106. The remaining (one or more) liners and conductive materials form source / drain contacts 114 and gate contacts 112 in the opening. An annealing process may be performed to form silicide at the interface between the epitaxial source / drain regions 92 and the source / drain contacts 114. The source / drain contacts 114 are physically and electrically coupled to the epitaxial source / drain regions 92, and the gate contact 112 is physically and electrically coupled to the gate electrode 102. The source / drain contacts 114 and the gate contact 112 may be formed in different processes, or may be formed in the same process. Although shown as being formed in the same cross-section, it should be understood that each of the source / drain contacts 114 and the gate contact 112 may be formed in different cross-sections, which may avoid shorting the contacts.

[0073] Forming the inner spacer 90 by forming the first inner spacer layer 90A, the second inner spacer layer 90B, and the third inner spacer layer 90C from different materials having different dielectric constants and etching selectivities can reduce the effective k value of the inner spacer 90, improve the profile of the inner spacer 90, and avoid over-etching of the first inner spacer layer 90A, the second inner spacer layer 90B, and the third inner spacer layer 90C. This produces a NSFET including the inner spacer 90 with a reduced effective capacitance (C eff ), improved performance and reduced device defects.

[0074] According to one embodiment, a semiconductor device includes: a substrate; a plurality of semiconductor channel structures on the substrate; a gate structure on the plurality of semiconductor channel structures, the gate structure extending between adjacent semiconductor channel structures in the plurality of semiconductor channel structures; a source / drain region adjacent to the gate structure, the source / drain region contacting the plurality of semiconductor channel structures; and an internal spacer inserted between the source / drain region and the gate structure, the internal spacer including: a first internal spacer layer contacting the gate structure and the source / drain region, the first internal spacer layer including silicon and nitrogen; and a second internal spacer layer contacting the first internal spacer layer and the source / drain region, the second internal spacer layer including silicon, oxygen and nitrogen, the second internal spacer layer having a lower dielectric constant than the first internal spacer layer. In one embodiment, a first sidewall of the internal spacer contacts the source / drain region, the first sidewall having a W shape in a cross-sectional view. In one embodiment, the first inner spacer layer comprises silicon carbonitride, the first inner spacer layer has a carbon atomic percentage of 5% to 20%, and the first inner spacer layer has a nitrogen atomic percentage of 25% to 45%. In one embodiment, the first inner spacer layer comprises silicon nitride, and the first inner spacer layer has a nitrogen atomic percentage from 35% to 50%. In one embodiment, the second inner spacer layer comprises silicon carbon oxynitride, the second inner spacer layer has an oxygen atomic percentage of 25% to 60%, the second inner spacer layer has a carbon atomic percentage of less than 10%, and the second inner spacer layer has a nitrogen atomic percentage of 10% to 50%. In one embodiment, the second inner spacer layer comprises silicon oxynitride, the second inner spacer layer has an oxygen atomic percentage of 25% to 60%, and the second inner spacer layer has a nitrogen atomic percentage of 10% to 50%. In one embodiment, the first inner spacer layer has a dielectric constant of 6.0 to 7.3, and the second inner spacer layer has a dielectric constant of 4.2 to 6.0. In one embodiment, a ratio of the thickness of the first inner spacer layer to the thickness of the second inner spacer layer is 4.5.

[0075] According to another embodiment, a semiconductor device includes: a semiconductor substrate; a plurality of channel regions on the semiconductor substrate; a gate structure on the plurality of channel regions, the gate structure extending between adjacent ones of the plurality of channel regions; an upper spacer along a sidewall of the gate structure; a source / drain region adjacent to the gate structure; and a plurality of internal spacers, each internal spacer being inserted between adjacent ones of the plurality of channel regions, each internal spacer being inserted between the source / drain region and the gate structure, each internal spacer comprising The invention relates to a first inner spacer layer, which contacts the gate structure and the source / drain region, and the first inner spacer layer includes silicon and nitrogen; a second inner spacer layer, which contacts the first inner spacer layer and the source / drain region, and the second inner spacer layer includes silicon, oxygen and nitrogen, and the second inner spacer layer has a lower dielectric constant than the first inner spacer layer; and a third inner spacer layer, which contacts the second inner spacer layer and the source / drain region, and the third inner spacer layer includes silicon and nitrogen, and the sidewall of the inner spacer adjacent to the source / drain region is W-shaped in a cross-sectional view. In one embodiment, the third inner spacer layer includes silicon, nitrogen and oxygen, and the atomic percentage of oxygen in the second inner spacer layer is greater than the atomic percentage of oxygen in the third inner spacer layer. In one embodiment, the first inner spacer layer, the second inner spacer layer and the third inner spacer layer include carbon, and the atomic percentage of carbon in the first inner spacer layer is greater than the atomic percentage of carbon in the second inner spacer layer and the third inner spacer layer. In one embodiment, the thickness of the inner spacer measured between the source / drain region and the gate structure is greater than 3nm. In one embodiment, the sidewalls of the inner spacer are recessed less than 10° from the sidewalls of the plurality of channel regions. In one embodiment, the dielectric constant of the first inner spacer layer is 6.0 to 7.3, the dielectric constant of the second inner spacer layer is 4.2 to 5.7, and the dielectric constant of the third inner spacer layer is 4.5 to 6.0.

[0076] According to another embodiment, a method includes: forming a multilayer stack above a semiconductor substrate, the multilayer stack including alternating layers of a first semiconductor material and a second semiconductor material, the second semiconductor material being different from the first semiconductor material; etching the sidewalls of the first semiconductor material to form sidewall grooves; depositing a first internal spacer layer above the multilayer stack and in the sidewall grooves; depositing a second internal spacer layer above the first internal spacer layer; depositing a third internal spacer layer to fill the sidewall grooves; performing a first etching process to etch the first internal spacer layer, the second internal spacer layer, and the third internal spacer layer, and forming an internal spacer including the remaining portions of the first internal spacer layer, the second internal spacer layer, and the third internal spacer layer in the sidewall groove, the first etching process etching the second internal spacer layer at a greater etching rate than the etching rate of the third internal spacer layer; performing a second etching process to remove the first semiconductor material and form a first groove extending between the internal spacers, the second etching process etching the first internal spacer layer at a smaller etching rate than the etching rate of the first semiconductor material; and forming a gate structure in the first groove. In one embodiment, the first inner spacer layer, the second inner spacer layer, and the third inner spacer layer are deposited in situ. In one embodiment, the first inner spacer layer, the second inner spacer layer, and the third inner spacer layer are deposited at a temperature of 500° C. to 680° C. In one embodiment, during the second etching process, the ratio of the etching rate of the first semiconductor material to the etching rate of the first inner spacer layer is 50 to 500. In one embodiment, during the first etching process, the ratio of the etching rate of the second inner spacer layer to the etching rate of the third inner spacer layer is 1.2 to 3.0. In one embodiment, during the first etching process, the ratio of the etching rate of the second inner spacer layer to the etching rate of the first inner spacer layer is 1.2 to 3.0.

[0077] The features of several embodiments are summarized above so that those skilled in the art can better understand the specific embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0078] Example 1. A semiconductor device, comprising: a substrate; a plurality of semiconductor channel structures located on the substrate; a gate structure located on the plurality of semiconductor channel structures, wherein the gate structure extends between adjacent semiconductor channel structures among the plurality of semiconductor channel structures; a source / drain region adjacent to the gate structure, the source / drain region contacting the plurality of semiconductor channel structures; and an internal spacer inserted between the source / drain region and the gate structure, the internal spacer comprising: a first internal spacer layer contacting the gate structure and the source / drain region, the first internal spacer layer comprising silicon and nitrogen; and a second internal spacer layer contacting the first internal spacer layer and the source / drain region, the second internal spacer layer comprising silicon, oxygen and nitrogen, the second internal spacer layer having a lower dielectric constant than the first internal spacer layer.

[0079] Example 2. The semiconductor device of Example 1, wherein a first sidewall of the inner spacer contacts the source / drain region, the first sidewall having a W-shape in a cross-sectional view.

[0080] Example 3. A semiconductor device according to Example 1, wherein the first inner spacer layer includes silicon carbon nitride, wherein the first inner spacer layer has a carbon atomic percentage of 5% to 20%, and wherein the first inner spacer layer has a nitrogen atomic percentage of 25% to 45%.

[0081] Example 4. The semiconductor device of Example 1, wherein the first inner spacer layer comprises silicon nitride, and wherein the first inner spacer layer has a nitrogen atomic percentage from 35% to 50%.

[0082] Example 5. A semiconductor device according to Example 1, wherein the second internal spacer layer includes silicon oxycarbonitride, wherein the second internal spacer layer has an oxygen atomic percentage of 25% to 60%, wherein the second internal spacer layer has a carbon atomic percentage of less than 10%, and wherein the second internal spacer layer has a nitrogen atomic percentage of 10% to 50%.

[0083] Example 6. A semiconductor device according to Example 1, wherein the second internal spacer layer includes silicon oxynitride, wherein the second internal spacer layer has an oxygen atomic percentage of 25% to 60%, and wherein the second internal spacer layer has a nitrogen atomic percentage of 10% to 50%.

[0084] Example 7. The semiconductor device of Example 1, wherein the first inner spacer layer has a dielectric constant of 6.0 to 7.3, and wherein the second inner spacer layer has a dielectric constant of 4.2 to 6.0.

[0085] Example 8. The semiconductor device of Example 1, wherein a ratio of a thickness of the first inner spacer layer to a thickness of the second inner spacer layer is 4.5.

[0086] Example 9. A semiconductor device, comprising: a semiconductor substrate; a plurality of channel regions located on the semiconductor substrate; a gate structure located on the plurality of channel regions, wherein the gate structure extends between adjacent ones of the plurality of channel regions; an upper spacer along a sidewall of the gate structure; a source / drain region adjacent to the gate structure; and a plurality of internal spacers, each of the internal spacers being inserted between adjacent ones of the plurality of channel regions, each of the internal spacers being inserted between the source / drain region and the gate structure, each of the internal spacers comprising: an inner spacer layer in contact with the gate structure and the source / drain region, the first inner spacer layer comprising silicon and nitrogen; a second inner spacer layer in contact with the first inner spacer layer and the source / drain region, the second inner spacer layer comprising silicon, oxygen and nitrogen, the second inner spacer layer having a lower dielectric constant than the first inner spacer layer; and a third inner spacer layer in contact with the second inner spacer layer and the source / drain region, the third inner spacer layer comprising silicon and nitrogen, wherein a sidewall of the inner spacer adjacent to the source / drain region is W-shaped in a cross-sectional view.

[0087] Example 10. The semiconductor device of Example 9, wherein the third inner spacer layer comprises silicon, nitrogen, and oxygen, and wherein an atomic percentage of oxygen in the second inner spacer layer is greater than an atomic percentage of oxygen in the third inner spacer layer.

[0088] Example 11. A semiconductor device according to Example 9, wherein the first internal spacer layer, the second internal spacer layer, and the third internal spacer layer include carbon, and wherein the atomic percentage of carbon in the first internal spacer layer is greater than the atomic percentage of carbon in the second internal spacer layer and the third internal spacer layer.

[0089] Example 12. The semiconductor device of Example 9, wherein a thickness of the internal spacer measured between the source / drain region and the gate structure is greater than 3 nm.

[0090] Example 13. The semiconductor device of Example 9, wherein a sidewall of the inner spacer is recessed from a sidewall of the plurality of channel regions by less than

[0091] Example 14. The semiconductor device of Example 9, wherein the dielectric constant of the first inner spacer layer is 6.0 to 7.3, wherein the dielectric constant of the second inner spacer layer is 4.2 to 5.7, and wherein the dielectric constant of the third inner spacer layer is 4.5 to 6.0.

[0092] Example 15. A method for forming a semiconductor device, comprising: forming a multilayer stack above a semiconductor substrate, the multilayer stack comprising alternating layers of a first semiconductor material and a second semiconductor material, the second semiconductor material being different from the first semiconductor material; etching the sidewalls of the first semiconductor material to form sidewall grooves; depositing a first internal spacer layer above the multilayer stack and in the sidewall grooves; depositing a second internal spacer layer above the first internal spacer layer; depositing a third internal spacer layer to fill the sidewall grooves; performing a first etching process to etch the first internal spacer layer, the second internal spacer layer, and the third internal spacer layer, and forming an internal spacer in the sidewall groove comprising the first internal spacer layer, the second internal spacer layer, and the remaining portion of the third internal spacer layer, wherein the first etching process etches the second internal spacer layer at a greater etching rate than the etching rate of the third internal spacer layer; performing a second etching process to remove the first semiconductor material and form a first groove extending between the internal spacers, wherein the second etching process etches the first internal spacer layer at a smaller etching rate than the etching rate of the first semiconductor material; and forming a gate structure in the first groove.

[0093] Example 16. The method of Example 15, wherein the first inner spacer layer, the second inner spacer layer, and the third inner spacer layer are deposited in situ.

[0094] Example 17. The method of Example 15, wherein the first inner spacer layer, the second inner spacer layer, and the third inner spacer layer are deposited at a temperature of 500°C to 680°C.

[0095] Example 18. The method of Example 15, wherein during the second etching process, a ratio of an etching rate of the first semiconductor material to an etching rate of the first inner spacer layer is 50 to 500.

[0096] Example 19. The method of Example 15, wherein during the first etching process, a ratio of an etching rate of the second inner spacer layer to an etching rate of the third inner spacer layer is 1.2 to 3.0.

[0097] Example 20. The method of Example 19, wherein during the first etching process, a ratio of an etching rate of the second inner spacer layer to an etching rate of the first inner spacer layer is 1.2 to 3.0.

Claims

1. A semiconductor device, comprising: substrate; A plurality of semiconductor channel structures are located on the substrate; a gate structure located on the plurality of semiconductor channel structures, wherein the gate structure extends between adjacent semiconductor channel structures among the plurality of semiconductor channel structures; a source / drain region adjacent to the gate structure, the source / drain region contacting the plurality of semiconductor channel structures; and an inner spacer, interposed between the source / drain region and the gate structure, the inner spacer comprising: a first inner spacer layer in contact with the gate structure and the source / drain regions, the first inner spacer layer comprising silicon and nitrogen; and a second inner spacer layer in contact with the first inner spacer layer and the source / drain regions, the second inner spacer layer comprising silicon, oxygen, and nitrogen, the second inner spacer layer having a lower dielectric constant than the first inner spacer layer; The first sidewall of the inner spacer contacts the source / drain region, the first sidewall has a W-shape in a cross-sectional view, and the sidewall of the source / drain region has a shape corresponding to the W-shape of the first sidewall.

2. The semiconductor device according to claim 1, wherein The first inner spacer layer includes silicon carbonitride, wherein the first inner spacer layer has a carbon atomic percentage of 5% to 20%, and wherein the first inner spacer layer has a nitrogen atomic percentage of 25% to 45%.

3. The semiconductor device according to claim 1, wherein The first inner spacer layer includes silicon nitride, and wherein the first inner spacer layer has a nitrogen atomic percentage from 35% to 50%.

4. The semiconductor device according to claim 1, wherein: The second inner spacer layer includes silicon oxycarbonitride, wherein the second inner spacer layer has an oxygen atomic percentage of 25% to 60%, wherein the second inner spacer layer has a carbon atomic percentage of less than 10%, and wherein the second inner spacer layer has a nitrogen atomic percentage of 10% to 50%.

5. The semiconductor device according to claim 1, wherein The second inner spacer layer includes silicon oxynitride, wherein the second inner spacer layer has an oxygen atomic percentage of 25% to 60%, and wherein the second inner spacer layer has a nitrogen atomic percentage of 10% to 50%.

6. The semiconductor device according to claim 1, wherein The first inner spacer layer has a dielectric constant of 6.0 to 7.3, and wherein the second inner spacer layer has a dielectric constant of 4.2 to 6.

0.

7. The semiconductor device according to claim 1, wherein A ratio of a thickness of the first inner spacer layer to a thickness of the second inner spacer layer is 4.

5.

8. A semiconductor device comprising: Semiconductor substrate; A plurality of channel regions are located on the semiconductor substrate; a gate structure located above the plurality of channel regions, wherein the gate structure extends between adjacent channel regions among the plurality of channel regions; an upper spacer along a sidewall of the gate structure; a source / drain region adjacent to the gate structure; and a plurality of inner spacers, each of the inner spacers being interposed between adjacent channel regions among the plurality of channel regions, each of the inner spacers being interposed between the source / drain region and the gate structure, each of the inner spacers comprising: a first inner spacer layer in contact with the gate structure and the source / drain regions, the first inner spacer layer comprising silicon and nitrogen; a second inner spacer layer in contact with the first inner spacer layer and the source / drain regions, the second inner spacer layer comprising silicon, oxygen, and nitrogen, the second inner spacer layer having a lower dielectric constant than the first inner spacer layer; and a third inner spacer layer in contact with the second inner spacer layer and the source / drain region, the third inner spacer layer comprising silicon and nitrogen, wherein a sidewall of the inner spacer adjacent to the source / drain region is W-shaped in a cross-sectional view, and a sidewall of the source / drain region has a shape corresponding to the W-shape of the sidewall of the inner spacer.

9. The semiconductor device according to claim 8, wherein: The third inner spacer layer includes silicon, nitrogen, and oxygen, and wherein an atomic percentage of oxygen in the second inner spacer layer is greater than an atomic percentage of oxygen in the third inner spacer layer.

10. The semiconductor device according to claim 8, wherein The first, second, and third inner spacer layers include carbon, and wherein an atomic percentage of carbon in the first inner spacer layer is greater than an atomic percentage of carbon in the second and third inner spacer layers.

11. The semiconductor device according to claim 8, wherein: The thickness of the inner spacer measured between the source / drain region and the gate structure is greater than 3 nm.

12. The semiconductor device according to claim 8, wherein: The sidewalls of the inner spacer are recessed less than 10 Å from the sidewalls of the plurality of channel regions.

13. The semiconductor device according to claim 8, wherein: The first inner spacer layer has a dielectric constant of 6.0 to 7.3, wherein the second inner spacer layer has a dielectric constant of 4.2 to 5.7, and wherein the third inner spacer layer has a dielectric constant of 4.5 to 6.

0.

14. A method for forming a semiconductor device, comprising: forming a multilayer stack over a semiconductor substrate, the multilayer stack comprising alternating layers of a first semiconductor material and a second semiconductor material, the second semiconductor material being different from the first semiconductor material; etching sidewalls of the first semiconductor material to form sidewall recesses; depositing a first inner spacer layer over the multilayer stack and in the sidewall recesses; depositing a second inner spacer layer over the first inner spacer layer; depositing a third inner spacer layer to fill the sidewall recess; performing a first etching process to etch the first inner spacer layer, the second inner spacer layer, and the third inner spacer layer and form an inner spacer including remaining portions of the first inner spacer layer, the second inner spacer layer, and the third inner spacer layer in the sidewall recess, wherein the first etching process etches the second inner spacer layer at a greater etching rate than an etching rate of the third inner spacer layer; performing a second etching process to remove the first semiconductor material and form a first recess extending between the inner spacers, wherein the second etching process etches the first inner spacer layer at a smaller etching rate than an etching rate of the first semiconductor material; and A gate structure is formed in the first groove.

15. The method according to claim 14, wherein: The first inner spacer layer, the second inner spacer layer, and the third inner spacer layer are deposited in-situ.

16. The method according to claim 14, wherein: The first inner spacer layer, the second inner spacer layer, and the third inner spacer layer are deposited at a temperature of 500°C to 680°C.

17. The method according to claim 14, wherein: During the second etching process, a ratio of an etching rate of the first semiconductor material to an etching rate of the first inner spacer layer is 50 to 500.

18. The method according to claim 14, wherein: During the first etching process, a ratio of an etching rate of the second inner spacer layer to an etching rate of the third inner spacer layer is 1.2 to 3.

0.

19. The method according to claim 18, wherein: During the first etching process, a ratio of an etching rate of the second inner spacer layer to an etching rate of the first inner spacer layer is 1.2 to 3.0.

Images