Amplifier circuit, corresponding comparator device and method

Abstract

Embodiments disclose an amplifier circuit, a corresponding comparator device, and a method. A preamplifier circuit includes a first pair of transistors and a second pair of transistors. The first pair of transistors and the second pair of transistors have current flow paths therethrough that are coupled at first and second output nodes, and first and second current flow lines are provided intermediate a power supply node and ground. The two pairs of transistors include: first and second input transistors located intermediate one of a power supply node and ground providing a respective input node and an output node; first and second load transistors located intermediate one of a power supply node and ground and an output node. The load transistors have control terminals capacitively coupled to the other of the power supply node and ground, and a reset switch means is provided that can be periodically activated to short-circuit the first output node, the second output node, and the control terminals of the first and second load transistors.

Description

Technical Field

[0001] The present disclosure relates to a (pre-)amplifier circuit.

[0002] One or more embodiments may be applied to, for example, a dynamic comparator. Background Art

[0003] Currently, whenever it is necessary to compare two electrical quantities (e.g., two analog voltages), a comparator circuit is used.

[0004] In a conventional manner, the result of the comparison is returned as a logic value, and this logic value is stored using some kind of digital latch.

[0005] The circuit devices involved may be affected by non-ideal factors such as noise and mismatch, which may lead to a reduction in comparison accuracy. This reduced accuracy may in turn lead to a certain amount of incorrect decisions. For example, these incorrect decisions may be taken into account during system design, thereby increasing the robustness against these errors. Improving the comparator performance may additionally lead to an improvement in the efficiency of the system as a whole.

[0006] To achieve this goal in comparator design, one method that has been considered may involve introducing one or more (pre-)amplifiers upstream of the latch to reduce latch offset and input-referred noise generators. Summary of the Invention

[0007] The aim of one or more embodiments is to provide an improved solution that provides, for example, improved pre-amplifier behavior in a comparator circuit.

[0008] According to one or more embodiments, this aim may be achieved by a circuit having: a first input transistor having conductive terminals coupled to one of a power supply node and a ground, and a first output node, wherein the first input transistor has a control terminal coupled to a first input node. The circuit includes a second input transistor having conductive terminals coupled to one of a power supply node and a ground, and a second output node, wherein the second input transistor has a control terminal coupled to a second input node. The circuit includes a capacitor having a first side coupled to the other of a power supply node and a ground and having a second side.

[0009] The circuit includes a first load transistor having conductive terminals coupled to a first output node and to the other of a power supply node and a ground node, respectively, wherein the first load transistor has a control terminal coupled to a second side of a capacitor. The circuit includes a second load transistor having conductive terminals coupled to a second output node and to the other of a power supply node and a ground node, respectively, wherein the second load transistor has a control terminal coupled to a second side of the capacitor. The circuit includes a reset switch circuit configured to short circuit the first output node, the second output node, the control terminal of the first load transistor, and the control terminal of the second load transistor in response to being activated. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0011] Figure 1 is an overall block diagram of a comparator circuit including a preamplifier,

[0012] Figure 2 and Figure 3 is a circuit diagram of a conventional preamplifier,

[0013] Figure 4 shows an exemplary diagram of possible operations of the preamplifier circuit as Figure 3 shown,

[0014] Figure 5 is Figure 3 an example of certain characteristics of a part of the circuit diagram of

[0015] Figure 6 is a circuit diagram of an embodiment described in this specification,

[0016] Figure 7A and Figure 7B are examples of possible operations of an embodiment described in this specification, and

[0017] Figure 8 is a circuit diagram of an embodiment illustrated as Figure 6 implemented with other component (transistor) types. DETAILED DESCRIPTION

[0018] In the following description, various specific details are given to provide a thorough understanding of the various exemplary embodiments of this specification. These embodiments may be practiced without one or more of the specific details, or may be practiced using other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring various aspects of the embodiments. Throughout the specification, references to "one embodiment" or "an embodiment" mean that the particular features, structures, or characteristics described in connection with that embodiment are included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Additionally, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0019] As previously mentioned, one method that has been considered in comparator design may involve introducing one or more (pre-)amplifiers upstream of the latch to reduce latch offset and input-referred noise generators.

[0020] Figure 1 is a general example of such a method in comparator circuit 10, which includes a pre-amplifier 12 having two inputs IN P and IN N , and these two inputs IN P and IN N are configured to receive two corresponding (analog) signals - hereinafter, for simplicity, the same name will be used for the signal and the circuit element where the signal may appear - for comparison.

[0021] As Figure 1 illustrated, the pre-amplifier 12 is configured as a differential amplifier having a differential output with two lines leading to the latch circuit 14, and the latch circuit 14 has two outputs OUT P and OUT N , and these two outputs OUT P and OUT N are configured to provide a (differential) output signal OUT′ = OUT′ P –OUT′ N therebetween, and the value of this output signal is a function of the comparison result IN P >IN N or IN P <IN N .

[0022] The structure of the latch circuit 14 as illustrated herein can be considered a conventional structure in the art and is well-known to those skilled in the art, which makes it unnecessary to provide a more detailed description of such a latch structure herein.

[0023] One or more embodiments discussed herein relate primarily to the (pre-)amplifier 12.

[0024] A typical example of a conventional preamplifier can be based on a classical gm / gm (transconductance) gain stage, such as that discussed in I. Mehr and L. Singer: “A 55-mW, 10-bit, 40-Msamples / s Nyquist-Rate CMOS ADC,” IEEE Journal of Solid-State Circuits, Vol. 35, No. 3, March 2000.

[0025] As Figure 2 illustrated, such a gain stage can include two current flow lines from the power supply node VDD to a common tail current generator I T (referred to as ground GND). Each current line includes a cascaded current flow path through two transistors (MOSFET transistors, e.g., having a source-drain current flow path through the MOSFET transistor) M1, M3 and M2, M4.

[0026] The control terminals (e.g., gates in the case of field effect transistors such as MOSFET transistors) of the two transistors M1 and M2 facing the current generator I T provide two inputs INP and INN to the preamplifier stage 12.

[0027] The two transistors M3 and M4 facing the power supply node VDD are in a diode arrangement, their control terminals are shorted to the current flow path (i.e., e.g., in the case of field effect transistors such as MOSFET transistors, the gates are shorted to the source-drain current flow path), and are adapted to provide two outputs OUT P and OUT N to Figure 1 the latch 14 in the comparator device illustrated.

[0028] Figure 2 An advantage of the illustrated circuit is that it does not involve common-mode feedback. A major disadvantage may be its inherently low gain, and many such stages may be involved in those arrangements aimed at reducing input-referred non-idealities in the latch: this can have a negative impact on area, power consumption, and speed.

[0029] An improved architecture is disclosed in "A Distortion Compensation Flash Analog-to-Digital Conversion Technique" by V. Srinivas, S. Pavan, A. Lachhwani, and N. Sasidhar, IEEE Journal of solid state circuit (IEEE Solid-State Circuits Magazine), Vol. 41, No. 9, September 2006.

[0030] In Figure 3 such an arrangement is illustrated, where components or assemblies similar to those already discussed in connection with the previous figures are denoted by the same reference symbols, and thus the corresponding description will not be repeated for the sake of brevity.

[0031] Here, transistors M1 and M2 again provide a differential input pair, which is configured to receive the input signals IN P and IN N , while transistors M3 and M4 again provide two outputs OUT P and OUT N .

[0032] In the arrangement illustrated as Figure 3 , transistors M3 and M4:

[0033] are no longer (directly) diode-connected,

[0034] couple (short-circuit) the current paths passing through them at the sides of M3 and M4 opposite to the power supply node VDD, and

[0035] provide common-mode feedback, while the other two transistors M5 and M6 are respectively provided with current flow paths passing through them (e.g., source-drain in the case of field-effect transistors such as MOSFET transistors), and the current flow paths are along from VDD to GND (via I T ), through M1, M3 (in the case of M5) in the middle, and through M2, M4 (in the case of M6) in the middle.

[0036] In this way, M5 and M6 act as active loads, which have mutually coupled control terminals (e.g., gates in the case of field-effect transistors such as MOSFET transistors) held at a bias voltage V BIAS (provided in a manner known to those skilled in the art).

[0037] In the arrangement illustrated as Figure 3 , M3 and M4 provide two outputs OUT P and OUTN For completeness, Figure 3 also shown is an output capacitor C coupled between the control terminals (e.g., the gates in the case of MOSFET transistors) of M3 and M4 and ground GND L The capacitor C L represents the parasitic capacitance at the input of the latch circuit 14 and the parasitic capacitance associated with the wiring (i.e., the wiring coupling the preamplifier 12 and the latch circuit 14).

[0038] In the arrangement illustrated as Figure 3 shown, the control terminals of M3 and M4 are coupled between M1 and M5 and between M2 and M6 (at the current path passing through them), and a reset switch is coupled therebetween, i.e., between OUT P and OUT N .

[0039] Such a reset switch can be controlled in a manner known to those skilled in the art, for example, by a reset block RST that can operate in a coordinated manner with the latch circuit 14, as illustrated below.

[0040] Assuming that all the transistors shown are operating in the saturation region, example waveforms of RST (“high” = conducting and “low” = non-conducting) and the differential output OUT (i.e., OUT P - OUT N ) can be as shown in the figures of Figure 4 . These figures refer to a common time (abscissa) scale t.

[0041] During the reset phase (RST = 1, i.e., the reset switch controlled by RST is conducting), the nodes OUT P and OUT N are shorted to each other, and the differential output OUT = OUT P - OUT N is zero.

[0042] As a result of the reset being released (RST = 0, i.e., the reset switch controlled by RST is non-conducting), the circuit operates as an integrator, and the dynamic gain G is limited by the parasitic capacitance C L at the output node:

[0043] G = output / input = gm 12 ·T INT / C L

[0044] where IN = IN P - IN N and OUT = OUT P - OUT N are the differential input and output, respectively, and gm12 is the input transconductance, T INT is the integration time separating the two reset operations, C L is the total load capacitance including the parasitic capacitance, as described above.

[0045] The above equation shows that for a given integration time (usually set by the operating frequency of the system), reducing the load capacitance can help save current without sacrificing gain.

[0046] Note that from this point of view, the (always-connected) gate capacitances of the common-mode feedback transistors M3 and M4 can represent a source of gain loss, which may be unacceptable for (very) low-power designs.

[0047] Also note that another source of additional power consumption may be related to the bias V of the "active load" transistors M5 and M6 BIAS and the transistors M5 and M6 may involve additional current branches.

[0048] Finally, as Figure 3 illustrated, the arrangement may require a trade-off between noise and output swing, which cannot be ignored when the noise performance of the preamplifier is an important aspect.

[0049] In this regard, the circuit portion Figure 5 reproduced in Figure 3 can be considered.

[0050] The common-mode output of this circuit portion can be written as:

[0051] V CM = (OUT P + OUT N ) / 2 = VDD - |V TH | - |V OV3 |

[0052] where |V TH | and |V OV3 | are the threshold voltage and overdrive voltage of transistor M3, respectively.

[0053] The maximum output voltage V MAX OUT that keeps the output generator in saturation can be expressed as:

[0054] V MAX OUT = VDD - |V OV3 | - |V OV5 |

[0055] Each term has an obvious meaning.

[0056] Therefore, the maximum output swing ΔV MAX is:

[0057] ΔV MAX = V MAX OUT - V CM = |V TH |- |V OV5 |

[0058] This equation indicates that for a certain threshold voltage (determined by technology options), increasing the output swing means a decrease in the overdrive voltage of the load transistor, which may lead to an undesirable deterioration in terms of the associated noise contribution.

[0059] In one or more embodiments, the aforementioned discussed drawbacks can be overcome by resorting to a circuit such as Figure 6 illustrated.

[0060] Here again, components or assemblies similar to those already discussed in connection with the previous figures are denoted by the same reference symbols, and thus the corresponding descriptions will not be repeated for the sake of brevity.

[0061] It should also be understood that the circuit illustrated in Figure 6 (and Figure 7A 、 Figure 7B and Figure 8 ) is suitable for use as a pre - amplifier 12 in a comparator device 10 such as illustrated in Figure 1 .

[0062] Figure 6 The basic operating principle of the illustrated circuit is substantially the same as that provided by V. Srinivas et al.: Here again, consider integrating the current on the load capacitor C L at the pre - amplifier stage.

[0063] By direct comparison with the circuit of Figure 3 , in the circuit illustrated in Figure 6 , the transistor pairs M3 and M5 and the transistor pairs M4 and M6 of Figure 3 are "merged" into separate transistors M3 and M4, and the control terminals of transistors M3 and M4 (e.g., the gates in the case of field - effect transistors such as MOSFET transistors) are commonly:

[0064] coupled to the power supply node VDD via the capacitor C G , and

[0065] coupled to the output nodes OUT P and OUT N via the respective switches S1 and S2 driven by the reset unit RST, as discussed previously.

[0066] By reference to Figure 7A and Figure 7B the advantages provided by the illustrated arrangement can be explained Figure 6 .

[0067] Figure 7A Refers to the case where RST = 1, i.e., the case where switches S1 and S2 - which can be any known type of electronic switch, such as a MOSFET - are closed, i.e., conducting

[0068] Conversely Figure 7B refers to the case where RST = 0, i.e., the case where switches S1 and S2 are open, i.e., non - conducting

[0069] In both cases, it is assumed that there is a (differential) DC signal of magnitude IN = IN P - IN N at the input of the pre - amplifier

[0070] In the reset phase (RST = 1), the reset switches S1 and S2 are closed (conducting), and the two outputs OUT P and OUT N are short - circuited together (the current through the load capacitor C L is zero).

[0071] In this case, the common - mode output is defined by the voltage threshold that causes the transistors to conduct (i.e., have conductivity) (in the case of field - effect transistors such as MOSFET transistors, it is the gate - source), and by the overdrive of transistors M3 and M4 that provide the common - mode feedback of the circuit, as in the case of V. Srinivas et al., i.e.:

[0072] V CM = VDD - |V TH |-|V OV3 |

[0073] As a result of the reset being released (RST = 0), the reset switches S1 and S2 open (non - conduct), so that transistors M3 and M4 can perform their role as active loads

[0074] They provide a current that depends (only) on their gate voltage. This can be kept constant by their own "gate" capacitance C G charged at the output common - mode voltage

[0075] Optionally, an auxiliary capacitor (not visible in the figure for simplicity) can be connected in parallel with C G to increase the stability of the gate voltage: i.e., C GIt can be the gate parasitic capacitances of M3 and M4, which may be increased via supplementary external components to "boost" the V in M3 and M4 GS .

[0076] The differential gain in this case is the same as that calculated at the beginning of this specification and refers to the circuit proposed by V. Srinivas et al., but the notable difference is that: now the gate capacitances of the common-mode feedback no longer contribute to the load capacitance C L , which avoids the associated gain loss and improves the overall efficiency.

[0077] In addition, there is no biasing of the active load transistors as they can be refreshed during each reset phase when the associated gates are used as common-mode feedback.

[0078] Compared with the solution proposed by V. Srinivas et al., in the Figure 6 illustrated arrangement, the output swing is extended and no longer depends on the overdrive of the load transistors. In one or more embodiments, the output swing depends only on the threshold voltage, which can free one or more embodiments from any trade-off between the output swing and the active load noise.

[0079] In fact, the maximum output voltage that keeps M3 and M4 in the saturation region can be written as:

[0080] V MAX OUT = VDD - |V OV3 |

[0081] which results in the maximum output swing, and the maximum output swing can be expressed as:

[0082] ΔV MAX = V MAX OUT - V CM = |V TH |

[0083] This maximum output swing is independent of the MOS overdrive.

[0084] Figure 8 The circuit diagram of Figure 6 is an example of the possibility of implementing the same basic principle (resulting in operations as shown in Figure 6 and Figure 6 ) as the circuit diagram of Figure 7A and Figure 7B by using PMOS input transistors M1 and M2 (instead of the NMOS input transistors M1 and M2 as illustrated in

[0085] Those skilled in the art will readily understand that although different transistor types (PMOS versus NMOS) and inverted representations are used for simplicity, Figure 8 the circuit topology with respect to Figure 6 remains unchanged in other aspects, such as Figure 8 the illustrated circuit is equally suitable for use as a preamplifier 12 in a comparator device 10 as Figure 1 illustrated.

[0086] A circuit (e.g., 12) as illustrated herein may include: a first pair of transistors (e.g., M1, M3) having a current flow path therethrough (e.g., source-drain in a field effect transistor such as a MOSFET transistor) coupled at a first output node (e.g., OUT N ) and providing a first current flow line intermediate a power supply node (e.g., VDD) and ground (e.g., GND); a second pair of transistors (e.g., M2, M4) having a current flow path therethrough (e.g., source-drain in a field effect transistor such as a MOSFET transistor) coupled at a second output node (e.g., OUT P ) and providing a second current flow line intermediate the power supply node and ground. The first pair of transistors and the second pair of transistors include: a first input transistor (e.g., M1) in the first pair of transistors located intermediate the first output node and one of the power supply node and ground (e.g., Figure 6 GND in Figure 8 , and correspondingly, P VDD in Figure 6 ), the first input transistor including a control terminal (e.g., gate in a field effect transistor such as a MOSFET transistor) providing a first input node (e.g., IN Figure 8 ); a second input transistor (e.g., M2) in the second pair of transistors located intermediate the second output node and the one of the power supply node and ground (e.g., N ), the second input transistor including a control terminal providing a second input node (e.g., IN Figure 6 ), and correspondingly, Figure 8 GND in Figure 6VDD therein, and correspondingly, Figure 8 in the middle of GND) in Figure 8 ; a reset switch device (e.g., semiconductor switches S1, S2), which is arranged and configured to short-circuit the first output node and the second output node as a result of being activated (i.e., turned on, e.g., via RST).

[0087] The first load transistor and the second load transistor are capacitively coupled (e.g., via capacitor C G , which capacitor C G may include the gate parasitic capacitances of M3 and M4, which may be increased by additional external components) to the control terminal of the other of the power supply node and the ground, and the reset switch device is configured to short-circuit the control terminals of the first load transistor and the second load transistor (also) to the first output node and the second output node (short-circuited to each other) as a result of being activated (i.e., turned on, e.g., via RST).

[0088] The circuit as illustrated herein may include a current supply source (e.g., current generator I T ) for both the first current flow line through the first pair of transistors (e.g., M1, M3) and the second current flow line through the second pair of transistors (e.g., M2, M4), and the current supply source is located in the middle of one of the power supply node and the ground on one side and the first current flow line through the first pair of transistors and the second current flow line through the second pair of transistors on the other side.

[0089] In the circuit as illustrated herein, the first input transistor and the second input transistor may have a first common polarity (e.g., two NMOSs as Figure 6 illustrated or two PMOSs as Figure 8 illustrated), and the first load transistor and the second load transistor may have a second common polarity opposite to the first polarity (e.g., two PMOSs as Figure 6 illustrated or two NMOSs as Figure 8 illustrated).

[0090] In the circuit as illustrated herein, the first pair of transistors and the second pair of transistors may include field effect transistors, optionally including MOSFET transistors.

[0091] Therefore, the current flow path through it includes a source-drain current flow path, and the control terminal includes a gate terminal. In contrast, in a bipolar transistor, the current flow path through it includes an emitter-collector current flow path, and the control terminal includes a base terminal.

[0092] The comparator device (eg, 10) as illustrated herein may include a latch circuit (eg, 14) coupled to the first output node (eg, OUT) of the (preamplifier) ​​circuit (eg, 12) as illustrated herein. N ) and the second output node (e.g., OUT P ), wherein the first input node (IN P ) and the second input node (IN N ) is configured to receive a first input signal and a second input signal to compare between them, and the latch circuit has a corresponding output node (eg, OUT′ N ,OUT′ P ), and is configured to provide a differential latch signal (e.g., OUT′=OUT′) between the corresponding output nodes P –OUT′ N ), the value of the differential latch signal is the result of the comparison between the first input signal and the second input signal (eg, IN P >IN N or IN P <IN N ) function.

[0093] A method of operating a circuit as illustrated herein (eg, 12) or a comparator device as illustrated herein (eg, 10, ie, 12 plus 14) may include: applying a first input node (IN P ) and the second input node (IN N ) applies a first input signal and a second input signal to compare therebetween, collects (e.g., via a latch circuit such as 14) an output signal (e.g., OUT P ,OUT N ).

[0094] Methods as illustrated herein may include activating (eg, via RST) the switching device (eg, S1 , S2 ) at a subsequent activation event to short the first output node and the second output node, wherein the output signal returns to zero as a result of the activation of the switching device.

[0095] In the method exemplified herein, the subsequent activation event of the switching device can be determined by an output signal integration interval (eg, T INT ) are separated, and wherein the method comprises collecting the output signal between the first and second output nodes at a (final) end of the integration interval.

[0096] Details and embodiments may vary with respect to what is disclosed herein, and by way of example only, without departing from the scope of protection.

[0097] The various embodiments described above may be combined to provide further embodiments. These and other changes may be made to the embodiments in light of the above detailed description. In general, in the claims, the terms used should not be construed as limiting the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments and the full scope of equivalents to which these claims are entitled. Accordingly, the claims are not limited by the present disclosure.

Claims

1. A circuit, comprising: A first input transistor having conductive terminals respectively coupled to one of a power supply node and a ground, and a first output node, the first input transistor having a control terminal coupled to a first input node; A second input transistor having conductive terminals respectively coupled to the one of the power supply node and the ground, and a second output node, the second input transistor having a control terminal coupled to a second input node; A capacitor having a first side coupled to the other of the power supply node and the ground, and having a second side; A first load transistor having conductive terminals respectively coupled to the first output node, and the other of the power supply node and the ground, the first load transistor having a control terminal coupled to the second side of the capacitor; A second load transistor having conductive terminals respectively coupled to the second output node, and the other of the power supply node and the ground, the second load transistor having a control terminal coupled to the second side of the capacitor; And A reset switch circuit configured to short-circuit the first output node, the second output node, the control terminal of the first load transistor, and the control terminal of the second load transistor in response to being activated.

2. The circuit according to claim 1, comprising: A current supply source having an anode and a cathode, wherein one of the anode and the cathode is coupled to one of the power supply node and the ground, and wherein the other of the anode and the cathode is configured to sink or source both a first current and a second current, the first current flowing through the first input transistor and the first load transistor, and the second current flowing through the second input transistor and the second load transistor.

3. The circuit according to claim 1, wherein the first input transistor and the second input transistor have a common first polarity, and the first load transistor and the second load transistor have a common second polarity opposite to the first polarity.

4. The circuit according to claim 1, wherein the first input transistor, the second input transistor, the first load transistor, and the second load transistor are field effect transistors (FETs).

5. The circuit according to claim 4, wherein the first input transistor, the second input transistor, the first load transistor, and the second load transistor are metal oxide semiconductor FETs (MOSFETs).

6. The circuit according to claim 1, wherein the reset switch circuit is configured to set the first output node to a zero voltage in response to being activated.

7. A comparator, comprising: A first input transistor having conductive terminals respectively coupled to one of a power supply node and a ground, and a first output node, the first input transistor having a control terminal coupled to a first input node; A second input transistor having conductive terminals coupled to one of the power supply node and the ground and a second output node, the second input transistor having a control terminal coupled to a second input node; A capacitor having a first side coupled to the other of the power supply node and the ground and having a second side; A first load transistor having conductive terminals coupled to the first output node and the other of the power supply node and the ground, the first load transistor having a control terminal coupled to the second side of the capacitor; A second load transistor having conductive terminals coupled to the second output node and the other of the power supply node and the ground, the second load transistor having a control terminal coupled to the second side of the capacitor; A reset switch circuit configured to short circuit the first output node, the second output node, the control terminal of the first load transistor, and the control terminal of the second load transistor in response to being activated; And A latch circuit having an input node and an output node, the input node being coupled to the first output node and the second output node respectively, wherein in response to receiving a first input signal at the first input node and a second input signal at the second input node, the latch circuit is configured to provide a differential latch signal between the corresponding output nodes, the differential latch signal being based on a comparison result between the first input signal and the second input signal.

8. The comparator according to claim 7, comprising: A current supply having an anode and a cathode, wherein one of the anode and the cathode is coupled to one of the power supply node and the ground, and wherein the other of the anode and the cathode is configured to sink or source both a first current and a second current, the first current flowing through the first input transistor and the first load transistor, and the second current flowing through the second input transistor and the second load transistor.

9. The comparator according to claim 7, wherein the first input transistor and the second input transistor have a common first polarity, and the first load transistor and the second load transistor have a common second polarity opposite to the first polarity.

10. The comparator according to claim 7, wherein the first input transistor, the second input transistor, the first load transistor, and the second load transistor are field effect transistors (FETs).

11. The comparator according to claim 10, wherein the first input transistor, the second input transistor, the first load transistor, and the second load transistor are metal oxide semiconductor FETs (MOSFETs).

12. The comparator according to claim 7, wherein the reset switch circuit is configured to set the first output node to a zero voltage in response to being activated.

13. A method, comprising: A first input signal is provided to a first input node, and a second input signal is provided to a second input node, where: the first input node is coupled to a control terminal of a first input transistor, and the first input transistor has conductive terminals coupled to one of a power supply node and a ground, respectively, and a first output node, and the second input node is coupled to a control terminal of a second input transistor, and the second input transistor has conductive terminals coupled to the one of the power supply node and the ground, respectively, and a second output node, an output signal is output through the first output node and the second output node, where: the first output node is coupled to a first conductive terminal of a first load transistor, the first load transistor having a second conductive terminal coupled to the other of the power supply node and the ground, and a control terminal coupled to a first side of a capacitor, and the capacitor having a second side coupled to the other of the power supply node and the ground, and the second output node is coupled to a first conductive terminal of a second load transistor, the second load transistor having a second conductive terminal coupled to the other of the power supply node and the ground, and a control terminal coupled to the first side of the capacitor, and a reset switch circuit is activated to short-circuit the first output node, the second output node, the control terminal of the first load transistor, and the control terminal of the second load transistor.

14. The method according to claim 13, comprising: setting the output signal to a zero voltage in response to activation of the reset switch circuit in a subsequent activation event.

15. The method according to claim 14, comprising: separating subsequent activation events of the reset switch circuit by respective output signal integration intervals; and collecting the output signal through the first output node and the second output node at respective ends of the respective output signal integration intervals.

16. The method according to claim 13, wherein one of an anode and a cathode of a current supply source is coupled to one of the power supply node and the ground, and the other of the anode and the cathode of the current supply source sinks or sources both a first current and a second current, the first current flowing through the first input transistor and the first load transistor, and the second current flowing through the second input transistor and the second load transistor.

17. The method according to claim 13, wherein the first input transistor and the second input transistor have a common first polarity, and the first load transistor and the second load transistor have a common second polarity opposite to the first polarity.

18. The method according to claim 13, wherein the first input transistor, the second input transistor, the first load transistor, and the second load transistor are field effect transistors (FETs).

19. The method according to claim 18, wherein the first input transistor, the second input transistor, the first load transistor, and the second load transistor are metal oxide semiconductor FETs (MOSFETs).

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