Display panel and display device

Abstract

The display panel and the display device provided by the embodiments of the present disclosure have the following beneficial effects: the display panel includes a display substrate having a display area and a first bonding area located at at least one side of the display area, the first bonding area is provided with a first test pin and a second test pin, the first test pin is connected with the second test pin, and the first test pin and the second test pin are grounded; a first flexible circuit board is bonded in the first bonding area, the first flexible circuit board has a second bonding area, the second bonding area is provided with a third test pin and a fourth test pin, and a first test pad and a second test pad, the third test pin is connected with the first test pin and the first test pad, and the fourth test pin is connected with the second test pin and the second test pad.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] With the development and widespread adoption of electronic devices, such as wearable devices, the anti-static performance of these devices is becoming increasingly important. Furthermore, the trend towards narrower bezels and higher screen-to-body ratios in electronic devices significantly limits the trace space on the display substrate, resulting in poorer anti-static performance.

[0003] Therefore, improving the anti-static capability of electronic devices is an urgent problem to be solved. Summary of the Invention

[0004] The purpose of this disclosure is to provide a display panel and display device to improve the anti-static performance of electronic devices. The specific technical solution is as follows:

[0005] A first aspect of this disclosure provides a display panel, the display panel comprising:

[0006] The display substrate has a display area and a first bonding area located on at least one side of the display area. The first bonding area is provided with a first test pin and a second test pin. The first test pin is electrically connected to the second test pin, and the first test pin and the second test pin are grounded.

[0007] A first flexible circuit board is bonded to a first bonding area. The first flexible circuit board has a second bonding area. The second bonding area is provided with a third test pin and a fourth test pin, as well as a first test pad and a second test pad. The third test pin is connected to the first test pin and the first test pad, and the fourth test pin is connected to the second test pin and the second test pad.

[0008] In some embodiments, both the first test pad and the second test pad are grounded.

[0009] In some embodiments, the first test pin is connected to the second test pin via a connection portion, the connection portion comprising a first metal layer and a first transparent conductive layer stacked together.

[0010] In some embodiments, the display panel further includes:

[0011] A protective line is provided in the first bonding area, and the first test pin and the second test pin are grounded through the protective line;

[0012] The test line is located in the second bonding area, the third test pin is connected to the first test pad through the test line, and the fourth test pin is connected to the second test pad through the test line.

[0013] In some embodiments, the protective line includes a second metal layer and a second transparent conductive layer stacked together, wherein the width of the second transparent conductive layer is the same as the distance between the two opposite sides of the first test pin and the second test pin.

[0014] In some embodiments, the display panel further includes:

[0015] A first alignment identifier is set in the first binding area;

[0016] A second alignment identifier is disposed in the second binding area, and the position of the second alignment identifier matches that of the first alignment identifier.

[0017] In some embodiments, the first alignment identifier is grounded, and / or the second alignment identifier is grounded.

[0018] In some embodiments, the display panel further includes:

[0019] A copper sheet is disposed in an area of ​​the first bonding region where there are no traces, and both the first test pin and the second test pin are connected to the copper sheet.

[0020] In some embodiments, the test pin includes a substrate and a first metal layer, a first insulating layer, a first transparent conductive layer, a second transparent conductive layer, and a second insulating layer, which are sequentially distributed on one side of the substrate away from it. The second transparent conductive layer is connected to the first transparent conductive layer through a first via. The test pin includes at least one of the first test pin, the second test pin, the third test pin, and the fourth test pin.

[0021] In some embodiments, the display area of ​​the display panel includes a substrate and a pixel circuit located on one side of the substrate. The pixel circuit includes an active layer, a first gate insulating layer, a first metal layer of the display area, a second gate insulating layer, a second metal layer of the display area, an interlayer dielectric layer, and a third metal layer of the display area, which are sequentially distributed along a direction away from the substrate. The first metal layer of the pins is fabricated in the same layer as the first metal layer of the display area, and the first transparent conductive layer of the pins is fabricated in the same layer as the third metal layer of the display area.

[0022] In some embodiments, the display area of ​​the display panel includes at least one organic light-emitting device, the at least one organic light-emitting device including an anode layer, a pixel defining layer, an organic light-emitting layer and a cathode layer sequentially distributed along a direction away from the pixel circuit, wherein the pin second transparent electrode layer is fabricated in the same layer as the anode layer.

[0023] A second aspect of this disclosure provides a touch panel, the touch panel comprising:

[0024] A touch substrate having a touch display area and a third bonding area located on at least one side of the display area, the third bonding area being provided with a fifth test pin and a sixth test pin, the fifth test pin being electrically connected to the sixth test pin, and the fifth test pin being grounded to the sixth test pin;

[0025] A second flexible circuit board is bonded to the third bonding area. The second flexible circuit board has a third bonding area, which is provided with a seventh test pin and an eighth test pin, as well as a third test pad and a fourth test pad. The seventh test pin is connected to the fourth test pin and the third test pad, and the eighth test pin is connected to the fifth test pin and the fourth test pad.

[0026] In some embodiments, the fourth test pad is grounded along with the fifth test pad.

[0027] In some embodiments, the test pin includes a substrate and a first metal layer, a first insulating layer, a first transparent conductive layer, a second transparent conductive layer, and a second insulating layer, which are sequentially distributed on one side of the substrate away from it. The second transparent conductive layer is connected to the first transparent conductive layer through a first via. The test pin includes at least one of the fourth test pin, the fifth test pin, the sixth test pin, and the seventh test pin.

[0028] In some embodiments, the touch display area of ​​the touch substrate includes a buffer layer and a bridging layer, an insulating layer, a touch pattern layer, and a protective layer that are sequentially distributed on one side of the buffer layer and in a direction away from the buffer layer, wherein the first transparent conductive layer of the pin is fabricated in the same layer as the bridging layer, and the second transparent conductive layer is fabricated in the same layer as the touch pattern layer.

[0029] A third aspect of this disclosure provides a display device, the display device including any of the aforementioned display panels, or the display device including any of the aforementioned touch panels.

[0030] Beneficial effects of the embodiments disclosed herein:

[0031] This disclosure provides a display panel and a display device. The display panel includes a display substrate with a display area and a first bonding area located on at least one side of the display area. The first bonding area is provided with a first test pin and a second test pin connected to each other for bonding impedance testing. The display panel also includes a first flexible circuit board bonded to the first bonding area. The first flexible circuit board has a second bonding area, and the second bonding area is provided with a third test pin and a fourth test pin for bonding impedance testing. The second bonding area is also provided with a first test pad and a second test pad for connection to an external test power supply. The first test pad is connected to the first test pin through the third test pin, and the second test pad is connected to the second test pin through the fourth test pin. In the display panel provided by this disclosure, the first test pin and the second test pin on the display substrate for bonding impedance testing are both grounded, forming a good ESD discharge channel between the first test pin and the second test pin. This facilitates ESD discharge through the discharge channel, thereby improving the anti-static performance of the display panel and, consequently, the anti-static performance of the display device.

[0032] Of course, implementing any product or method of this disclosure does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other embodiments can be obtained based on these accompanying drawings.

[0034] Figure 1 This is a schematic diagram of the structure of a display panel according to some embodiments of the present disclosure;

[0035] Figure 2 This is a schematic diagram of the structure of a first bonding area of ​​a display substrate and a second bonding area of ​​a flexible circuit board according to some embodiments of the present disclosure.

[0036] Figure 3 For along Figure 1 Cross-sectional view along the AA direction;

[0037] Figure 4 For along Figure 1 Cross-sectional view along the CC direction;

[0038] Figure 5 This is a schematic diagram of the structure of another display panel according to some embodiments of the present disclosure;

[0039] Figure 6 For along Figure 1Cross-sectional view along the BB direction;

[0040] Figure 7 This is a schematic diagram illustrating another structure of the first bonding area of ​​the display substrate and the second bonding area of ​​the flexible circuit board according to some embodiments of this disclosure.

[0041] Reference numerals in the figures: 1-Display substrate; 10-Display area; 11-First bonding area; 12-First test pin; 121-First metal layer of pin; 122-First transparent conductive layer of pin; 123-First insulating layer of pin; 124-Second transparent conductive layer of pin; 125-Second insulating layer of pin; 13-Second test pin; 14-Guard line; 141-First guard line; 142-Second guard line; 15-First alignment mark; 2-First flexible circuit board ; 21-Second Bonding Area; 22-Third Test Pin; 23-Fourth Test Pin; 24-First Test Pad; 25-Second Test Pad; 26-Test Line; 27-Second Alignment Mark; 3-Connection; 31-First Metal Layer; 32-First Transparent Conductive Layer; 4-First Grounding Structure; 5-Second Grounding Structure; 51-Copper Sheet; 100-Substrate; 101-First Substrate Layer; 102-First Waterproof Oxygen Layer; 103-Amorphous Silicon Layer; 104 - Second substrate layer; 105 - Second waterproof oxygen layer; 201 - Buffer layer; 202 - Active layer; 203 - First gate insulating layer; 204 - First metal layer of display area; 204a - Gate; 206a - Second electrode plate; 204b - First electrode plate; 205 - Second gate insulating layer; 206 - Second metal layer of display area; 207 - Interlayer dielectric layer; 208 - Third metal layer of display area; 208a - Source; 208b - Drain; 209 - Passivation layer ; 300 - Organic light-emitting device; 301 - Anode layer; 302 - Pixel defining layer; 303 - Organic light-emitting layer; 304 - Cathode layer; 305 - Spacer layer; 400 - Planarization layer; 500 - Encapsulation layer; 501 - First inorganic encapsulation layer; 502 - Organic encapsulation layer; 503 - Second inorganic encapsulation layer; 600 - Touch substrate; 601 - Buffer layer; 602 - Bridging layer; 603 - Insulating layer; 604 - Touch pattern layer; 605 - Protective layer. Detailed Implementation

[0042] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art based on this disclosure are within the scope of protection of this disclosure.

[0043] In related technologies, the anti-static performance of touch display modules can be improved by adding TVS (Transient Voltage Suppressor) on flexible circuit boards and increasing the grounding area of ​​the copper leakage region. However, the aforementioned methods cannot directly protect the ITO (Indium Tin Oxides) bridge points of the touch panel, making it easy to damage the ITO bridge points of the touch panel during ESD (Electro-Static Discharge) testing, thereby causing the touch panel to malfunction.

[0044] To address the aforementioned problems, this disclosure provides a display panel and a display device. The display panel and display device provided in this disclosure will be described in detail below with reference to the accompanying drawings. The display panel includes, but is not limited to, LCD (Liquid Crystal Display) display panels, OLED (Organic Light-Emitting Diode) display panels, QLED (Quantum Dot Light-Emitting Diodes) display panels, mini LED (mini Light-Emitting Diode) display panels, and micro LED (micro Light-Emitting Diode) display panels, etc.

[0045] like Figure 1 and Figure 2 As shown, the display panel provided in this embodiment includes:

[0046] Display substrate 1 has a display area 10 and a first bonding area 11 located on at least one side of the display area 10. The first bonding area 11 is provided with a first test pin 12 and a second test pin 13 for bonding impedance testing. The first test pin 12 is connected to the second test pin 13, and the first test pin 12 and the second test pin 13 are grounded.

[0047] A first flexible circuit board 2 is bonded to a first bonding area 11. The first flexible circuit board 2 has a second bonding area 21. The second bonding area 21 is provided with a third test pin 22 and a fourth test pin 23 for bonding impedance testing, and a first test pad 24 and a second test pad 25 for connecting to an external test power supply. The third test pin 22 is connected to the first test pin 12 and the first test pad 24, and the fourth test pin 23 is connected to the second test pin 13 and the second test pad 25.

[0048] The first test pin 12 and the second test pin 13 are used for bonding impedance testing. When the first flexible circuit board 2 is bonded to the first bonding area 11, the third test pin 22 on the first flexible circuit board 2 is connected to the first test pin 12, thereby connecting the first test pin 12 to the first test pad 24 through the third test pin 22. Furthermore, the fourth test pin 23 on the first flexible circuit board 2 is connected to the second test pin 13, thereby connecting the second test pin 13 to the second test pad 25 through the fourth test pin 23. Since the first test pad 24 and the second test pad 25 can be connected to an external test power supply, such as a bonding impedance testing device, bonding impedance testing between the display substrate 1 and the first flexible circuit board 2 can be achieved through the first test pad 24 and the second test pad 25. Both the first test pad 24 and the second test pad 25 can be circular windowed pads, and they can also have other structures; this embodiment does not specifically limit these.

[0049] The number of each test pin can be set according to actual needs, for example, Figure 2 As shown, the first bonding area 11 is provided with two first test pins 12 and two second test pins 13, and the corresponding second bonding area 21 is provided with two third test pins 22 and two fourth test pins 23, as follows. Figure 2 As shown. The first bonding area 11 and the second bonding area 21 also have transmitter pins, receiver pins, and ground pins. It should be noted that, taking a first test pin 12 and a second test pin 13 as a pair of test pins as an example, when the first bonding area 11 has two pairs of test pins, along the long side of the first bonding area 11, i.e. Figure 2 In the direction S, the transmitting pin, receiving pin, and ground pin can be located between two pairs of test pins so that the two pairs of test pins can protect the transmitting pin, receiving pin, and ground pin. The third test pin 22 and the fourth test pin 23 in the second bonding area 21 are set to correspond to the first test pin 12 and the second test pin 13, so the position of each pin in the second bonding area 21 will not be described again.

[0050] In some embodiments, the first test pin 12, the second test pin 13, the third test pin 22, and the fourth test pin 23 may have the same structure. For ease of description, at least one of the first test pin 12, the second test pin 13, the third test pin 22, and the fourth test pin 23 will be referred to as a test pin. Figure 3As shown, the test pin includes a substrate 100 and pin first metal layer 121, pin first transparent conductive layer 122, pin first insulating layer 123, pin second transparent conductive layer 124 and pin second insulating layer 125, which are located on one side of the substrate 100 and distributed sequentially in the direction away from the substrate 100.

[0051] Among them, such as Figure 3 As shown, the second transparent conductive layer 124 of the pin and the first transparent conductive layer 122 of the pin are connected through the first via. The first transparent conductive layer 122 and the second transparent conductive layer 124 of the pin can be ITO (Indium Tin Oxides) layers or IZO (Indium Zinc Oxides) layers, etc.

[0052] In some embodiments, the first test pin 12 is connected to the second test pin 13 via a connection portion 3. The connection portion 3 includes a first metal layer 31 and a first transparent conductive layer 32 stacked together, such as... Figure 4 As shown.

[0053] In this embodiment of the present disclosure, the first metal layer 31 in the connection portion 3 can be fabricated in the same layer as the first metal layer 121 of the first test pin 12 and the second test pin 13, and the first transparent conductive layer 32 in the connection portion 3 can be fabricated in the same layer as the first transparent conductive layer 122 of the first test pin 12 and the second test pin 13. The first test pin 12 and the second test pin 13 can also be connected in other ways, such as by wire connection, etc., and this embodiment of the present disclosure does not specifically limit this. The first transparent conductive layer 32 can be an ITO (Indium Tin Oxides) layer or an IZO (Indium ZinOxides) layer, etc.

[0054] In some embodiments, such as Figure 5As shown, the display area 10 of the display panel includes a substrate 100 and a pixel circuit located on one side of the substrate 100. The pixel circuit includes a thin-film transistor device and a capacitor. The pixel circuit includes a buffer layer 201, an active layer 202 of the thin-film transistor device, a first gate insulating layer 203, a first metal layer 204 of the display area, a second gate insulating layer 205, a second metal layer 206 of the display area, an interlayer dielectric layer 207, a third metal layer 208 of the display area, and a passivation layer 209, which are sequentially distributed along the direction away from the substrate 100. The first metal layer 204 of the display area includes at least the gate 204a of the thin-film transistor device and the first electrode plate 204b of the capacitor. The second metal layer 206 of the display area includes at least the second electrode plate 206a of the capacitor. The third metal layer 208 of the display area includes at least the source 208a and the drain 208b of the thin-film transistor device. The source 208a and the drain 208b are connected to the active layer 202 through a second via. In some embodiments, the first metal layer 121 of the pins is fabricated in the same layer as the first metal layer 204 of the display area, and the first transparent conductive layer 122 of the pins is fabricated in the same layer as the third metal layer 208 of the display area.

[0055] In this embodiment, the buffer layer 201 is used to protect the thin-film transistor device in the pixel circuit, ensuring that the thin-film transistor device is separated from the substrate 100, preventing impurities on the substrate 100 from affecting the thin-film transistor device, and ensuring that the thin-film transistor device can work normally. The material of the buffer layer 201 can be silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0056] In some embodiments, such as Figure 5 As shown, the substrate 100 includes a first substrate layer 101, a first waterproof oxygen layer 102, an amorphous silicon layer 103, a second substrate layer 104, and a second waterproof oxygen layer 105, which are stacked sequentially.

[0057] The first substrate layer 101 and the second substrate layer 104 can be flexible substrate layers. The first substrate layer 101 and the second substrate layer 104 can be made of flexible organic materials, such as polyimide, polycarbonate, polyacrylate, polyetherimide, and other resin-based organic materials. The first waterproof oxygen layer 102 and the second waterproof oxygen layer 105 are used to prevent moisture and oxygen from entering the display area 10 of the display panel, causing the display area 10 to malfunction. The materials of the first waterproof oxygen layer 102 and the second waterproof oxygen layer 105 can be silicon nitride, silicon oxide, aluminum oxide, etc. The amorphous silicon layer 103 is an insulating layer that ensures the insulation of the substrate 100 and prevents the substrate 100 from affecting the electrical connection of the pixel circuit.

[0058] In some embodiments, the display area 10 of the display panel includes at least one organic light-emitting device 300, the organic light-emitting device 300 being located on the side of the pixel circuit away from the substrate 100, and a planarization layer 400 being present between the organic light-emitting device 300 and the pixel circuit.

[0059] In this embodiment of the disclosure, there may be one or more organic light-emitting devices 300, and the pixel circuit is used to power at least one organic light-emitting device 300.

[0060] In some embodiments, the organic light-emitting device 300 is located on the side of the planarization layer 400 away from the pixel circuit. The organic light-emitting device 300 includes an anode layer 301, a pixel defining layer 302, an organic light-emitting layer 303, and a cathode layer 304 that are sequentially distributed along a direction away from the planarization layer 400. The second transparent electrode layer 124 with pins is fabricated in the same layer as the anode layer 301.

[0061] In this embodiment, the planarization layer 400 makes the surface of the pixel circuit flatter, facilitating the placement of the organic light-emitting device 300. The material of the planarization layer 400 can be an insulating material such as resin to ensure its insulation. Furthermore, the pixel defining layer 302 is used to separate the various sub-pixel regions of the organic light-emitting device 300. Specifically, the pixel defining layer 302 can form multiple sub-pixel regions through its own groove structure. The organic light-emitting layer 303 may include at least a stacked hole transport layer, a light-emitting layer, and an electron transport layer.

[0062] In some embodiments, such as Figure 5 As shown, a spacer layer 305 is arranged between the pixel defining layer 302 and the organic light-emitting layer 303. The spacer layer 305 is used to support the mask during the deposition of the organic light-emitting layer 303.

[0063] In some embodiments, such as Figure 5 As shown, the display area 10 of the display panel also includes an encapsulation layer 500. The encapsulation layer 500 is located on the side of the organic light-emitting device 300 away from the substrate 100. It is used to encapsulate the organic light-emitting device 300 and the pixel circuit, protect the display panel, and ensure the encapsulation performance of the display panel.

[0064] In some embodiments, such as Figure 5 As shown, the encapsulation layer 500 includes a first inorganic encapsulation layer 501, an organic encapsulation layer 502, and a second inorganic encapsulation layer 503 sequentially stacked on the cathode layer 304. That is, multiple encapsulation layers are arranged on the display panel to ensure the encapsulation effect.

[0065] In this embodiment of the disclosure, such as Figure 2As shown, the first test pin 12 and the second test pin 13 are grounded, meaning they are connected to the first grounding structure 4. Furthermore, the first test pad 24 and the second test pad 25 are grounded, meaning they are both connected to the second grounding structure 5. The first grounding structure 4 and the second grounding structure 5 are electrically connected.

[0066] In some embodiments, the display panel further includes a copper sheet 51 disposed in an area of ​​the second bonding region 21 where there are no traces, and both the first test pad 24 and the second test pad 25 are connected to the copper sheet 51.

[0067] In this embodiment, the second grounding structure 5 can be a copper sheet 51 or may include a copper sheet 51. The connection between the first test pad 24 and the second test pad 25 and the copper sheet 51 means that the first test pad 24 and the second test pad 25 are connected to the second grounding structure 5, i.e., the first test pad 24 and the second test pad 25 are grounded. The copper sheet 51 is placed in an area of ​​the second bonding area 21 without traces, preventing the copper sheet 51 from affecting the traces within the second bonding area 21. Based on this, the first test pin 12 can be connected to the copper sheet 51 through the first test pad 24, and the second test pin 13 can be connected to the copper sheet 51 through the second test pad 25, thereby achieving grounding of the first test pin 12 and the second test pin 13. Furthermore, the first grounding structure 4 and the second grounding structure 5 can also be other structures, such as a ground wire. Based on this, the first test pin 12, the second test pin 13, the first test pad 24, and the second test pad 25 can also be directly grounded through a ground wire; this embodiment does not specifically limit this.

[0068] In the display panel provided in this embodiment, the first test pin 12 and the second test pin 13 on the display substrate 1 for bonding impedance testing are both grounded, and the first test pin 12 and the second test pin 13 are connected through the connecting part 3, forming a good ESD discharge channel between the first test pin 12 and the second test pin 13, which facilitates ESD discharge through the discharge channel. In addition, since the first test pad 24 and the second test pad 25 are both grounded, each test pin can be grounded more effectively, reducing the impedance to ground of each test pin, the first test pad 24 and the second test pad 25, and allowing ESD to be discharged better through the first test pad 24 and the second test pad 25, thereby improving the anti-static performance of the display panel and thus improving the anti-static performance of the display device.

[0069] In some embodiments, such as Figure 2As shown, the aforementioned display panel also includes a guard line 14 disposed in the first bonding area 11, and the first test pin 12 and the second test pin 13 are grounded through the guard line 14; a test line 26 disposed in the second bonding area 21, the third test pin 22 is connected to the first test pad 24 through the test line 26, and the fourth test pin 23 is connected to the second test pad 25 through the test line 26.

[0070] In this embodiment of the disclosure, such as Figure 2 As shown, one end of the guard line 14 is connected to the first test pin 12 and the second test pin 13, and the other end of the guard line 14 is electrically connected to the first grounding structure 4, so that the first test pin 12 and the second test pin 13 are grounded through the guard line 14. In addition, the second bonding area 21 can be provided with multiple test lines 26. The third test pin 22 can be connected to the first test pad 24 through at least one test line 26, and the fourth test pin 23 can be connected to the second test pad 25 through at least another test line 26.

[0071] The protection line 14 grounds the first test pin 12 and the second test pin 13 respectively, forming an ESD discharge channel between the protection line 14 and the first grounding structure 4. This allows static electricity on the display substrate 1 to be discharged through this channel, thereby improving the anti-static performance of the display substrate 1. The test line 26 connects the third test pin 22 to the first test pad 24, and also connects the fourth test pin 23 to the second test pad 25, thus performing impedance testing on the display substrate 1 through the first test pad 24 and the second test pad 25.

[0072] In some embodiments, both the first test pad 24 and the second test pad 25 are grounded. For example... Figure 2 As shown, the first test pad 24 and the second test pad 25 are also connected to the second grounding structure 5, so that each test pin can be grounded better. This allows ESD to be discharged not only through the ESD discharge channel formed by the first test pin 12, the second test pin 13 and the protection line 14, but also through the first test pad 24 and the second test pad 25, further improving the anti-static performance of the display substrate 1 and the display panel.

[0073] In some embodiments, the protection line 14 is arranged around the display area 11.

[0074] In this embodiment of the disclosure, taking a first test pin 12 and a second test pin 13 as a pair of test pins as an example, in some embodiments of the disclosure, when the first bonding area 11 can be provided with a pair of test pins, the first bonding area 11 is provided with a guard line 14 connected to the pair of test pins, and the trace of the guard line 14 is arranged around the periphery of the display area 10. In some embodiments of the disclosure, such as Figure 6 As shown, the first bonding area 11 can be provided with two pairs of test pins, and the first bonding area 11 is provided with two guard lines 14. Specifically, the guard lines 14 include a first guard line 141 and a second guard line 142, and the Captain America test pins are connected to one guard line respectively. In one example, such as Figure 6 As shown, Figure 6 The display substrate 1 is circular. The first bonding area 11 has two pairs of test pins, one on the left and one on the right. The test pins on the left are connected to the first protection line 141, and the test pins on the right are connected to the second protection line 142. The first protection line 141 is semi-circular and its trace runs along the left edge of the display area 10. The second protection line 142 is also semi-circular and its trace runs along the right edge of the display area 10. The first protection line 141 and the second protection line 142 overlap vertically on opposite sides of the first bonding area 11 but are not connected, so that the first protection line 141 and the second protection line 142 together wrap around the periphery of the display area 10.

[0075] In this embodiment of the present disclosure, the protection line 14 is arranged around the display area 10, such that the transmitter trace of the transmitter pin and the receiver trace of the receiver pin are both located between the protection line 14 and the edge of the display area 10 of the display substrate 1. That is, the trace of the protection line 14 surrounds the transmitter trace and the receiver trace, thereby protecting the transmitter trace and the receiver trace.

[0076] In some embodiments, the protective line 14 includes a second metal layer and a second transparent conductive layer stacked together, such as... Figure 2 As shown, the width w of the second transparent conductive layer is the same as the distance d between the two opposite sides of the first test pin 12 and the second test pin 13. The second metal layer of the guard line 14 is connected to or fabricated in the same layer as the first metal layer 121 of the pins of the first test pin 12 and the second test pin 13. The second transparent conductive layer of the guard line 14 is connected to or fabricated in the same layer as the first transparent conductive layer 122 of the pins of the first test pin 12 and the second test pin 13.

[0077] In this embodiment of the disclosure, the protective line 14 includes a second metal layer and a second transparent conductive layer, such as... Figure 2As shown, the width w of the second transparent conductive layer is equal to the sum of the width w1 of the first test pin 12, the width w2 of the second test pin 13, and the gap width w3 between the first test pin 12 and the second test pin 13. Based on this, the trace width of the guard line 14 is wider, thereby increasing the width of the ESD discharge channel and enabling better ESD discharge on the display substrate 1. Furthermore, since the guard line 14 includes a second metal layer and a second transparent conductive layer, the first test pin 12 and the second test pin 13 are grounded through the guard line 14. That is, the first metal layer 121 and the first transparent conductive layer 122 of the first test pin 12 and the second test pin 13 are both grounded, allowing for better grounding of the first test pin 12 and the second test pin 13.

[0078] In some embodiments, the aforementioned display panel further includes a first alignment mark 15, which is disposed in the first bonding area 11;

[0079] The second alignment mark 27 is disposed in the second bonding area 21, and the position of the second alignment mark 27 matches that of the first alignment mark 15.

[0080] In this embodiment, the first alignment mark 15 and the second alignment mark 27 are opposite each other and are used to position the first flexible circuit board 2 when it is bonded to the first bonding area 11, thereby facilitating the connection between the third test pin 22 and the fourth test pin 23 on the first flexible circuit board 2 and the first test pin 12 and the second test pin 13 on the first bonding area 11. Both the first alignment mark 15 and the second alignment mark 27 can be metal sheets. To facilitate the alignment of the first alignment mark 15 and the second alignment mark 27, the first alignment mark 15 and the second alignment mark 27 can be disposed on the outside of the first test pin 12 and the third test pin 22, that is, on the side of the first test pin 12 and the third test pin 22 away from other pins.

[0081] The number of the first alignment marker 15 and the second alignment marker 27 can be set according to actual needs, for example, such as Figure 2 As shown, the number of first alignment identifiers 15 and second alignment identifiers 27 can be two. When the number of first alignment identifiers 15 and second alignment identifiers 27 is two, each pin of the first bonding area 11 is located between two first alignment identifiers 15, and each pin of the second bonding area 21 is located between two second alignment identifiers 27.

[0082] In some embodiments, the first alignment identifier 15 is grounded, and the second alignment identifier 27 is grounded.

[0083] In some embodiments, the first alignment identifier 15 is grounded, or the second alignment identifier 27 is grounded.

[0084] In this embodiment of the disclosure, such as Figure 7 As shown, both the first alignment mark 15 and the second alignment mark 27 can be grounded to further enhance the protection of the ESD discharge channel between the first test pin 12 and the second test pin 13, the receiving channel corresponding to the receiving pin, and the transmitting channel corresponding to the transmitting pin, thereby further improving the anti-static performance of the display panel.

[0085] The inventive concepts described in the embodiments of this disclosure are also applicable to touch panels.

[0086] Specifically, this disclosure provides a touch panel, which includes:

[0087] A touch substrate has a touch display area and a third bonding area located on at least one side of the display area. The third bonding area is provided with a fifth test pin and a sixth test pin. The fifth test pin and the sixth test pin are electrically connected and grounded.

[0088] The second flexible circuit board is bonded to the third bonding area. The third bonding area is provided with a seventh test pin and an eighth test pin, as well as a third test pad and a fourth test pad. The seventh test pin is connected to the fourth test pin and the third test pad, and the eighth test pin is connected to the fifth test pin and the fourth test pad.

[0089] In this embodiment, the structures of the fifth and sixth test pins on the touch substrate and the seventh and eighth test pins on the second flexible circuit board can refer to any one of the aforementioned first test pin 12, second test pin 13, third test pin 22 and fourth test pin 23, and will not be repeated here.

[0090] In some embodiments, such as Figure 5 As shown, the touch display area of ​​the touch substrate 600 includes a buffer layer 601 and a bridging layer 602, an insulating layer 603, a touch pattern layer 604, and a protective layer 605, which are sequentially distributed on one side of the buffer layer 601 and in a direction away from the buffer layer 601. In one possible embodiment, the first transparent conductive layer 122 of the pins is fabricated in the same layer as the bridging layer 602, and the second transparent conductive layer 124 of the pins is fabricated in the same layer as the touch pattern layer 604.

[0091] In the touch panel provided in this embodiment, the fifth test pin and the sixth test pin used for bonding impedance testing on the touch panel are both grounded, forming a good ESD discharge channel between the fifth test pin and the sixth test pin, which facilitates ESD discharge through the discharge channel, thereby improving the anti-static performance of the touch panel and thus improving the anti-static performance of the display device.

[0092] It is understood that the essential difference between the touch panel in this embodiment and the display panel in the aforementioned embodiments lies in the difference in the structure of the touch panel itself. The structure and setting of each test pin, the structure and setting of each test pad, the structure of the protection line and its connection relationship with each test pin in this embodiment can all be the same as in the aforementioned embodiments.

[0093] This disclosure also provides a display device, which includes the aforementioned display panel or touch panel. Since display panels and touch panels have good anti-static properties, display devices including such panels also have good anti-static properties. These display devices include, but are not limited to, electronic bracelets, electronic watches, mobile phones, and tablet computers.

[0094] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0095] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure are included within the scope of protection of this disclosure.

Claims

1. A display panel, characterized by, The display substrate has a display area and a first bonding area located at least one side of the display area, the first bonding area is provided with a first test pin and a second test pin, the first test pin is electrically connected with the second test pin, the first test pin is connected with the second test pin through a connecting part, and the first test pin and the second test pin are grounded. The first flexible circuit board is bonded in the first bonding area, the first flexible circuit board has a second bonding area, the second bonding area is provided with a third test pin and a fourth test pin, and a first test pad and a second test pad, the third test pin is connected with the first test pin and the first test pad, the fourth test pin is connected with the second test pin and the second test pad; the first flexible circuit board is provided with a second grounding structure; the first test pad and the second test pad are connected with the second grounding structure, and the first test pad and the second test pad are grounded through the second grounding structure. The display panel further comprises a first grounding structure and a protection line provided in the first bonding area, the first test pin and the second test pin are grounded through the protection line; one end of the protection line is connected with the first test pin and the second test pin, and the other end of the protection line is electrically connected with the first grounding structure. The connecting part comprises a first metal layer and a first transparent conductive layer which are stacked.

2. The display panel of claim 1, wherein, Further comprising:

3. The display panel of claim 1, wherein, A test line is provided in the second bonding area, the third test pin is connected with the first test pad through the test line, and the fourth test pin is connected with the second test pad through the test line. The protection line comprises a second metal layer and a second transparent conductive layer which are stacked, and the width of the second transparent conductive layer is the same as the distance between the two sides of the first test pin and the second test pin away from each other.

4. The display panel of claim 3, wherein, The protection line is arranged around the display area.

5. The display panel of claim 3, wherein, Further comprising:

6. The display panel of claim 1, wherein, A first alignment mark is provided in the first bonding area; A second alignment mark is provided in the second bonding area, and the position of the second alignment mark matches the first alignment mark. The first alignment mark is grounded, and / or the second alignment mark is grounded.

7. The display panel of claim 6, wherein, Further comprising:

8. The display panel of claim 1, wherein, A copper sheet is provided in the area of the second bonding area without wiring, and the first test pad and the second test pad are connected with the copper sheet. The test pin comprises a substrate and a pin first metal layer, a pin first insulating layer, a pin first transparent conductive layer, a pin second transparent conductive layer and a pin second insulating layer which are sequentially distributed on one side of the substrate away from the substrate, wherein the pin second transparent conductive layer is connected with the pin first transparent conductive layer through a first via, and the test pin comprises at least one of the first test pin, the second test pin, the third test pin and the fourth test pin.

9. The display panel of claim 1, wherein, ​ 10. The display panel of claim 9, wherein, The display area of the display panel comprises a substrate and a pixel circuit on one side of the substrate, the pixel circuit comprises, in sequence away from the substrate, an active layer, a first gate insulating layer, a first display area metal layer, a second gate insulating layer, a second display area metal layer, an interlayer dielectric layer and a third display area metal layer, wherein the first metal layer of the pin is fabricated in the same layer as the first display area metal layer, and the first transparent conductive layer of the pin is fabricated in the same layer as the third display area metal layer.

11. The display panel of claim 10, wherein, The display area of the display panel comprises at least one organic light emitting device, the at least one organic light emitting device comprises, in sequence away from the pixel circuit, an anode layer, a pixel defining layer, an organic light emitting layer and a cathode layer, wherein the second transparent electrode layer of the pin is fabricated in the same layer as the anode layer.

12. A touch panel, characterized by comprising: The display panel comprises: A touch substrate having a touch display area and a third bonding area on at least one side of the touch display area, the third bonding area being provided with a fifth test pin and a sixth test pin, the fifth test pin being electrically connected to the sixth test pin, the fifth test pin being connected to the sixth test pin through a connecting portion, and the fifth test pin and the sixth test pin being grounded; A second flexible circuit board bonded to the third bonding area, the second flexible circuit board having a fourth bonding area thereon, the third bonding area being provided with a seventh test pin and an eighth test pin, a third test pad and a fourth test pad, the seventh test pin being connected to the fifth test pin and the third test pad, the eighth test pin being connected to the sixth test pin and the fourth test pad; the second flexible circuit board being provided with a second grounding structure; the third test pad and the fourth test pad being connected to the second grounding structure, and the third test pad and the fourth test pad being grounded through the second grounding structure; The touch panel further comprises a first grounding structure and a protection line provided in the third bonding area, the fifth test pin and the sixth test pin being grounded through the protection line; one end of the protection line being connected to the fifth test pin and the sixth test pin, and the other end of the protection line being electrically connected to the first grounding structure.

13. The touch panel according to claim 12, wherein The test pin comprises a substrate and, in sequence away from the substrate, a first metal layer of the pin, a first insulating layer of the pin, a first transparent conductive layer of the pin, a second transparent conductive layer of the pin and a second insulating layer of the pin, wherein the second transparent conductive layer of the pin is connected to the first transparent conductive layer of the pin through a first via, and the test pin comprises at least one of the fifth test pin, the sixth test pin, the seventh test pin and the eighth test pin.

14. The touch panel according to claim 13, wherein The touch display area of the touch substrate comprises a buffer layer and, located on one side of the buffer layer and sequentially distributed in a direction away from the buffer layer, a bridge layer, an insulating layer, a touch pattern layer and a protective layer, wherein the first transparent conductive layer of the pin is made in the same layer as the bridge layer, and the second transparent conductive layer is made in the same layer as the touch pattern layer.

15. A display device comprising: The display device comprises the display panel of any one of claims 1 to 11, or the display device comprises the touch panel of any one of claims 12 to 14.

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