Semiconductor modules and methods for manufacturing semiconductor modules

Abstract

This invention provides a semiconductor module and a method for manufacturing a semiconductor module. It reduces thermal resistance and inductance. The semiconductor module (1) includes: a laminated substrate (2) formed by a circuit pattern (22) disposed on the upper surface of an insulating plate (20) and a heat sink (21) disposed on the lower surface of the insulating plate; a semiconductor element (3) having a collector electrode (30) disposed on its upper surface and an emitter electrode (32) and a gate electrode (31) disposed on its lower surface, the emitter electrode and the gate electrode being bonded to the upper surface of the circuit pattern via bumps (B); and a block electrode (4) bonded to the collector electrode. The block electrode has: a flat plate portion (44) covering the top of the semiconductor element; and a pair of protrusions (45) protruding from both ends of the flat plate portion toward the circuit pattern and bonded to it.

Description

Technical Field

[0001] This invention relates to semiconductor modules and methods for manufacturing semiconductor modules. Background Technology

[0002] Semiconductor devices have substrates containing semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors), power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and FWDs (Free Wheeling Diodes), and are used in converter devices, etc.

[0003] For example, the semiconductor device (semiconductor module) shown in Patent Documents 1 and 2 below is constructed by arranging a substrate, an insulating circuit board, and a semiconductor element within a housing. The insulating circuit board has a first conductive plate (first metal layer) formed on its upper surface and a second conductive plate (second metal layer) formed on its lower surface. The semiconductor element is disposed on the upper surface of the first conductive plate, and the substrate is disposed on the lower surface of the second conductive plate. Furthermore, wires (connection wires) are used as electrical wiring components between the semiconductor element and the first conductive plate.

[0004] The internal space of the housing is filled with sealing material (sealing resin) to seal the various structures described above. Additionally, a cooler is disposed on the lower surface of the substrate via a bonding material such as solder.

[0005] Patent Document 1: Japanese Patent Application Publication No. 2017-28132

[0006] Patent Document 2: Utility Model Registration No. 3198019 Summary of the Invention

[0007] The problem the invention aims to solve

[0008] However, in conventional semiconductor module heat dissipation structures, to suppress the heat generated by the chip (semiconductor element), the heat from the chip is released to the air via a cooler. Furthermore, the chip primarily generates heat on the emitter electrode side, which serves as the surface side. Therefore, the heat generated by the chip is transferred to the back side (collector side) and dissipated outwards through the insulating circuit board, substrate, bonding material, and cooler.

[0009] Thus, since the chip generates heat on the emitter side, the heat generated on the emitter side needs to be transferred to the collector side, which serves as the cooler. Therefore, there is a problem where the overall thermal resistance of the semiconductor module is higher than the amount corresponding to the chip's thermal conductivity and thickness. Furthermore, in conventional semiconductor modules, the use of wires for wiring between the gate and emitter sides results in longer wiring lengths, which in turn increases inductance.

[0010] The present invention was made in view of this aspect, and one object is to provide a semiconductor module and a method for manufacturing a semiconductor module that can reduce thermal resistance and reduce inductance.

[0011] Solution for solving the problem

[0012] A semiconductor module according to one embodiment of the present invention is characterized in that the semiconductor module includes: a laminated substrate having a circuit pattern disposed on an upper surface of an insulating plate and a heat sink disposed on a lower surface of the insulating plate; a semiconductor element having a collector electrode disposed on an upper surface and an emitter electrode and a gate electrode disposed on a lower surface, the emitter electrode and the gate electrode being bonded to the upper surface of the circuit pattern via bumps; and a block electrode bonded to the collector electrode, the block electrode having: a flat plate portion covering the upper surface of the semiconductor element; and a pair of protrusions protruding from both ends of the flat plate portion toward the circuit pattern and bonding to the circuit pattern.

[0013] A method for manufacturing a semiconductor module according to an embodiment of the present invention is characterized by performing the following steps in the method: a preparation step in which a multilayer substrate and a block electrode are prepared, the multilayer substrate being formed by having a circuit pattern disposed on the upper surface of an insulating plate and a heat sink disposed on the lower surface of the insulating plate, the block electrode having a flat plate portion covering the upper part of a semiconductor element and a pair of protrusions extending from both ends of the flat plate portion toward the circuit pattern; a chip placement step in which the semiconductor element is placed on the lower surface of the flat plate portion such that the collector electrode faces the lower surface of the flat plate portion; and a block electrode placement step after the chip placement step, in which an emitter electrode disposed on the lower surface of the semiconductor element is joined to the circuit pattern of the insulating plate via bumps, and the pair of protrusions are joined to the circuit pattern.

[0014] The effects of the invention

[0015] According to the present invention, thermal resistance and inductance can be reduced. Attached Figure Description

[0016] Figure 1This is a perspective view of the semiconductor module involved in this embodiment.

[0017] Figure 2 This is a top view of the semiconductor module involved in this embodiment.

[0018] Figure 3 This is a top view showing the circuit pattern of the semiconductor module involved in this embodiment.

[0019] Figure 4 (A) and Figure 4 (B) is a cross-sectional view of the semiconductor module involved in this embodiment.

[0020] Figure 5 (A) and Figure 5 (B) is a schematic diagram showing the flow of refrigerant in the semiconductor module according to this embodiment.

[0021] Figure 6 (A) and Figure 6 (B) is a perspective view showing a step example of a semiconductor module manufacturing method according to this embodiment.

[0022] Figure 7 (A) and Figure 7 (B) is a perspective view showing a step example of a semiconductor module manufacturing method according to this embodiment.

[0023] Figure 8 This is a perspective view illustrating a step example of a semiconductor module manufacturing method according to this embodiment.

[0024] Figure 9 (A) and Figure 9 (B) is a perspective view showing a step example of a semiconductor module manufacturing method according to this embodiment.

[0025] Explanation of reference numerals in the attached figures

[0026] 1. Semiconductor module; 2. Laminated substrate; 3. Semiconductor element; 4. Block electrode; 5. Sealing resin; 10. Cooler; 10a. Heat sink; 10b. Groove; 20. Insulating plate; 21. Heat sink; 22. Circuit pattern; 23. Collector circuit pattern; 24. Gate circuit pattern; 24a. L section; 24b. H section; 25. Emitter circuit pattern; 25a. Emitter section; 25b. Strip section; 25c. Strip section; 25d. Sensing emitter section; 30. Collector; 31. Gate electrode; 32. Emitter electrode; 40. Collector block; 41. Gate electrode block; 42. Emitter electrode block; 43. Sensing emitter electrode block; 44. Flat plate section; 45. Protrusion; 46. Through hole; B. Bump; F. Cooling direction (direction of refrigerant flow); S. Bonding material. Detailed Implementation

[0027] The following describes a semiconductor module to which the present invention can be applied. Figure 1 This is a perspective view of the semiconductor module involved in this embodiment. Figure 2 This is a top view of the semiconductor module involved in this embodiment. Figure 3 This is a top view showing the circuit pattern of the semiconductor module involved in this embodiment. Figure 4 (A) and Figure 4 (B) is a cross-sectional view of the semiconductor module involved in this embodiment. Figure 4 (A) is along Figure 2 A cross-sectional view cut off by line A-A. Figure 4 (B) is along Figure 2 A cross-sectional view cut off by the B-B line. Figure 5 (A) and Figure 5 (B) is a schematic diagram showing the flow of refrigerant in the semiconductor module according to this embodiment. Figure 5 (A) is a top view of the semiconductor module. Figure 5 (B) is a cross-sectional view of the semiconductor module. Furthermore, the semiconductor module shown below is merely an example and is not limited to it; appropriate modifications are possible.

[0028] In the following figures, the short side of the semiconductor module is defined as the X-direction, the long side as the Y-direction, and the height as the Z-direction. Additionally, depending on the context, the X-direction may sometimes be referred to as the left-right direction, the Y-direction as the front-back direction, and the Z-direction as the up-down direction. These directions (front-back, left-right, up-down) are terms used for ease of explanation, and the correspondence between the X, Y, and Z directions may change depending on the mounting orientation of the semiconductor module. For example, the heat dissipation surface (cooler side) of the semiconductor module may be designated as the lower surface side, and its opposite side as the upper surface side. Furthermore, in this specification, "top view" refers to the view of the upper surface of the semiconductor module from the Z-direction.

[0029] Semiconductor module 1 is used, for example, in power conversion devices such as power modules. Figures 1 to 4 (A) and Figure 4 As shown in (B), the semiconductor module 1 is constructed by arranging a plurality of semiconductor elements 3 and a plurality of block electrodes 4 on the upper surface of the laminated substrate 2.

[0030] The laminated substrate 2 is formed by stacking metal layers and insulating layers, and may be composed of, for example, a DCB (Direct Copper Bonding) substrate, an AMB (Active Metal Brazing) substrate, or a metal substrate. Specifically, the laminated substrate 2 has an insulating plate 20, a heat sink 21 disposed on the lower surface of the insulating plate 20, and a plurality of circuit patterns 22 disposed on the upper surface of the insulating plate 20. In addition, the laminated substrate 2 is formed into a rectangular shape in plan view, where the Y direction is longer than the X direction.

[0031] The insulating plate 20 has a thickness in the Z direction and is formed into a flat plate with an upper surface and a lower surface. The insulating plate 20 is formed from insulating materials such as ceramic materials like alumina (Al2O3), aluminum nitride (AlN), and silicon nitride (Si3N4), resin materials like epoxy, or epoxy resin materials using ceramic materials as fillers. Furthermore, the insulating plate 20 may also be referred to as an insulating layer or insulating film.

[0032] The heat sink 21 has a specified thickness and is formed as a whole covering the lower surface of the insulating plate 20. The heat sink 21 is formed, for example, from a metal plate with good thermal conductivity such as copper or aluminum. The lower surface of the heat sink 21 serves as a heat dissipation surface, and a cooler 10 is mounted on the heat dissipation surface.

[0033] The cooler 10 is, for example, a heat sink and has a rectangular shape when viewed from above. The cooler 10 is formed of metals such as copper and aluminum, or an alloy containing one or more of these metals, and its surface is, for example, plated. The cooler 10 is mounted to the semiconductor module 1 (heat sink 21) with a thermally conductive mixture or similar material spaced between it and the lower surface of the semiconductor module 1. The upper surface of the cooler 10 forms a smooth mating surface for contact with the lower surface of the semiconductor module 1. Multiple heat sink fins 10a protruding in the Z-direction are formed on the lower surface side of the cooler.

[0034] Multiple heat sinks 10a are arranged side-by-side with spacing along the Y direction. This forms a groove 10b between adjacent heat sinks 10a. Cooling of the semiconductor module 1 is achieved by the flow of refrigerant, such as air, through the groove 10b. The direction of refrigerant flow (flow direction) is referred to as the cooling direction F, which will be described in detail later. Furthermore, the cooler 10 is not limited to the structure described above and may also be a water-cooled cooler equipped with a water-cooling jacket.

[0035] like Figure 3 As shown, multiple (four in this embodiment) circuit patterns 22 are formed in an island shape (electrically insulated from each other) on the main surface of the insulating plate 20. The multiple circuit patterns 22 are composed of a pair of collector circuit patterns 23 connected to the collector electrode 30 of the semiconductor element 3 described later, a gate circuit pattern 24 connected to the gate electrode 31, and an emitter circuit pattern 25 connected to the emitter electrode 32.

[0036] The collector circuit pattern 23 has a top view elongated strip shape extending along the long side (Y direction) of the insulating plate 20 on the outer periphery of the insulating plate 20. A pair of collector circuit patterns 23 are arranged opposite each other in the short side (X direction) of the insulating plate 20.

[0037] The gate circuit pattern 24 has an L-shaped bend from one end of the insulating plate 20 along its long side toward the center and branches into four branches from the center of the insulating plate 20. Specifically, the gate circuit pattern 24 is formed by connecting an L-shaped portion 24a (viewed from above) and an H-shaped portion 24b (viewed from above). The L-shaped portion 24a extends from one corner of the insulating plate 20 toward the X direction and bends at a right angle at approximately the middle portion of the insulating plate 20 in the X direction, extending to the center of the insulating plate 20. The H-shaped portion 24b is formed by connecting the center of a pair of elongated portions extending in the Y direction with elongated portions extending in the X direction. The H-shaped portion 24b is disposed in the center of the insulating plate 20. The center of the H-shaped portion 24b is connected to the end of the central side of the L-shaped portion 24a. Furthermore, the H-shaped portion 24b constitutes a region in the center of the insulating plate 20 where the gate electrode 31 is joined via bump B, as will be described in detail later.

[0038] The emitter circuit pattern 25 is formed in a roughly U-shape when viewed from above, surrounding the outer periphery of the H portion 24b. Specifically, the emitter circuit pattern 25 consists of an emitter portion 25a extending in the X direction along the short side on the other side of the long side of the insulating plate 20, a pair of elongated portions 25b and 25c extending from the emitter portion 25a in the Y direction, and a sensing emitter portion 25d connected to one of the elongated portions 25c.

[0039] One end of each of a pair of elongated portions 25b and 25c is connected to the emitter portion 25a, and the other end of each pair of elongated portions 25b and 25c extends along the Y direction. The pair of elongated portions 25b and 25c are arranged opposite each other such that the H portion 24b is sandwiched in the middle in the X direction. Each elongated portion 25b and 25c is arranged such that it is sandwiched between the collector circuit pattern 23 and the H portion 24b. The pair of collector circuit patterns 23, the pair of elongated portions 25b and 25c, and the pair of elongated portions of the H portion 24b extend parallel to each other in the Y direction. The sensing emitter portion 25d is arranged on the opposite side of the emitter portion 25a such that it sandwiches a collector circuit pattern 23 between itself and the emitter portion 25a. Furthermore, the sensing emitter portion 25d is arranged parallel to the L portion 24a of the gate circuit pattern 24 in the X direction and extends along the X direction. The sensing emitter portion 25d is connected to an elongated portion 25c. In addition, a pair of elongated portions 25b and 25c form an area on the outside of portion H 24b for the emitter electrode 32 to be engaged via bump B, as will be described in detail later.

[0040] In the circuit pattern 22 constructed in this way, as follows: Figure 3 As shown, the H-section 24b of the gate circuit pattern 24 is sandwiched between a pair of elongated sections 25b and 25c. Furthermore, the H-section 24b and the pair of elongated sections 25b and 25c are both sandwiched between a pair of collector circuit patterns 23. In addition, Figure 3 The double-dotted section represents the area for bonding the block electrode 4 or semiconductor element 3, which will be described later.

[0041] Multiple semiconductor elements 3 are arranged at predetermined locations in the circuit pattern 22. The semiconductor elements 3 are formed into a square shape from a top view using a semiconductor substrate such as silicon (Si) or silicon carbide (SiC). In this embodiment, the semiconductor element 3 is composed of an RC (Reverse Conducting)-IGBT element that integrates the functions of an IGBT (Insulated Gate Bipolar Transistor) element and an FWD (Free Wheeling Diode) element.

[0042] Furthermore, semiconductor element 3 is not limited to this; it can also be constructed by combining switching elements such as IGBTs, power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and diodes such as FWDs (Free Wheeling Diodes). Additionally, RB (Reverse Blocking) IGBTs, which have sufficient withstand voltage relative to reverse bias, can also be used as semiconductor element 3. Furthermore, the shape, number, and placement of semiconductor elements 3 can be appropriately modified.

[0043] In this embodiment, four semiconductor elements 3 are disposed on the upper surface of the H portion 24b and the upper surface of a pair of elongated portions 25b and 25c via multiple bumps B. Specifically, the semiconductor elements 3 are disposed above the top of the branched H portion 24b and above the top or base of the elongated portions 25b and 25c. A collector electrode 30 is disposed on the upper surface of the semiconductor element 3, and a gate electrode 31 and an emitter electrode 32 are disposed on the lower surface of the semiconductor element 3. The gate electrode 31 is disposed at the center of one end side of the semiconductor element 3, and the emitter electrode 32 is disposed at the opposite end side.

[0044] Semiconductor element 3 has its gate electrode 31 positioned opposite the top surface of the H-section 24b, and its emitter electrode 32 positioned opposite the top surfaces of the elongated sections 25b and 25c. Semiconductor element 3 is bonded to circuit pattern 22 via bumps B. More specifically, for a semiconductor element 3, gate electrode 31 is electrically bonded to the top surface of the branched H-section 24b via one bump B. Furthermore, for a semiconductor element 3, emitter electrode 32 is electrically bonded to the top surfaces of the elongated sections 25b and 25c via three bumps B.

[0045] Thus, the gate electrode 31 and the emitter electrode 32 are arranged side by side in the X direction. In particular, in the X direction, the gate electrode 31 is positioned further inward than the emitter electrode 32. That is, the four gate electrodes 31 are arranged to be more biased toward the center of the module than the four emitter electrodes 32.

[0046] Bump B can be made of a paste-like metal sintering material. For example, a metal nanoparticle sintering agent such as silver can be used as bump B. Bump B is formed into a cylindrical shape, for example, extending along the thickness direction (Z direction). Furthermore, bump B is not limited to a metal sintering material and can also be made of solder.

[0047] Additionally, block electrodes 4 are attached to each circuit pattern 22. Specifically, the block electrode 4 is composed of a collector block 40 attached to the collector circuit pattern 23, a gate electrode block 41 attached to the gate circuit pattern 24, an emitter electrode block 42 attached to the emitter circuit pattern 25, and a sensing emitter electrode block 43.

[0048] The collector block 40 is formed in a generally square shape when viewed from above, covering most of the upper part of the laminated substrate 2. Specifically, the collector block 40 has a flat plate portion 44 covering the upper part of the semiconductor element 3 and a pair of protrusions 45 protruding from both ends of the flat plate portion 44 in the X direction toward the collector circuit pattern 23. Thus, the collector block 40 appears generally U-shaped when viewed from the Y direction.

[0049] The plate portion 44 is formed in a generally square shape when viewed from above, covering a pair of collector circuit patterns 23, a pair of elongated portions 25b and 25c disposed between the pair of collector circuit patterns 23, an H portion 24b, and four semiconductor elements 3. The width of the plate portion 44 in the X direction corresponds to the relative spacing between the pair of collector circuit patterns 23. The width of the plate portion 44 in the Y direction corresponds to the length of the collector circuit patterns 23 in the Y direction. In addition, a circular through-hole 46 extending along the thickness direction is formed in the center of the plate portion 44.

[0050] The protrusion 45 has a generally cuboid shape, projecting downwards in the Z direction from its end in the X direction of the flat plate 44. The width of the protrusion 45 in the X direction is slightly smaller than the width of the collector circuit pattern 23. Furthermore, the width of the protrusion 45 in the Y direction corresponds to the width of the flat plate 44 and is slightly smaller than the width of the collector circuit pattern 23. Additionally, chamfers are formed at each corner on the upper surface side of the collector block 40. A pair of protrusions 45 are arranged along two opposite sides of the insulating plate 20.

[0051] The collector 30 of the semiconductor element 3 is electrically bonded to the lower surface of the flat plate portion 44 via a bonding material S. Additionally, the lower surfaces of each protrusion 45 are electrically bonded to the collector circuit pattern 23 via the bonding material S. The bonding material S can be a sheet-like metal sintering material. For example, a metal nanoparticle sintering agent such as silver can be formed into a sheet and used as the bonding material S. The bonding material S is formed, for example, into a rectangular shape of a predetermined thickness. Furthermore, the bonding material S is not limited to a metal sintering material and can also be made of solder. Additionally, the bonding material S is not limited to a sheet shape and can also be made of a paste. Furthermore, the height of the protrusion 45 in the Z direction preferably corresponds to the combined height of the thickness of the semiconductor element 3 and the height of the bump B.

[0052] The gate electrode block 41 has a long cuboid shape in the X direction. Specifically, the width of the gate electrode block 41 in the X direction corresponds to the width of the elongated portion in the X direction of the L portion 24a. The width of the gate electrode block 41 in the Y direction is slightly smaller than the width of the L portion 24a. In addition, chamfers are formed at each corner on the upper surface side of the collector electrode block 40. The lower surface of the gate electrode block 41 is electrically bonded to the upper surface of the elongated portion in the X direction of the L portion 24a via a bonding material S.

[0053] The emitter electrode block 42 has a cuboid shape extending in the X direction along the short side on the other side of the long side of the insulating plate 20. Specifically, the width of the emitter electrode block 42 in the X direction and the width in the Y direction are slightly smaller than the width of the emitter portion 25a. In addition, chamfers are formed at each corner of the upper surface side of the emitter electrode block 42. The lower surface of the emitter electrode block 42 is electrically bonded to the upper surface of the emitter portion 25a via a bonding material S. When viewed from above, the emitter electrode block 42 is disposed outside the collector block 40 (flat plate portion 44).

[0054] The sensing emitter electrode block 43 has a rectangular parallelepiped shape that is longer in the X direction. Specifically, the width of the sensing emitter electrode block 43 in both the X and Y directions is slightly smaller than the width of the sensing emitter portion 25d. Furthermore, chamfers are formed at each corner on the upper surface side of the collector block 40. The lower surface of the sensing emitter electrode block 43 is electrically bonded to the upper surface of the sensing emitter portion 25d via a bonding material S. The sensing emitter electrode block 43 is disposed outside the collector block 40 (flat plate portion 44) when viewed from above. The sensing emitter electrode block 43 and the gate electrode block 41 are arranged side-by-side in the X direction. Additionally, the length of the sensing emitter electrode block 43 in the X direction is less than the length of the gate electrode block 41.

[0055] The block electrode 4 thus constructed is configured such that its height is equal in the Z direction. Furthermore, the block electrode 4 is preferably formed from a metal material with good thermal conductivity, such as copper or aluminum. Additionally, the collector block 40 can be formed either integrally with the flat plate portion 44 and the pair of protrusions 45, or by joining the flat plate portion 44 and the pair of protrusions 45 together using welding or the like.

[0056] Additionally, a sealing resin 5 is filled into the space above the laminated substrate 2 (see reference). Figure 1 The sealing resin 5, for example, is filled with the through-hole 46 to seal the semiconductor element 3, the laminated substrate 2, and the block electrode 4. The sealing resin 5 can be epoxy resin or silicone gel.

[0057] However, in conventional semiconductor modules, semiconductor elements are disposed on the upper surface of a laminated substrate. An emitter electrode is disposed on the upper surface of the semiconductor element, and a collector electrode is disposed on the lower surface of the semiconductor element. The circuit patterns of the emitter electrode and the laminated substrate are electrically connected, for example, by bonding wires. Additionally, a cooler is disposed on the lower surface of the laminated substrate.

[0058] In conventional structures, the heat generated by the emitter electrode is dissipated through a cooler. In this case, since the emitter electrode is located on the surface side of the semiconductor device, the generated heat is transferred to the back side (collector side) of the semiconductor device and dissipated through the laminated substrate and the cooler.

[0059] Thus, since the semiconductor element generates heat on the emitter electrode side, the heat generated on the emitter electrode side needs to be transferred to the collector electrode side, which serves as the cooler side. Therefore, there is a problem of increased overall module thermal resistance corresponding to the thermal conductivity and thickness of the semiconductor element. Furthermore, as mentioned above, the emitter electrode is conventionally wired using bonding wires, resulting in longer wiring lengths and consequently, increased inductance.

[0060] Therefore, the inventors of this application conceived of the present invention by focusing on the orientation of the emitter electrode, which serves as a heat source, in the semiconductor element. Specifically, the main objective of this invention is to reverse the bonding direction of the semiconductor element 3, positioning the emitter electrode 32 towards the laminated substrate 2. In this embodiment, the semiconductor element 3 is disposed on the upper surface of the laminated substrate 2. A collector electrode 30 is disposed on the upper surface of the semiconductor element 3, and an emitter electrode 32 is disposed on the lower surface of the semiconductor element 3. The emitter electrode 32 is bonded to the circuit pattern 22 on the laminated substrate 2 via a bump B.

[0061] Additionally, a block electrode 4 (collector block 40) is attached to the collector 30, which is located on the upper surface side of the semiconductor element 3. The collector block 40 has a flat plate portion 44 covering the upper part of the semiconductor element 3 and protrusions 45 extending from both ends of the flat plate portion 44 toward the circuit pattern 22. The protrusions 45 are attached to the circuit pattern 22.

[0062] According to this structure, the emitter electrode 32 faces the laminated substrate 2 and is bonded to the laminated substrate 2 via bumps B. Therefore, the heat generated by the emitter electrode 32 does not pass through the interior of the semiconductor device but can be directly transferred to the laminated substrate 2 (heat sink 21) through the bumps B. This reduces thermal resistance and improves cooling efficiency. Because the thermal resistance is reduced, the module size can be made close to the chip size, enabling overall module miniaturization. Furthermore, by implementing the wiring of the emitter electrode 32 via bumps B, the wiring length can be shortened compared to conventional bonding wires, and inductance can also be reduced.

[0063] Furthermore, the collector block 40 enables electrical connection of the collector 30, thereby eliminating unnecessary wiring and allowing heat from the semiconductor element 3 to be transferred to the laminated substrate 2 via the collector block 40. In other words, the collector block 40 can be used not only as an electrical bonding component but also as a heat transfer component. Therefore, the cooling effect can be further improved. Additionally, the use of numerous metal block electrodes 4 with high heat capacity enables the realization of modules with high thermal conductivity and short-circuit withstand capability.

[0064] Furthermore, in this embodiment, it is preferable that the relative directions of the pair of protrusions 45 in the collector block 40 are aligned with the direction of refrigerant flow (cooling direction F) within the range corresponding to the collector block 40 in the cooler 10 mounted on the lower surface of the semiconductor module 1. For example, Figure 1 As shown, the direction of refrigerant flow may be parallel to the grooves 10b in a cooler 10 having multiple heat sinks 10a with grooves 10b in one direction (X direction). Alternatively, for example, in a cooler 10 composed of a water-cooled jacket, the direction of liquid flow inside the water-cooled jacket may be aligned with the opposite direction of a pair of protrusions 45.

[0065] Specifically, such as Figure 5 As shown in (A), a pair of protrusions 45 have a cuboid shape that is longer in the Y direction and are opposite to each other in the X direction. In this case, it is preferable that the flow direction (cooling direction F) of the refrigerant flowing into the cooler 10 is towards the X direction. According to this structure, as Figure 5 As shown in (B), the refrigerant flows from below one protrusion 45, through the underside of the flat plate 44, towards the underside of another protrusion 45. Thus, because the refrigerant flows in a direction perpendicular to the long side (long side) of the protrusion 45, a larger area of ​​refrigerant contributes to the cooling of the collector block 40.

[0066] like Figure 5 As shown in (B), on the midstream side of the refrigerant (the central side in the X direction of the semiconductor module 1), heat from the semiconductor element 3 can be released to the cooler 10 via the bump B. Additionally, on the upstream and downstream sides of the refrigerant (the outer sides in the X direction of the semiconductor module 1), heat from the semiconductor element 3 can be released to the cooler 10 via the plate portion 44 and the pair of protrusions 45. Thus, heat can be effectively released from both sides of the semiconductor element 3. As a result, the four semiconductor elements 3 disposed below the plate portion 44 and between the pair of protrusions 45 can be cooled uniformly. Therefore, temperature deviations of each semiconductor element 3 can be suppressed, and cooling performance can be improved.

[0067] Furthermore, in this embodiment, a through hole 46 extending along the thickness direction is formed in the center of the plate portion 44. With this structure, the through hole 46 can be utilized as an injection port for the sealing resin 5. Therefore, the sealing resin 5 can be filled completely between the plate portion 44 and the semiconductor element 3. Additionally, voids present during the injection of the sealing resin 5 can be easily removed.

[0068] Furthermore, in this embodiment, the gate electrode 31 is positioned closer to the center of the plate portion 44 than the emitter electrode 32. That is, as... Figure 3 as well as Figure 4 (A) and Figure 4 As shown in (B), the gate electrodes 31 of the four semiconductor elements 3 face the center of the plate portion 44, and the emitter electrodes 32 are located on the outer periphery of the gate electrodes 31. More specifically, when viewed from above, four semiconductor elements 3 are arranged in a 2×2 configuration below the plate portion 44, and the gate electrodes 31 of the semiconductor elements 3 are arranged opposite each other in the center of the plate portion 44. According to this structure, the emitter electrodes 32, which are heat-generating components, are not concentrated in the center of the module, but are spaced apart from each other. As a result, heat is not concentrated in the center of the module, but is dispersed to improve cooling efficiency. In addition, the gate electrodes 31 are disposed in the center of the laminated substrate 2, and the gate electrodes 31 are bonded to the branched top surface of the H portion 24b via bump B, thereby uniformly shortening the wiring length from the outside to the gate electrodes 31 and suppressing gate oscillation.

[0069] Furthermore, in this embodiment, a gate electrode block 41, an emitter electrode block 42, and a sensing emitter electrode block 43 are disposed on the outside of the collector block 40. That is, the collector block 40 is configured to be sandwiched between the gate electrode block 41, the emitter electrode block 42, and the sensing emitter electrode block 43 in the Y direction. According to this structure, since the emitter electrode block 42 and the sensing emitter electrode block 43 are disposed on the outside of the collector block 40, external connections can be easily obtained.

[0070] Next, refer to Figure 6 (A) and Figure 6 (B) to Figure 9 (A) and Figure 9 (B) describes the method for manufacturing the semiconductor module involved in this embodiment. Figure 6 (A) and Figure 6 (B) to Figure 9 (A) and Figure 9(B) is a perspective view illustrating a step example of the manufacturing method of the semiconductor module according to this embodiment. Furthermore, the semiconductor module manufacturing method shown below is merely an example and is not limited to this structure, but can be appropriately modified. Additionally, for ease of explanation, the heat sink is omitted in the following figures. Figure 6 (A) and Figure 6 (B) Figure 7 (A) and Figure 7 (B) Figure 9 (A) and Figure 9 (B) is a diagram showing the state before and after each process.

[0071] The semiconductor module 1 manufacturing method according to this embodiment is configured by sequentially performing the following steps: a preparation step, in which a multilayer substrate 2 and a block electrode 4 are prepared; a chip placement step (see...). Figure 6 (A) and Figure 6 In the chip configuration process (B), semiconductor element 3 is configured on collector block 40; the first electrode configuration process (refer to...) Figure 7 (A) and Figure 7 In the first electrode configuration process (B), a gate electrode block 41, an emitter electrode block 42, and a sensing emitter electrode block 43 are configured on the laminated substrate 2; the bump configuration process (see reference) Figure 8 In the bump configuration process, bumps are configured on semiconductor element 3; the second electrode configuration process (refer to...) Figure 9 (A) and Figure 9 In the second electrode configuration process (B), the collector block 40 and the semiconductor element 3 are configured on the laminated substrate 2; and the sealing process (see reference) Figure 1 In this sealing process, sealing resin 5 is filled. Furthermore, the order of these processes can be appropriately changed as long as no contradictions arise.

[0072] First, prepare the aforementioned stacked substrate 2 and block electrodes 4 (collector block 40, gate electrode block 41, emitter electrode block 42 and sensing emitter electrode block 43) in advance (preparation process).

[0073] Next, the chip configuration process is carried out. For example... Figure 6 (A) and Figure 6 As shown in (B), in the chip manufacturing process, four semiconductor elements 3 are arranged such that the collector 30 faces the lower surface of the plate portion 44. A bonding material S (see reference) is disposed on the upper surface (collector surface) of the semiconductor elements 3. Figure 4 (A) and Figure 4(B)) and the bonding material S is disposed at a predetermined location on the plate portion 44. At this time, the gate electrode 31 of each semiconductor element 3 is disposed in such a way that it is located inside the emitter electrode 32 in the X direction. Then, the collector surface of the semiconductor element 3 is pressed toward the plate portion 44 with a predetermined pressure, and heated at a predetermined temperature for a predetermined time, thereby electrically bonding the semiconductor element 3 and the plate portion 44 via the bonding material S. In addition, the bonding material S can be a bonding material that is pre-formed into a sheet shape to match the shape of the semiconductor element 3, or a paste-like metal sintering material can be coated on the collector surface.

[0074] Next, the first electrode configuration process is performed. For example... Figure 7 (A) and Figure 7 As shown in (B), in the first electrode arrangement process, the gate electrode block 41, the emitter electrode block 42, and the sensing emitter electrode block 43 are arranged at predetermined locations on the circuit pattern 22. Specifically, the gate electrode block 41 is arranged on the upper surface of the L portion 24a via the bonding material S. The emitter electrode block 42 is arranged on the upper surface of the emitter portion 25a via the bonding material S. The sensing emitter electrode block 43 is arranged on the upper surface of the sensing emitter portion 25d via the bonding material S. Then, these block electrodes 4 are pressed toward the laminated substrate 2 with a predetermined pressure and heated at a predetermined temperature for a predetermined time, thereby electrically bonding the portions of the block electrodes 4, excluding the collector electrode block 40, to each circuit pattern 22 via the bonding material S.

[0075] Next, the bump configuration process is performed. For example... Figure 8 As shown, in the bump configuration process, bumps B of predetermined height are configured on the emitter electrode 32 and the gate electrode 31. Additionally, a bonding material S is configured on the lower surface of a pair of protrusions 45. Furthermore, the bumps B preferably have a height that slightly protrudes from the lower surface of the bonding material S.

[0076] Next, the second electrode configuration process is performed. For example... Figure 9 (A) and Figure 9 As shown in (B), in the second electrode configuration process, the emitter electrode 32 is bonded to the circuit pattern 22 via bump B, and a pair of protrusions 45 are bonded to the circuit pattern 22 via bonding material S. Specifically, the bump B disposed on the emitter electrode 32 is positioned on the upper surface of a pair of elongated portions 25b and 25c, and the bump B disposed on the gate electrode 31 is positioned on the upper surface of the H portion 24b. In addition, a pair of protrusions 45 are disposed on the upper surface of a pair of collector circuit patterns 23 via bonding material S. Then, the collector block 40 is pressed toward the laminated substrate 2 with a predetermined pressure and heated at a predetermined temperature for a predetermined time, thereby bonding the emitter electrode 32 to the circuit pattern 22 via bump B and bonding the collector block 40 to the collector circuit pattern 23 via bonding material S.

[0077] Next, the sealing process is carried out. For example... Figure 1 As shown, in the sealing process, the space above the laminated substrate 2 is sealed with sealing resin 5. For example, a rectangular frame (not shown) is arranged around the laminated substrate 2, allowing the sealing resin 5 to be filled into the space within the frame without any omissions from the through-hole 46. By curing the sealing resin 5, the laminated substrate 2, the semiconductor element 3, and the block electrode 4 are sealed. Thus, the integrated semiconductor module 1 is completed.

[0078] As explained above, according to the present invention, by reversing the bonding direction of the semiconductor element 3 from the conventional orientation and arranging the emitter electrode 32 toward the side of the stacked substrate 2, thermal resistance and inductance can be reduced. Furthermore, compared to the conventional approach, structures such as wires can be omitted, enabling simplification and miniaturization of the overall module structure.

[0079] Furthermore, in the above embodiments, the number and arrangement of semiconductor elements 3 are not limited to the above structure, but can be appropriately changed.

[0080] Furthermore, in the above embodiments, the number and layout of the circuit patterns 22 are not limited to the above structure, but can be appropriately changed.

[0081] Furthermore, in the above embodiments, the laminated substrate 2 and the semiconductor element 3 are formed into a rectangular or square shape when viewed from above, but are not limited to this structure. The laminated substrate 2 and the semiconductor element 3 may also be formed into polygonal shapes other than those described above.

[0082] Furthermore, this embodiment and its variations have been described. As other embodiments, the above-described embodiments and variations may be combined in whole or in part.

[0083] Furthermore, this embodiment is not limited to the above-described embodiments and variations. Various changes, substitutions, and modifications can be made without departing from the spirit of the technical concept. Moreover, if the technical concept can be realized in other ways through technological advancements or derived technologies, this method can also be used to implement the present invention. Therefore, the claims cover all embodiments that may be included within the scope of the technical concept.

[0084] The following is a summary of the features described in the above embodiments.

[0085] The semiconductor module described in the above embodiments is characterized in that it includes: a laminated substrate having a circuit pattern disposed on the upper surface of an insulating plate and a heat sink disposed on the lower surface of the insulating plate; a semiconductor element having a collector electrode disposed on its upper surface and an emitter electrode and a gate electrode disposed on its lower surface, the emitter electrode and the gate electrode being joined to the upper surface of the circuit pattern via bumps; and a block electrode joined to the collector electrode, the block electrode having: a flat plate portion covering the upper part of the semiconductor element; and a pair of protrusions protruding from both ends of the flat plate portion toward the circuit pattern and joining the circuit pattern.

[0086] Furthermore, in the semiconductor module described in the above embodiments, the opposite direction of the pair of protrusions is consistent with the direction of refrigerant flow.

[0087] Furthermore, in the semiconductor module described in the above embodiments, the semiconductor element is characterized in that it is disposed between the pair of protrusions.

[0088] Furthermore, in the semiconductor module described in the above embodiments, a through hole is formed in the center of the flat plate portion.

[0089] Furthermore, in the semiconductor module described in the above embodiments, the semiconductor element is characterized in that it has a gate electrode disposed on its lower surface, and the gate electrode is disposed at a position closer to the center of the plate portion than the emitter electrode.

[0090] Furthermore, in the semiconductor module described in the above embodiments, the semiconductor elements are arranged in a 2×2 configuration below the plate portion when viewed from above, and the gate electrodes of each semiconductor element are arranged opposite each other at the center of the plate portion.

[0091] Furthermore, in the semiconductor module described in the above embodiments, the circuit pattern comprises: a collector circuit pattern connected to the collector electrode; a gate circuit pattern connected to the gate electrode; and an emitter circuit pattern connected to the emitter electrode. The block electrode comprises: a collector block bonded to the collector circuit pattern; a gate block bonded to the gate circuit pattern; an emitter block bonded to the emitter portion of the emitter circuit pattern; and a sensing emitter block bonded to the sensing emitter portion of the emitter circuit pattern. The collector block is composed of the flat plate portion and the pair of protrusions. The gate block, the emitter block, and the sensing emitter block are disposed outside the collector block.

[0092] Furthermore, in the semiconductor module described in the above embodiments, the gate circuit pattern has a region in the center of the insulating plate for the gate electrode to be joined via the bump, and the emitter circuit pattern has a region on the outside of the gate circuit pattern for the emitter electrode to be joined via the bump.

[0093] Furthermore, in the semiconductor module described in the above embodiments, the gate circuit pattern is characterized in that the gate circuit pattern is disposed in the center of the insulating plate and has an H portion that is H-shaped when viewed from above. The gate electrode is joined to the upper surface of the branching top of the H portion via the bump. The emitter circuit pattern has a pair of elongated portions that are arranged opposite each other between the pair of protrusions in such a way that the H portion is sandwiched in the middle. The emitter electrode is joined to the pair of elongated portions via the bump.

[0094] Furthermore, in the semiconductor module described in the above embodiments, the collector circuit pattern is characterized in that the collector circuit pattern has an elongated shape corresponding to the pair of protrusions, and the pair of elongated portions are disposed between the H portion and the collector circuit pattern.

[0095] Furthermore, in the semiconductor module described in the above embodiments, the emitter circuit pattern is characterized by having: an emitter portion that connects one end of the pair of elongated portions to each other; and a sensing emitter portion that connects to one of the pair of elongated portions, the emitter electrode block being engaged with the upper surface of the emitter portion, the sensing emitter electrode block being engaged with the upper surface of the sensing emitter portion, and the emitter electrode block and the sensing emitter electrode block being arranged such that, when viewed from above, the plate portion is sandwiched between the outer sides of the plate portion.

[0096] Furthermore, in the semiconductor module described in the above embodiments, the gate electrode block is positioned opposite the emitter electrode block across the plate portion and is arranged side-by-side with the sensing emitter block.

[0097] Furthermore, the semiconductor module manufacturing method described in the above embodiments is characterized by performing the following steps in the semiconductor module manufacturing method: a preparation step, in which a multilayer substrate and a block electrode are prepared, the multilayer substrate being formed by distributing a circuit pattern on the upper surface of an insulating plate and distributing a heat sink on the lower surface of the insulating plate, the block electrode having a flat plate portion covering the upper part of a semiconductor element and a pair of protrusions extending from both ends of the flat plate portion toward the circuit pattern; a chip placement step, in which the semiconductor element is placed on the lower surface of the flat plate portion such that the collector electrode faces the lower surface of the flat plate portion; and a block electrode placement step, after the chip placement step, in which the emitter electrode disposed on the lower surface of the semiconductor element is joined to the circuit pattern of the insulating plate via bumps, and the pair of protrusions are joined to the circuit pattern.

[0098] Furthermore, in the semiconductor module manufacturing method described in the above embodiments, a through hole is formed in the center of the plate portion, and a sealing process is performed after the block electrode arrangement process, in which sealing resin is filled into the through hole to seal the semiconductor element.

[0099] Industrial availability

[0100] As described above, the present invention has the effect of reducing thermal resistance and reducing inductance, and is particularly useful for semiconductor modules and methods of manufacturing semiconductor modules.

Claims

1. A semiconductor module characterized by comprising: a laminated substrate which is formed by disposing a circuit pattern on an upper surface of an insulating board and disposing a heat dissipation board on a lower surface of the insulating board; a semiconductor element which is disposed with a collector electrode on an upper surface and with an emitter electrode and a gate electrode on a lower surface, the emitter electrode and the gate electrode being joined with an upper surface of the circuit pattern via a bump; and a block electrode, the circuit pattern has: a collector electrode circuit pattern connected with the collector electrode; a gate electrode circuit pattern connected with the gate electrode, and an emitter electrode circuit pattern connected with the emitter electrode, the block electrode has: a collector electrode block joined with the collector electrode circuit pattern; a gate electrode block joined with the gate electrode circuit pattern; an emitter electrode block joined with an emitter portion of the emitter electrode circuit pattern; and a sensing emitter electrode block joined with a sensing emitter portion of the emitter electrode circuit pattern, the collector electrode block is composed of a flat plate portion which covers above the semiconductor element and a pair of protruding portions which protrude from both ends of the flat plate portion toward the collector electrode circuit pattern to be joined with the collector electrode circuit pattern, the gate electrode block, the emitter electrode block, and the sensing emitter electrode block are disposed outside the collector electrode block.

2. The semiconductor module according to claim 1, characterized in that the pair of protruding portions are disposed along opposite two edges of the insulating board.

3. The semiconductor module according to claim 1 or 2, characterized in that opposite directions of the pair of protruding portions are in line with a direction of refrigerant flow.

4. The semiconductor module according to claim 1, characterized in that the semiconductor element is disposed between the pair of protruding portions.

5. The semiconductor module according to claim 1, characterized in that a through hole is formed in a center of the flat plate portion.

6. The semiconductor module according to claim 1, characterized in that the gate electrode is disposed at a position on a center side of the flat plate portion than the emitter electrode.

7. The semiconductor module according to claim 1, characterized in that four semiconductor elements are disposed below the flat plate portion in a 2 x 2 manner in plan view, the gate electrode of each semiconductor element being disposed in opposite directions in a center of the flat plate portion.

8. The semiconductor module according to claim 1, characterized in that the gate electrode circuit pattern has an area for the gate electrode to be joined via the bump in a center of the insulating board, the emitter electrode circuit pattern has an area for the emitter electrode to be joined via the bump outside the gate electrode circuit pattern.

9. The semiconductor module according to claim 8, characterized in that the gate electrode circuit pattern is disposed in a center of the insulating board, has an H portion in plan view in an H shape, and the gate electrode is joined with an upper surface of a top end of a branch of the H portion via the bump, ​ The emitter electrode circuit pattern has a pair of long strip portions arranged opposite each other in a manner to sandwich the H portion between the pair of protruding portions of the collector block, and the emitter electrode is joined to the pair of long strip portions via bumps.

10. The semiconductor module according to claim 9, wherein The collector electrode circuit pattern has a long strip shape corresponding to the pair of protruding portions of the collector block in plan view, The pair of long strip portions of the emitter electrode circuit pattern are arranged between the H portion and the collector electrode circuit pattern.

11. The semiconductor module according to claim 10, wherein The emitter electrode circuit pattern has: The emitter portion links one end of the pair of long strip portions of the emitter electrode circuit pattern to each other; The sensing emitter portion is linked to one of the pair of long strip portions, The emitter electrode block is joined to the upper surface of the emitter portion, The sensing emitter electrode block is joined to the upper surface of the sensing emitter portion, The emitter electrode block and the sensing emitter electrode block are arranged in a manner to sandwich the flat plate portion between the outside of the flat plate portion in plan view.

12. The semiconductor module according to claim 11, wherein The gate electrode block is arranged opposite to the emitter electrode block via the flat plate portion and is arranged side by side with the sensing emitter electrode block.

13. A manufacturing method of a semiconductor module, comprising: In the manufacturing method of the semiconductor module, the following steps are implemented: A preparation step in which a laminated substrate and a plurality of block electrodes are prepared, The laminated substrate is formed by arranging an electrode circuit pattern on the upper surface of an insulating plate and arranging a heat dissipation plate on the lower surface of the insulating plate, The block electrode has a collector block having a flat plate portion covering the upper side of a semiconductor element and a pair of protruding portions protruding from both ends of the flat plate portion toward the electrode circuit pattern; A chip arrangement step in which the semiconductor element is arranged on the lower surface of the flat plate portion in a manner that the collector faces the lower surface of the flat plate portion; And A first block electrode arrangement step implemented after the chip arrangement step in which an emitter electrode arranged on the lower surface of the semiconductor element is joined to the electrode circuit pattern of the insulating plate via bumps, and the pair of protruding portions are joined to the electrode circuit pattern, A second block electrode arrangement step implemented before or after the first block electrode arrangement step in which an emitter electrode block and a sensing emitter electrode block included in the plurality of block electrodes are respectively joined to the upper surface of an emitter portion and the upper surface of a sensing emitter portion in the electrode circuit pattern to which the emitter electrode is joined, and a gate electrode block included in the plurality of block electrodes is joined to the upper surface of the electrode circuit pattern to which a gate electrode arranged on the lower surface of the semiconductor element is joined.

14. The manufacturing method of the semiconductor module according to claim 13, wherein A through hole is formed in the center of the flat plate portion, After the first block electrode arrangement process and the second block electrode arrangement process, a sealing process is performed in which the semiconductor element is sealed by filling a sealing resin into the through holes. After the first block electrode arrangement process and the second block electrode arrangement process, a sealing process is performed in which the semiconductor element is sealed by filling a sealing resin into the through holes.

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