Capacitor structure and method of manufacturing the same

Abstract

A capacitor structure and a method of fabricating the same are disclosed. The capacitor structure includes a lower electrode plate on a substrate, the lower electrode plate having a plurality of recesses, a capacitor dielectric layer on the lower electrode plate and the recesses, and an upper electrode plate on the capacitor dielectric layer. The capacitor dielectric layer and the edge of the upper electrode plate have vertically extending portions extending in a direction perpendicular to the top surface of the lower electrode plate.

Description

TECHNICAL FIELD

[0001] The present invention relates to a capacitor structure, and more particularly, to a Metal-Insulator-Metal (MIM) capacitor structure with a plurality of recesses and vertically extended edge portions to increase its capacitance value. BACKGROUND

[0002] Currently, capacitors in semiconductor devices can be roughly classified into Poly-Insulator-Poly (PIP) capacitors, Metal-Oxide-Silicon (MOS) structures, and Metal-Insulator-Metal (MIM) capacitors according to their structures. These capacitors can be selectively used according to the characteristics of semiconductor devices in practical applications. For example, MIM capacitors can be used in high frequency semiconductor devices.

[0003] In recent years, with the rapid development of wireless communication technology, it is strongly desired to implant capacitors with high performance decoupling and filtering functions into the metal interconnection back-end manufacturing process of integrated circuits to obtain powerful radio frequency systems. To achieve such a design, the implanted capacitors must have high capacitance density, ideal voltage linearity, precise capacitance value control, and high reliability. The conventional PIP capacitors or MOS capacitors cannot meet the application at gigahertz frequency because they have the disadvantages of large voltage linearity, large parasitic resistance and capacitance loss, etc. Therefore, the use of MIM capacitors will be the inevitable choice for the development of radio frequency and analog / hybrid signal integrated circuits. Since MIM uses metal electrodes, it can effectively reduce the parasitic capacitance and the contact resistance of the electrodes, greatly improving the performance of the elements.

[0004] However, with the development of radio frequency technology, the requirement for the capacitance density of MIM capacitors will be higher and higher, while maintaining very small voltage linearity and good insulation performance. Therefore, how to meet the requirements of MIM capacitors in these aspects will be one of the key factors for the success of future wireless communication technology innovation. SUMMARY

[0005] In view of the foregoing need to improve the capacitance density of existing MIM capacitors and provide good insulation performance, the present invention proposes a novel capacitor structure that utilizes the micro loading effect inherent in the etching manufacturing process to form specially designed recesses, and can increase the surface area of the recesses through an additional back-pulling manufacturing process, thereby increasing the overall capacitance value of the capacitor structure. In addition, the additional manufacturing process treatment enables the formed MIM capacitor to have good insulation characteristics.

[0006] One of the aspects of the present application is to provide a capacitor structure, comprising a substrate, a lower electrode plate on the substrate, wherein the lower electrode plate has a plurality of recesses thereon, a capacitor dielectric layer on the lower electrode plate and the recesses, and an upper electrode plate on the capacitor dielectric layer, wherein the capacitor dielectric layer and the edges of the upper electrode plate have vertically extending portions extending in a direction perpendicular to the top surface of the lower electrode plate.

[0007] Another aspect of the present application is to provide a method for fabricating a capacitor structure, comprising forming a lower electrode material layer on a substrate, performing a first photolithography process to pattern the lower electrode material layer to form a lower electrode plate, wherein the first photolithography process simultaneously forms a plurality of recesses on the lower electrode plate, forming an oxide layer on the lower electrode plate, performing a second photolithography process to remove part of the oxide layer to form a capacitor recess including the recesses, the capacitor recess exposing the recesses, sequentially forming a capacitor dielectric layer and an upper electrode plate on the capacitor recess and the surface of the oxide layer, and removing the capacitor dielectric layer and the upper electrode plate on the top surface of the oxide layer, so that the capacitor dielectric layer and the edges of the upper electrode plate have vertically extending portions on the sidewalls of the oxide layer.

[0008] These and other aspects of the present application will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the application. BRIEF DESCRIPTION OF DRAWINGS

[0009] The accompanying drawings incorporated in and forming a part of the specification, illustrate several aspects of the present application. The drawings illustrate principles of the application in one or more embodiments. In the drawings:

[0010] Figures 1 to 8 FIG. 1 is a cross-sectional schematic view of a fabrication process of a capacitor structure in a preferred embodiment of the present application;

[0011] Figure 9 FIG. 2 is a cross-sectional schematic view of a capacitor structure and its fabrication steps in another embodiment of the present application; Figure 10 FIG. 3 is a cross-sectional schematic view of a fabrication process of a capacitor structure in yet another embodiment of the present application;

[0012] Figure 11 FIG. 4 is a cross-sectional schematic view of a fabrication process of a capacitor structure in yet another embodiment of the present application;

[0013] Figure 12 FIG. 5 is a cross-sectional schematic view of a fabrication process of a capacitor structure in yet another embodiment of the present application; and

[0014] Figure 13 FIG. 6 is a cross-sectional schematic view of a fabrication process of a capacitor structure in yet another embodiment of the present application; and Figure 14An enlarged schematic view of a capacitor structure in accordance with yet another embodiment of the present invention.

[0015] It is to be understood that all drawings included herein are for illustrative purposes only, that the figures shown are examples of exemplary embodiments and are not limiting as to the scope, the drawings are not necessarily drawn to scale, and that the various embodiments can include the same, equivalent or similar structures, functions, or elements wherever it is practical. When a particular element is indicated to be optional, it is contemplated that the particular element can be included in some embodiments and excluded from other embodiments.

[0016] Symbol Description

[0017] 100 substrate / dielectric layer

[0018] 102 lower electrode material layer

[0019] 104 titanium nitride layer

[0020] 106 aluminum layer

[0021] 108 titanium nitride layer

[0022] 110 photoresist

[0023] 112 lower electrode plate

[0024] 114a, 114b recesses

[0025] 116 dielectric layer

[0026] 118 photoresist

[0027] 120 capacitor recess

[0028] 122 capacitor dielectric layer

[0029] 122a vertically extending portion

[0030] 124 upper electrode plate

[0031] 124a vertically extending portion

[0032] 124b oxidized portion

[0033] 126 organic planarization layer

[0034] 128 dielectric layer

[0035] 130 contact

[0036] 132 metal layer

[0037] 134 lower electrode layer

[0038] 134a vertically extending portion

[0039] 134b oxidized portion

[0040] 136 side wall DETAILED DESCRIPTION

[0041] Reference will now be made to specific embodiments of the application, examples of which are illustrated in the accompanying drawings, in which the features shown are by way of illustration of the described features and not by way of limitation of the technical effect. It will be understood that the description herein is only by way of example and is not intended to limit the present case. Various embodiments of the present case and various features in the embodiments that do not conflict with each other can be combined or rearranged in various ways. Modifications, equivalents or improvements of the present case that do not depart from the spirit and scope of the present case can be understood by those skilled in the art, and are intended to be included in the scope of the present case.

[0042] The reader should readily appreciate that the terms "on", "over", and "above" in the present case should be interpreted in a broad manner to mean not only "directly on" something but also to include the meaning of being "on" something with intervening features or layers therebetween, and that "over" or "above" something not only means "over" or "above" something but can also include the meaning of being "over" or "above" something without intervening features or layers therebetween (i.e., directly on something).

[0043] In addition, spatially relative terms such as "under", "below", "lower", "over", "upper" and the like can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.

[0044] As used herein, the term "substrate" refers to a material to which subsequent materials are added. The substrate itself can be patterned. The materials added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0045] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over the entirety of an underlying or overlying structure, or can have a scope less than the scope of an underlying or overlying structure. Further, a layer can be a region of a continuous structure having a thickness that is less than the thickness of the continuous structure, whether homogenous or heterogeneous. For example, a layer can be located between or between any horizontal pair of top and bottom surfaces of a continuous structure. Layers can extend horizontally, vertically, and / or along an inclined surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, thereabove, and / or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which contacts, interconnect lines, and / or vias are formed) and one or more dielectric layers.

[0046] The following embodiments will now be described in sequence according to Figures 1 to 8 The fabrication flow of the present application's capacitor structure will now be described in sequence according to the cross-sectional structure of

[0047] First refer to Figure 1 The capacitor structure of the present application can be constructed on a semiconductor substrate, such as a P-type silicon substrate, which can have shallow trench isolation (STI) structures formed thereon and define active regions, and various active and passive elements, such as field effect transistors, diodes, memory elements, etc., can be further formed on the active regions. Since the capacitor structure of the present application is preferably formed in the back end of line (BEOL) process, the structures and elements in the front end of line (FEOL) process are not the focus of the present application and are not related to the features of the present application, and for the sake of simplicity of the drawings and the description, these elements will be omitted and only a dielectric layer 100 formed on the semiconductor substrate, such as an intermetal dielectric layer (IMD), will be used to represent the substrate. In the embodiments of the present application, the material of the dielectric layer 100 is preferably a low dielectric constant material (k < 3.0) or silicon oxide, which can be formed on the substrate by spin coating or chemical vapor deposition (CVD) fabrication process.

[0048] Refer to Figure 1A lower electrode material layer 102, forming a capacitor structure, is formed on the dielectric layer 100. In this embodiment, the lower electrode material layer 102 may be a three-layer composite structure, possibly comprising a lower titanium nitride layer 104, an aluminum layer 106, and an upper titanium nitride layer 108, wherein the thickness of the upper and lower titanium nitride layers 104 and 108 is much smaller than that of the middle aluminum layer 106. The composite lower electrode material layer 102 helps to reduce the series resistance of the capacitor and improve its quality factor. In other embodiments, the aluminum layer may also be a copper-aluminum alloy layer, and the titanium nitride layer may also be titanium, tantalum, or tantalum nitride. In some embodiments, the lower electrode material layer 102 may be one of the metal layers in a subsequent fabrication process, preferably a metal layer before the top metal layer, which may be formed on the dielectric layer 100 by physical vapor deposition (PVD) or various chemical vapor deposition (CVD) processes.

[0049] Please refer to the following. Figure 2 After the lower electrode material layer 102 is formed, a photolithography process is then performed to form a patterned photoresist 110 on the lower electrode material layer 102. Using the photoresist 110 as an etching mask, dry etching is performed to pattern the lower electrode material layer 102, forming a lower electrode plate 112, and simultaneously forming multiple grooves 114a on it. It should be noted that in this embodiment of the invention, the width of the grooves 114a on the lower electrode plate 112 is significantly smaller than the width of the grooves 114b surrounding the lower electrode plate 112. In this case, due to the micro-load effect, the depth of the etched grooves 114a will be less than the depth of the grooves 114b. Figure 2 As shown, the groove 114a on the lower electrode plate 112 extends downward through the upper titanium nitride layer 108 to the aluminum layer 106, while the groove 114b around the lower electrode plate 112 further penetrates the lower titanium nitride layer 104 to expose the dielectric layer 100, and even extends into the dielectric layer 100, thereby separating the lower electrode plate 112 from the surrounding lower electrode material layer 102. The above embodiment of the invention utilizes the inherent micro-load effect of the etching process to define the lower electrode plate 112 and simultaneously form the desired groove 114a structure on the lower electrode plate 112 in the same etching process. This method has the advantage over conventional practices in that it reduces the cost of a photomask and etching process, and increases production capacity.

[0050] In other embodiments, such as Figure 11As shown, the recesses 114a on the lower electrode plate 112 can also extend through the aluminum layer 106 to expose the underlying titanium nitride layer 104. This embodiment has the advantage of providing a more uniform depth of the recesses 114a, since in a typical etching process, the etching process has different etching rates for the areas near the center of the wafer and near the edge of the wafer, which can result in a large difference in the depth of the recesses 114a at the center of the wafer and the depth of the recesses 114a at the edge of the wafer. This embodiment takes advantage of the different etching rates of titanium nitride and aluminum, using the titanium nitride layer 104 as an etch stop layer, so that the recesses 114a on the lower electrode plate 112 can be controlled to uniformly extend to the surface of the titanium nitride layer 104, while the micro-loading effect can be used to control the recesses 114b around the lower electrode plate 112 to extend through the titanium nitride layer 104 to the underlying dielectric layer 100 to define the lower electrode plate 112.

[0051] Referring next to FIG. 2, a dielectric layer 100 is formed on the substrate 102. The dielectric layer 100 can be an intermetallic dielectric layer, which is preferably a low dielectric constant material (k < 3.0) or silicon oxide, formed on the substrate by a spin-on or chemical vapor deposition process. The dielectric layer 100 can be formed by a first deposition process to a predetermined thickness, followed by a chemical mechanical polishing (CMP) process to planarize the surface of the dielectric layer 100, and then a second deposition process to achieve the desired thickness of the dielectric layer 100. Figure 3 Referring next to FIG. 3, a photoresist 110 is formed on the dielectric layer 100. The photoresist 110 is then patterned by a photolithography process to form a patterned photoresist 110 on the dielectric layer 100. The patterned photoresist 110 is then used as an etch mask to etch the dielectric layer 100 to form recesses 114a on the lower electrode plate 112. In this embodiment, the etching process can be sputter etching, ion beam etching, or plasma etching, and the recesses 114a formed on the lower electrode plate 112 can include the recesses 114a formed by the previous etching process.

[0052] Figure 4 Referring next to FIG. 4, the photoresist 110 is removed by a standard ashing process and cleaning process. A second dielectric layer 116 is then formed on the lower electrode plate 112. The dielectric layer 116 can be an intermetallic dielectric layer, which is preferably a low dielectric constant material (k < 3.0) or silicon oxide, formed on the substrate by a spin-on or chemical vapor deposition process. The dielectric layer 116 can be formed by a first deposition process to a predetermined thickness, followed by a chemical mechanical polishing (CMP) process to planarize the surface of the dielectric layer 116, and then a second deposition process to achieve the desired thickness of the dielectric layer 116.

[0053] Referring next to FIG. 5, a photoresist 118 is formed on the dielectric layer 116. The photoresist 118 is then patterned by a photolithography process to form a patterned photoresist 118 on the dielectric layer 116. The patterned photoresist 118 is then used as an etch mask to etch the dielectric layer 116 to form a capacitor recess 120 on the lower electrode plate 112. In this embodiment, the etching process can be sputter etching, ion beam etching, or plasma etching, and the capacitor recess 120 formed on the lower electrode plate 112 can include the recesses 114a formed by the previous etching process. Figure 5 ​After the formation of the capacitor recess 120, a photoresist removal process, such as a dry etch process or a wet etch process, is performed to remove the photoresist 118. Then, a conformal capacitor dielectric layer 122 and an upper electrode plate 124 are sequentially formed on the surface of the dielectric layer 116 and the capacitor recess 120. As shown in the figure, the upper electrode plate 124 fills the space in the recess 114a. In other embodiments, the upper electrode plate 124 filling the recess 114a can have voids. In the embodiment of the present application, the capacitor dielectric layer 122 can be formed of a high dielectric constant material, such as aluminum oxide (AI2O3), hafnium oxide (HfO2), silicon oxide (SiO2), silicon nitride (SiN), tantalum pentoxide (Ta2O5), tantalum oxynitride (TaON), titanium oxide (TiO2), zirconium oxide (ZrO2), tetraethoxysilane (TEOS), spin-on-glass (SOG), or fluorine-doped silicon glass (FSG), which can be formed by a PVD, CVD, atomic layer deposition (ALD), or molecular beam epitaxy (MBE) process. The upper electrode plate 124 can be formed of titanium nitride, titanium, tantalum, tantalum nitride, or tungsten, which can be formed on the capacitor dielectric layer 122 by a physical vapor deposition process or various chemical vapor deposition processes. As shown in the figure, in the embodiment of the present application, the electrode area per unit area of the wafer can be significantly increased due to the presence of the recess 114a. The more the number of the recess 114a, the more the electrode area is increased, thereby increasing the overall capacitance of the capacitor structure.

[0054] Referring to FIG. 1C, Figure 6 After the formation of the capacitor dielectric layer 122 and the upper electrode plate 124, an organic planarization layer (OPL) 126 is formed on the upper electrode plate 124. As shown in the figure, the organic planarization layer 126 covers the entire substrate and fills the capacitor recess 120, which provides a flat surface for subsequent processes. The organic planarization layer 126 can be formed of organosiloxane or spin-on-carbon (SOC), which can be formed on the upper electrode plate 124 by a spin-coating process and provides good recess filling effect.

[0055] Referring to FIG. 1C, Figure 7 After the formation of the organic planarization layer 126, a removal process, such as an etch-back process or a chemical mechanical polishing process, is performed to remove a certain thickness of the layer structure. The removal process removes the organic planarization layer 126, the upper electrode plate 124, and the capacitor dielectric layer 122 on the top surface of the dielectric layer 116, thereby defining the capacitor structures. As a result, the edges of the capacitor dielectric layer 122 and the upper electrode plate 124 have vertical extension portions 122a, 124a extending in a direction perpendicular to the top surface of the lower electrode plate 112.

[0056] Finally, please refer to... Figure 8 After separating the individual capacitor structures, the remaining organic planarization layer 126 is removed, and another dielectric layer 128 is deposited over the entire substrate. The fabrication process of the dielectric layer 128 is as follows: Figure 3 The dielectric layer 116 described herein will not be repeated here. Subsequently, contacts 130 are formed in dielectric layers 116 and 128 to connect the upper electrode plate 124 and the lower electrode plate 112 of the capacitor structure, respectively. The steps may include: using the upper electrode plate 124 and the lower electrode plate 112 as etch stop layers, performing a photolithography process to form vias in dielectric layers 116 and 128; then filling the vias with a metal material such as copper, aluminum, titanium, or tungsten to form the contacts 130. After the contacts 130 are formed, a patterned metal layer 132 connecting to the capacitor is formed above dielectric layer 128, thus completing the fabrication of the capacitor structure.

[0057] The above embodiments illustrate the fabrication process of the capacitor structure of the present invention. Based on the above fabrication process, the present invention also proposes a capacitor structure, such as... Figure 8 As shown, it includes a substrate 100, a lower electrode plate 112 located on the substrate 100, wherein the lower electrode plate 112 has a plurality of grooves 114a, a capacitor dielectric layer 122 located on the lower electrode plate 112 and the grooves 114a, and an upper electrode plate 124 located on the capacitor dielectric layer 122, wherein the edges of the capacitor dielectric layer 122 and the upper electrode plate 124 have vertically extending portions 122a and 124a extending in a direction perpendicular to the top surface of the lower electrode plate 112.

[0058] Please refer to the following. Figure 9 and Figure 10 This is a cross-sectional schematic diagram of a capacitor structure and its fabrication steps according to another embodiment of the present invention. In this embodiment, an additional pullback fabrication process can be applied after the groove 114a on the lower electrode plate 112 is formed to change the shape of the groove 114a, thereby further increasing the electrode area. This pullback fabrication process can use a solution with different etching selectivity ratios for aluminum and titanium nitride (e.g., diluted sulfur peroxide (DSP)) to etch the sidewalls 136 of the groove 114a in an immersion manner, making them convex outward in an arc shape. Such an arc-shaped convex groove sidewall 136 can provide a higher electrode area than... Figure 4 The conventional straight groove sidewalls show more electrode area.

[0059] Please refer to the following. Figure 12 This is a cross-sectional schematic diagram of the fabrication steps of a capacitor structure according to yet another embodiment of the present invention. In this embodiment of the present invention, in Figure 4After forming the capacitor recess 120 and before forming the capacitor dielectric layer 122, an additional lower electrode layer 134 can be formed on the surface of the capacitor recess 120. The material of the lower electrode layer 134 can be titanium nitride, titanium, tantalum, tantalum nitride, or tungsten, and it can be formed using physical vapor deposition (PVD) or various chemical vapor deposition (CVD) processes. Thus, as... Figure 12 As shown, similar to the capacitor dielectric layer 122 and the upper electrode plate 124, the lower electrode layer 134 also has a vertically extending portion located on the sidewall of the dielectric layer 116. Compared with the aforementioned embodiment, due to the presence of this vertically extending portion of the lower electrode layer 134, this vertically extending portion can also provide an effective electrode area, further increasing the capacitance value of the overall capacitor structure.

[0060] Please refer to the following. Figure 13 This is an enlarged schematic diagram of a capacitor structure according to yet another embodiment of the present invention. Figure 12 In embodiments where an additional lower electrode layer 134 is formed, it is possible to Figure 7 After separating the individual capacitor structures, an additional etching process is performed to remove portions of the upper electrode plate 124 and the lower electrode layer 134, ensuring that the length of its vertical extension portion 124a and 134a is less than the length of the vertical extension portion 122a of the capacitor dielectric layer 122. Figure 13 As shown, this ensures that the edges of the vertical extensions of the upper electrode plate 124 and the lower electrode layer 134 will not cause component failure due to contact.

[0061] Please refer to the following. Figure 14 This is an enlarged schematic diagram of a capacitor structure according to yet another embodiment of the present invention. Figure 12 In embodiments where an additional lower electrode layer 134 is formed, it is possible to Figure 7 After separating the individual capacitor structures, an additional oxidation process is performed in the next step, causing the tops of the vertically extending portions 124a and 134a of the upper electrode plate 124 and the lower electrode layer 134 to be oxidized into oxidized portions 124b and 134b, respectively. Figure 14 As shown, this ensures that the edges of the vertically extending portions of the upper electrode plate 124 and the lower electrode layer 134 are insulated from each other, thus preventing component failure.

[0062] According to the capacitor structure and manufacturing method described in the above embodiments of the present invention, the special groove is formed by utilizing the inherent micro-load effect of the etching process, and the surface area of ​​the groove can be increased by an additional pull-back process, thereby increasing the overall capacitance value of the capacitor structure. Furthermore, the additional etching or oxidation process gives the resulting MIM capacitor excellent insulation properties, making it an invention with both distinctive and functional characteristics.

[0063] The above merely describes the preferred embodiments of the present application, and any equivalent changes and modifications made according to the claims of the present application shall fall within the scope of the present application.

Claims

1. A method for fabricating a capacitor structure, comprising: forming a lower electrode material layer on a substrate; performing a first photolithography fabrication process to pattern the lower electrode material layer to form a lower electrode plate, wherein the first photolithography fabrication process simultaneously forms a plurality of recesses on the lower electrode plate; forming a dielectric layer on the lower electrode plate; performing a second photolithography fabrication process to remove portions of the dielectric layer to expose portions of the lower electrode plate including the recesses; sequentially forming a capacitor dielectric layer and an upper electrode plate on the lower electrode plate and the surface of the dielectric layer; removing the capacitor dielectric layer and the upper electrode plate on the top surface of the dielectric layer such that the edges of the capacitor dielectric layer and the upper electrode plate have vertically extending portions on the sidewalls of the dielectric layer.

2. The method for fabricating a capacitor structure of claim 1, wherein the step of removing the capacitor dielectric layer and the upper electrode plate on the top surface of the dielectric layer comprises: forming an organic planarization layer on the upper electrode plate; and performing an etch-back fabrication process to remove portions of the organic planarization layer, the upper electrode plate on the top surface of the dielectric layer, and the capacitor dielectric layer.

3. The method for fabricating a capacitor structure of claim 1, wherein the step of removing the capacitor dielectric layer and the upper electrode plate on the top surface of the dielectric layer comprises: forming an organic planarization layer on the upper electrode plate; and performing a chemical mechanical polishing fabrication process to remove portions of the organic planarization layer, the upper electrode plate on the top surface of the dielectric layer, and the capacitor dielectric layer.

4. The method for fabricating a capacitor structure of claim 1, further comprising performing a pull-back fabrication process after forming the recesses such that the sidewalls of the recesses are curved outwardly.

5. The method for fabricating a capacitor structure of claim 1, further comprising forming a lower electrode layer on the surface of the dielectric layer and the lower electrode plate before forming the capacitor dielectric layer, and the step of removing the capacitor dielectric layer and the upper electrode plate on the top surface of the dielectric layer also simultaneously removes the lower electrode layer on the top surface of the dielectric layer such that the edges of the lower electrode layer have vertically extending portions on the sidewalls of the dielectric layer.

6. The method for fabricating a capacitor structure of claim 5, further comprising performing an oxidation fabrication process to oxidize the top ends of the vertically extending portions of the upper electrode plate and the lower electrode layer to form oxidation portions.

7. The method for fabricating a capacitor structure of claim 5, further comprising performing an etching fabrication process to remove portions of the upper electrode plate and the vertically extending portions of the lower electrode layer such that the vertically extending portions of the upper electrode plate and the lower electrode layer have a length less than the length of the vertically extending portions of the capacitor dielectric layer. comprising:

8. A capacitor structure produced by the method of claim 1, wherein a substrate; a lower electrode plate on the substrate, wherein the lower electrode plate has a plurality of recesses; a capacitor dielectric layer on the lower electrode plate; and an upper electrode plate on the capacitor dielectric layer and extending into the recesses, wherein the edges of the capacitor dielectric layer and the upper electrode plate have vertically extending portions that are perpendicular to the top surface of the lower electrode plate and extend away from the recesses. ​ 9. The capacitor structure of claim 8, wherein the bottom electrode plate is a multi-layer structure of a titanium nitride layer - an aluminum layer - a titanium nitride layer, and the recesses extend through the titanium nitride layer to the aluminum layer.

10. The capacitor structure of claim 8, wherein sidewalls of the recesses are curved outwardly.

11. The capacitor structure of claim 8, further comprising a bottom electrode layer disposed on the bottom electrode plate, and the capacitor dielectric layer is disposed between the bottom electrode layer and the top electrode plate.

12. The capacitor structure of claim 11, wherein the bottom electrode layer has a vertically extending portion perpendicular to a top surface of the bottom electrode plate.

13. The capacitor structure of claim 12, wherein a length of the vertically extending portion of the bottom electrode layer is less than a length of the vertically extending portion of the capacitor dielectric layer.

14. The capacitor structure of claim 12, wherein a top end of the vertically extending portion of the bottom electrode layer has an oxidation portion.

15. The capacitor structure of claim 11, wherein the bottom electrode layer is made of titanium nitride or titanium.

16. The capacitor structure of claim 8, wherein a length of the vertically extending portion of the top electrode plate is less than a length of the vertically extending portion of the capacitor dielectric layer.

17. The capacitor structure of claim 8, wherein a top end of the vertically extending portion of the top electrode plate has an oxidation portion.

18. The capacitor structure of claim 8, wherein the capacitor dielectric layer is made of a high dielectric constant material or silicon nitride.

19. The capacitor structure of claim 8, wherein the top electrode plate is made of titanium nitride or titanium.

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