Semiconductor devices

Abstract

Semiconductor device. A semiconductor device is disclosed. The semiconductor device includes: a first slit, at least one word line, and a second slit. The first slit is arranged at a boundary between adjacent memory blocks to isolate the memory blocks from each other, and includes a first outer slit and a second outer slit, the second outer slit being spaced apart from the first outer slit by a predetermined distance in a first direction. The word line is arranged between the first outer slit and the second outer slit, the word line includes a central region having a first end and a second end and an edge region located at the first end and the second end of the central region, the second slit is arranged at the central region, the second slit isolates a region of the word line in the central region on either side of the second slit, wherein the word line is continuous in the edge region.

Description

Technical Field

[0001] Techniques and implementations disclosed herein relate generally to a semiconductor device, and more particularly, to a three-dimensional (3D) semiconductor memory device. Background Art

[0002] A semiconductor device may include a memory cell array having a plurality of memory cells. The memory cell array may include a plurality of memory cells arranged in a structure having different shapes or sizes. For example, in order to increase the integration of the semiconductor device, the memory cells may be arranged three-dimensionally (3D) above the semiconductor substrate. In the manufacturing process of a three-dimensional (3D) semiconductor device, a stacked structure may be formed by stacking a plurality of material films. Summary of the invention

[0003] Various embodiments of the disclosed technology are directed to a semiconductor device having reduced word line resistance in which edge portions of word lines are merged.

[0004] In one aspect of the disclosed technology, a semiconductor device may include: a first slit, which is arranged at a boundary between adjacent memory blocks to isolate the memory blocks from each other, and includes a first outer slit and a second outer slit, the second outer slit being spaced apart from the first outer slit by a predetermined distance in a first direction; at least one word line, which is arranged between the first outer slit and the second outer slit, the at least one word line including a central region having a first end and a second end, and an edge region located at the first end and the second end of the central region; and a second slit, which is arranged at the central region, the second slit isolates a region of the word line in the central region on either side of the second slit, wherein the word line is continuous in the edge region.

[0005] In another aspect of the disclosed technology, a semiconductor device may include a plurality of first slits disposed at boundary regions of adjacent memory blocks to isolate the memory blocks from each other and disposed to be spaced a predetermined distance apart from each other in a first direction; at least one word line disposed between the first slits disposed in a quadrilateral; at least one drain selection line disposed above the word line; and a plurality of isolation patterns disposed to isolate fragments of at least one drain selection line into block units, wherein at least one word line is integrated into a single structure.

[0006] In another aspect of the disclosed technology, a semiconductor device may include: a source selection line disposed above a substrate; a plurality of word lines vertically stacked above the source selection line; a drain selection line stacked above the plurality of word lines; a slit defined in a central region of the plurality of word lines, the slit vertically penetrating the source selection line, the plurality of word lines, and the drain selection line, and the slit isolates the source selection line, the plurality of word lines, and the drain selection line from one another in the central region; and a plurality of isolation patterns spaced apart from one another by a predetermined distance in an edge region of the plurality of word lines and dividing the drain selection line into a plurality of isolation segments.

[0007] It is to be understood that both the foregoing general description and the following detailed description of the technology disclosed herein are exemplary and explanatory and are intended to provide further explanation of the scope of the disclosure to those skilled in the art. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other features and advantageous aspects of the disclosed technology will become apparent with reference to the following detailed description considered in conjunction with the accompanying drawings.

[0009] Figure 1A and Figure 1B is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 2 It is an example Figure 1A and Figure 1B A cross-sectional view of the peripheral circuit structure shown in .

[0011] Figure 3 is a schematic diagram illustrating a layout structure of a semiconductor device according to one embodiment of the disclosed technology.

[0012] Figure 4 is an example of an embodiment of the disclosed technology. Figure 3 A plan view of a word line structure used in a memory block of a semiconductor device shown in FIG.

[0013] Figure 5 is a schematic diagram illustrating a layout structure of a semiconductor device according to another embodiment of the disclosed technology.

[0014] Figure 6 is an example of another embodiment according to the disclosed technology. Figure 5 A plan view of a word line structure used in a memory block of a semiconductor device shown in FIG.

[0015] Fig. 7A and Figure 7B It is an example Figure 3 and Figure 4 A cross-sectional view of a semiconductor device shown in FIG.

[0016] FIG. 8A to FIG. 8D is an example for forming Fig. 7A sectional view of the manufacturing process of the structure shown in FIG.

[0017] 9A to 9D is an example for forming Figure 7B sectional view of the manufacturing process of the structure shown in FIG.

[0018] Fig.10 is a schematic diagram illustrating a layout structure of a semiconductor device according to still another embodiment of the disclosed technology.

[0019] Fig.11 is a diagram illustrating another embodiment of the disclosed technology. Fig.10 A plan view of a word line structure used in the semiconductor device shown in FIG.

[0020] Fig.12 This is a diagram illustrating another embodiment of the disclosed technology. Fig.10 A cross-sectional view of a semiconductor device shown in FIG.

[0021] FIG. 13A to FIG. 13C is an example of another embodiment according to the disclosed technology Fig.12 A cross-sectional view of the structure shown in FIG.

[0022] List of reference numerals:

[0023] SLIT1: Multiple first slits

[0024] SLIT2: Second Slit

[0025] DSM1 to DSM3: Multiple isolation patterns

[0026] DSL1 to DSL4: Multiple drain select lines DETAILED DESCRIPTION

[0027] The patent document provides implementations and examples of semiconductor devices that substantially solve one or more problems associated with limitations or disadvantages of the related art. Some implementations of the disclosed technology propose a semiconductor device capable of reducing word line resistance by merging edge portions of word lines. The disclosed technology provides various implementations of semiconductor devices capable of improving performance or throughput by reducing word line resistance.

[0028] Reference will now be made in detail to various aspects of the disclosed technology, implementations and examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used throughout the drawings to refer to the same or like parts.

[0029] In connection with the embodiments of the disclosed technology, specific structural and functional descriptions are disclosed only for exemplary purposes. These embodiments represent a limited number of possible embodiments. However, the embodiments of the disclosed technology can be implemented in various or different ways without departing from the scope or spirit of the disclosed technology.

[0030] When describing the disclosed technology, the terms "first" and "second" may be used to describe multiple components, but these components are not limited in quantity or order by the terms. These terms may be used to distinguish one component from another component. For example, a first component may be referred to as a second component, and a second component may be referred to as a first component without departing from the scope of the present disclosure.

[0031] The terms used in the present application are only used to describe specific embodiments and are not intended to limit the disclosed technology. Unless clearly stated otherwise, a singular expression may include a plural expression.

[0032] Unless otherwise defined, all terms (including technical or scientific terms) used herein have the same meanings as understood by those skilled in the art. Terms defined in general dictionaries may be analyzed to have the same meanings as in the context of the relevant field, and unless clearly defined in this application, they should not be analyzed to have ideal meanings or overly formal meanings. The terms used in the disclosed technology are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0033] Figure 1A and Figure 1B is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0034] Reference Figure 1A and Figure 1B , each semiconductor device may include a peripheral circuit structure (PC) and a cell array (CAR) disposed over a substrate (SUB).

[0035] The substrate (SUB) may be a single crystal semiconductor film. For example, the substrate (SUB) may be any one of a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a germanium-on-insulator (GOI) substrate, and a silicon-germanium substrate, or an epitaxial thin film formed by a selective epitaxial growth (SEG) process.

[0036] The cell array (CAR) may include a plurality of memory blocks. Each memory block may include a plurality of cell strings. Each cell string may be electrically connected to a bit line, a source line, a word line, and a select line. Each cell string may include memory cells connected in series with each other and select transistors connected in series with each other. Each select line may be used as a gate of a corresponding select transistor, and each word line may be used as a gate of a corresponding memory cell.

[0037] The peripheral circuit structure (PC) may include NMOS and PMOS transistors, resistors and capacitors electrically coupled to the cell array (CAR). The NMOS and PMOS transistors, resistors and capacitors may be used as constituent elements of a row decoder, a column decoder, a page buffer and a control circuit.

[0038] Reference Figure 1A , the peripheral circuit structure (PC) may be disposed on a region of the substrate (SUB) that does not overlap with the cell array (CAR).

[0039] Alternatively, if Figure 1B As shown, the peripheral circuit structure (PC) can be arranged between the cell array (CAR) and the substrate (SUB). In this example, the peripheral circuit structure (PC) is formed to overlap with the cell array (CAR), so that the size of the substrate (SUB) area occupied by both the cell array (CAR) and the peripheral circuit structure (PC) can be reduced. In other embodiments of the disclosed technology, the cell array (CAR) can be arranged between the substrate (SUB) and the peripheral circuit structure (PC).

[0040] Figure 2 It is an example Figure 1A and Figure 1B A cross-sectional view of the peripheral circuit structure (PC) shown. Figure 2 The peripheral circuit structure (PC) shown can be included or arranged in Figure 1A The peripheral circuit structure (PC) shown in the figure may be included or arranged in Figure 1B In the peripheral circuit structure (PC) shown.

[0041] Reference Figure 2 , the peripheral circuit structure (PC) may include a peripheral gate (PG), a peripheral gate insulating film (PGI), a junction (Jn), a peripheral circuit line (PCL), a peripheral contact plug (PCP) and a peripheral circuit insulating film (PIL).

[0042] The peripheral gate (PG) may be used as a gate of an NMOS or PMOS transistor of the peripheral circuit structure (PC). A peripheral gate insulating film PGI may be provided between the substrate (SUB) and each peripheral gate (PG).

[0043] The junction (Jn) may be defined by implanting N-type or P-type impurities into the active region of the substrate (SUB). For example, the junction (Jn) may be disposed on both sides or opposite sides of each peripheral gate (PG) so that the junction (Jn) may be used as a source junction and a drain junction. The active region of the substrate (SUB) may be separated by a device isolation layer (ISO) formed in the substrate (SUB). The device isolation layer (also referred to as a device isolation film) may be formed of an insulating material.

[0044] The peripheral circuit line (PCL) may be electrically coupled to a circuit of the peripheral circuit structure (PC) through a peripheral contact plug (PCP).

[0045] The peripheral circuit insulating film (PIL) may be formed to cover the circuits of the peripheral circuit structure (PC), the peripheral circuit line (PCL), and the peripheral contact plug (PCP). The peripheral circuit insulating film (PIL) may include or be formed of insulating films stacked in a multi-layer structure.

[0046] Figure 3 is a schematic diagram illustrating a layout structure of a semiconductor device according to one embodiment of the disclosed technology. Figure 4 is a plan view illustrating a word line (WL) structure used in a plan view Figure 3 In the memory block BLK of the semiconductor device shown in FIG. Figure 3 Compared to the structure shown, Figure 4 The structure shown does not include upper drain selection lines DSL1 to DSL4, but includes a plan view of word lines (WL). For ease of description and better understanding of the disclosed technology, Figure 3 and Figure 4 An interlayer insulating film (ie, a layer between word lines) is not illustrated.

[0047] Reference Figure 3 and Figure 4 , a semiconductor device according to an embodiment of the disclosed technology may include a plurality of first slits ( SLIT1 ) (including first outer slits and second outer slits) and second slits ( SLIT2 ) formed over a substrate (not shown). Figure 3 A plurality of isolation patterns DSM1 , DSM2 , and DSM3 and a plurality of drain selection lines DSL1 to DSL4 are illustrated. Figure 4 Word lines WL_U and WL_D and a vertical channel (CH) are illustrated. For ease of description and better understanding of the disclosed technology, it is assumed that Figure 3 and Figure 4 Each of the semiconductor devices shown includes only one memory block BLK among a plurality of memory blocks.

[0048] In a three-dimensional (3D) memory device, slits configured to pass through word lines (WL) may be formed to isolate stacked word lines (WL) from each other in units of a memory block BLK.

[0049] For example, a plurality of first slits (SLIT1) may be formed on both sides or opposite sides of a memory block BLK. The first slits (SLIT1) may be disposed at a boundary region between adjacent memory blocks (BLK) so that the first slits (SLIT1) may isolate adjacent memory blocks (BLK) from each other. The first slits (SLIT1) may be formed to penetrate a conductive film (not shown) so that the conductive films are isolated from each other in units of memory blocks BLK. In an example, the conductive film may include word lines WL_U and WL_D.

[0050] The first slits (SLIT1) may be disposed on both sides or opposite sides of the structure including the word lines WL_U and WL_D. For example, the first slits (SLIT1) may be spaced apart in the Y-axis direction to be located on opposite sides of the structure including the word lines WL_U and WL_D. Figure 3 As shown, one first slit (SLIT1) may be disposed at one side of the drain selection line DSL1 with respect to the Y axis. Another first slit (SLIT1) may be disposed at the other side of the drain selection line DSL4 with respect to the Y axis direction. In addition, each of the first slits (SLIT1) may be formed in a line shape extending in the X axis direction.

[0051] An insulating film (not shown) may be formed between each first slit (SLIT1) and each word line WL_U and WL_D. For example, the insulating film may include a nitride film or an oxide film. Each of the first slits (SLIT1) may operate as a support for supporting the word lines WL_U and WL_D. Each first slit (SLIT1) may include a metal material. For example, each first slit (SLIT1) may include tungsten (W).

[0052] The second slit (SLIT2) may be disposed at or near a central region (C) of a structure including word lines WL_U and WL_D. For example, the second slit (SLIT2) may be disposed so that the second slit (SLIT2) passes through the central region of the stacked word lines WL_U and WL_D. The second slit (SLIT2) may be formed in a line shape extending in the X-axis direction. The length of the second slit (SLIT2) in the X-direction may be shorter than that of each first slit (SLIT1), and may completely overlap with each first slit (SLIT1).

[0053] Each memory block BLK may include a plurality of drain selection lines DSL1 to DSL4. The drain selection lines DSL1 to DSL4 may be formed over the word lines WL_U and WL_D. The drain selection lines DSL1 to DSL4 may be spaced apart from each other by a predetermined distance or interval in the Y-axis direction.

[0054] The drain selection lines DSL1 to DSL4 may be arranged symmetrically with each other across the second slit (SLIT2). For example, the drain selection lines DSL1 and DSL2 may be mirror images of the drain selection lines DSL4 and DSL3, respectively, across a plane centered on the second slit (SLIT2) and perpendicular to the top surface of the substrate. The drain selection lines DSL2 and DSL3 may be isolated from each other by the isolation pattern DSM3.

[0055] The isolation pattern DSM1 may be formed between the drain selection line DSL1 and the drain selection line DSL2. The isolation pattern DSM2 may be formed between the drain selection line DSL3 and the drain selection line DSL4. Each of the isolation patterns DSM1 and DSM2 may be formed in a line shape extending in the X-axis direction.

[0056] The isolation pattern DSM3, together with the second slit (SLIT2), can isolate the drain selection line DSL2 and the drain selection line DSL3 from each other. Each of the isolation patterns DSM3 can be formed in a line shape extending in the X-axis direction. In an embodiment, the length of each of the isolation patterns DSM3 can be shorter than the second slit (SLIT2). The isolation pattern DSM3 can be formed or positioned to traverse the edge regions EL and ER at either end of the second slit (SLIT2). The isolation pattern DSM3 can be disposed at both ends of the second slit (SLIT2) and spaced apart in the X-axis direction. The isolation patterns DSM1, DSM2, and DSM3 can isolate the drain selection lines DSL1 to DSL4 from each other in the cells within the memory block BLK.

[0057] Each memory block BLK may include a vertical channel (CH) formed to penetrate the word lines WL_U and WL_D in a vertical direction (ie, in a direction perpendicular to the XY plane). The vertical channel (CH) may be used to implement a plurality of cell strings. The cell strings of the memory block BLK may electrically interconnect the memory cells of the semiconductor device through the vertical channel (CH).

[0058] In the cell array CAR, the memory block BLK may include a word line structure including word lines WL_U and WL_D disposed between the first slit (SLIT1). The second slit (SLIT2) may be formed in the central region (C) of the word line structure and extend in the X direction. The second slit (SLIT2) may also extend through the word line structure in the vertical direction to reach the substrate SUB. The region of the word line structure at the end of the second slit (SLIT2) may be designated as a left edge region (EL) and a right edge region (ER). The left edge region (EL) and the right edge region (ER), together with the second slit (SLIT2), may divide the word line structure into a word line WL_U on one side of the second slit (SLIT2) and a word line WL_D on the other side of the second slit (SLIT2). Therefore, the word line (WL_U) and the word line (WL_D) are spaced apart in the Y-axis direction relative to the center region (C), and may be thicker in the Y-axis direction relative to the center region (C) than the left edge region (EL) and the right edge region (ER).

[0059] In other words, the memory block BLK may be divided into one half block and the other half block by the second slit (SLIT2) and the left edge region (EL) and the right edge region (ER). That is, the upper word line (WL_U) arranged in the Y-axis direction relative to the center region (C) may correspond to one half block, and the lower word line (WL_D) may correspond to the other half block.

[0060] The upper half block corresponding to the upper word line (WL_U) may include drain selection lines DSL1 and DSL2 isolated from each other by an isolation pattern DSM1. The lower half block corresponding to the lower word line (WL_D) may include drain selection lines DSL3 and DSL4 isolated from each other by an isolation pattern (DSM2). Therefore, in the example, one memory block BLK may be divided into a total of 4 quarter blocks corresponding to the drain selection lines DSL1 to DSL4, respectively. The drain selection lines DSL1 to DSL4 and the four quarter blocks may operate independently of each other.

[0061] In some implementations of the disclosed technology, the left edge region (EL) and the right edge region (ER) of the word line structure connect the upper word line WL_U and the lower word line WL_D together. In other words, although the central region (C) of the word line (WL) is isolated by the second slit (SLIT2), in the edge regions EL and ER, the word lines can be merged together to avoid isolation. As described above, the upper word line WL_U and the lower word line WL_D can be merged with each other in the two edge regions EL and ER, thereby reducing the resistance of the word line (WL) compared to the word line structure in which the word lines are merged only in one edge region.

[0062] For example, if a memory chip and a logic circuit chip are stacked in a 3D semiconductor memory device, the edge regions EL and ER of the word line (WL) can be isolated from each other by the second slit (SLIT2). In this case, during the programming operation time of the semiconductor memory device, the channel capacitance of the unselected cell string can be reduced, so that the RC load (RC delay) can be increased. Therefore, the edge regions EL and ER according to the present embodiment can be merged with each other so that the final edge region can be realized in a tied edge shape, thereby reducing the resistance of the word line (WL).

[0063] Figure 5 is a schematic diagram illustrating a layout structure of a semiconductor device according to another embodiment of the disclosed technology. Figure 6 is an example of Figure 5 A plan view of a word line structure used in a memory block BLK of a semiconductor device shown in FIG. Figure 5 and Figure 6 In order to facilitate description and better understand the disclosed technology, the above described Figure 3 and Figure 4 The same or similar components are referred to by the same components, and therefore, redundant items will be omitted here for the sake of brevity.

[0064] Reference Figure 5 and Figure 6 , the second slit (SLIT2) may be disposed at the central region (C) of the word line (WL). The second slit (SLIT2) may be disposed above a through-region (T) for isolating the upper word line WL_U and the lower word line WL_D from each other.

[0065] The drain selection lines DSL1 to DSL4 may be formed symmetrically with respect to each other with the second slit (SLIT2) interposed therebetween. The shape structure is formed. The shaped structures are mirrored or face each other with respect to the through region (T). The drain selection line DSL2 and the drain selection line DSL3 may be isolated from each other by the isolation pattern DSM3.

[0066] The isolation pattern DSM3 may isolate the drain selection line DSL2 and the drain selection DSL3 from each other. In an example, the isolation pattern DSM3 may be coupled to the through region (T) in a region overlapping an end of the second slit (SLIT2). The isolation pattern DSM3 may be coupled to both ends of the second slit (SLIT2).

[0067] The upper word line WL_U and the lower word line WL_D may be formed in a quadrilateral band shape in which a through region (T) is formed at or near a central region (C). A second slit (SLIT2) may be formed in the through region (T). The thickness of an upper word line WL_U and a lower word line WL_D relative to the through region (T) may be greater than the thickness of a left edge region EL and a right edge region ER relative to the through region (T). In the through region (T), an insulating film may be formed between the second slit (SLIT2) and each word line WL_U and WL_D. As an example, the insulating film may include a nitride film or an oxide film.

[0068] Fig. 7A and Figure 7B It is an example Figure 3 and Figure 4 A cross-sectional view of a semiconductor device shown.

[0069] Fig. 7A is an example of Figure 3 and Figure 4 The cross-sectional view of the semiconductor device is taken along line AA′. Figure 7B is an example of Figure 3 and Figure 4 BB′ is a cross-sectional view of a semiconductor device. For ease of description, it should be noted that Figure 3 and Figure 4 Compared with the components shown, Fig. 7A and Figure 7B Only some of the main necessary elements are illustrated. In order to facilitate description and better understand the disclosed technology, Fig. 7A and Figure 7B The interlayer insulating film is not shown.

[0070] Reference Fig. 7A , the semiconductor device may include a source selection line SSL, a plurality of word lines (WL), and a drain selection line (DSL) vertically stacked over a substrate 101. The source selection line SSL, the plurality of word lines (WL), and the drain selection line DSL may be spaced apart from each other by a predetermined distance or pitch in an extension direction of a vertical channel (CH), and may be stacked over the substrate 101.

[0071] A vertical channel (CH) may be formed to penetrate the source select line SSL, a plurality of word lines (WL), and the drain select line DSL to reach the substrate 101. One end of the vertical channel (CH) may be coupled to a corresponding bit line (not shown) through a bit line contact plug (not shown).

[0072] A plurality of word lines (WL) may be stacked in a multi-layer structure surrounding the vertical channel (CH). A drain select line DSL may be disposed above the plurality of word lines (WL). A source select line SSL may be disposed below the plurality of word lines (WL).

[0073] In an example, the drain selection line DSL may be coupled to the gate of a corresponding drain selection transistor (not shown). The word lines (WL) may be coupled to the gates of memory cells (not shown) corresponding thereto, respectively. The source selection line SSL may be coupled to the gate of a source selection transistor (not shown).

[0074] from Fig. 7A It can be seen that in the central area (C) of the memory block BLK, the drain selection line DSL can be divided into a predetermined number of sections corresponding to the number of cell blocks (e.g., a quarter block). For example, the drain selection line DSL can be divided into four sections by the isolation pattern DSM1, the second slit (SLIT2), and the isolation pattern DSM2.

[0075] exist Fig. 7A , the memory block BLK is divided by the second slit ( SLIT2 ), and similarly, the source selection line SSL is also divided by the second slit ( SLIT2 ).

[0076] exist Figure 7B In the left edge region EL of the memory block BLK, the drain selection line DSL may be divided into a predetermined number of sections corresponding to the number of cell blocks (e.g., a quarter block). That is, the drain selection line DSL may be divided into four sections by the isolation pattern DSM1, the isolation pattern DSM3, and the isolation pattern DSM2.

[0077] However, with Fig. 7A In comparison, Figure 7B At the left edge region EL of the word line structure in FIG. 1 , the word lines (WL) are not isolated from each other by the second slit (SLIT2) in the single memory block BLK. Similarly, the source selection line SSL is not divided into isolation sections by the second slit (SLIT2) in the memory block BLK. Since the source selection line SSL is not isolated, the number of mask processes required to isolate the source selection line SSL can be reduced.

[0078] As described above, the second slit (SLIT2) does not extend through the edge regions EL and ER, and the word lines WL_U and WL_D may be coupled to each other in the edge regions EL and ER. However, in some embodiments, the isolation pattern DSM3 is coupled to the second slit (SLIT2) in the edge regions EL and ER, thereby being able to isolate the drain select line DSL.

[0079] FIG. 8A to FIG. 8D is an example for forming Fig. 7A A cross-sectional view of the manufacturing process of the structure shown. 9A to 9D is an example for forming Figure 7BThe manufacturing process of the structure shown in FIG. 8A to 9D The interlayer insulating film is omitted.

[0080] Reference Fig. 8A and Fig.9A , a source select line SSL, a plurality of word lines (WL), and a drain select line DSL may be sequentially stacked over the substrate 101 .

[0081] Reference Figure 8B and Fig. 9B , the drain select line DSL, the plurality of word lines (WL), and the source select line SSL may be etched to a predetermined depth to expose the substrate 101, thereby forming a channel hole (not shown). The channel hole (not shown) may be filled with a channel structure to form a vertical channel (CH) extending through the drain select line DSL, the plurality of word lines (WL), and the source select line SSL.

[0082] After that, from Figure 8C It can be seen that the central area (C) of the drain select line DSL, the plurality of word lines (WL), and the source select line SSL is etched to form a trench (not shown). The trench (not shown) may be filled with an insulating film to form a second slit (SLIT2) that isolates the drain select line DSL, the plurality of word lines (WL), and the source select line SSL from each other.

[0083] On the contrary, Fig. 9C In the process, the second slit (SLIT2) is not formed in the edge regions EL and ER of the word line (WL). Figure 8C During the etching process of the trench (not shown) shown in FIG. 1 , the central region (C) of the drain select line DSL, the plurality of word lines (WL), and the source select line SSL is etched. However, in the edge regions EL and ER, as shown in FIG. Fig. 9C As shown, the drain select line DSL, a plurality of word lines (WL), and the source select line SSL may not be etched.

[0084] Then, from Fig.8D It can be seen that in the central area (C), isolation patterns DSM1 and DSM2 may be formed so that segments of the drain select line DSL are isolated from each other. In this case, when isolating the drain select lines DSL from each other, a drain select line (DSL) separation mask (DSM) process may be used.

[0085] That is, a mask film (not shown) is formed over the stacked structure and then patterned by a photolithography process. Subsequently, the stacked structure can be etched by an etching process using the mask film as an etching stopper, thereby forming isolation patterns DSM1 and DSM2. As a result, the drain selection lines DSL can be isolated from each other.

[0086] Reference Fig.9D In the edge regions EL and ER, isolation patterns DSM1, DSM3, and DSM2 may be formed so that segments of the drain select line DSL are isolated from each other. However, in the edge regions EL and ER, a plurality of word lines (WL) and a source select line SSL are not etched.

[0087] Fig.10 is a schematic diagram illustrating a layout structure of a semiconductor device according to still another embodiment of the disclosed technology. Fig.11 is an example of the Fig.10 FIG. 1 is a plan view of a word line (WL) structure in a memory block BLK of a semiconductor device shown in FIG. Fig.10 and Fig.11 For the convenience of description, the Figure 3 and Figure 4 The same constituent elements in the embodiment of the present invention are used, and hereinafter, Figure 3 and Figure 4 The differences in the structures shown are centered on the Fig.10 and Fig.11 In order to more easily identify and better understand the disclosed technology, Fig.10 and Fig.11 The interlayer insulating film is not shown.

[0088] Reference Fig.10 and Fig.11 According to another embodiment of the disclosed technology, a semiconductor device may include: a plurality of first slits (SLIT1) formed above a substrate (not shown); a plurality of isolation patterns DSM1, DSM2, and DSM3; a plurality of drain selection lines DSL1 to DSL4; a word line (WL); and a plurality of vertical channels (CH).

[0089] Fig.10 and Fig.11 The embodiment of exemplifies a word line structure in which word lines (WL) are merged into one structure so that a plate structure can be implemented. As an example, in a plan view, the word line (WL) may have a straight line shape.

[0090] and Figure 3 and Figure 4 Compared with the implementation method, Fig.10 and Fig.11 The word line (WL) shown in FIG. 1 may not include the second slit (SLIT2). Figure 3 and Figure 4Compared to the embodiment of the present invention, the isolation pattern DSM3 may be formed to extend in the X-axis direction. The isolation pattern DSM3 may be formed to extend in the X-axis direction similarly to the isolation patterns DSM1 and DSM2. The isolation pattern DSM3 may be formed to extend in the X-axis direction to cross the word line (WL).

[0091] The memory block BLK may include a plurality of drain selection lines DSL1 to DSL4. The drain selection lines DSL1 to DSL4 may be formed above the word lines (WL). The drain selection lines DSL1 to DSL4 may be spaced apart from each other by a predetermined distance or pitch in the Y-axis direction. Each of the drain selection lines DSL1 to DSL4 may be formed in a line shape extending in the X-axis direction.

[0092] Fig.12 It is an example Fig.10 In order to facilitate description and better understand the disclosed technology, Fig.12 The interlayer insulating film is not shown.

[0093] Reference Fig.12 , word lines (WL) can be integrated into a single structure without isolation from each other. Fig.10 The cross-sectional view of the semiconductor device taken along line CC′ shown in FIG. Fig.10 The cross-sectional view of the semiconductor device taken along line DD′ shown in FIG.

[0094] Reference Fig.12 , the semiconductor device may include a source selection line SSL, a plurality of word lines (WL), and a drain selection line DSL vertically stacked above a substrate 101. In other words, the source selection line SSL, the word line (WL), and the drain selection line DSL may be spaced apart from each other by a predetermined distance in an extension direction of a vertical channel (CH), and then may be stacked on the substrate 101.

[0095] A vertical channel (CH) may be formed to penetrate the source selection line SSL, a plurality of word lines (WL), and the drain selection line DSL in a direction perpendicular to the surface of the substrate 101. One end of the vertical channel (CH) may be coupled to a corresponding bit line (not shown) through a bit line contact plug (not shown).

[0096] A plurality of word lines (WL) may be stacked in the form of a multilayer structure surrounding the vertical channel (CH) (together with an interlayer insulating film not shown). A drain select line DSL may be disposed above the plurality of word lines (WL). A source select line SSL may be disposed below the plurality of word lines (WL).

[0097] from Fig.12It can be seen that in the entire area (i.e., the central area and the edge area) of the memory block BLK, the drain selection line DSL can be divided into a predetermined number of sections corresponding to the number of cell blocks (e.g., a quarter block). For example, the drain selection line DSL can be divided into four sections by the isolation pattern DSM1, the isolation pattern DSM3, and the isolation pattern DSM2.

[0098] Therefore, the word lines (WL) may be formed in an integrated structure without forming an isolation region so that the word lines (WL) are not isolated from each other in a single memory block BLK. Likewise, the source select lines SSL are also not isolated in a single memory block BLK.

[0099] FIG. 13A to FIG. 13C is an example of another embodiment according to the disclosed technology Fig.12 Schematic diagram of the manufacturing process of the semiconductor device shown in FIG. In order to facilitate description and better understand the disclosed technology, FIG. 13A to FIG. 13C An interlayer insulating film is not illustrated.

[0100] from Fig.13A It can be seen that the source selection line SSL, a plurality of word lines (WL) and the drain selection line DSL may be sequentially stacked on the substrate 101. Fig. 13B It can be seen that the drain select line DSL, the plurality of word lines (WL), and the source select line SSL may be etched to a predetermined depth to expose the substrate 101, thereby forming a channel hole (not shown). The channel hole (not shown) may be filled with a channel structure to form a vertical channel (CH) extending through the drain select line DSL, the plurality of word lines (WL), and the source select line SSL.

[0101] Then, from Fig. 13C It can be seen that the drain select line (DSL) can be etched, and isolation patterns DSM1, DSM3, and DSM2 can be formed so that segments of the drain select line (DSL) can be isolated from each other. In this case, when the segments of the drain select line DSL are isolated from each other, a DSL (drain select line) separation mask (DSM) process can be used as needed.

[0102] According to an embodiment of the disclosed technology, a plurality of word lines (WL) and a source select line SSL are not isolated from each other, so that the number of mask processes required to isolate the source select line SSL and the plurality of word lines (WL) from each other can be reduced.

[0103] As is apparent from the above description, a semiconductor device based on an embodiment of the disclosed technology can improve its performance or throughput by reducing the resistance of a word line.

[0104] Those skilled in the art will appreciate that, without departing from the spirit and essential features of the present disclosure, embodiments may be implemented in other specific ways other than those set forth herein. Therefore, the above embodiments are interpreted as exemplary and non-restrictive in all respects. The scope of the present disclosure should be determined by the attached claims and their legal equivalents, rather than by the above description. In addition, all variations falling within the meaning and equivalent scope of the attached claims are intended to be included in the present invention. In addition, those skilled in the art will appreciate that claims that are not explicitly referenced to each other in the attached claims may be combined to present an embodiment, or included as a new claim by subsequent amendments after submitting an application.

[0105] Although a number of exemplary embodiments have been described, it will be appreciated that those skilled in the art may devise many other modifications and embodiments that will fall within the spirit and scope of the principles of the present disclosure. In particular, a variety of variations and modifications may be made in the components and / or arrangements within the scope of the present disclosure, the drawings, and the appended claims. In addition to variations and modifications in the components and / or arrangements, alternative uses will also be apparent to those skilled in the art.

[0106] CROSS-REFERENCE TO RELATED APPLICATIONS

[0107] This patent application claims the benefit of Korean Patent Application No. 10-2020-0013092, filed on February 4, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor device, comprising: a first slit provided at a boundary between adjacent memory blocks to isolate the memory blocks from each other and including a first outer slit and a second outer slit spaced apart from the first outer slit by a predetermined distance in a first direction; a word line disposed between the first outer slit and the second outer slit, the word line including a central region having a first end and a second end and edge regions at the first end and the second end of the central region; a second slit disposed at the central region, the second slit isolating a region of the word line in the central region on either side of the second slit; a plurality of drain selection lines disposed between the first outer slit and the second outer slit and disposed to be spaced apart from each other by a predetermined distance with respect to the first direction; as well as a first isolation pattern, wherein the first isolation pattern isolates a first drain selection line and a second drain selection line from among the plurality of drain selection lines, respectively; The word lines are continuous in the edge region.

2. The semiconductor device according to claim 1, wherein The first outer slit and the second outer slit are disposed at opposite sides of the word line with respect to the first direction, and extend in a second direction.

3. The semiconductor device according to claim 1, wherein The length of the second slit in the second direction is shorter than the length of each of the first outer slit and the second outer slit.

4. The semiconductor device according to claim 1, wherein Each of the plurality of drain selection lines extends in the second direction.

5. The semiconductor device according to claim 1, wherein The first isolation pattern extends in the second direction.

6. The semiconductor device according to claim 1, wherein The first isolation pattern is disposed above an upper word line, and the upper word line is disposed at one side of the central region in the first direction.

7. The semiconductor device according to claim 1, further comprising: A second isolation pattern is provided to isolate a third drain selection line and a fourth drain selection line from among the plurality of drain selection lines.

8. The semiconductor device according to claim 7, wherein: The second isolation pattern extends in a second direction.

9. The semiconductor device according to claim 7, wherein: The second isolation pattern is disposed above a lower word line disposed at the other side of the central region in the first direction.

10. The semiconductor device according to claim 1, further comprising: a third isolation pattern, wherein the third isolation pattern isolates the second drain selection line and the third drain selection line from among the plurality of drain selection lines; Wherein, the third isolation pattern is arranged to cross the edge region.

11. The semiconductor device according to claim 10, wherein The third isolation pattern extends in the second direction.

12. The semiconductor device according to claim 1, wherein The word line is defined as a straight line layer having the second slit in the center region in a direction perpendicular to an upper surface of the substrate.

13. A semiconductor device, comprising: a plurality of first slits disposed at boundary regions of adjacent memory blocks, isolating the memory blocks from each other, and disposed to be spaced apart from each other by a predetermined distance in a first direction; a word line disposed between the plurality of first slits disposed in a quadrilateral; a drain selection line, the drain selection line being arranged above the word line; a source selection line disposed above the substrate and below the word line; a plurality of isolation patterns, the plurality of isolation patterns being configured to isolate each segment of the drain selection line into a block unit, wherein the word line and the source selection line are integrated into one on a plane and have a single plate structure, The plurality of isolation patterns extend longer than the word lines in a second direction intersecting the word lines.

14. The semiconductor device according to claim 13, wherein: The plurality of isolation patterns include: a first isolation pattern, the first isolation pattern crossing a central region of the word line; a second isolation pattern arranged in the first direction relative to the first isolation pattern, and a third isolation pattern, the third isolation pattern being arranged opposite to the second isolation pattern in a first direction relative to the first isolation pattern, The first isolation pattern, the second isolation pattern, and the third isolation pattern isolate segments of the drain selection line from each other.

15. The semiconductor device according to claim 14, wherein: The first isolation pattern extends in the second direction and is longer than each of the second isolation pattern and the third isolation pattern in the second direction.

16. A semiconductor device, comprising: A source selection line disposed above the substrate; a plurality of word lines, the plurality of word lines being vertically stacked above the source select line; a plurality of drain select lines stacked above the plurality of word lines; a slit defined in a central region of the plurality of word lines, the slit vertically penetrating the source selection line, the plurality of word lines, and the plurality of drain selection lines, and the slit isolating the source selection line, the plurality of word lines, and the plurality of drain selection lines from each other in the central region; as well as a plurality of isolation patterns which are spaced apart from each other by a predetermined distance in edge regions of the plurality of word lines and divide the plurality of drain selection lines into a plurality of isolation segments, wherein each of the plurality of isolation patterns extends in the same direction as the slit and penetrates the plurality of drain selection lines, and wherein each of the plurality of word lines is continuous in the edge region, The plurality of isolation patterns are arranged symmetrically to each other in the second direction across a plane centered on the slit.

17. The semiconductor device according to claim 16, further comprising: A vertical channel vertically penetrates the source selection line, the plurality of word lines, and the plurality of drain selection lines.

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