Three-dimensional semiconductor memory device and manufacturing method thereof

Abstract

Disclosed are a three-dimensional semiconductor memory device and a method for manufacturing the same. The three-dimensional semiconductor memory device includes a substrate having a cell and a connection region. An electrode structure is disposed on the substrate, and the electrode structure has a stepped structure on the connection region. A first vertical channel structure and a first dummy structure at least partially penetrate the electrode structure on the cell region and the connection region, respectively. The bottoms of the extended portions of the first vertical channel structure and the first dummy structure are located at a first horizontal height and a second horizontal height, respectively. The second horizontal height is higher than the first horizontal height.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority from Korean Patent Application No. 10-2020-0007787 filed on January 21, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor device, and more particularly, to a three-dimensional semiconductor memory device and a method for manufacturing the same. Background Art

[0004] The high integration of semiconductor devices can be used to meet consumer demand for superior performance and low prices. In traditional semiconductor devices, which can be called two-dimensional or planar semiconductor devices, since their size is mainly determined by the area occupied by the unit memory cell, the fineness of pattern formation greatly affects the integration. However, the cost of the equipment required to increase the fineness of the pattern sets a practical limit on increasing the integration of two-dimensional or planar semiconductor devices. To overcome this limitation, semiconductor devices such as semiconductor memory devices can be made to include a stacked structure in which circuit components can be arranged three-dimensionally. These semiconductor devices can be called three-dimensional semiconductor devices. A three-dimensional semiconductor memory device can therefore include memory cells arranged in a stacked structure extending three-dimensionally. Summary of the Invention

[0005] According to an embodiment of the present invention, a semiconductor memory device includes: a substrate including a cell region and a connection region; an electrode structure disposed on the substrate, the electrode structure having a stepped structure on the connection region; a first vertical channel structure at least partially penetrating the electrode structure on the cell region; and a first dummy structure at least partially penetrating the electrode structure on the connection region. The electrode structure includes: a first electrode structure including a plurality of first electrodes stacked on the substrate; and a second electrode structure including a plurality of second electrodes stacked on the first electrode structure. Each of the first vertical channel structure and the first dummy structure includes: a first vertical extension portion at least partially penetrating the first electrode structure; a second vertical extension portion at least partially penetrating the second electrode structure; and an extension portion disposed between the first vertical extension portion and the second vertical extension portion. The bottom of the extension portion of the first vertical channel structure is located at a first horizontal height, and the bottom of the extension portion of the first dummy structure is located at a second horizontal height higher than the first horizontal height.

[0006] According to an embodiment of the present invention, a semiconductor memory device includes: a substrate including a cell region, a connection region, and a cell edge region disposed between the cell region and the connection region; an electrode structure disposed on the substrate; a first vertical channel structure at least partially penetrating the electrode structure on the cell region; and a second vertical channel structure at least partially penetrating the electrode structure on the cell edge region. The electrode structure includes: a first electrode structure including a plurality of first electrodes stacked on the substrate; and a second electrode structure including a plurality of second electrodes stacked on the first electrode structure. Each of the first vertical channel structure and the second vertical channel structure includes: a first vertical extension portion at least partially penetrating the first electrode structure; a second vertical extension portion at least partially penetrating the second electrode structure; and an extension portion disposed between the first vertical extension portion and the second vertical extension portion. The vertical length of the extension portion of the first vertical channel structure is greater than the vertical length of the extension portion of the second vertical channel structure.

[0007] According to an embodiment of the present inventive concept, a semiconductor memory device includes: a substrate including a cell region and a connection region; an electrode structure disposed on the substrate, the electrode structure having a stepped structure on the connection region; a first vertical channel structure at least partially penetrating the electrode structure on the cell region; and a first dummy structure at least partially penetrating the electrode structure on the connection region. The electrode structure includes: a first electrode structure including a plurality of first electrodes stacked on the substrate; and a second electrode structure including a plurality of second electrodes stacked on the first electrode structure. Each of the first vertical channel structure and the first dummy structure includes: a first vertical extension portion at least partially penetrating the first electrode structure; a second vertical extension portion at least partially penetrating the second electrode structure; and an extension portion disposed between the first and second vertical extension portions. The maximum width of the first vertical extension portion of the first vertical channel structure is a first width, the maximum width of the extension portion of the first vertical channel structure is a second width, the maximum width of the first vertical extension portion of the first dummy structure is a third width, the maximum width of the extension portion of the first dummy structure is a fourth width, and the ratio of the second width to the first width is greater than the ratio of the fourth width to the third width.

[0008] According to an embodiment of the present invention, a method for manufacturing a semiconductor memory device includes: alternately stacking a first insulating layer and a first sacrificial layer on a substrate to form a first mold structure, the substrate including a cell region and a connection region; forming a channel hole that at least partially penetrates the first mold structure on the cell region; forming a dummy hole that at least partially penetrates the first mold structure on the connection region; forming a first sacrificial mask layer to fill the channel hole and the dummy hole; the level of the top surface of the first sacrificial mask layer increases in a direction from the cell region to the connection region; recessing the first sacrificial mask layer to expose an upper portion of the channel hole and an upper portion of the dummy hole; expanding the upper portion of the channel hole and the upper portion of the dummy hole; and removing the first sacrificial mask layer and forming a second sacrificial mask layer to fill the channel hole and the dummy hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings.The accompanying drawings illustrate non-limiting example embodiments as described herein.

[0010] Figure 1 is a schematic perspective view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept;

[0011] Figure 2 is a schematic plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept;

[0012] Figure 3 is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept;

[0013] Figure 4A and Figure 4B Along the Figure 3 A sectional view taken along line II' and line II-II';

[0014] Figure 5A and Figure 5B They are shown respectively Figure 4A an enlarged cross-sectional view of a portion 'M' and a portion 'N';

[0015] Figure 6A 、 Figure 7A 、 Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 14A and Figure 15A It is along Figure 3 A cross-sectional view taken along line II' of FIG. 1 , illustrating a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the inventive concept;

[0016] Figure 6B 、 Figure 7B 、 Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 11B 、 Figure 12B 、 Figure 13B 、 Figure 14B and Figure 15B It is along Figure 3 A cross-sectional view taken along line II-II' of FIG. 1 , illustrating a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the inventive concept;

[0017] Figure 16A and Figure 16B FIG. 1 is a diagram showing some parts of a semiconductor memory device according to an embodiment of the inventive concept (eg, Figure 4A an enlarged cross-sectional view of a portion 'M' and a portion 'N');

[0018] Figure 17 It is along Figure 3 A cross-sectional view taken along line II' of FIG. 1 shows a semiconductor memory device according to an embodiment of the inventive concept;

[0019] Figure 18 is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept;

[0020] Figure 19 It is along Figure 18 A sectional view taken along line II';

[0021] Figure 20 It is along Figure 3 A cross-sectional view taken along line II' of FIG. 1 shows a three-dimensional semiconductor memory device according to other embodiments of the inventive concept; and

[0022] Figure 21 is a cross-sectional view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0023] It should be noted that these figures are intended to illustrate the general characteristics of methods, structures and / or materials used in certain example embodiments and are intended to supplement the written description provided below. These figures are not necessarily drawn to scale and may not precisely reflect the precise structure or performance characteristics of any given embodiment and are not necessarily to be interpreted as defining or limiting the range of values ​​or properties encompassed by the example embodiments. For example, the relative thicknesses and positions of molecules, layers, regions and / or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numerals in the various figures may be intended to indicate the presence of similar or identical elements or features.

[0024] Figure 1is a schematic perspective view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0025] Reference Figure 1 A three-dimensional semiconductor memory device according to an embodiment of the present inventive concept may include a peripheral circuit structure PS, a cell array structure CS disposed on the peripheral circuit structure PS, and a through-contact vertically connecting the cell array structure CS to the peripheral circuit structure PS. In a plan view, the cell array structure CS may overlap with the peripheral circuit structure PS and may have at least similar widths and lengths to each other.

[0026] In an embodiment of the present inventive concept, the peripheral circuit structure PS may include a row decoder and a column decoder, a page buffer, a control circuit, and a peripheral logic circuit. The peripheral logic circuit constituting the peripheral circuit structure PS may be integrated on a semiconductor substrate.

[0027] The cell array structure CS may include a cell array in which a plurality of memory cells are arranged in three dimensions. For example, the cell array structure CS may include a plurality of memory blocks BLK0-BLKn. Each of the memory blocks BLK0-BLKn may include memory cells arranged in three dimensions.

[0028] Figure 2 is a schematic plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0029] Reference Figure 1 and Figure 2 , refer to Figure 1 The peripheral circuit structure PS and the cell array structure CS described above may be provided on the first substrate SUB. Figure 1 The row decoder ROWDEC and the column decoder COLDEC of the peripheral circuit structure PS, the page buffer PBR, and the control circuit may be disposed on the first substrate SUB.

[0030] constitute Figure 1 A plurality of pads MT of the cell array structure CS may be provided on the first substrate SUB. The pads MT may be arranged in the first direction D1 and the second direction D2. Each of the pads MT may include the previously referenced Figure 1 Described memory blocks BLK0-BLKn.

[0031] Pad MT can be set up with Figure 1 In the embodiment, the peripheral circuit structure PS is overlapped. Figure 1 The peripheral logic circuit of the peripheral circuit structure PS can be freely provided under the pad MT.

[0032] Figure 3is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. Figure 4A and Figure 4B Along the Figure 3 Cross-sectional views taken along lines II' and II-II'. Figure 5A and Figure 5B are shown separately Figure 4A An enlarged cross-sectional view of parts 'M' and 'N'. Figure 3 The semiconductor memory device shows Figure 2 An example of a memory cell structure in one of the pads MT is shown.

[0033] Reference Figure 3 、 Figure 4A 、 Figure 4B 、 Figure 5A and Figure 5B A peripheral circuit structure PS including a peripheral transistor PTR may be disposed on a first substrate SUB. A cell array structure CS including an electrode structure ST may be disposed on the peripheral circuit structure PS. The first substrate SUB may be a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single crystal epitaxial layer grown on a single crystal silicon substrate. The first substrate SUB may include an active region defined by a device isolation layer DIL.

[0034] The peripheral circuit structure PS may include a peripheral transistor PTR disposed on an active region of the first substrate SUB. The peripheral transistor PTR may constitute the row decoder and column decoder, the page buffer, the control circuit, and the peripheral logic circuit as described above.

[0035] The peripheral circuit structure PS may further include a lower interconnect line INL disposed on the peripheral transistor PTR and a first interlayer insulating layer ILD1 disposed to cover the peripheral transistor PTR and the lower interconnect line INL. A peripheral contact PCNT may be disposed between the lower interconnect line INL and the peripheral transistor PTR to electrically connect the lower interconnect line INL to the peripheral transistor PTR. The first interlayer insulating layer ILD1 may include a plurality of stacked insulating layers. For example, the first interlayer insulating layer ILD1 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a low-k dielectric layer stacked one on top of the other.

[0036] The cell array structure CS may be disposed on the first interlayer insulating layer ILD1 of the peripheral circuit structure PS. The cell array structure CS will be described in more detail below. A second substrate SL may be disposed on the first interlayer insulating layer ILD1. In an embodiment, the second substrate SL may be a plate-shaped structure that forms the lower portion of the pad MT and has a rectangular shape in plan view. The second substrate SL may support the electrode structure ST disposed thereon.

[0037] The second substrate SL may include a lower semiconductor layer LSL, a source semiconductor layer SSL, and an upper semiconductor layer USL stacked sequentially. Each of the lower semiconductor layer LSL, the source semiconductor layer SSL, and the upper semiconductor layer USL may be formed of or may include a semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof. Each of the lower semiconductor layer LSL, the source semiconductor layer SSL, and the upper semiconductor layer USL may have a single crystal, an amorphous, and / or a polycrystalline structure. In an embodiment, each of the lower semiconductor layer LSL, the source semiconductor layer SSL, and the upper semiconductor layer USL may include an n-type polycrystalline silicon layer doped with impurities. The lower semiconductor layer LSL, the source semiconductor layer SSL, and the upper semiconductor layer USL may have different impurity concentrations from each other.

[0038] The source semiconductor layer SSL may be interposed between the lower semiconductor layer LSL and the upper semiconductor layer USL. The lower semiconductor layer LSL and the upper semiconductor layer USL may be electrically connected to each other through the source semiconductor layer SSL. As an example, in a plan view, the upper semiconductor layer USL and the source semiconductor layer SSL may overlap with the lower semiconductor layer LSL.

[0039] The second substrate SL may include a cell array region CAR, a cell edge region EDR, and a connection region CNR. The cell array region CAR may overlap with the center of the second substrate SL. The connection region CNR may be provided at a side region of the second substrate SL. The connection region CNR may extend from the side region of the cell array region CAR in the second direction D2. The cell edge region EDR may be provided outside or around the cell array region CAR. The cell edge region EDR may be interposed between the cell array region CAR and the connection region CNR.

[0040] The electrode structure ST may be disposed on the second substrate SL. The electrode structure ST may include a first electrode structure ST1 and a second electrode structure ST2 disposed on the first electrode structure ST1. A second interlayer insulating layer ILD2 and a third interlayer insulating layer ILD3 may be disposed on the second substrate SL. The top surface of the second interlayer insulating layer ILD2 may be coplanar with the top surface of the first electrode structure ST1. The top surface of the third interlayer insulating layer ILD3 may be coplanar with the top surface of the second electrode structure ST2. The second interlayer insulating layer ILD2 and the third interlayer insulating layer ILD3 may at least partially cover the electrode structure ST on the connection region CNR.

[0041] The first electrode structure ST1 may include first electrodes EL1 stacked on the second substrate SL in a vertical direction (i.e., a third direction D3). The first electrode structure ST1 may also include first insulating layers IL1 that separate the first electrodes EL1 from each other. The first insulating layers IL1 of the first electrode structure ST1 and the first electrodes EL1 may be alternately stacked in the third direction D3. The second insulating layer IL2 may be disposed at the top of the first electrode structure ST1. The second insulating layer IL2 may be thicker than each of the first insulating layers IL1.

[0042] The second electrode structure ST2 may include second electrodes EL2 stacked on the first electrode structure ST1 in a third direction D3. The second electrode structure ST2 may also include third insulating layers IL3 separating the second electrodes EL2 from each other. The third insulating layers IL3 and the second electrodes EL2 of the second electrode structure ST2 may be alternately stacked in the third direction D3. A fourth insulating layer IL4 may be disposed on top of the second electrode structure ST2. The fourth insulating layer IL4 may be thicker than each of the third insulating layers IL3.

[0043] The electrode structure ST may extend from the cell array region CAR to the connection region CNR. The electrode structure ST may have a stepped structure on the connection region CNR. The stepped structure of the electrode structure ST may have a height or thickness that decreases as the distance from the cell array region CAR increases. For example, the stepped structure of the electrode structure ST on the cell array region CAR may have a height or thickness that decreases in the second direction D2.

[0044] The bottommost one of the first electrodes EL1 of the electrode structure ST may be a lower selection line. The topmost one of the second electrodes EL2 of the electrode structure ST may be an upper selection line. Each of the first and second electrodes EL1 and EL2 except the lower and upper selection lines may be a word line.

[0045] The first electrode EL1 and the second electrode EL2 may be formed of or include at least one conductive material, such as a doped semiconductor material (e.g., doped silicon), a metal (e.g., tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), and / or a transition metal (e.g., titanium or tantalum). The first to fourth insulating layers IL1 to IL4 may be formed of or include silicon oxide.

[0046] A plurality of first vertical channel structures VS1 may be provided on the cell array region CAR to at least partially pass through the electrode structure ST. Figure 3As shown, the first vertical channel structures VS1 can be arranged to form a first column C1 and a second column C2, the first column C1 consisting of four first vertical channel structures VS1 arranged in a first direction D1, and the second column C2 consisting of five first vertical channel structures VS1 arranged in the first direction D1. In an embodiment, the first column C1 and the second column C2 can be repeatedly and / or alternately arranged in the second direction D2. The diameter of each of the first vertical channel structures VS1 can gradually decrease as the distance from the first substrate SUB decreases.

[0047] A plurality of second vertical channel structures VS2 may be disposed on the cell edge region EDR to at least partially pass through the electrode structure ST. The second vertical channel structures VS2 may have the same arrangement and pattern density as the first vertical channel structures VS1, except that the second vertical channel structures VS2 are disposed on the cell edge region EDR.

[0048] The first dummy structure DS1 and the second dummy structure DS2 may be provided on the connection region CNR so as to at least partially pass through the electrode structure ST. In a plan view, the size of each of the first and second dummy structures DS1 and DS2 may be larger than the size of each of the first and second vertical channel structures VS1 and VS2. The first dummy structure DS1 may be adjacent to the cell edge region EDR. The second dummy structure DS2 may be provided on an outer region of the connection region CNR. The second dummy structure DS2 may at least partially pass through the third interlayer insulating layer ILD3, the second interlayer insulating layer ILD2, and the stepped structure of the electrode structure ST below the second interlayer insulating layer ILD2.

[0049] Each of the first and second vertical channel structures VS1 and VS2 may include a vertical insulation pattern VP, a vertical semiconductor pattern SP, and a gap-filling insulation pattern VI. The vertical semiconductor pattern SP may be interposed between the vertical insulation pattern VP and the gap-filling insulation pattern VI. A conductive pad PAD may be provided on each of the first and second vertical channel structures VS1 and VS2.

[0050] The gap-filling insulating pattern VI may have a cylindrical shape. The vertical semiconductor pattern SP may at least partially cover the surface of the gap-filling insulating pattern VI and may extend from the lower semiconductor layer LSL to the conductive pad PAD in the third direction D3. The vertical semiconductor pattern SP may be shaped like a tube with an open top. The vertical insulating pattern VP may at least partially cover the outer surface of the vertical semiconductor pattern SP and may extend from the lower semiconductor layer LSL to the top surface of the second insulating layer IL2 in the third direction D3. The vertical insulating pattern VP may also be shaped like a tube with an open top. The vertical insulating pattern VP may be interposed between the electrode structure ST and the vertical semiconductor pattern SP.

[0051] The vertical insulation pattern VP may include one or more layers. In an embodiment, the vertical insulation pattern VP may include a data storage layer. For example, Figure 5A As shown, the vertical insulating pattern VP may include a tunnel insulating layer TNL, a charge storage layer CTL, and a blocking insulating layer BKL serving as a data storage layer of a NAND FLASH memory device.

[0052] For example, the charge storage layer CTL may be a trapping insulating layer including conductive nanodots, a floating gate electrode, or an insulating layer. The charge storage layer CTL may be formed of a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, and / or a laminated trapping layer, or may include a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, and / or a laminated trapping layer. The tunnel insulating layer TNL may be formed of or include a material having a band gap greater than the band gap of the charge storage layer CTL. The tunnel insulating layer TNL may be formed of or include a high-k dielectric material (e.g., aluminum oxide and hafnium oxide) or silicon oxide. As used herein, a high-k dielectric material is a material with a dielectric constant greater than that of silicon dioxide. The blocking insulating layer BKL may include a silicon oxide layer.

[0053] The vertical semiconductor pattern SP may be formed of or include a semiconductor material, such as silicon (Si), germanium (Ge), or a mixture thereof. Furthermore, the vertical semiconductor pattern SP may be formed of or include an impurity-doped semiconductor material or an intrinsic semiconductor material. The vertical semiconductor pattern SP including the semiconductor material may serve as a channel region of a transistor constituting a cell string of a NAND FLASH memory device.

[0054] The conductive pad PAD may at least partially cover the top surface of the vertical semiconductor pattern SP and the top surface of the gap-filling insulating pattern VI. The conductive pad PAD may be formed of, or may include, a doped semiconductor material and / or a conductive material. The bit line contact plug BPLG may be electrically connected to the vertical semiconductor pattern SP through the conductive pad PAD.

[0055] The source semiconductor layer SSL may be in direct contact with the lower sidewall of each of the vertical semiconductor patterns SP. The source semiconductor layer SSL may electrically connect the vertical semiconductor patterns SP to each other. For example, the vertical semiconductor patterns SP may also be electrically connected to the second substrate SL. The second substrate SL may serve as a source electrode of the memory cell. A common source voltage may be applied to the second substrate SL.

[0056] Similar to the first vertical channel structure VS1 and the second vertical channel structure VS2, each of the first dummy structure DS1 and the second dummy structure DS2 may include a vertical insulation pattern VP, a vertical semiconductor pattern SP and a gap-filling insulation pattern VI. However, unlike the first vertical channel structure VS1 and the second vertical channel structure VS2, the first dummy structure DS1 and the second dummy structure DS2 may not be used as the channel region of the memory cell. The first dummy structure DS1 and the second dummy structure DS2 may not be electrically connected to the bit line BL and the upper interconnect line UIL to be described below. For example, the first dummy structure DS1 and the second dummy structure DS2 may be dummy structures that do not have any operational function relative to the circuit (for example, do not affect any voltage characteristics or current characteristics of the circuit), but may be formed in a manner similar to actual circuit elements and / or formed together with actual circuit elements. The first dummy structure DS1 and the second dummy structure DS2 may physically support the step structure of the electrode structure ST.

[0057] Reference Figure 4A and Figure 5A Each of the first vertical channel structures VS1 may include a first vertical extension portion VEP1 at least partially penetrating the first electrode structure ST1, a second vertical extension portion VEP2 at least partially penetrating the second electrode structure ST2, and a first expansion portion EXP1 between the first and second vertical extension portions VEP1 and VEP2. The first expansion portion EXP1 may be disposed in the second insulating layer IL2.

[0058] The width of the first vertical extending portion VEP1 in the second direction D2 may increase in an upward direction from bottom to top. For example, the width of the upper portion of the first vertical extending portion VEP1 in the second direction D2 may be a first width W1. The first width W1 of the first vertical extending portion VEP1 may be a value measured at the topmost level of the first electrode EL1 or at a horizontal level. The first width W1 may be the maximum width of the first vertical extending portion VEP1. The width of the second vertical extending portion VEP2 in the second direction D2 may increase in an upward direction from bottom to top. The maximum width of the second vertical extending portion VEP2 may be at least similar to the first width W1.

[0059] The width of the upper portion of the first expansion portion EXP1 in the second direction D2 may be a third width W3. The third width W3 may be the maximum width of the first expansion portion EXP1. The third width W3 may be greater than the first width W1. As an example, the first expansion portion EXP1 may extend horizontally from the first vertical extension portion VEP1 by a first recessed distance RCD1. Therefore, the third width W3 may be equal to the sum of the first width W1 and twice the first recessed distance RCD1 (i.e., W3 = W1 + 2 × RCD1).

[0060] The bottom of the first expansion portion EXP1 may be located at a first level LV1. The first level LV1 may be at the same level as the top surface of the first electrode EL1. The first level LV1 may be at the same level as the bottom surface of the second insulating layer IL2.

[0061] A vertical length or height of the first expansion portion EXP1 may be a first length L1. The vertical length may be a length from the bottom of the first expansion portion EXP1 to the top surface of the first expansion portion EXP1.

[0062] Reference Figure 4A , each of the second vertical channel structures VS2 may include a first vertical extension portion VEP1, a second vertical extension portion VEP2, and a second extension portion EXP2 between the first vertical extension portion VEP1 and the second vertical extension portion VEP2. The second extension portion EXP2 may be disposed in the second insulating layer IL2. The bottom of the second extension portion EXP2 may be located at a second horizontal height LV2. The second horizontal height LV2 may be higher than the first horizontal height LV1. The second horizontal height LV2 may be located between the bottom surface and the top surface of the second insulating layer IL2. The vertical length of the second extension portion EXP2 may be a second length L2 that is less than the first length L1. Except for the aforementioned differences, the second vertical channel structure VS2 may be constructed to have features substantially the same as those of the first vertical channel structure VS1.

[0063] Reference Figure 4A Each of the first dummy structures DS1 may include a first vertical extension portion VEP1, a second vertical extension portion VEP2, and a third extension portion EXP3 between the first vertical extension portion VEP1 and the second vertical extension portion VEP2. The third extension portion EXP3 may be disposed in the second insulating layer IL2. The bottom of the third extension portion EXP3 may be located at a third horizontal height LV3. The third horizontal height LV3 may be higher than the second horizontal height LV2. The third horizontal height LV3 may be located between the bottom surface and the top surface of the second insulating layer IL2. The vertical length of the third extension portion EXP3 may be a third length L3 that is less than the second length L2.

[0064] The width of the upper portion of the first vertical extension portion VEP1 of the first dummy structure DS1 in the second direction D2 may be a second width W2. The second width W2 may be the maximum width of the first vertical extension portion VEP1 of the first dummy structure DS1. The second width W2 may be greater than the first width W1. The width of the upper portion of the third expansion portion EXP3 in the second direction D2 may be a fourth width W4. The fourth width W4 may be the maximum width of the third expansion portion EXP3. The fourth width W4 may be greater than the second width W2.

[0065] Reference Figure 4A and Figure 5B Each of the second dummy structures DS2 may include a first vertical extension portion VEP1, a second vertical extension portion VEP2, and a fourth extension portion EXP4 between the first vertical extension portion VEP1 and the second vertical extension portion VEP2. The fourth extension portion EXP4 may be disposed in the second interlayer insulating layer ILD2. The bottom of the fourth extension portion EXP4 may be located at a fourth horizontal height LV4. The fourth horizontal height LV4 may be higher than the third horizontal height LV3. The fourth horizontal height LV4 may be lower than the top surface of the second interlayer insulating layer ILD2. The vertical length of the fourth extension portion EXP4 may be a fourth length L4 that is less than the third length L3.

[0066] The width of the upper portion of the first vertical extension portion VEP1 of the second dummy structure DS2 in the second direction D2 may be the second width W2. The width of the upper portion of the fourth extension portion EXP4 in the second direction D2 may be the fourth width W4. As an example, the fourth extension portion EXP4 may be horizontally extended from the first vertical extension portion VEP1 by the second recessed distance RCD2. Therefore, the fourth width W4 may be equal to the sum of the second width W2 and twice the second recessed distance RCD2 (i.e., W4=W2+2×RCD2). In an embodiment, the second recessed distance RCD2 may be substantially equal to Figure 4A The first recess distance RCD1.

[0067] Reference Figure 4A , the top surfaces of the first to fourth expansion parts EXP1 to EXP4 may be coplanar with each other. The top surfaces of the first to fourth expansion parts EXP1 to EXP4 may be coplanar with the top surface of the second insulating layer IL2. The bottoms of the first to fourth expansion parts EXP1 to EXP4 may be located at different levels. The level of the bottoms of the first to fourth expansion parts EXP1 to EXP4 may increase in a direction from the first to fourth expansion parts EXP1 to EXP4. The vertical lengths of the first to fourth expansion parts EXP1 to EXP4 may decrease in a direction from the first expansion part EXP1 toward the fourth expansion part EXP4.

[0068] Reference Figure 5A and Figure 5B, the ratio W3 / W1 of the third width W3 to the first width W1 in the first vertical channel structure VS1 can be greater than the ratio W4 / W2 of the fourth width W4 to the second width W2 in the second dummy structure DS2. For example, for the first vertical channel structure VS1, since the first width W1 is relatively small, the difference between the third width W3 and the first width W1 (i.e., 2×RCD1) can be relatively large compared to the first width W1. For the second dummy structure DS2, since the second width W2 is relatively large, the difference between the fourth width W4 and the second width W2 (i.e., 2×RCD2) can be relatively small compared to the second width W2.

[0069] Return to reference Figure 3 、 Figure 4A and Figure 4B , a plurality of separation structures SPS may at least partially penetrate the electrode structure ST. The separation structures SPS may extend parallel to each other in the second direction D2. The electrode structure ST may be divided into a plurality of structures horizontally spaced apart from each other by the separation structures SPS. For example, each electrode EL1 or EL2 of the electrode structure ST may be divided into a plurality of electrodes horizontally spaced apart from each other by the separation structures SPS. The separation structures SPS may be formed of an insulating material (e.g., silicon oxide), or include an insulating material (e.g., silicon oxide).

[0070] A three-dimensional semiconductor memory device according to an embodiment of the present inventive concept may be a three-dimensional NAND FLASH memory device. NAND cell strings may be integrated into an electrode structure ST located on a second substrate SL. For example, the electrode structure ST and first and second vertical channel structures VS1 and VS2 that at least partially penetrate the electrode structure ST may constitute memory cells three-dimensionally arranged on the second substrate SL. The first and second electrodes EL1 and EL2 of the electrode structure ST may serve as gate electrodes of transistors.

[0071] A fourth interlayer insulating layer ILD4 may be disposed on the third interlayer insulating layer ILD3. Bitline contact plugs BPLG may at least partially penetrate the fourth interlayer insulating layer ILD4 and may be coupled to conductive pads PAD, respectively. Bitlines BL may be disposed on the fourth interlayer insulating layer ILD4. The bitlines BL may extend parallel to each other in a first direction D1. The bitlines BL may be electrically connected to the first vertical channel structure VS1 and the second vertical channel structure VS2, respectively, through the bitline contact plugs BPLG.

[0072] The cell contact plugs PLG may at least partially penetrate the second interlayer insulating layer to the fourth interlayer insulating layers ILD2, ILD3, and ILD4, and may be respectively coupled to the first electrode EL1 and the second electrode EL2 forming the stepped structure. The upper interconnection line UIL may be disposed on the fourth interlayer insulating layer ILD4. The upper interconnection line UIL may be electrically connected to the first electrode EL1 and the second electrode EL2, respectively, through the cell contact plugs PLG.

[0073] According to an embodiment of the present invention, the vertical channel structure on the cell region may include an extension portion disposed between a first vertical extension portion and a second vertical extension portion. The first vertical extension portion and the second vertical extension portion may be stably connected to each other via the extension portion. Therefore, it is possible to increase the reliability of the semiconductor memory device according to an embodiment of the present invention and maintain its electrical characteristics.

[0074] Figure 6A 、 Figure 7A 、 Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 14A and Figure 15A It is along Figure 3 1 is a cross-sectional view taken along line II′ to illustrate a method of fabricating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. Figure 6B 、 Figure 7B 、 Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 11B 、 Figure 12B 、 Figure 13B 、 Figure 14B and Figure 15B It is along Figure 3 1 is a cross-sectional view taken along line II-II′ to illustrate a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0075] Reference Figure 3 、 Figure 6A and Figure 6B , a peripheral circuit structure PS may be formed on the first substrate SUB. Forming the peripheral circuit structure PS may include: forming a peripheral transistor PTR on the first substrate SUB; and forming a lower interconnect line INL on the peripheral transistor PTR. For example, forming the peripheral transistor PTR may include: forming a device isolation layer DIL on the first substrate SUB to define an active region; forming a gate insulating layer and a gate electrode on the active region; and implanting impurities into the active region to form source / drain regions. A first interlayer insulating layer ILD1 may cover the peripheral transistor PTR and the lower interconnect line INL.

[0076] Reference Figure 3 、 Figure 7A and Figure 7B A second substrate SL may be formed on the first interlayer insulating layer ILD1. Forming the second substrate SL may include sequentially forming a lower semiconductor layer LSL, a fifth insulating layer IL5, a lower sacrificial layer LHL, a sixth insulating layer IL6, and an upper semiconductor layer USL. For example, the lower semiconductor layer LSL and the upper semiconductor layer USL may be formed of or include a semiconductor material (e.g., polysilicon). The fifth insulating layer IL5 and the sixth insulating layer IL6 may include silicon oxide layers, and the lower sacrificial layer LHL may include a silicon nitride layer or a silicon oxynitride layer.

[0077] The first mold structure MO1 may be formed on the second substrate SL. For example, first insulating layers IL1 and first sacrificial layers HL1 may be alternately stacked on the upper semiconductor layer USL to form the first mold structure MO1. The second insulating layer IL2 may be formed as the topmost layer of the first mold structure MO1.

[0078] The first insulating layer IL1, the first sacrificial layer HL1, and the second insulating layer IL2 may be deposited using a thermal chemical vapor deposition process, a plasma enhanced chemical vapor deposition (PE-CVD) process, a physical chemical vapor deposition process, and / or an atomic layer deposition (ALD) process. The first insulating layer IL1 and the second insulating layer IL2 may be formed of or include silicon oxide, and the first sacrificial layer HL1 may be formed of or include silicon nitride or silicon oxynitride.

[0079] A step structure may be formed in the first mold structure MO1 on the connection region CNR. For example, the step structure on the connection region CNR may be formed by performing a cyclic process on the first mold structure MO1. Forming the step structure may include: forming a mask pattern on the first mold structure MO1; and performing a cyclic process multiple times using the mask pattern. Each cyclic process may include etching a portion of the first mold structure MO1 using the mask pattern as an etching mask and a trimming process to reduce the size of the mask pattern.

[0080] A second interlayer insulating layer ILD2 may be formed on the first mold structure MO1. The formation of the second interlayer insulating layer ILD2 may include forming an insulating layer to cover the first mold structure MO1 and performing a planarization process on the insulating layer to expose the second insulating layer IL2.

[0081] Reference Figure 3 、 Figure 8A and Figure 8BThe first channel hole CH1 may be formed on the cell array region CAR to at least partially penetrate the first mold structure MO1. The second channel hole CH2 may be formed on the cell edge region EDR to at least partially penetrate the first mold structure MO1. The first dummy hole DH1 and the second dummy hole DH2 may be formed on the connection region CNR to at least partially penetrate the first mold structure MO1. The second dummy hole DH2 may be provided to at least partially penetrate the second interlayer insulating layer ILD2. Each of the first and second channel holes CH1 and CH2 and the first and second dummy holes DH1 and DH2 may expose the lower semiconductor layer LSL.

[0082] For example, the formation of the first and second channel holes CH1 and CH2 and the first and second dummy holes DH1 and DH2 may include: forming a mask pattern on the first mold structure MO1, the mask pattern having openings that define the arrangement and positions of the holes; and anisotropically etching the first mold structure MO1 using the mask pattern as an etching mask. The anisotropic etching process may include a plasma etching process, a reactive ion etching (RIE) process, an inductively coupled plasma reactive ion etching (ICP-RIE) process, and / or an ion beam etching (IBE) process.

[0083] In a plan view, the first channel hole CH1 and the second channel hole CH2 may be arranged in a specific direction or in a zigzag shape. The first channel hole CH1 and the second channel hole CH2 may have the same structure as previously described. Figure 3 The first vertical channel structure VS1 and the second vertical channel structure VS2 are described as having the same planar arrangement.

[0084] The pattern density of the first and second channel holes CH1 and CH2 may be greater than that of the first and second dummy holes DH1 and DH2. For example, the number of first and second channel holes CH1 and CH2 formed per unit area may be greater than that of the first and second dummy holes DH1 and DH2 formed per unit area.

[0085] The upper portion of each of the first channel hole CH1 and the second channel hole CH2 may have a first width W1 in the second direction D2. For example, the maximum diameter of each of the first channel hole CH1 and the second channel hole CH2 may be equal to the first width W1. The upper portion of each of the first dummy hole DH1 and the second dummy hole DH2 may have a second width W2 in the second direction D2. For example, the maximum diameter of each of the first dummy hole DH1 and the second dummy hole DH2 may be equal to the second width W2. In embodiments, the second width W2 may be greater than the first width W1.

[0086] Reference Figure 3 、 Figure 9A and Figure 9B, the first sacrificial mask layer SAL1 may fill the first and second channel holes CH1 and CH2 and the first and second dummy holes DH1 and DH2. The first sacrificial mask layer SAL1 may be formed by a spin coating process. The first sacrificial mask layer SAL1 may include a spin-on hard mask (SOH). For example, the first sacrificial mask layer SAL1 may include a layer (e.g., an amorphous carbon layer) having a high carbon content (e.g., a carbon content exceeding the nominal). Immediately after forming the first sacrificial mask layer SAL1 on the first mold structure MO1, the first sacrificial mask layer SAL1 may have a uniform thickness on the first mold structure MO1. For example, the first sacrificial mask layer SAL1 may have a substantially coplanar top surface from the cell array region CAR to the connection region CNR.

[0087] Reference Figure 3 、 Figure 10A and Figure 10B , a baking process may be performed on the first sacrificial mask layer SAL1. As a result of the baking process, the first sacrificial mask layer SAL1' may shrink.

[0088] The first sacrificial mask layer SAL1' may shrink more over the first channel holes CH1, which have a high pattern density. The first sacrificial mask layer SAL1' may shrink less over the second dummy holes DH2, which have a low pattern density. Therefore, the thickness of the first sacrificial mask layer SAL1' on the first mold structure MO1 may gradually increase in a direction from the first channel holes CH1 in the cell array region CAR toward the second dummy holes DH2 in the connection region CNR. For example, the level of the top surface of the first sacrificial mask layer SAL1' may gradually increase in a direction from the cell array region CAR toward the connection region CNR.

[0089] For example, the first sacrificial mask layer SAL1' of the cell array region CAR may have a first thickness T1, the first sacrificial mask layer SAL1' of the cell edge region EDR may have a second thickness T2, and the first sacrificial mask layer SAL1' of the connection region CNR may have a third thickness T3. The second thickness T2 may be greater than the first thickness T1, and the third thickness T3 may be greater than the second thickness T2.

[0090] The second substrate SL may include a peripheral circuit region PER as its outer edge region, and an upper peripheral transistor UPTR is formed on the peripheral circuit region PER. The first sacrificial mask layer SAL1 ′ on the peripheral circuit region PER may have a fourth thickness T4 that is greater than the third thickness T3.

[0091] Reference Figure 3 、 Figure 11A and Figure 11BAs a result of the recessing of the first sacrificial mask layer SAL1 ′, the first and second channel holes CH1 and CH2 and the first and second dummy holes DH1 and DH2 may be filled with the recessed first sacrificial mask layer SAL1 ′.

[0092] The first sacrificial mask layer SAL1′ may be recessed to the same depth over the entire area of ​​the second substrate SL. As described above, since the thickness of the first sacrificial mask layer SAL1′ increases in the direction from the cell array region CAR to the connection region CNR, the height of the recessed first sacrificial mask layer SAL1′ may gradually increase in the direction from the cell array region CAR toward the connection region CNR.

[0093] For example, the top surface of the first sacrificial mask layer SAL1′ in the first channel hole CH1 may be located at a first level LV1, the top surface of the first sacrificial mask layer SAL1′ in the second channel hole CH2 may be located at a second level LV2, the top surface of the first sacrificial mask layer SAL1′ in the first dummy hole DH1 may be located at a third level LV3, and the top surface of the first sacrificial mask layer SAL1′ in the second dummy hole DH2 may be located at a fourth level LV4. The second level LV2 may be higher than the first level LV1, the third level LV3 may be higher than the second level LV2, and the fourth level LV4 may be higher than the third level LV3.

[0094] The first to fourth expanded holes EXH1 to EXH4 can be formed by expanding the first and second channel holes CH1 and CH2 and the upper portions of the first and second dummy holes DH1 and DH2 using the recessed first sacrificial mask layer SAL1' as a mask. The formation of the first to fourth expanded holes EXH1 to EXH4 may include horizontally recessing the second insulating layer IL2 and the second interlayer insulating layer ILD2 exposed by the recessed first sacrificial mask layer SAL1' using a wet etching process.

[0095] In the recessing process, the second insulating layer IL2 may be recessed. Figure 5A In the recessing process, the second interlayer insulating layer ILD2 may be recessed by a first recess distance RCD1. Figure 5B In an embodiment, the second recess distance RCD2 may be substantially equal to Figure 4A The first recess distance RCD1.

[0096] The bottoms of the first to fourth expansion holes EXH1 to EXH4 may be located at first to fourth levels LV1 to LV4, respectively. Each of the first to second expansion holes EXH1 to EXH2 may have a third width W3. The third width W3 may be greater than the first width W1. Each of the third to fourth expansion holes EXH3 to EXH4 may have a fourth width W4. The fourth width W4 may be greater than the second width W2.

[0097] Reference Figure 3 、 Figure 12A and Figure 12B The first sacrificial mask layer SAL1' in the first and second channel holes CH1 and CH2 and the first and second dummy holes DH1 and DH2 can be selectively removed. A second sacrificial mask layer SAL2 can be formed in the first and second channel holes CH1 and CH2 and the first and second dummy holes DH1 and DH2. For example, the second sacrificial mask layer SAL2 can be formed of or include polysilicon. When the second sacrificial mask layer SAL2 is formed, a void VOI can be formed in each of the first and second channel holes CH1 and CH2 and the first and second dummy holes DH1 and DH2.

[0098] A second mold structure MO2 may be formed on the first mold structure MO1. For example, the second mold structure MO2 may be formed by alternately stacking a third insulating layer IL3 and a second sacrificial layer HL2 on the first mold structure MO1. A fourth insulating layer IL4 may be formed at the topmost level of the second mold structure MO2. The first mold structure MO1 and the second mold structure MO2 may constitute a single mold structure MO. The third insulating layer IL3 and the fourth insulating layer IL4 may be formed of or include silicon oxide, and the second sacrificial layer HL2 may be formed of or include silicon nitride or silicon oxynitride.

[0099] A step structure may be formed in the second mold structure MO2 on the connection region CNR. The step structure of the second mold structure MO2 may be formed by the same method as that of the first mold structure MO1.

[0100] A third interlayer insulating layer ILD3 may be formed on the second mold structure MO2 . The formation of the third interlayer insulating layer ILD3 may include forming an insulating layer to cover the second mold structure MO2 , and performing a planarization process on the insulating layer to expose the fourth insulating layer IL4 .

[0101] Reference Figure 3 、 Figure 13A and Figure 13BThe first and second channel holes CH1 and CH2 and the first and second dummy holes DH1 and DH2 may at least partially penetrate the second mold structure MO2. In a plan view, the first and second channel holes CH1 and CH2 and the first and second dummy holes DH1 and DH2 that at least partially penetrate the second mold structure MO2 may respectively overlap with the first and second channel holes CH1 and CH2 and the first and second dummy holes DH1 and DH2 that at least partially penetrate the first mold structure MO1.

[0102] The second sacrificial mask layer SAL2 may be exposed by at least partially passing through the first and second channel holes CH1 and CH2 and the first and second dummy holes DH1 and DH2 of the second mold structure MO2. The exposed second sacrificial mask layer SAL2 may be selectively removed to form the first and second channel holes CH1 and CH2 and the first and second dummy holes DH1 and DH2 that at least partially penetrate the mold structure MO.

[0103] According to embodiments of the present invention, the diameters of the aforementioned expanded holes EXH1-EXH4 can be larger than the diameters of the holes below them. Because the expanded holes have relatively large areas, holes that at least partially penetrate the second mold structure MO2 can be more easily aligned with the expanded holes. As a result, when forming holes that at least partially penetrate the second mold structure MO2, it is possible to prevent the holes that at least partially penetrate the second mold structure MO2 from being misaligned with the holes formed in the first mold structure MO1. By preventing processing defects such as the aforementioned misalignment, the reliability of the semiconductor memory device can be improved.

[0104] Reference Figure 3 、 Figure 14A and Figure 14B The first and second vertical channel structures VS1 and VS2 may be formed in the first and second channel holes CH1 and CH2, respectively. Forming the first and second vertical channel structures VS1 and VS2 may include sequentially forming a vertical insulation pattern VP, a vertical semiconductor pattern SP, and a gap-filling insulation pattern VI on inner surfaces of the first and second channel holes CH1 and CH2. The vertical insulation pattern VP and the vertical semiconductor pattern SP may be conformally formed.

[0105] The first dummy structure DS1 and the second dummy structure DS2 may be formed in the first dummy hole DH1 and the second dummy hole DH2, respectively. In an embodiment, the first dummy structure DS1 and the second dummy structure DS2 may be formed simultaneously with the first vertical channel structure VS1 and the second vertical channel structure VS2. A conductive pad may be formed in or on the upper portion of each of the first vertical channel structure VS1 and the second vertical channel structure VS2 and the first dummy structure DS1 and the second dummy structure DS2.

[0106] The fourth interlayer insulating layer ILD4 may be formed on the mold structure MO. The mold structure MO may be patterned to form trenches TR that at least partially penetrate the mold structure MO. The trenches TR may extend parallel to each other in the second direction D2 (eg, see FIG. 2 ). Figure 3 The trench TR may expose the lower semiconductor layer LSL. The trench TR may expose sidewalls of the first sacrificial layer HL1 and the second sacrificial layer HL2. The trench TR may expose side surfaces of the fifth insulating layer IL5, the lower sacrificial layer LHL, and the sixth insulating layer IL6.

[0107] Reference Figure 3 、 Figure 15A and Figure 15B , the lower sacrificial layer LHL exposed by the trench TR may be replaced by the source semiconductor layer SSL. For example, the lower sacrificial layer LHL exposed by the trench TR may be selectively removed. As a result of removing the lower sacrificial layer LHL, the lower portion of the vertical insulation pattern VP of each of the first vertical channel structure VS1 and the second vertical channel structure VS2 may be exposed.

[0108] The exposed lower portion of the vertical insulation pattern VP may be selectively removed. Thus, the lower portion of the vertical semiconductor pattern SP may be exposed. In an embodiment, the fifth and sixth insulation layers IL5 and IL6 may be removed during the removal of the lower portion of the vertical insulation pattern VP.

[0109] A source semiconductor layer SSL may be formed in the space formed by removing the fifth insulating layer IL5, the lower sacrificial layer LHL, and the sixth insulating layer IL6. The source semiconductor layer SSL may be in direct contact with the exposed lower portion of the vertical semiconductor pattern SP. The source semiconductor layer SSL may be in direct contact with the lower semiconductor layer LSL therebelow. The source semiconductor layer SSL may be in direct contact with the upper semiconductor layer USL thereover. The lower semiconductor layer LSL, the source semiconductor layer SSL, and the upper semiconductor layer USL may constitute a second substrate SL.

[0110] The electrode structure ST may be formed by replacing the first and second sacrificial layers HL1 and HL2 exposed through the trenches TR with the first and second electrodes EL1 and EL2. For example, the first and second sacrificial layers HL1 and HL2 exposed through the trenches TR may be selectively removed. The first and second electrodes EL1 and EL2 may be formed in the spaces formed by removing the first and second sacrificial layers HL1 and HL2, respectively. Separation structures SPS may fill the trenches TR, respectively.

[0111] Return to reference Figure 3 、 Figure 4A and Figure 4BThe bit line contact plugs BPLG, respectively coupled to the conductive pads PAD, may at least partially penetrate the fourth interlayer insulating layer ILD4. The cell contact plugs PLG, respectively coupled to the first electrode EL1 and the second electrode EL2, may at least partially penetrate the second interlayer insulating layer to the fourth interlayer insulating layers ILD2, ILD3, and ILD4. The bit lines BL electrically connected to the bit line contact plugs BPLG and the upper interconnect lines UIL electrically connected to the cell contact plugs PLG may be formed on the fourth interlayer insulating layer ILD4.

[0112] Figure 16A and Figure 16B is a diagram showing a portion of a semiconductor memory device according to an embodiment of the inventive concept (eg, Figure 4A For the sake of simplicity, the previously referenced Figure 3 、 Figure 4A 、 Figure 4B 、 Figure 5A and Figure 5B The elements described will be identified by the same reference numerals without repeating their overlapping descriptions, and features that differ from the previous embodiments will be described in more detail below. Therefore, where a detailed description of a particular element is omitted, it can be assumed that the element is at least similar to the corresponding element described elsewhere in this specification.

[0113] Reference Figure 4A 、 Figure 16A and Figure 16B , the topmost one of the first electrodes EL1 that contacts the first expansion portion EXP1 may have a curved surface CTS. The curved surface CTS may be in direct contact with the lower portion of the first expansion portion EXP1. Figure 3 、 Figure 11A and Figure 11B During the described process of expanding the first channel hole CH1 , a curved surface CTS of the topmost one of the first electrodes EL1 may be formed by etching a portion of the exposed surface of the topmost one of the first sacrificial layers HL1 .

[0114] The first expansion portion EXP1 may horizontally extend from the first vertical extension portion VEP1 by a first recessed distance RCD1 (eg, see Figure 16A The fourth extended portion EXP4 may horizontally extend from the first vertically extending portion VEP1 by a second recessed distance RCD2 (eg, see Figure 16B). The second recess distance RCD2 may be greater than the first recess distance RCD1. The first expansion portion EXP1 may be formed by horizontally recessing the second insulating layer IL2, and the fourth expansion portion EXP4 may be formed by horizontally recessing the second interlayer insulating layer ILD2. Since the second insulating layer IL2 and the second interlayer insulating layer ILD2 have different properties from each other, the recess depth of the second interlayer insulating layer ILD2 may be greater than the recess depth of the second insulating layer IL2.

[0115] Figure 17 It is along Figure 3 The cross-sectional view taken along line II' shows a semiconductor memory device according to an embodiment of the present invention. Figure 3 、 Figure 4A 、 Figure 4B 、 Figure 5A and Figure 5B The elements described will be identified by the same reference numerals without repeating their overlapping descriptions, and features that differ from the previous embodiments will be described in more detail below. Therefore, where a detailed description of a particular element is omitted, it can be assumed that the element is at least similar to the corresponding element described elsewhere in this specification.

[0116] Reference Figure 3 and Figure 17 In terms of film or material properties, the first and second vertical channel structures VS1 and VS2 may be different from the first and second dummy structures DS1 and DS2. Each of the first and second vertical channel structures VS1 and VS2 may include a vertical insulation pattern VP, a vertical semiconductor pattern SP, and a gap-filling insulation pattern VI. Each of the first and second dummy structures DS1 and DS2 may be formed of or include an insulating material.

[0117] Figure 18 is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. Figure 19 It is along Figure 18 For the sake of simplicity, the previously referenced Figure 3 、 Figure 4A 、 Figure 4B 、 Figure 5A and Figure 5B The elements described will be identified by the same reference numerals without repeating their overlapping descriptions, and features that differ from the previous embodiments will be described in more detail below. Therefore, where a detailed description of a particular element is omitted, it can be assumed that the element is at least similar to the corresponding element described elsewhere in this specification.

[0118] Reference Figure 18 and Figure 19, the first vertical channel structure VS1 adjacent to the separation structure SPS may be defined as a third vertical channel structure VS3. The third vertical channel structure VS3 may be arranged along the separation structure SPS and in the second direction D2.

[0119] Each of the third vertical channel structures VS3 may include a first vertical extension portion VEP1 at least partially penetrating the first electrode structure ST1, a second vertical extension portion VEP2 at least partially penetrating the second electrode structure ST2, and a fifth expansion portion EXP5 between the first and second vertical extension portions VEP1 and VEP2. The fifth expansion portion EXP5 may be disposed in the second insulating layer IL2.

[0120] The upper portion of the first vertical extension portion VEP1 of the third vertical channel structure VS3 may have a fifth width W5. The fifth width W5 may be greater than the first width W1. The upper portion of the fifth expansion portion EXP5 may have a sixth width W6. The sixth width W6 may be greater than the fifth width W5. A ratio W6 / W5 of the sixth width W6 to the fifth width W5 in the third vertical channel structure VS3 may be smaller than a ratio W3 / W1 of the third width W3 to the first width W1 in the first vertical channel structure VS1.

[0121] Figure 20 It is along Figure 3 The cross-sectional view taken along line II' shows a three-dimensional semiconductor memory device according to another embodiment of the present invention. Figure 3 、 Figure 4A 、 Figure 4B 、 Figure 5A and Figure 5B The elements described will be identified by the same reference numerals without repeating their overlapping descriptions, and features that differ from the previous embodiments will be described in more detail below. Therefore, where a detailed description of a particular element is omitted, it can be assumed that the element is at least similar to the corresponding element described elsewhere in this specification.

[0122] Reference Figure 20 , the first dummy structure DS1 and the second dummy structure DS2 on the connection area CNR may not include an extension portion. For example, the first dummy structure DS1 may not include the previously referenced Figure 4A The second pseudo structure DS2 may not include the third extended part EXP3 described previously. Figure 4A The fourth extended portion EXP4 is described. The first dummy structure DS1 and the second dummy structure DS2 may be configured to have a width or diameter that gradually decreases as the distance from the second substrate SL decreases.

[0123] By contrast, the first and second vertical channel structures VS1 and VS2 disposed on the cell array region CAR and the cell edge region EDR may include first and second expansion portions EXP1 and EXP2 , respectively.

[0124] The formation of the first and second dummy structures DS1 and DS2 may include forming dummy holes on the connection region CNR through a single etching process after forming the first and second mold structures MO1 and MO2 and the first and second channel holes CH1 and CH2 as described in the aforementioned manufacturing method.

[0125] Figure 21 is a cross-sectional view showing a three-dimensional semiconductor memory device according to an embodiment of the present invention. Figure 3 、 Figure 4A 、 Figure 4B 、 Figure 5A and Figure 5B The elements described will be identified by the same reference numerals without repeating their overlapping descriptions, and features that differ from the previous embodiments will be described in more detail below. Therefore, where a detailed description of a particular element is omitted, it can be assumed that the element is at least similar to the corresponding element described elsewhere in this specification.

[0126] Reference Figure 21 The electrode structure ST may further include a third electrode structure ST3 disposed on the second electrode structure ST2. The third electrode structure ST3 may include third electrodes EL3 stacked on the second electrode structure ST2 in a third direction D3. The third electrode structure ST3 may further include a seventh insulating layer IL7 separating the third electrodes EL3 from each other. An eighth insulating layer IL8 may be disposed at the topmost portion of the third electrode structure ST3.

[0127] Each of the first and second vertical channel structures VS1 and VS2 may include a lower expansion portion LEXP disposed in the second insulating layer IL2 of the first electrode structure ST1 and an upper expansion portion UEXP disposed in the fourth insulating layer IL4 of the second electrode structure ST2 .

[0128] The first dummy structure DS1, the second dummy structure DS2, and the third dummy structure DS3 may be disposed on the connection region CNR. The first dummy structure DS1 may be adjacent to the cell edge region EDR. The third dummy structure DS3 may be adjacent to the end of the stepped structure of the electrode structure ST. The second dummy structure DS2 may be disposed between the first dummy structure DS1 and the third dummy structure DS3.

[0129] The first dummy structure DS1 may include a first lower expansion portion LEXP1 disposed in the second insulating layer IL2 of the first electrode structure ST1 and a first upper expansion portion UEXP1 disposed in the fourth insulating layer IL4 of the second electrode structure ST2 .

[0130] The second dummy structure DS2 may include a first lower expansion portion LEXP1 disposed in the second insulating layer IL2 of the first electrode structure ST1 and a second upper expansion portion UEXP2 disposed in an upper portion of the third interlayer insulating layer ILD3 .

[0131] The width of the second upper extension portion UEXP2 of the second dummy structure DS2 may be greater than the width of the first lower extension portion LEXP1 of the second dummy structure DS2. For example, the second recess distance RCD2 of the first lower extension portion LEXP1 may be relatively small, as previously described with reference to FIG. Figure 5B The second recess distance RCD2 of the second upper extension portion UEXP2 may be relatively large, as previously described with reference to Figure 16B As described.

[0132] The first lower expansion portion LEXP1 may be formed by horizontally recessing the second insulating layer IL2 of the first electrode structure ST1, and the second upper expansion portion UEXP2 may be formed by horizontally recessing the third interlayer insulating layer ILD3. Since the second insulating layer IL2 and the third interlayer insulating layer ILD3 have different characteristics from each other, the width of the second upper expansion portion UEXP2 of the second dummy structure DS2 may be greater than the width of the first lower expansion portion LEXP1 thereunder.

[0133] The third dummy structure DS3 may include a second lower expansion portion LEXP2 disposed in an upper portion of the second interlayer insulating layer ILD2 and a second upper expansion portion UEXP2 disposed in an upper portion of the third interlayer insulating layer ILD3. Both the second lower expansion portion LEXP2 and the second upper expansion portion UEXP2 of the third dummy structure DS3 may have relatively large widths.

[0134] According to an embodiment of the present inventive concept, the vertical channel structure on the cell region may include an expansion portion disposed between the first vertical extension portion and the second vertical extension portion. Due to the existence of the expansion portion, the reliability of the semiconductor memory device can be increased and the electrical characteristics of the semiconductor memory device can be supported.

[0135] While example embodiments of the inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes may be made in form and details without departing from the spirit and scope of the specification.

Claims

1. A semiconductor memory device comprising: a substrate comprising a cell region and a connection region; an electrode structure disposed on the substrate, wherein the electrode structure has a step structure on the connection area; a first vertical channel structure at least partially penetrating the electrode structure on the cell region; as well as a first dummy structure at least partially penetrating the electrode structure on the connection region, Wherein, the electrode structure comprises: a first electrode structure comprising a plurality of first electrodes stacked on the substrate; and a second electrode structure comprising a plurality of second electrodes stacked on the first electrode structure, Wherein, each of the first vertical channel structure and the first dummy structure includes: a first vertically extending portion at least partially penetrating the first electrode structure; a second vertically extending portion at least partially penetrating the second electrode structure; and an expansion portion disposed between the first vertically extending portion and the second vertically extending portion, In which, a first height from the top surface of the topmost first electrode among the multiple first electrodes to the bottom of the extended portion of the first vertical channel structure is less than a second height from the top surface of the topmost first electrode among the multiple first electrodes to the bottom of the extended portion of the first dummy structure.

2. The semiconductor memory device according to claim 1, wherein The substrate further includes a cell edge region disposed between the cell region and the connection region. The semiconductor memory device further includes a second vertical channel structure at least partially penetrating the electrode structure on the cell edge region. A third height from the top surface of the uppermost first electrode among the plurality of first electrodes to the bottom of the extended portion of the second vertical channel structure is greater than the first height and less than the second height.

3. The semiconductor memory device according to claim 1 , further comprising a second dummy structure at least partially penetrating the electrode structure on the connection region, in, The distance between the second dummy structure and the cell area is greater than the distance between the first dummy structure and the cell area, and A third height from the top surface of the uppermost first electrode among the plurality of first electrodes to the bottom of the extended portion of the second dummy structure is greater than the second height.

4. The semiconductor memory device according to claim 1, wherein The maximum width of the first vertical extension portion of the first vertical channel structure is a first width, wherein the maximum width of the extended portion of the first vertical channel structure is the second width, The maximum width of the first vertical extension portion of the first dummy structure is the third width. wherein the maximum width of the extended portion of the first dummy structure is a fourth width, and The ratio of the second width to the first width is greater than the ratio of the fourth width to the third width.

5. The semiconductor memory device according to claim 4, wherein The expansion portion of the first vertical channel structure horizontally extends a first distance from the first vertical extension portion of the first vertical channel structure, wherein the extension portion of the first dummy structure extends horizontally a second distance from the first vertical extension portion of the first dummy structure, and The second distance is greater than the first distance.

6. The semiconductor memory device according to claim 1, wherein The first electrode structure includes an insulating layer on an uppermost first electrode of the plurality of first electrodes, and A top surface of the extended portion of the first vertical channel structure and a top surface of the extended portion of the first dummy structure are respectively coplanar with a top surface of the insulating layer.

7. The semiconductor memory device according to claim 1, wherein An upper portion of an uppermost first electrode among the plurality of first electrodes has a curved surface, and Wherein, the extended portion of the first vertical channel structure contacts the curved surface.

8. The semiconductor memory device according to claim 1, wherein The expansion portion of the first vertical channel structure horizontally extends a first distance from the first vertical extension portion of the first vertical channel structure, wherein the extension portion of the first dummy structure extends horizontally a second distance from the first vertical extension portion of the first dummy structure, and The second distance is greater than the first distance.

9. The semiconductor memory device according to claim 1, further comprising: a separation structure at least partially penetrating the electrode structure and extending in a specific direction, wherein the separation structure horizontally divides the electrode structure; as well as a second vertical channel structure at least partially penetrating the electrode structure and adjacent to the separation structure, The maximum width of the first vertical extension portion of the first vertical channel structure is the first width, wherein the maximum width of the extended portion of the first vertical channel structure is the second width, wherein the maximum width of the first vertical extension portion of the second vertical channel structure is the third width, wherein the maximum width of the extended portion of the second vertical channel structure is a fourth width, and The ratio of the second width to the first width is greater than the ratio of the fourth width to the third width.

10. The semiconductor memory device according to claim 1, wherein The substrate includes a first substrate and a second substrate provided on the first substrate, The semiconductor memory device further includes a peripheral circuit structure between the first substrate and the second substrate, and The electrode structure is provided on the second substrate, so that the first vertical channel structure is connected to the second substrate.

11. The semiconductor memory device according to claim 1, wherein Each of the first vertical channel structure and the first dummy structure includes: vertical semiconductor patterns; and a vertical insulating pattern, which is between the vertical semiconductor pattern and the electrode structure, Wherein, the vertical insulating pattern of the first vertical channel structure includes a data storage layer.

12. A semiconductor memory device comprising: a substrate comprising a cell region, a connection region, and a cell edge region disposed between the cell region and the connection region; an electrode structure disposed on the substrate; a first vertical channel structure at least partially penetrating the electrode structure on the cell region; as well as a second vertical channel structure at least partially penetrating the electrode structure on the cell edge region; Wherein, the electrode structure comprises: a first electrode structure comprising a plurality of first electrodes stacked on the substrate; and a second electrode structure comprising a plurality of second electrodes stacked on the first electrode structure, Wherein, each of the first vertical channel structure and the second vertical channel structure has: a first vertically extending portion at least partially penetrating the first electrode structure; a second vertically extending portion at least partially penetrating the second electrode structure; and an expansion portion disposed between the first vertically extending portion and the second vertically extending portion, Wherein, a vertical length of the extended portion of the first vertical channel structure is greater than a vertical length of the extended portion of the second vertical channel structure.

13. The semiconductor memory device according to claim 12, further comprising a first dummy structure at least partially penetrating the electrode structure on the connection region, in, A vertical length of the extended portion of the second vertical channel structure is greater than a vertical length of the extended portion of the first dummy structure.

14. The semiconductor memory device according to claim 13, further comprising a second dummy structure at least partially penetrating the electrode structure on the connection region, in, The distance between the second dummy structure and the cell area is greater than the distance between the first dummy structure and the cell area, and The vertical length of the extended portion of the first dummy structure is greater than the vertical length of the extended portion of the second dummy structure.

15. The semiconductor memory device according to claim 12, wherein The first electrode structure includes an insulating layer on a topmost first electrode of the plurality of first electrodes, and A top surface of the extended portion of the first vertical channel structure and a top surface of the extended portion of the second vertical channel structure are each coplanar with a top surface of the insulating layer.

16. The semiconductor memory device according to claim 12, further comprising: a separation structure at least partially penetrating the electrode structure and extending in a specific direction, wherein the separation structure horizontally divides the electrode structure; as well as a third vertical channel structure at least partially penetrating the electrode structure on the cell region and adjacent to the separation structure; The maximum width of the first vertical extension portion of the first vertical channel structure is the first width, wherein the maximum width of the extended portion of the first vertical channel structure is the second width, The maximum width of the first vertical extension portion of the third vertical channel structure is the third width. wherein the maximum width of the extended portion of the third vertical channel structure is a fourth width, and The ratio of the second width to the first width is greater than the ratio of the fourth width to the third width.

17. A semiconductor memory device comprising: a substrate comprising a cell region and a connection region; an electrode structure disposed on the substrate, wherein the electrode structure has a step structure on the connection region; a first vertical channel structure at least partially penetrating the electrode structure on the cell region; as well as a first dummy structure at least partially penetrating the electrode structure on the connection region, Wherein, the electrode structure comprises: a first electrode structure comprising a plurality of first electrodes stacked on the substrate; and a second electrode structure comprising a plurality of second electrodes stacked on the first electrode structure, Wherein, each of the first vertical channel structure and the first dummy structure has: a first vertically extending portion at least partially penetrating the first electrode structure; a second vertically extending portion at least partially penetrating the second electrode structure; and an expansion portion disposed between the first vertically extending portion and the second vertically extending portion, The maximum width of the first vertical extension portion of the first vertical channel structure is the first width, wherein the maximum width of the extended portion of the first vertical channel structure is the second width, The maximum width of the first vertical extension portion of the first dummy structure is the third width. wherein the maximum width of the extended portion of the first dummy structure is a fourth width, and The ratio of the second width to the first width is greater than the ratio of the fourth width to the third width.

18. The semiconductor memory device according to claim 17, wherein The substrate further includes a cell edge region disposed between the cell region and the connection region. Wherein, the semiconductor memory device comprises: a second vertical channel structure at least partially penetrating the electrode structure on the cell edge region; and a second dummy structure at least partially penetrating the electrode structure on the connection region, The distance between the second dummy structure and the unit area is greater than the distance between the first dummy structure and the unit area. The bottom of the extended portion of the second vertical channel structure is higher than the bottom of the extended portion of the first vertical channel structure. The bottom of the extended portion of the first dummy structure is higher than the bottom of the extended portion of the second vertical channel structure, and The bottom of the extended portion of the second dummy structure is higher than the bottom of the extended portion of the first dummy structure.

19. The semiconductor memory device according to claim 18, wherein The first electrode structure includes an insulating layer on a topmost first electrode of the plurality of first electrodes, and The top surfaces of the first vertical channel structure, the second vertical channel structure, and the extended portions of the first dummy structure and the second dummy structure are coplanar with the top surface of the insulating layer.

20. The semiconductor memory device according to claim 17, further comprising: a separation structure at least partially penetrating the electrode structure and extending in a specific direction, wherein the separation structure horizontally divides the electrode structure; as well as a second vertical channel structure at least partially penetrating the electrode structure and adjacent to the separation structure, wherein the maximum width of the first vertical extension portion of the second vertical channel structure is a fifth width, wherein the maximum width of the extended portion of the second vertical channel structure is a sixth width, and The ratio of the second width to the first width is greater than the ratio of the sixth width to the fifth width.

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